1# SPDX-License-Identifier: GPL-2.0-only 2# 3# Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 4# 5 6config ARC 7 def_bool y 8 select ARC_TIMERS 9 select ARCH_HAS_CPU_CACHE_ALIASING 10 select ARCH_HAS_CACHE_LINE_SIZE 11 select ARCH_HAS_DEBUG_VM_PGTABLE 12 select ARCH_HAS_DMA_PREP_COHERENT 13 select ARCH_HAS_PTE_SPECIAL 14 select ARCH_HAS_SETUP_DMA_OPS 15 select ARCH_HAS_SYNC_DMA_FOR_CPU 16 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 17 select ARCH_NEED_CMPXCHG_1_EMU 18 select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC 19 select ARCH_32BIT_OFF_T 20 select BUILDTIME_TABLE_SORT 21 select CLONE_BACKWARDS 22 select COMMON_CLK 23 select DMA_DIRECT_REMAP 24 select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC) 25 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP 26 select GENERIC_IRQ_SHOW 27 select GENERIC_PCI_IOMAP 28 select GENERIC_PENDING_IRQ if SMP 29 select GENERIC_SCHED_CLOCK 30 select GENERIC_SMP_IDLE_THREAD 31 select GENERIC_IOREMAP 32 select GENERIC_STRNCPY_FROM_USER if MMU 33 select GENERIC_STRNLEN_USER if MMU 34 select HAVE_ARCH_KGDB 35 select HAVE_ARCH_TRACEHOOK 36 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARC_MMU_V4 37 select HAVE_DEBUG_STACKOVERFLOW 38 select HAVE_DEBUG_KMEMLEAK 39 select HAVE_IOREMAP_PROT 40 select HAVE_KERNEL_GZIP 41 select HAVE_KERNEL_LZMA 42 select HAVE_KPROBES 43 select HAVE_KRETPROBES 44 select HAVE_REGS_AND_STACK_ACCESS_API 45 select HAVE_MOD_ARCH_SPECIFIC 46 select HAVE_PERF_EVENTS 47 select HAVE_SYSCALL_TRACEPOINTS 48 select IRQ_DOMAIN 49 select LOCK_MM_AND_FIND_VMA 50 select MODULES_USE_ELF_RELA 51 select OF 52 select OF_EARLY_FLATTREE 53 select PCI_SYSCALL if PCI 54 select HAVE_ARCH_JUMP_LABEL if ISA_ARCV2 && !CPU_ENDIAN_BE32 55 select TRACE_IRQFLAGS_SUPPORT 56 select HAVE_EBPF_JIT if ISA_ARCV2 57 58config LOCKDEP_SUPPORT 59 def_bool y 60 61config SCHED_OMIT_FRAME_POINTER 62 def_bool y 63 64config GENERIC_CSUM 65 def_bool y 66 67config ARCH_FLATMEM_ENABLE 68 def_bool y 69 70config MMU 71 def_bool y 72 73config NO_IOPORT_MAP 74 def_bool y 75 76config GENERIC_CALIBRATE_DELAY 77 def_bool y 78 79config GENERIC_HWEIGHT 80 def_bool y 81 82config STACKTRACE_SUPPORT 83 def_bool y 84 select STACKTRACE 85 86menu "ARC Architecture Configuration" 87 88menu "ARC Platform/SoC/Board" 89 90source "arch/arc/plat-tb10x/Kconfig" 91source "arch/arc/plat-axs10x/Kconfig" 92source "arch/arc/plat-hsdk/Kconfig" 93 94endmenu 95 96choice 97 prompt "ARC Instruction Set" 98 default ISA_ARCV2 99 100config ISA_ARCOMPACT 101 bool "ARCompact ISA" 102 select CPU_NO_EFFICIENT_FFS 103 help 104 The original ARC ISA of ARC600/700 cores 105 106config ISA_ARCV2 107 bool "ARC ISA v2" 108 select ARC_TIMERS_64BIT 109 help 110 ISA for the Next Generation ARC-HS cores 111 112endchoice 113 114menu "ARC CPU Configuration" 115 116choice 117 prompt "ARC Core" 118 default ARC_CPU_770 if ISA_ARCOMPACT 119 default ARC_CPU_HS if ISA_ARCV2 120 121config ARC_CPU_770 122 bool "ARC770" 123 depends on ISA_ARCOMPACT 124 select ARC_HAS_SWAPE 125 help 126 Support for ARC770 core introduced with Rel 4.10 (Summer 2011) 127 This core has a bunch of cool new features: 128 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4) 129 Shared Address Spaces (for sharing TLB entries in MMU) 130 -Caches: New Prog Model, Region Flush 131 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr 132 133config ARC_CPU_HS 134 bool "ARC-HS" 135 depends on ISA_ARCV2 136 help 137 Support for ARC HS38x Cores based on ARCv2 ISA 138 The notable features are: 139 - SMP configurations of up to 4 cores with coherency 140 - Optional L2 Cache and IO-Coherency 141 - Revised Interrupt Architecture (multiple priorites, reg banks, 142 auto stack switch, auto regfile save/restore) 143 - MMUv4 (PIPT dcache, Huge Pages) 144 - Instructions for 145 * 64bit load/store: LDD, STD 146 * Hardware assisted divide/remainder: DIV, REM 147 * Function prologue/epilogue: ENTER_S, LEAVE_S 148 * IRQ enable/disable: CLRI, SETI 149 * pop count: FFS, FLS 150 * SETcc, BMSKN, XBFU... 151 152endchoice 153 154config ARC_TUNE_MCPU 155 string "Override default -mcpu compiler flag" 156 default "" 157 help 158 Override default -mcpu=xxx compiler flag (which is set depending on 159 the ISA version) with the specified value. 160 NOTE: If specified flag isn't supported by current compiler the 161 ISA default value will be used as a fallback. 162 163config CPU_BIG_ENDIAN 164 bool "Enable Big Endian Mode" 165 help 166 Build kernel for Big Endian Mode of ARC CPU 167 168config SMP 169 bool "Symmetric Multi-Processing" 170 select ARC_MCIP if ISA_ARCV2 171 help 172 This enables support for systems with more than one CPU. 173 174if SMP 175 176config NR_CPUS 177 int "Maximum number of CPUs (2-4096)" 178 range 2 4096 179 default "4" 180 181config ARC_SMP_HALT_ON_RESET 182 bool "Enable Halt-on-reset boot mode" 183 help 184 In SMP configuration cores can be configured as Halt-on-reset 185 or they could all start at same time. For Halt-on-reset, non 186 masters are parked until Master kicks them so they can start off 187 at designated entry point. For other case, all jump to common 188 entry point and spin wait for Master's signal. 189 190endif #SMP 191 192config ARC_MCIP 193 bool "ARConnect Multicore IP (MCIP) Support " 194 depends on ISA_ARCV2 195 default y if SMP 196 help 197 This IP block enables SMP in ARC-HS38 cores. 198 It provides for cross-core interrupts, multi-core debug 199 hardware semaphores, shared memory,.... 200 201menuconfig ARC_CACHE 202 bool "Enable Cache Support" 203 default y 204 205if ARC_CACHE 206 207config ARC_CACHE_LINE_SHIFT 208 int "Cache Line Length (as power of 2)" 209 range 5 7 210 default "6" 211 help 212 Starting with ARC700 4.9, Cache line length is configurable, 213 This option specifies "N", with Line-len = 2 power N 214 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively 215 Linux only supports same line lengths for I and D caches. 216 217config ARC_HAS_ICACHE 218 bool "Use Instruction Cache" 219 default y 220 221config ARC_HAS_DCACHE 222 bool "Use Data Cache" 223 default y 224 225config ARC_CACHE_PAGES 226 bool "Per Page Cache Control" 227 default y 228 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE 229 help 230 This can be used to over-ride the global I/D Cache Enable on a 231 per-page basis (but only for pages accessed via MMU such as 232 Kernel Virtual address or User Virtual Address) 233 TLB entries have a per-page Cache Enable Bit. 234 Note that Global I/D ENABLE + Per Page DISABLE works but corollary 235 Global DISABLE + Per Page ENABLE won't work 236 237endif #ARC_CACHE 238 239config ARC_HAS_ICCM 240 bool "Use ICCM" 241 help 242 Single Cycle RAMS to store Fast Path Code 243 244config ARC_ICCM_SZ 245 int "ICCM Size in KB" 246 default "64" 247 depends on ARC_HAS_ICCM 248 249config ARC_HAS_DCCM 250 bool "Use DCCM" 251 help 252 Single Cycle RAMS to store Fast Path Data 253 254config ARC_DCCM_SZ 255 int "DCCM Size in KB" 256 default "64" 257 depends on ARC_HAS_DCCM 258 259config ARC_DCCM_BASE 260 hex "DCCM map address" 261 default "0xA0000000" 262 depends on ARC_HAS_DCCM 263 264choice 265 prompt "MMU Version" 266 default ARC_MMU_V3 if ISA_ARCOMPACT 267 default ARC_MMU_V4 if ISA_ARCV2 268 269config ARC_MMU_V3 270 bool "MMU v3" 271 depends on ISA_ARCOMPACT 272 help 273 Introduced with ARC700 4.10: New Features 274 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4) 275 Shared Address Spaces (SASID) 276 277config ARC_MMU_V4 278 bool "MMU v4" 279 depends on ISA_ARCV2 280 281endchoice 282 283 284choice 285 prompt "MMU Page Size" 286 default ARC_PAGE_SIZE_8K 287 288config ARC_PAGE_SIZE_8K 289 bool "8KB" 290 select HAVE_PAGE_SIZE_8KB 291 help 292 Choose between 8k vs 16k 293 294config ARC_PAGE_SIZE_16K 295 select HAVE_PAGE_SIZE_16KB 296 bool "16KB" 297 298config ARC_PAGE_SIZE_4K 299 bool "4KB" 300 select HAVE_PAGE_SIZE_4KB 301 302endchoice 303 304choice 305 prompt "MMU Super Page Size" 306 depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE 307 default ARC_HUGEPAGE_2M 308 309config ARC_HUGEPAGE_2M 310 bool "2MB" 311 312config ARC_HUGEPAGE_16M 313 bool "16MB" 314 315endchoice 316 317config PGTABLE_LEVELS 318 int "Number of Page table levels" 319 default 2 320 321config ARC_COMPACT_IRQ_LEVELS 322 depends on ISA_ARCOMPACT 323 bool "Setup Timer IRQ as high Priority" 324 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy 325 depends on !SMP 326 327config ARC_FPU_SAVE_RESTORE 328 bool "Enable FPU state persistence across context switch" 329 help 330 ARCompact FPU has internal registers to assist with Double precision 331 Floating Point operations. There are control and stauts registers 332 for floating point exceptions and rounding modes. These are 333 preserved across task context switch when enabled. 334 335config ARC_CANT_LLSC 336 def_bool n 337 338config ARC_HAS_LLSC 339 bool "Insn: LLOCK/SCOND (efficient atomic ops)" 340 default y 341 depends on !ARC_CANT_LLSC 342 343config ARC_HAS_SWAPE 344 bool "Insn: SWAPE (endian-swap)" 345 default y 346 347if ISA_ARCV2 348 349config ARC_USE_UNALIGNED_MEM_ACCESS 350 bool "Enable unaligned access in HW" 351 default y 352 select HAVE_EFFICIENT_UNALIGNED_ACCESS 353 help 354 The ARC HS architecture supports unaligned memory access 355 which is disabled by default. Enable unaligned access in 356 hardware and use software to use it 357 358config ARC_HAS_LL64 359 bool "Insn: 64bit LDD/STD" 360 help 361 Enable gcc to generate 64-bit load/store instructions 362 ISA mandates even/odd registers to allow encoding of two 363 dest operands with 2 possible source operands. 364 default y 365 366config ARC_HAS_DIV_REM 367 bool "Insn: div, divu, rem, remu" 368 default y 369 370config ARC_HAS_ACCL_REGS 371 bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6 and/or DSP)" 372 default y 373 help 374 Depending on the configuration, CPU can contain accumulator reg-pair 375 (also referred to as r58:r59). These can also be used by gcc as GPR so 376 kernel needs to save/restore per process 377 378config ARC_DSP_HANDLED 379 def_bool n 380 381config ARC_DSP_SAVE_RESTORE_REGS 382 def_bool n 383 384choice 385 prompt "DSP support" 386 default ARC_DSP_NONE 387 help 388 Depending on the configuration, CPU can contain DSP registers 389 (ACC0_GLO, ACC0_GHI, DSP_BFLY0, DSP_CTRL, DSP_FFT_CTRL). 390 Below are options describing how to handle these registers in 391 interrupt entry / exit and in context switch. 392 393config ARC_DSP_NONE 394 bool "No DSP extension presence in HW" 395 help 396 No DSP extension presence in HW 397 398config ARC_DSP_KERNEL 399 bool "DSP extension in HW, no support for userspace" 400 select ARC_HAS_ACCL_REGS 401 select ARC_DSP_HANDLED 402 help 403 DSP extension presence in HW, no support for DSP-enabled userspace 404 applications. We don't save / restore DSP registers and only do 405 some minimal preparations so userspace won't be able to break kernel 406 407config ARC_DSP_USERSPACE 408 bool "Support DSP for userspace apps" 409 select ARC_HAS_ACCL_REGS 410 select ARC_DSP_HANDLED 411 select ARC_DSP_SAVE_RESTORE_REGS 412 help 413 DSP extension presence in HW, support save / restore DSP registers to 414 run DSP-enabled userspace applications 415 416config ARC_DSP_AGU_USERSPACE 417 bool "Support DSP with AGU for userspace apps" 418 select ARC_HAS_ACCL_REGS 419 select ARC_DSP_HANDLED 420 select ARC_DSP_SAVE_RESTORE_REGS 421 help 422 DSP and AGU extensions presence in HW, support save / restore DSP 423 and AGU registers to run DSP-enabled userspace applications 424endchoice 425 426config ARC_IRQ_NO_AUTOSAVE 427 bool "Disable hardware autosave regfile on interrupts" 428 default n 429 help 430 On HS cores, taken interrupt auto saves the regfile on stack. 431 This is programmable and can be optionally disabled in which case 432 software INTERRUPT_PROLOGUE/EPILGUE do the needed work 433 434config ARC_LPB_DISABLE 435 bool "Disable loop buffer (LPB)" 436 help 437 On HS cores, loop buffer (LPB) is programmable in runtime and can 438 be optionally disabled. 439 440endif # ISA_ARCV2 441 442endmenu # "ARC CPU Configuration" 443 444config LINUX_LINK_BASE 445 hex "Kernel link address" 446 default "0x80000000" 447 help 448 ARC700 divides the 32 bit phy address space into two equal halves 449 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU 450 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel 451 Typically Linux kernel is linked at the start of untransalted addr, 452 hence the default value of 0x8zs. 453 However some customers have peripherals mapped at this addr, so 454 Linux needs to be scooted a bit. 455 If you don't know what the above means, leave this setting alone. 456 This needs to match memory start address specified in Device Tree 457 458config LINUX_RAM_BASE 459 hex "RAM base address" 460 default LINUX_LINK_BASE 461 help 462 By default Linux is linked at base of RAM. However in some special 463 cases (such as HSDK), Linux can't be linked at start of DDR, hence 464 this option. 465 466config HIGHMEM 467 bool "High Memory Support" 468 select HAVE_ARCH_PFN_VALID 469 select KMAP_LOCAL 470 help 471 With ARC 2G:2G address split, only upper 2G is directly addressable by 472 kernel. Enable this to potentially allow access to rest of 2G and PAE 473 in future 474 475config ARC_HAS_PAE40 476 bool "Support for the 40-bit Physical Address Extension" 477 depends on ARC_MMU_V4 478 depends on !ARC_PAGE_SIZE_4K 479 select HIGHMEM 480 select PHYS_ADDR_T_64BIT 481 help 482 Enable access to physical memory beyond 4G, only supported on 483 ARC cores with 40 bit Physical Addressing support 484 485config ARC_KVADDR_SIZE 486 int "Kernel Virtual Address Space size (MB)" 487 range 0 512 488 default "256" 489 help 490 The kernel address space is carved out of 256MB of translated address 491 space for catering to vmalloc, modules, pkmap, fixmap. This however may 492 not suffice vmalloc requirements of a 4K CPU EZChip system. So allow 493 this to be stretched to 512 MB (by extending into the reserved 494 kernel-user gutter) 495 496config ARC_CURR_IN_REG 497 bool "cache current task pointer in gp" 498 default y 499 help 500 This reserves gp register to point to Current Task in 501 kernel mode eliding memory access for each access 502 503 504config ARC_EMUL_UNALIGNED 505 bool "Emulate unaligned memory access (userspace only)" 506 select SYSCTL_ARCH_UNALIGN_NO_WARN 507 select SYSCTL_ARCH_UNALIGN_ALLOW 508 depends on ISA_ARCOMPACT 509 help 510 This enables misaligned 16 & 32 bit memory access from user space. 511 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide 512 potential bugs in code 513 514config HZ 515 int "Timer Frequency" 516 default 100 517 518config ARC_METAWARE_HLINK 519 bool "Support for Metaware debugger assisted Host access" 520 help 521 This options allows a Linux userland apps to directly access 522 host file system (open/creat/read/write etc) with help from 523 Metaware Debugger. This can come in handy for Linux-host communication 524 when there is no real usable peripheral such as EMAC. 525 526menuconfig ARC_DBG 527 bool "ARC debugging" 528 default y 529 530if ARC_DBG 531 532config ARC_DW2_UNWIND 533 bool "Enable DWARF specific kernel stack unwind" 534 default y 535 select KALLSYMS 536 help 537 Compiles the kernel with DWARF unwind information and can be used 538 to get stack backtraces. 539 540 If you say Y here the resulting kernel image will be slightly larger 541 but not slower, and it will give very useful debugging information. 542 If you don't debug the kernel, you can say N, but we may not be able 543 to solve problems without frame unwind information 544 545config ARC_DBG_JUMP_LABEL 546 bool "Paranoid checks in Static Keys (jump labels) code" 547 depends on JUMP_LABEL 548 default y if STATIC_KEYS_SELFTEST 549 help 550 Enable paranoid checks and self-test of both ARC-specific and generic 551 part of static keys (jump labels) related code. 552endif 553 554config ARC_BUILTIN_DTB_NAME 555 string "Built in DTB" 556 help 557 Set the name of the DTB to embed in the vmlinux binary 558 Leaving it blank selects the "nsim_700" dtb. 559 560endmenu # "ARC Architecture Configuration" 561 562config ARCH_FORCE_MAX_ORDER 563 int "Maximum zone order" 564 default "11" if ARC_HUGEPAGE_16M 565 default "10" 566 567source "kernel/power/Kconfig" 568