1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _AV7110_HW_H_ 3 #define _AV7110_HW_H_ 4 5 #include "av7110.h" 6 7 /* DEBI transfer mode defs */ 8 9 #define DEBINOSWAP 0x000e0000 10 #define DEBISWAB 0x001e0000 11 #define DEBISWAP 0x002e0000 12 13 #define ARM_WAIT_FREE (HZ) 14 #define ARM_WAIT_SHAKE (HZ / 5) 15 #define ARM_WAIT_OSD (HZ) 16 17 enum av7110_bootstate { 18 BOOTSTATE_BUFFER_EMPTY = 0, 19 BOOTSTATE_BUFFER_FULL = 1, 20 BOOTSTATE_AV7110_BOOT_COMPLETE = 2 21 }; 22 23 enum av7110_type_rec_play_format { 24 AV7110_RP_NONE, 25 AV7110_AUDIO_PES, 26 AV7110_AUDIO_MP2, 27 AV7110_AUDIO_PCM, 28 AV7110_VIDEO_PES, 29 AV7110_AV_PES, 30 }; 31 32 enum av7110_osd_palette_type { 33 NoPalet = 0, /* No palette */ 34 Pal1Bit = 2, /* 2 colors for 1 Bit Palette */ 35 Pal2Bit = 4, /* 4 colors for 2 bit palette */ 36 Pal4Bit = 16, /* 16 colors for 4 bit palette */ 37 Pal8Bit = 256 /* 256 colors for 16 bit palette */ 38 }; 39 40 /* switch defines */ 41 #define SB_GPIO 3 42 #define SB_OFF SAA7146_GPIO_OUTLO /* SlowBlank off (TV-Mode) */ 43 #define SB_ON SAA7146_GPIO_INPUT /* SlowBlank on (AV-Mode) */ 44 #define SB_WIDE SAA7146_GPIO_OUTHI /* SlowBlank 6V (16/9-Mode) (not implemented) */ 45 46 #define FB_GPIO 1 47 #define FB_OFF SAA7146_GPIO_LO /* FastBlank off (CVBS-Mode) */ 48 #define FB_ON SAA7146_GPIO_OUTHI /* FastBlank on (RGB-Mode) */ 49 #define FB_LOOP SAA7146_GPIO_INPUT /* FastBlank loop-through (PC graphics ???) */ 50 51 enum av7110_video_output_mode { 52 NO_OUT = 0, /* disable analog output */ 53 CVBS_RGB_OUT = 1, 54 CVBS_YC_OUT = 2, 55 YC_OUT = 3 56 }; 57 58 /* firmware internal msg q status: */ 59 #define GPMQFull 0x0001 /* Main Message Queue Full */ 60 #define GPMQOver 0x0002 /* Main Message Queue Overflow */ 61 #define HPQFull 0x0004 /* High Priority Msg Queue Full */ 62 #define HPQOver 0x0008 63 #define OSDQFull 0x0010 /* OSD Queue Full */ 64 #define OSDQOver 0x0020 65 #define GPMQBusy 0x0040 /* Queue not empty, FW >= 261d */ 66 #define HPQBusy 0x0080 67 #define OSDQBusy 0x0100 68 69 /* hw section filter flags */ 70 #define SECTION_EIT 0x01 71 #define SECTION_SINGLE 0x00 72 #define SECTION_CYCLE 0x02 73 #define SECTION_CONTINUOS 0x04 74 #define SECTION_MODE 0x06 75 #define SECTION_IPMPE 0x0C /* size up to 4k */ 76 #define SECTION_HIGH_SPEED 0x1C /* larger buffer */ 77 #define DATA_PIPING_FLAG 0x20 /* for Data Piping Filter */ 78 79 #define PBUFSIZE_NONE 0x0000 80 #define PBUFSIZE_1P 0x0100 81 #define PBUFSIZE_2P 0x0200 82 #define PBUFSIZE_1K 0x0300 83 #define PBUFSIZE_2K 0x0400 84 #define PBUFSIZE_4K 0x0500 85 #define PBUFSIZE_8K 0x0600 86 #define PBUFSIZE_16K 0x0700 87 #define PBUFSIZE_32K 0x0800 88 89 /* firmware command codes */ 90 enum av7110_osd_command { 91 WCreate, 92 WDestroy, 93 WMoveD, 94 WMoveA, 95 WHide, 96 WTop, 97 DBox, 98 DLine, 99 DText, 100 Set_Font, 101 SetColor, 102 SetBlend, 103 SetWBlend, 104 SetCBlend, 105 SetNonBlend, 106 LoadBmp, 107 BlitBmp, 108 ReleaseBmp, 109 SetWTrans, 110 SetWNoTrans, 111 Set_Palette 112 }; 113 114 enum av7110_pid_command { 115 AV7110_MULTI_PID, 116 AV7110_VIDEO_PID, 117 AV7110_AUDIO_PID, 118 AV7110_INIT_FILT, 119 AV7110_FILT_ERROR, 120 AV7110_NEW_VERSION, 121 AV7110_CACHE_ERROR, 122 AV7110_ADD_PID_FILTER, 123 AV7110_DEL_PID_FILTER, 124 AV7110_SCAN, 125 AV7110_SET_DESCR, 126 AV7110_SET_IR, 127 AV7110_FLUSH_TS_QUEUE, 128 }; 129 130 enum av7110_mpeg_command { 131 SelAudChannels 132 }; 133 134 enum av7110_audio_command { 135 AudioDAC, 136 CabADAC, 137 ON22K, 138 OFF22K, 139 MainSwitch, 140 ADSwitch, 141 SendDiSEqC, 142 SetRegister, 143 SpdifSwitch 144 }; 145 146 enum av7110_request_command { 147 AudioState, 148 AudioBuffState, 149 VideoState1, 150 VideoState2, 151 VideoState3, 152 CrashCounter, 153 ReqVersion, 154 ReqVCXO, 155 ReqRegister, 156 ReqSecFilterError, 157 ReqSTC 158 }; 159 160 enum av7110_encoder_command { 161 AV7110_SET_VID_MODE, 162 AV7110_SET_TEST_MODE, 163 AV7110_LOAD_VID_CODE, 164 AV7110_SET_MONITOR_TYPE, 165 AV7110_SET_PANSCAN_TYPE, 166 AV7110_SET_FREEZE_MODE, 167 AV7110_SET_WSS_CONFIG, 168 }; 169 170 enum av7110_rec_play_state { 171 AV7110_REC_PLAY_RECORD, 172 AV7110_REC_PLAY_STOP, 173 AV7110_REC_PLAY_PLAY, 174 AV7110_REC_PLAY_PAUSE, 175 AV7110_REC_PLAY_SLOW, 176 AV7110_REC_PLAY_FF_IP, 177 AV7110_REC_PLAY_SCAN_I, 178 AV7110_REC_PLAY_CONTINUE, 179 }; 180 181 enum av7110_fw_cmd_misc { 182 AV7110_FW_VIDEO_ZOOM = 1, 183 AV7110_FW_VIDEO_COMMAND, 184 AV7110_FW_AUDIO_COMMAND 185 }; 186 187 enum av7110_command_type { 188 COMTYPE_NOCOM, 189 COMTYPE_PIDFILTER, 190 COMTYPE_MPEGDECODER, 191 COMTYPE_OSD, 192 COMTYPE_BMP, 193 COMTYPE_ENCODER, 194 COMTYPE_AUDIODAC, 195 COMTYPE_REQUEST, 196 COMTYPE_SYSTEM, 197 COMTYPE_REC_PLAY, 198 COMTYPE_COMMON_IF, 199 COMTYPE_PID_FILTER, 200 COMTYPE_PES, 201 COMTYPE_TS, 202 COMTYPE_VIDEO, 203 COMTYPE_AUDIO, 204 COMTYPE_CI_LL, 205 COMTYPE_MISC = 0x80 206 }; 207 208 #define VID_NONE_PREF 0x00 /* No aspect ration processing preferred */ 209 #define VID_PAN_SCAN_PREF 0x01 /* Pan and Scan Display preferred */ 210 #define VID_VERT_COMP_PREF 0x02 /* Vertical compression display preferred */ 211 #define VID_VC_AND_PS_PREF 0x03 /* PanScan and vertical Compression if allowed */ 212 #define VID_CENTRE_CUT_PREF 0x05 /* PanScan with zero vector */ 213 214 /* MPEG video decoder commands */ 215 #define AV_VIDEO_CMD_STOP 0x000e 216 #define AV_VIDEO_CMD_PLAY 0x000d 217 #define AV_VIDEO_CMD_FREEZE 0x0102 218 #define AV_VIDEO_CMD_FFWD 0x0016 219 #define AV_VIDEO_CMD_SLOW 0x0022 220 221 /* MPEG audio decoder commands */ 222 #define AUDIO_CMD_MUTE 0x0001 223 #define AUDIO_CMD_UNMUTE 0x0002 224 #define AUDIO_CMD_PCM16 0x0010 225 #define AUDIO_CMD_STEREO 0x0080 226 #define AUDIO_CMD_MONO_L 0x0100 227 #define AUDIO_CMD_MONO_R 0x0200 228 #define AUDIO_CMD_SYNC_OFF 0x000e 229 #define AUDIO_CMD_SYNC_ON 0x000f 230 231 /* firmware data interface codes */ 232 #define DATA_NONE 0x00 233 #define DATA_FSECTION 0x01 234 #define DATA_IPMPE 0x02 235 #define DATA_MPEG_RECORD 0x03 236 #define DATA_DEBUG_MESSAGE 0x04 237 #define DATA_COMMON_INTERFACE 0x05 238 #define DATA_MPEG_PLAY 0x06 239 #define DATA_BMP_LOAD 0x07 240 #define DATA_IRCOMMAND 0x08 241 #define DATA_PIPING 0x09 242 #define DATA_STREAMING 0x0a 243 #define DATA_CI_GET 0x0b 244 #define DATA_CI_PUT 0x0c 245 #define DATA_MPEG_VIDEO_EVENT 0x0d 246 247 #define DATA_PES_RECORD 0x10 248 #define DATA_PES_PLAY 0x11 249 #define DATA_TS_RECORD 0x12 250 #define DATA_TS_PLAY 0x13 251 252 /* ancient CI command codes, only two are actually still used 253 * by the link level CI firmware 254 */ 255 #define CI_CMD_ERROR 0x00 256 #define CI_CMD_ACK 0x01 257 #define CI_CMD_SYSTEM_READY 0x02 258 #define CI_CMD_KEYPRESS 0x03 259 #define CI_CMD_ON_TUNED 0x04 260 #define CI_CMD_ON_SWITCH_PROGRAM 0x05 261 #define CI_CMD_SECTION_ARRIVED 0x06 262 #define CI_CMD_SECTION_TIMEOUT 0x07 263 #define CI_CMD_TIME 0x08 264 #define CI_CMD_ENTER_MENU 0x09 265 #define CI_CMD_FAST_PSI 0x0a 266 #define CI_CMD_GET_SLOT_INFO 0x0b 267 268 #define CI_MSG_NONE 0x00 269 #define CI_MSG_CI_INFO 0x01 270 #define CI_MSG_MENU 0x02 271 #define CI_MSG_LIST 0x03 272 #define CI_MSG_TEXT 0x04 273 #define CI_MSG_REQUEST_INPUT 0x05 274 #define CI_MSG_INPUT_COMPLETE 0x06 275 #define CI_MSG_LIST_MORE 0x07 276 #define CI_MSG_MENU_MORE 0x08 277 #define CI_MSG_CLOSE_MMI_IMM 0x09 278 #define CI_MSG_SECTION_REQUEST 0x0a 279 #define CI_MSG_CLOSE_FILTER 0x0b 280 #define CI_PSI_COMPLETE 0x0c 281 #define CI_MODULE_READY 0x0d 282 #define CI_SWITCH_PRG_REPLY 0x0e 283 #define CI_MSG_TEXT_MORE 0x0f 284 285 #define CI_MSG_CA_PMT 0xe0 286 #define CI_MSG_ERROR 0xf0 287 288 /* base address of the dual ported RAM which serves as communication 289 * area between PCI bus and av7110, 290 * as seen by the DEBI bus of the saa7146 291 */ 292 #define DPRAM_BASE 0x4000 293 294 /* boot protocol area */ 295 #define AV7110_BOOT_STATE (DPRAM_BASE + 0x3F8) 296 #define AV7110_BOOT_SIZE (DPRAM_BASE + 0x3FA) 297 #define AV7110_BOOT_BASE (DPRAM_BASE + 0x3FC) 298 #define AV7110_BOOT_BLOCK (DPRAM_BASE + 0x400) 299 #define AV7110_BOOT_MAX_SIZE 0xc00 300 301 /* firmware command protocol area */ 302 #define IRQ_STATE (DPRAM_BASE + 0x0F4) 303 #define IRQ_STATE_EXT (DPRAM_BASE + 0x0F6) 304 #define MSGSTATE (DPRAM_BASE + 0x0F8) 305 #define COMMAND (DPRAM_BASE + 0x0FC) 306 #define COM_BUFF (DPRAM_BASE + 0x100) 307 #define COM_BUFF_SIZE 0x20 308 309 /* various data buffers */ 310 #define BUFF1_BASE (DPRAM_BASE + 0x120) 311 #define BUFF1_SIZE 0xE0 312 313 #define DATA_BUFF0_BASE (DPRAM_BASE + 0x200) 314 #define DATA_BUFF0_SIZE 0x0800 315 316 #define DATA_BUFF1_BASE (DATA_BUFF0_BASE + DATA_BUFF0_SIZE) 317 #define DATA_BUFF1_SIZE 0x0800 318 319 #define DATA_BUFF2_BASE (DATA_BUFF1_BASE + DATA_BUFF1_SIZE) 320 #define DATA_BUFF2_SIZE 0x0800 321 322 #define DATA_BUFF3_BASE (DATA_BUFF2_BASE + DATA_BUFF2_SIZE) 323 #define DATA_BUFF3_SIZE 0x0400 324 325 #define Reserved (DPRAM_BASE + 0x1E00) 326 #define Reserved_SIZE 0x1C0 327 328 /* firmware status area */ 329 #define STATUS_BASE (DPRAM_BASE + 0x1FC0) 330 #define STATUS_LOOPS (STATUS_BASE + 0x08) 331 332 #define STATUS_MPEG_WIDTH (STATUS_BASE + 0x0C) 333 /* ((aspect_ratio & 0xf) << 12) | (height & 0xfff) */ 334 #define STATUS_MPEG_HEIGHT_AR (STATUS_BASE + 0x0E) 335 336 /* firmware data protocol area */ 337 #define RX_TYPE (DPRAM_BASE + 0x1FE8) 338 #define RX_LEN (DPRAM_BASE + 0x1FEA) 339 #define TX_TYPE (DPRAM_BASE + 0x1FEC) 340 #define TX_LEN (DPRAM_BASE + 0x1FEE) 341 342 #define RX_BUFF (DPRAM_BASE + 0x1FF4) 343 #define TX_BUFF (DPRAM_BASE + 0x1FF6) 344 345 #define HANDSHAKE_REG (DPRAM_BASE + 0x1FF8) 346 #define COM_IF_LOCK (DPRAM_BASE + 0x1FFA) 347 348 #define IRQ_RX (DPRAM_BASE + 0x1FFC) 349 #define IRQ_TX (DPRAM_BASE + 0x1FFE) 350 351 /* used by boot protocol to load firmware into av7110 DRAM */ 352 #define DRAM_START_CODE 0x2e000404 353 #define DRAM_MAX_CODE_SIZE 0x00100000 354 355 /* saa7146 gpio lines */ 356 #define RESET_LINE 2 357 #define DEBI_DONE_LINE 1 358 #define ARM_IRQ_LINE 0 359 360 int av7110_bootarm(struct av7110 *av7110); 361 int av7110_firmversion(struct av7110 *av7110); 362 #define FW_CI_LL_SUPPORT(arm_app) ((arm_app) & 0x80000000) 363 #define FW_4M_SDRAM(arm_app) ((arm_app) & 0x40000000) 364 #define FW_VERSION(arm_app) ((arm_app) & 0x0000FFFF) 365 366 int av7110_wait_msgstate(struct av7110 *av7110, u16 flags); 367 int av7110_fw_cmd(struct av7110 *av7110, int type, int com, int num, ...); 368 int av7110_fw_request(struct av7110 *av7110, u16 *request_buf, 369 int request_buf_len, u16 *reply_buf, int reply_buf_len); 370 371 /* DEBI (saa7146 data extension bus interface) access */ 372 int av7110_debiwrite(struct av7110 *av7110, u32 config, 373 int addr, u32 val, unsigned int count); 374 u32 av7110_debiread(struct av7110 *av7110, u32 config, 375 int addr, unsigned int count); 376 377 /* DEBI during interrupt */ 378 /* single word writes */ 379 static inline void iwdebi(struct av7110 *av7110, u32 config, int addr, u32 val, unsigned int count) 380 { 381 av7110_debiwrite(av7110, config, addr, val, count); 382 } 383 384 /* buffer writes */ 385 static inline void mwdebi(struct av7110 *av7110, u32 config, int addr, 386 const u8 *val, int count) 387 { 388 memcpy(av7110->debi_virt, val, count); 389 av7110_debiwrite(av7110, config, addr, 0, count); 390 } 391 392 static inline u32 irdebi(struct av7110 *av7110, u32 config, int addr, u32 val, unsigned int count) 393 { 394 u32 res; 395 396 res = av7110_debiread(av7110, config, addr, count); 397 if (count <= 4) 398 memcpy(av7110->debi_virt, (char *)&res, count); 399 return res; 400 } 401 402 /* DEBI outside interrupts, only for count <= 4! */ 403 static inline void wdebi(struct av7110 *av7110, u32 config, int addr, u32 val, unsigned int count) 404 { 405 unsigned long flags; 406 407 spin_lock_irqsave(&av7110->debilock, flags); 408 av7110_debiwrite(av7110, config, addr, val, count); 409 spin_unlock_irqrestore(&av7110->debilock, flags); 410 } 411 412 static inline u32 rdebi(struct av7110 *av7110, u32 config, int addr, u32 val, unsigned int count) 413 { 414 unsigned long flags; 415 u32 res; 416 417 spin_lock_irqsave(&av7110->debilock, flags); 418 res = av7110_debiread(av7110, config, addr, count); 419 spin_unlock_irqrestore(&av7110->debilock, flags); 420 return res; 421 } 422 423 /* handle mailbox registers of the dual ported RAM */ 424 static inline void ARM_ResetMailBox(struct av7110 *av7110) 425 { 426 unsigned long flags; 427 428 spin_lock_irqsave(&av7110->debilock, flags); 429 av7110_debiread(av7110, DEBINOSWAP, IRQ_RX, 2); 430 av7110_debiwrite(av7110, DEBINOSWAP, IRQ_RX, 0, 2); 431 spin_unlock_irqrestore(&av7110->debilock, flags); 432 } 433 434 static inline void ARM_ClearMailBox(struct av7110 *av7110) 435 { 436 iwdebi(av7110, DEBINOSWAP, IRQ_RX, 0, 2); 437 } 438 439 static inline void ARM_ClearIrq(struct av7110 *av7110) 440 { 441 irdebi(av7110, DEBINOSWAP, IRQ_RX, 0, 2); 442 } 443 444 /**************************************************************************** 445 * Firmware commands 446 ****************************************************************************/ 447 448 static inline int SendDAC(struct av7110 *av7110, u8 addr, u8 data) 449 { 450 return av7110_fw_cmd(av7110, COMTYPE_AUDIODAC, AudioDAC, 2, addr, data); 451 } 452 453 static inline int av7710_set_video_mode(struct av7110 *av7110, int mode) 454 { 455 return av7110_fw_cmd(av7110, COMTYPE_ENCODER, 456 AV7110_SET_VID_MODE, 1, mode); 457 } 458 459 static inline int vidcom(struct av7110 *av7110, u32 com, u32 arg) 460 { 461 return av7110_fw_cmd(av7110, COMTYPE_MISC, AV7110_FW_VIDEO_COMMAND, 4, 462 (com >> 16), (com & 0xffff), 463 (arg >> 16), (arg & 0xffff)); 464 } 465 466 static inline int audcom(struct av7110 *av7110, u32 com) 467 { 468 return av7110_fw_cmd(av7110, COMTYPE_MISC, AV7110_FW_AUDIO_COMMAND, 2, 469 (com >> 16), (com & 0xffff)); 470 } 471 472 static inline int Set22K(struct av7110 *av7110, int state) 473 { 474 return av7110_fw_cmd(av7110, COMTYPE_AUDIODAC, (state ? ON22K : OFF22K), 0); 475 } 476 477 int av7110_diseqc_send(struct av7110 *av7110, int len, u8 *msg, unsigned long burst); 478 479 #ifdef CONFIG_DVB_AV7110_OSD 480 int av7110_osd_cmd(struct av7110 *av7110, osd_cmd_t *dc); 481 int av7110_osd_capability(struct av7110 *av7110, osd_cap_t *cap); 482 #endif /* CONFIG_DVB_AV7110_OSD */ 483 484 #endif /* _AV7110_HW_H_ */ 485