1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell Octeon EP (EndPoint) Ethernet Driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #ifndef _OCTEP_REGS_CNXK_PF_H_ 9 #define _OCTEP_REGS_CNXK_PF_H_ 10 11 /* ############################ RST ######################### */ 12 #define CNXK_RST_BOOT 0x000087E006001600ULL 13 #define CNXK_RST_CHIP_DOMAIN_W1S 0x000087E006001810ULL 14 #define CNXK_RST_CORE_DOMAIN_W1S 0x000087E006001820ULL 15 #define CNXK_RST_CORE_DOMAIN_W1C 0x000087E006001828ULL 16 17 #define CNXK_CONFIG_XPANSION_BAR 0x38 18 #define CNXK_CONFIG_PCIE_CAP 0x70 19 #define CNXK_CONFIG_PCIE_DEVCAP 0x74 20 #define CNXK_CONFIG_PCIE_DEVCTL 0x78 21 #define CNXK_CONFIG_PCIE_LINKCAP 0x7C 22 #define CNXK_CONFIG_PCIE_LINKCTL 0x80 23 #define CNXK_CONFIG_PCIE_SLOTCAP 0x84 24 #define CNXK_CONFIG_PCIE_SLOTCTL 0x88 25 26 #define CNXK_PCIE_SRIOV_FDL 0x188 /* 0x98 */ 27 #define CNXK_PCIE_SRIOV_FDL_BIT_POS 0x10 28 #define CNXK_PCIE_SRIOV_FDL_MASK 0xFF 29 30 #define CNXK_CONFIG_PCIE_FLTMSK 0x720 31 32 /* ################# Offsets of RING, EPF, MAC ######################### */ 33 #define CNXK_RING_OFFSET (0x1ULL << 17) 34 #define CNXK_EPF_OFFSET (0x1ULL << 25) 35 #define CNXK_MAC_OFFSET (0x1ULL << 4) 36 #define CNXK_BIT_ARRAY_OFFSET (0x1ULL << 4) 37 #define CNXK_EPVF_RING_OFFSET (0x1ULL << 4) 38 39 /* ################# Scratch Registers ######################### */ 40 #define CNXK_SDP_EPF_SCRATCH 0x209E0 41 42 /* ################# Window Registers ######################### */ 43 #define CNXK_SDP_WIN_WR_ADDR64 0x20000 44 #define CNXK_SDP_WIN_RD_ADDR64 0x20010 45 #define CNXK_SDP_WIN_WR_DATA64 0x20020 46 #define CNXK_SDP_WIN_WR_MASK_REG 0x20030 47 #define CNXK_SDP_WIN_RD_DATA64 0x20040 48 49 #define CNXK_SDP_MAC_NUMBER 0x2C100 50 51 /* ################# Global Previliged registers ######################### */ 52 #define CNXK_SDP_EPF_RINFO 0x209F0 53 54 #define CNXK_SDP_EPF_RINFO_SRN(val) ((val) & 0x7F) 55 #define CNXK_SDP_EPF_RINFO_RPVF(val) (((val) >> 32) & 0xF) 56 #define CNXK_SDP_EPF_RINFO_NVFS(val) (((val) >> 48) & 0x7F) 57 58 /* SDP Function select */ 59 #define CNXK_SDP_FUNC_SEL_EPF_BIT_POS 7 60 #define CNXK_SDP_FUNC_SEL_FUNC_BIT_POS 0 61 62 /* ##### RING IN (Into device from PCI: Tx Ring) REGISTERS #### */ 63 #define CNXK_SDP_R_IN_CONTROL_START 0x10000 64 #define CNXK_SDP_R_IN_ENABLE_START 0x10010 65 #define CNXK_SDP_R_IN_INSTR_BADDR_START 0x10020 66 #define CNXK_SDP_R_IN_INSTR_RSIZE_START 0x10030 67 #define CNXK_SDP_R_IN_INSTR_DBELL_START 0x10040 68 #define CNXK_SDP_R_IN_CNTS_START 0x10050 69 #define CNXK_SDP_R_IN_INT_LEVELS_START 0x10060 70 #define CNXK_SDP_R_IN_PKT_CNT_START 0x10080 71 #define CNXK_SDP_R_IN_BYTE_CNT_START 0x10090 72 73 #define CNXK_SDP_R_IN_CONTROL(ring) \ 74 (CNXK_SDP_R_IN_CONTROL_START + ((ring) * CNXK_RING_OFFSET)) 75 76 #define CNXK_SDP_R_IN_ENABLE(ring) \ 77 (CNXK_SDP_R_IN_ENABLE_START + ((ring) * CNXK_RING_OFFSET)) 78 79 #define CNXK_SDP_R_IN_INSTR_BADDR(ring) \ 80 (CNXK_SDP_R_IN_INSTR_BADDR_START + ((ring) * CNXK_RING_OFFSET)) 81 82 #define CNXK_SDP_R_IN_INSTR_RSIZE(ring) \ 83 (CNXK_SDP_R_IN_INSTR_RSIZE_START + ((ring) * CNXK_RING_OFFSET)) 84 85 #define CNXK_SDP_R_IN_INSTR_DBELL(ring) \ 86 (CNXK_SDP_R_IN_INSTR_DBELL_START + ((ring) * CNXK_RING_OFFSET)) 87 88 #define CNXK_SDP_R_IN_CNTS(ring) \ 89 (CNXK_SDP_R_IN_CNTS_START + ((ring) * CNXK_RING_OFFSET)) 90 91 #define CNXK_SDP_R_IN_INT_LEVELS(ring) \ 92 (CNXK_SDP_R_IN_INT_LEVELS_START + ((ring) * CNXK_RING_OFFSET)) 93 94 #define CNXK_SDP_R_IN_PKT_CNT(ring) \ 95 (CNXK_SDP_R_IN_PKT_CNT_START + ((ring) * CNXK_RING_OFFSET)) 96 97 #define CNXK_SDP_R_IN_BYTE_CNT(ring) \ 98 (CNXK_SDP_R_IN_BYTE_CNT_START + ((ring) * CNXK_RING_OFFSET)) 99 100 /* Rings per Virtual Function */ 101 #define CNXK_R_IN_CTL_RPVF_MASK (0xF) 102 #define CNXK_R_IN_CTL_RPVF_POS (48) 103 104 /* Number of instructions to be read in one MAC read request. 105 * setting to Max value(4) 106 */ 107 #define CNXK_R_IN_CTL_IDLE (0x1ULL << 28) 108 #define CNXK_R_IN_CTL_RDSIZE (0x3ULL << 25) 109 #define CNXK_R_IN_CTL_IS_64B (0x1ULL << 24) 110 #define CNXK_R_IN_CTL_D_NSR (0x1ULL << 8) 111 #define CNXK_R_IN_CTL_D_ESR (0x1ULL << 6) 112 #define CNXK_R_IN_CTL_D_ROR (0x1ULL << 5) 113 #define CNXK_R_IN_CTL_NSR (0x1ULL << 3) 114 #define CNXK_R_IN_CTL_ESR (0x1ULL << 1) 115 #define CNXK_R_IN_CTL_ROR (0x1ULL << 0) 116 117 #define CNXK_R_IN_CTL_MASK (CNXK_R_IN_CTL_RDSIZE | CNXK_R_IN_CTL_IS_64B) 118 119 /* ##### RING OUT (out from device to PCI host: Rx Ring) REGISTERS #### */ 120 #define CNXK_SDP_R_OUT_CNTS_START 0x10100 121 #define CNXK_SDP_R_OUT_INT_LEVELS_START 0x10110 122 #define CNXK_SDP_R_OUT_SLIST_BADDR_START 0x10120 123 #define CNXK_SDP_R_OUT_SLIST_RSIZE_START 0x10130 124 #define CNXK_SDP_R_OUT_SLIST_DBELL_START 0x10140 125 #define CNXK_SDP_R_OUT_CONTROL_START 0x10150 126 #define CNXK_SDP_R_OUT_WMARK_START 0x10160 127 #define CNXK_SDP_R_OUT_ENABLE_START 0x10170 128 #define CNXK_SDP_R_OUT_PKT_CNT_START 0x10180 129 #define CNXK_SDP_R_OUT_BYTE_CNT_START 0x10190 130 131 #define CNXK_SDP_R_OUT_CONTROL(ring) \ 132 (CNXK_SDP_R_OUT_CONTROL_START + ((ring) * CNXK_RING_OFFSET)) 133 134 #define CNXK_SDP_R_OUT_ENABLE(ring) \ 135 (CNXK_SDP_R_OUT_ENABLE_START + ((ring) * CNXK_RING_OFFSET)) 136 137 #define CNXK_SDP_R_OUT_SLIST_BADDR(ring) \ 138 (CNXK_SDP_R_OUT_SLIST_BADDR_START + ((ring) * CNXK_RING_OFFSET)) 139 140 #define CNXK_SDP_R_OUT_SLIST_RSIZE(ring) \ 141 (CNXK_SDP_R_OUT_SLIST_RSIZE_START + ((ring) * CNXK_RING_OFFSET)) 142 143 #define CNXK_SDP_R_OUT_SLIST_DBELL(ring) \ 144 (CNXK_SDP_R_OUT_SLIST_DBELL_START + ((ring) * CNXK_RING_OFFSET)) 145 146 #define CNXK_SDP_R_OUT_WMARK(ring) \ 147 (CNXK_SDP_R_OUT_WMARK_START + ((ring) * CNXK_RING_OFFSET)) 148 149 #define CNXK_SDP_R_OUT_CNTS(ring) \ 150 (CNXK_SDP_R_OUT_CNTS_START + ((ring) * CNXK_RING_OFFSET)) 151 152 #define CNXK_SDP_R_OUT_INT_LEVELS(ring) \ 153 (CNXK_SDP_R_OUT_INT_LEVELS_START + ((ring) * CNXK_RING_OFFSET)) 154 155 #define CNXK_SDP_R_OUT_PKT_CNT(ring) \ 156 (CNXK_SDP_R_OUT_PKT_CNT_START + ((ring) * CNXK_RING_OFFSET)) 157 158 #define CNXK_SDP_R_OUT_BYTE_CNT(ring) \ 159 (CNXK_SDP_R_OUT_BYTE_CNT_START + ((ring) * CNXK_RING_OFFSET)) 160 161 /*------------------ R_OUT Masks ----------------*/ 162 #define CNXK_R_OUT_INT_LEVELS_BMODE BIT_ULL(63) 163 #define CNXK_R_OUT_INT_LEVELS_TIMET (32) 164 165 #define CNXK_R_OUT_CTL_IDLE BIT_ULL(40) 166 #define CNXK_R_OUT_CTL_ES_I BIT_ULL(34) 167 #define CNXK_R_OUT_CTL_NSR_I BIT_ULL(33) 168 #define CNXK_R_OUT_CTL_ROR_I BIT_ULL(32) 169 #define CNXK_R_OUT_CTL_ES_D BIT_ULL(30) 170 #define CNXK_R_OUT_CTL_NSR_D BIT_ULL(29) 171 #define CNXK_R_OUT_CTL_ROR_D BIT_ULL(28) 172 #define CNXK_R_OUT_CTL_ES_P BIT_ULL(26) 173 #define CNXK_R_OUT_CTL_NSR_P BIT_ULL(25) 174 #define CNXK_R_OUT_CTL_ROR_P BIT_ULL(24) 175 #define CNXK_R_OUT_CTL_IMODE BIT_ULL(23) 176 177 /* ############### Interrupt Moderation Registers ############### */ 178 #define CNXK_SDP_R_IN_INT_MDRT_CTL0_START 0x10280 179 #define CNXK_SDP_R_IN_INT_MDRT_CTL1_START 0x102A0 180 #define CNXK_SDP_R_IN_INT_MDRT_DBG_START 0x102C0 181 182 #define CNXK_SDP_R_OUT_INT_MDRT_CTL0_START 0x10380 183 #define CNXK_SDP_R_OUT_INT_MDRT_CTL1_START 0x103A0 184 #define CNXK_SDP_R_OUT_INT_MDRT_DBG_START 0x103C0 185 186 #define CNXK_SDP_R_MBOX_ISM_START 0x10500 187 #define CNXK_SDP_R_OUT_CNTS_ISM_START 0x10510 188 #define CNXK_SDP_R_IN_CNTS_ISM_START 0x10520 189 190 #define CNXK_SDP_R_IN_INT_MDRT_CTL0(ring) \ 191 (CNXK_SDP_R_IN_INT_MDRT_CTL0_START + ((ring) * CNXK_RING_OFFSET)) 192 193 #define CNXK_SDP_R_IN_INT_MDRT_CTL1(ring) \ 194 (CNXK_SDP_R_IN_INT_MDRT_CTL1_START + ((ring) * CNXK_RING_OFFSET)) 195 196 #define CNXK_SDP_R_IN_INT_MDRT_DBG(ring) \ 197 (CNXK_SDP_R_IN_INT_MDRT_DBG_START + ((ring) * CNXK_RING_OFFSET)) 198 199 #define CNXK_SDP_R_OUT_INT_MDRT_CTL0(ring) \ 200 (CNXK_SDP_R_OUT_INT_MDRT_CTL0_START + ((ring) * CNXK_RING_OFFSET)) 201 202 #define CNXK_SDP_R_OUT_INT_MDRT_CTL1(ring) \ 203 (CNXK_SDP_R_OUT_INT_MDRT_CTL1_START + ((ring) * CNXK_RING_OFFSET)) 204 205 #define CNXK_SDP_R_OUT_INT_MDRT_DBG(ring) \ 206 (CNXK_SDP_R_OUT_INT_MDRT_DBG_START + ((ring) * CNXK_RING_OFFSET)) 207 208 #define CNXK_SDP_R_MBOX_ISM(ring) \ 209 (CNXK_SDP_R_MBOX_ISM_START + ((ring) * CNXK_RING_OFFSET)) 210 211 #define CNXK_SDP_R_OUT_CNTS_ISM(ring) \ 212 (CNXK_SDP_R_OUT_CNTS_ISM_START + ((ring) * CNXK_RING_OFFSET)) 213 214 #define CNXK_SDP_R_IN_CNTS_ISM(ring) \ 215 (CNXK_SDP_R_IN_CNTS_ISM_START + ((ring) * CNXK_RING_OFFSET)) 216 217 /* ##################### Mail Box Registers ########################## */ 218 /* INT register for VF. when a MBOX write from PF happed to a VF, 219 * corresponding bit will be set in this register as well as in 220 * PF_VF_INT register. 221 * 222 * This is a RO register, the int can be cleared by writing 1 to PF_VF_INT 223 */ 224 /* Basically first 3 are from PF to VF. The last one is data from VF to PF */ 225 #define CNXK_SDP_R_MBOX_PF_VF_DATA_START 0x10210 226 #define CNXK_SDP_R_MBOX_PF_VF_INT_START 0x10220 227 #define CNXK_SDP_R_MBOX_VF_PF_DATA_START 0x10230 228 229 #define CNXK_SDP_MBOX_VF_PF_DATA_START 0x24000 230 #define CNXK_SDP_MBOX_PF_VF_DATA_START 0x22000 231 232 #define CNXK_SDP_R_MBOX_PF_VF_DATA(ring) \ 233 (CNXK_SDP_R_MBOX_PF_VF_DATA_START + ((ring) * CNXK_RING_OFFSET)) 234 235 #define CNXK_SDP_R_MBOX_PF_VF_INT(ring) \ 236 (CNXK_SDP_R_MBOX_PF_VF_INT_START + ((ring) * CNXK_RING_OFFSET)) 237 238 #define CNXK_SDP_R_MBOX_VF_PF_DATA(ring) \ 239 (CNXK_SDP_R_MBOX_VF_PF_DATA_START + ((ring) * CNXK_RING_OFFSET)) 240 241 #define CNXK_SDP_MBOX_VF_PF_DATA(ring) \ 242 (CNXK_SDP_MBOX_VF_PF_DATA_START + ((ring) * CNXK_EPVF_RING_OFFSET)) 243 244 #define CNXK_SDP_MBOX_PF_VF_DATA(ring) \ 245 (CNXK_SDP_MBOX_PF_VF_DATA_START + ((ring) * CNXK_EPVF_RING_OFFSET)) 246 247 /* ##################### Interrupt Registers ########################## */ 248 #define CNXK_SDP_R_ERR_TYPE_START 0x10400 249 250 #define CNXK_SDP_R_ERR_TYPE(ring) \ 251 (CNXK_SDP_R_ERR_TYPE_START + ((ring) * CNXK_RING_OFFSET)) 252 253 #define CNXK_SDP_R_MBOX_ISM_START 0x10500 254 #define CNXK_SDP_R_OUT_CNTS_ISM_START 0x10510 255 #define CNXK_SDP_R_IN_CNTS_ISM_START 0x10520 256 257 #define CNXK_SDP_R_MBOX_ISM(ring) \ 258 (CNXK_SDP_R_MBOX_ISM_START + ((ring) * CNXK_RING_OFFSET)) 259 260 #define CNXK_SDP_R_OUT_CNTS_ISM(ring) \ 261 (CNXK_SDP_R_OUT_CNTS_ISM_START + ((ring) * CNXK_RING_OFFSET)) 262 263 #define CNXK_SDP_R_IN_CNTS_ISM(ring) \ 264 (CNXK_SDP_R_IN_CNTS_ISM_START + ((ring) * CNXK_RING_OFFSET)) 265 266 #define CNXK_SDP_EPF_MBOX_RINT_START 0x20100 267 #define CNXK_SDP_EPF_MBOX_RINT_W1S_START 0x20120 268 #define CNXK_SDP_EPF_MBOX_RINT_ENA_W1C_START 0x20140 269 #define CNXK_SDP_EPF_MBOX_RINT_ENA_W1S_START 0x20160 270 271 #define CNXK_SDP_EPF_VFIRE_RINT_START 0x20180 272 #define CNXK_SDP_EPF_VFIRE_RINT_W1S_START 0x201A0 273 #define CNXK_SDP_EPF_VFIRE_RINT_ENA_W1C_START 0x201C0 274 #define CNXK_SDP_EPF_VFIRE_RINT_ENA_W1S_START 0x201E0 275 276 #define CNXK_SDP_EPF_IRERR_RINT 0x20200 277 #define CNXK_SDP_EPF_IRERR_RINT_W1S 0x20210 278 #define CNXK_SDP_EPF_IRERR_RINT_ENA_W1C 0x20220 279 #define CNXK_SDP_EPF_IRERR_RINT_ENA_W1S 0x20230 280 281 #define CNXK_SDP_EPF_VFORE_RINT_START 0x20240 282 #define CNXK_SDP_EPF_VFORE_RINT_W1S_START 0x20260 283 #define CNXK_SDP_EPF_VFORE_RINT_ENA_W1C_START 0x20280 284 #define CNXK_SDP_EPF_VFORE_RINT_ENA_W1S_START 0x202A0 285 286 #define CNXK_SDP_EPF_ORERR_RINT 0x20320 287 #define CNXK_SDP_EPF_ORERR_RINT_W1S 0x20330 288 #define CNXK_SDP_EPF_ORERR_RINT_ENA_W1C 0x20340 289 #define CNXK_SDP_EPF_ORERR_RINT_ENA_W1S 0x20350 290 291 #define CNXK_SDP_EPF_OEI_RINT 0x20400 292 #define CNXK_SDP_EPF_OEI_RINT_W1S 0x20500 293 #define CNXK_SDP_EPF_OEI_RINT_ENA_W1C 0x20600 294 #define CNXK_SDP_EPF_OEI_RINT_ENA_W1S 0x20700 295 296 #define CNXK_SDP_EPF_DMA_RINT 0x20800 297 #define CNXK_SDP_EPF_DMA_RINT_W1S 0x20810 298 #define CNXK_SDP_EPF_DMA_RINT_ENA_W1C 0x20820 299 #define CNXK_SDP_EPF_DMA_RINT_ENA_W1S 0x20830 300 301 #define CNXK_SDP_EPF_DMA_INT_LEVEL_START 0x20840 302 #define CNXK_SDP_EPF_DMA_CNT_START 0x20860 303 #define CNXK_SDP_EPF_DMA_TIM_START 0x20880 304 305 #define CNXK_SDP_EPF_MISC_RINT 0x208A0 306 #define CNXK_SDP_EPF_MISC_RINT_W1S 0x208B0 307 #define CNXK_SDP_EPF_MISC_RINT_ENA_W1C 0x208C0 308 #define CNXK_SDP_EPF_MISC_RINT_ENA_W1S 0x208D0 309 310 #define CNXK_SDP_EPF_DMA_VF_RINT_START 0x208E0 311 #define CNXK_SDP_EPF_DMA_VF_RINT_W1S_START 0x20900 312 #define CNXK_SDP_EPF_DMA_VF_RINT_ENA_W1C_START 0x20920 313 #define CNXK_SDP_EPF_DMA_VF_RINT_ENA_W1S_START 0x20940 314 315 #define CNXK_SDP_EPF_PP_VF_RINT_START 0x20960 316 #define CNXK_SDP_EPF_PP_VF_RINT_W1S_START 0x20980 317 #define CNXK_SDP_EPF_PP_VF_RINT_ENA_W1C_START 0x209A0 318 #define CNXK_SDP_EPF_PP_VF_RINT_ENA_W1S_START 0x209C0 319 320 #define CNXK_SDP_EPF_MBOX_RINT(index) \ 321 (CNXK_SDP_EPF_MBOX_RINT_START + ((index) * CNXK_BIT_ARRAY_OFFSET)) 322 #define CNXK_SDP_EPF_MBOX_RINT_W1S(index) \ 323 (CNXK_SDP_EPF_MBOX_RINT_W1S_START + ((index) * CNXK_BIT_ARRAY_OFFSET)) 324 #define CNXK_SDP_EPF_MBOX_RINT_ENA_W1C(index) \ 325 (CNXK_SDP_EPF_MBOX_RINT_ENA_W1C_START + ((index) * CNXK_BIT_ARRAY_OFFSET)) 326 #define CNXK_SDP_EPF_MBOX_RINT_ENA_W1S(index) \ 327 (CNXK_SDP_EPF_MBOX_RINT_ENA_W1S_START + ((index) * CNXK_BIT_ARRAY_OFFSET)) 328 329 #define CNXK_SDP_EPF_VFIRE_RINT(index) \ 330 (CNXK_SDP_EPF_VFIRE_RINT_START + ((index) * CNXK_BIT_ARRAY_OFFSET)) 331 #define CNXK_SDP_EPF_VFIRE_RINT_W1S(index) \ 332 (CNXK_SDP_EPF_VFIRE_RINT_W1S_START + ((index) * CNXK_BIT_ARRAY_OFFSET)) 333 #define CNXK_SDP_EPF_VFIRE_RINT_ENA_W1C(index) \ 334 (CNXK_SDP_EPF_VFIRE_RINT_ENA_W1C_START + ((index) * CNXK_BIT_ARRAY_OFFSET)) 335 #define CNXK_SDP_EPF_VFIRE_RINT_ENA_W1S(index) \ 336 (CNXK_SDP_EPF_VFIRE_RINT_ENA_W1S_START + ((index) * CNXK_BIT_ARRAY_OFFSET)) 337 338 #define CNXK_SDP_EPF_VFORE_RINT(index) \ 339 (CNXK_SDP_EPF_VFORE_RINT_START + ((index) * CNXK_BIT_ARRAY_OFFSET)) 340 #define CNXK_SDP_EPF_VFORE_RINT_W1S(index) \ 341 (CNXK_SDP_EPF_VFORE_RINT_W1S_START + ((index) * CNXK_BIT_ARRAY_OFFSET)) 342 #define CNXK_SDP_EPF_VFORE_RINT_ENA_W1C(index) \ 343 (CNXK_SDP_EPF_VFORE_RINT_ENA_W1C_START + ((index) * CNXK_BIT_ARRAY_OFFSET)) 344 #define CNXK_SDP_EPF_VFORE_RINT_ENA_W1S(index) \ 345 (CNXK_SDP_EPF_VFORE_RINT_ENA_W1S_START + ((index) * CNXK_BIT_ARRAY_OFFSET)) 346 347 #define CNXK_SDP_EPF_DMA_VF_RINT(index) \ 348 (CNXK_SDP_EPF_DMA_VF_RINT_START + ((index) + CNXK_BIT_ARRAY_OFFSET)) 349 #define CNXK_SDP_EPF_DMA_VF_RINT_W1S(index) \ 350 (CNXK_SDP_EPF_DMA_VF_RINT_W1S_START + ((index) + CNXK_BIT_ARRAY_OFFSET)) 351 #define CNXK_SDP_EPF_DMA_VF_RINT_ENA_W1C(index) \ 352 (CNXK_SDP_EPF_DMA_VF_RINT_ENA_W1C_START + ((index) + CNXK_BIT_ARRAY_OFFSET)) 353 #define CNXK_SDP_EPF_DMA_VF_RINT_ENA_W1S(index) \ 354 (CNXK_SDP_EPF_DMA_VF_RINT_ENA_W1S_START + ((index) + CNXK_BIT_ARRAY_OFFSET)) 355 356 #define CNXK_SDP_EPF_PP_VF_RINT(index) \ 357 (CNXK_SDP_EPF_PP_VF_RINT_START + ((index) + CNXK_BIT_ARRAY_OFFSET)) 358 #define CNXK_SDP_EPF_PP_VF_RINT_W1S(index) \ 359 (CNXK_SDP_EPF_PP_VF_RINT_W1S_START + ((index) + CNXK_BIT_ARRAY_OFFSET)) 360 #define CNXK_SDP_EPF_PP_VF_RINT_ENA_W1C(index) \ 361 (CNXK_SDP_EPF_PP_VF_RINT_ENA_W1C_START + ((index) + CNXK_BIT_ARRAY_OFFSET)) 362 #define CNXK_SDP_EPF_PP_VF_RINT_ENA_W1S(index) \ 363 (CNXK_SDP_EPF_PP_VF_RINT_ENA_W1S_START + ((index) + CNXK_BIT_ARRAY_OFFSET)) 364 365 /*------------------ Interrupt Masks ----------------*/ 366 #define CNXK_INTR_R_SEND_ISM BIT_ULL(63) 367 #define CNXK_INTR_R_OUT_INT BIT_ULL(62) 368 #define CNXK_INTR_R_IN_INT BIT_ULL(61) 369 #define CNXK_INTR_R_MBOX_INT BIT_ULL(60) 370 #define CNXK_INTR_R_RESEND BIT_ULL(59) 371 #define CNXK_INTR_R_CLR_TIM BIT_ULL(58) 372 373 /* ####################### Ring Mapping Registers ################################## */ 374 #define CNXK_SDP_EPVF_RING_START 0x26000 375 #define CNXK_SDP_IN_RING_TB_MAP_START 0x28000 376 #define CNXK_SDP_IN_RATE_LIMIT_START 0x2A000 377 #define CNXK_SDP_MAC_PF_RING_CTL_START 0x2C000 378 379 #define CNXK_SDP_EPVF_RING(ring) \ 380 (CNXK_SDP_EPVF_RING_START + ((ring) * CNXK_EPVF_RING_OFFSET)) 381 #define CNXK_SDP_IN_RING_TB_MAP(ring) \ 382 (CNXK_SDP_N_RING_TB_MAP_START + ((ring) * CNXK_EPVF_RING_OFFSET)) 383 #define CNXK_SDP_IN_RATE_LIMIT(ring) \ 384 (CNXK_SDP_IN_RATE_LIMIT_START + ((ring) * CNXK_EPVF_RING_OFFSET)) 385 #define CNXK_SDP_MAC_PF_RING_CTL(mac) \ 386 (CNXK_SDP_MAC_PF_RING_CTL_START + ((mac) * CNXK_MAC_OFFSET)) 387 388 #define CNXK_SDP_MAC_PF_RING_CTL_NPFS(val) ((val) & 0x3) 389 #define CNXK_SDP_MAC_PF_RING_CTL_SRN(val) (((val) >> 8) & 0x7F) 390 #define CNXK_SDP_MAC_PF_RING_CTL_RPPF(val) (((val) >> 16) & 0x3F) 391 392 /* Number of non-queue interrupts in CNXKxx */ 393 #define CNXK_NUM_NON_IOQ_INTR 32 394 395 /* bit 0 for control mbox interrupt */ 396 #define CNXK_SDP_EPF_OEI_RINT_DATA_BIT_MBOX BIT_ULL(0) 397 /* bit 1 for firmware heartbeat interrupt */ 398 #define CNXK_SDP_EPF_OEI_RINT_DATA_BIT_HBEAT BIT_ULL(1) 399 #define FW_STATUS_RUNNING 2ULL 400 #define CNXK_PEMX_PFX_CSX_PFCFGX(pem, pf, offset) ({ typeof(offset) _off = (offset); \ 401 ((0x8e0000008000 | \ 402 (uint64_t)(pem) << 36 \ 403 | (pf) << 18 \ 404 | ((_off >> 16) & 1) << 16 \ 405 | (_off >> 3) << 3) \ 406 + (((_off >> 2) & 1) << 2)); \ 407 }) 408 409 /* Register defines for use with CNXK_PEMX_PFX_CSX_PFCFGX */ 410 #define CNXK_PCIEEP_VSECST_CTL 0x418 411 412 #define CNXK_PEM_BAR4_INDEX 7 413 #define CNXK_PEM_BAR4_INDEX_SIZE 0x400000ULL 414 #define CNXK_PEM_BAR4_INDEX_OFFSET (CNXK_PEM_BAR4_INDEX * CNXK_PEM_BAR4_INDEX_SIZE) 415 416 #endif /* _OCTEP_REGS_CNXK_PF_H_ */ 417