1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2020 NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 /* 7 * This source file contains Tegra210 supported video formats, 8 * VI and CSI SoC specific data, operations and registers accessors. 9 */ 10 #include <linux/bitfield.h> 11 #include <linux/clk.h> 12 #include <linux/clk/tegra.h> 13 #include <linux/delay.h> 14 #include <linux/host1x.h> 15 #include <linux/kthread.h> 16 17 #include "csi.h" 18 #include "vi.h" 19 20 #define TEGRA210_MIN_WIDTH 32U 21 #define TEGRA210_MAX_WIDTH 32768U 22 #define TEGRA210_MIN_HEIGHT 32U 23 #define TEGRA210_MAX_HEIGHT 32768U 24 25 #define SURFACE_ALIGN_BYTES 64 26 27 #define TEGRA_VI_SYNCPT_WAIT_TIMEOUT msecs_to_jiffies(200) 28 29 /* Tegra210 VI registers */ 30 #define TEGRA_VI_CFG_VI_INCR_SYNCPT 0x000 31 #define VI_CFG_VI_INCR_SYNCPT_COND(x) (((x) & 0xff) << 8) 32 #define VI_CSI_PP_FRAME_START(port) (5 + (port) * 4) 33 #define VI_CSI_MW_ACK_DONE(port) (7 + (port) * 4) 34 #define TEGRA_VI_CFG_VI_INCR_SYNCPT_CNTRL 0x004 35 #define VI_INCR_SYNCPT_NO_STALL BIT(8) 36 #define TEGRA_VI_CFG_VI_INCR_SYNCPT_ERROR 0x008 37 #define TEGRA_VI_CFG_CG_CTRL 0x0b8 38 #define VI_CG_2ND_LEVEL_EN 0x1 39 40 /* Tegra210 VI CSI registers */ 41 #define TEGRA_VI_CSI_SW_RESET 0x000 42 #define TEGRA_VI_CSI_SINGLE_SHOT 0x004 43 #define SINGLE_SHOT_CAPTURE 0x1 44 #define TEGRA_VI_CSI_IMAGE_DEF 0x00c 45 #define BYPASS_PXL_TRANSFORM_OFFSET 24 46 #define IMAGE_DEF_FORMAT_OFFSET 16 47 #define IMAGE_DEF_DEST_MEM 0x1 48 #define TEGRA_VI_CSI_IMAGE_SIZE 0x018 49 #define IMAGE_SIZE_HEIGHT_OFFSET 16 50 #define TEGRA_VI_CSI_IMAGE_SIZE_WC 0x01c 51 #define TEGRA_VI_CSI_IMAGE_DT 0x020 52 #define TEGRA_VI_CSI_SURFACE0_OFFSET_MSB 0x024 53 #define TEGRA_VI_CSI_SURFACE0_OFFSET_LSB 0x028 54 #define TEGRA_VI_CSI_SURFACE1_OFFSET_MSB 0x02c 55 #define TEGRA_VI_CSI_SURFACE1_OFFSET_LSB 0x030 56 #define TEGRA_VI_CSI_SURFACE2_OFFSET_MSB 0x034 57 #define TEGRA_VI_CSI_SURFACE2_OFFSET_LSB 0x038 58 #define TEGRA_VI_CSI_SURFACE0_STRIDE 0x054 59 #define TEGRA_VI_CSI_SURFACE1_STRIDE 0x058 60 #define TEGRA_VI_CSI_SURFACE2_STRIDE 0x05c 61 #define TEGRA_VI_CSI_SURFACE_HEIGHT0 0x060 62 #define TEGRA_VI_CSI_ERROR_STATUS 0x084 63 64 /* Tegra210 CSI Pixel Parser registers: Starts from 0x838, offset 0x0 */ 65 #define TEGRA_CSI_INPUT_STREAM_CONTROL 0x000 66 #define CSI_SKIP_PACKET_THRESHOLD_OFFSET 16 67 #define TEGRA_CSI_PIXEL_STREAM_CONTROL0 0x004 68 #define CSI_PP_PACKET_HEADER_SENT BIT(4) 69 #define CSI_PP_DATA_IDENTIFIER_ENABLE BIT(5) 70 #define CSI_PP_WORD_COUNT_SELECT_HEADER BIT(6) 71 #define CSI_PP_CRC_CHECK_ENABLE BIT(7) 72 #define CSI_PP_WC_CHECK BIT(8) 73 #define CSI_PP_OUTPUT_FORMAT_STORE (0x3 << 16) 74 #define CSI_PPA_PAD_LINE_NOPAD (0x2 << 24) 75 #define CSI_PP_HEADER_EC_DISABLE (0x1 << 27) 76 #define CSI_PPA_PAD_FRAME_NOPAD (0x2 << 28) 77 #define TEGRA_CSI_PIXEL_STREAM_CONTROL1 0x008 78 #define CSI_PP_TOP_FIELD_FRAME_OFFSET 0 79 #define CSI_PP_TOP_FIELD_FRAME_MASK_OFFSET 4 80 #define TEGRA_CSI_PIXEL_STREAM_GAP 0x00c 81 #define PP_FRAME_MIN_GAP_OFFSET 16 82 #define TEGRA_CSI_PIXEL_STREAM_PP_COMMAND 0x010 83 #define CSI_PP_ENABLE 0x1 84 #define CSI_PP_DISABLE 0x2 85 #define CSI_PP_RST 0x3 86 #define CSI_PP_SINGLE_SHOT_ENABLE (0x1 << 2) 87 #define CSI_PP_START_MARKER_FRAME_MAX_OFFSET 12 88 #define TEGRA_CSI_PIXEL_STREAM_EXPECTED_FRAME 0x014 89 #define TEGRA_CSI_PIXEL_PARSER_INTERRUPT_MASK 0x018 90 #define TEGRA_CSI_PIXEL_PARSER_STATUS 0x01c 91 92 /* Tegra210 CSI PHY registers */ 93 /* CSI_PHY_CIL_COMMAND_0 offset 0x0d0 from TEGRA_CSI_PIXEL_PARSER_0_BASE */ 94 #define TEGRA_CSI_PHY_CIL_COMMAND 0x0d0 95 #define CSI_A_PHY_CIL_NOP 0x0 96 #define CSI_A_PHY_CIL_ENABLE 0x1 97 #define CSI_A_PHY_CIL_DISABLE 0x2 98 #define CSI_A_PHY_CIL_ENABLE_MASK 0x3 99 #define CSI_B_PHY_CIL_NOP (0x0 << 8) 100 #define CSI_B_PHY_CIL_ENABLE (0x1 << 8) 101 #define CSI_B_PHY_CIL_DISABLE (0x2 << 8) 102 #define CSI_B_PHY_CIL_ENABLE_MASK (0x3 << 8) 103 104 #define TEGRA_CSI_CIL_PAD_CONFIG0 0x000 105 #define BRICK_CLOCK_A_4X (0x1 << 16) 106 #define BRICK_CLOCK_B_4X (0x2 << 16) 107 #define TEGRA_CSI_CIL_PAD_CONFIG1 0x004 108 #define TEGRA_CSI_CIL_PHY_CONTROL 0x008 109 #define CLK_SETTLE_MASK GENMASK(13, 8) 110 #define THS_SETTLE_MASK GENMASK(5, 0) 111 #define TEGRA_CSI_CIL_INTERRUPT_MASK 0x00c 112 #define TEGRA_CSI_CIL_STATUS 0x010 113 #define TEGRA_CSI_CILX_STATUS 0x014 114 #define TEGRA_CSI_CIL_SW_SENSOR_RESET 0x020 115 116 #define TEGRA_CSI_PATTERN_GENERATOR_CTRL 0x000 117 #define PG_MODE_OFFSET 2 118 #define PG_ENABLE 0x1 119 #define PG_DISABLE 0x0 120 #define TEGRA_CSI_PG_BLANK 0x004 121 #define PG_VBLANK_OFFSET 16 122 #define TEGRA_CSI_PG_PHASE 0x008 123 #define TEGRA_CSI_PG_RED_FREQ 0x00c 124 #define PG_RED_VERT_INIT_FREQ_OFFSET 16 125 #define PG_RED_HOR_INIT_FREQ_OFFSET 0 126 #define TEGRA_CSI_PG_RED_FREQ_RATE 0x010 127 #define TEGRA_CSI_PG_GREEN_FREQ 0x014 128 #define PG_GREEN_VERT_INIT_FREQ_OFFSET 16 129 #define PG_GREEN_HOR_INIT_FREQ_OFFSET 0 130 #define TEGRA_CSI_PG_GREEN_FREQ_RATE 0x018 131 #define TEGRA_CSI_PG_BLUE_FREQ 0x01c 132 #define PG_BLUE_VERT_INIT_FREQ_OFFSET 16 133 #define PG_BLUE_HOR_INIT_FREQ_OFFSET 0 134 #define TEGRA_CSI_PG_BLUE_FREQ_RATE 0x020 135 #define TEGRA_CSI_PG_AOHDR 0x024 136 #define TEGRA_CSI_CSI_SW_STATUS_RESET 0x214 137 #define TEGRA_CSI_CLKEN_OVERRIDE 0x218 138 139 #define TEGRA210_CSI_PORT_OFFSET 0x34 140 #define TEGRA210_CSI_CIL_OFFSET 0x0f4 141 #define TEGRA210_CSI_TPG_OFFSET 0x18c 142 143 #define CSI_PP_OFFSET(block) ((block) * 0x800) 144 #define TEGRA210_VI_CSI_BASE(x) (0x100 + (x) * 0x100) 145 146 /* Tegra210 VI registers accessors */ 147 static void tegra_vi_write(struct tegra_vi_channel *chan, unsigned int addr, 148 u32 val) 149 { 150 writel_relaxed(val, chan->vi->iomem + addr); 151 } 152 153 static u32 tegra_vi_read(struct tegra_vi_channel *chan, unsigned int addr) 154 { 155 return readl_relaxed(chan->vi->iomem + addr); 156 } 157 158 /* Tegra210 VI_CSI registers accessors */ 159 static void vi_csi_write(struct tegra_vi_channel *chan, u8 portno, 160 unsigned int addr, u32 val) 161 { 162 void __iomem *vi_csi_base; 163 164 vi_csi_base = chan->vi->iomem + TEGRA210_VI_CSI_BASE(portno); 165 166 writel_relaxed(val, vi_csi_base + addr); 167 } 168 169 static u32 vi_csi_read(struct tegra_vi_channel *chan, u8 portno, 170 unsigned int addr) 171 { 172 void __iomem *vi_csi_base; 173 174 vi_csi_base = chan->vi->iomem + TEGRA210_VI_CSI_BASE(portno); 175 176 return readl_relaxed(vi_csi_base + addr); 177 } 178 179 /* 180 * Tegra210 VI channel capture operations 181 */ 182 183 static int tegra210_channel_host1x_syncpt_init(struct tegra_vi_channel *chan) 184 { 185 struct tegra_vi *vi = chan->vi; 186 unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED; 187 struct host1x_syncpt *fs_sp; 188 struct host1x_syncpt *mw_sp; 189 int ret, i; 190 191 for (i = 0; i < chan->numgangports; i++) { 192 fs_sp = host1x_syncpt_request(&vi->client, flags); 193 if (!fs_sp) { 194 dev_err(vi->dev, "failed to request frame start syncpoint\n"); 195 ret = -ENOMEM; 196 goto free_syncpts; 197 } 198 199 mw_sp = host1x_syncpt_request(&vi->client, flags); 200 if (!mw_sp) { 201 dev_err(vi->dev, "failed to request memory ack syncpoint\n"); 202 host1x_syncpt_put(fs_sp); 203 ret = -ENOMEM; 204 goto free_syncpts; 205 } 206 207 chan->frame_start_sp[i] = fs_sp; 208 chan->mw_ack_sp[i] = mw_sp; 209 spin_lock_init(&chan->sp_incr_lock[i]); 210 } 211 212 return 0; 213 214 free_syncpts: 215 for (i = 0; i < chan->numgangports; i++) { 216 host1x_syncpt_put(chan->mw_ack_sp[i]); 217 host1x_syncpt_put(chan->frame_start_sp[i]); 218 } 219 return ret; 220 } 221 222 static void tegra210_channel_host1x_syncpt_free(struct tegra_vi_channel *chan) 223 { 224 int i; 225 226 for (i = 0; i < chan->numgangports; i++) { 227 host1x_syncpt_put(chan->mw_ack_sp[i]); 228 host1x_syncpt_put(chan->frame_start_sp[i]); 229 } 230 } 231 232 static void tegra210_fmt_align(struct v4l2_pix_format *pix, unsigned int bpp) 233 { 234 unsigned int min_bpl; 235 unsigned int max_bpl; 236 unsigned int bpl; 237 238 /* 239 * The transfer alignment requirements are expressed in bytes. 240 * Clamp the requested width and height to the limits. 241 */ 242 pix->width = clamp(pix->width, TEGRA210_MIN_WIDTH, TEGRA210_MAX_WIDTH); 243 pix->height = clamp(pix->height, TEGRA210_MIN_HEIGHT, TEGRA210_MAX_HEIGHT); 244 245 /* Clamp the requested bytes per line value. If the maximum bytes per 246 * line value is zero, the module doesn't support user configurable 247 * line sizes. Override the requested value with the minimum in that 248 * case. 249 */ 250 min_bpl = pix->width * bpp; 251 max_bpl = rounddown(TEGRA210_MAX_WIDTH, SURFACE_ALIGN_BYTES); 252 bpl = roundup(pix->bytesperline, SURFACE_ALIGN_BYTES); 253 254 pix->bytesperline = clamp(bpl, min_bpl, max_bpl); 255 pix->sizeimage = pix->bytesperline * pix->height; 256 if (pix->pixelformat == V4L2_PIX_FMT_NV16) 257 pix->sizeimage *= 2; 258 } 259 260 static int tegra_channel_capture_setup(struct tegra_vi_channel *chan, 261 u8 portno) 262 { 263 u32 height = chan->format.height; 264 u32 width = chan->format.width; 265 u32 format = chan->fmtinfo->img_fmt; 266 u32 data_type = chan->fmtinfo->img_dt; 267 u32 word_count = (width * chan->fmtinfo->bit_width) / 8; 268 u32 bypass_pixel_transform = BIT(BYPASS_PXL_TRANSFORM_OFFSET); 269 270 /* 271 * VI Pixel transformation unit converts source pixels data format 272 * into selected destination pixel format and aligns properly while 273 * interfacing with memory packer. 274 * This pixel transformation should be enabled for YUV and RGB 275 * formats and should be bypassed for RAW formats as RAW formats 276 * only support direct to memory. 277 */ 278 if (chan->pg_mode || data_type == TEGRA_IMAGE_DT_YUV422_8 || 279 data_type == TEGRA_IMAGE_DT_RGB888) 280 bypass_pixel_transform = 0; 281 282 /* 283 * For x8 source streaming, the source image is split onto two x4 ports 284 * with left half to first x4 port and right half to second x4 port. 285 * So, use split width and corresponding word count for each x4 port. 286 */ 287 if (chan->numgangports > 1) { 288 width = width >> 1; 289 word_count = (width * chan->fmtinfo->bit_width) / 8; 290 } 291 292 vi_csi_write(chan, portno, TEGRA_VI_CSI_ERROR_STATUS, 0xffffffff); 293 vi_csi_write(chan, portno, TEGRA_VI_CSI_IMAGE_DEF, 294 bypass_pixel_transform | 295 (format << IMAGE_DEF_FORMAT_OFFSET) | 296 IMAGE_DEF_DEST_MEM); 297 vi_csi_write(chan, portno, TEGRA_VI_CSI_IMAGE_DT, data_type); 298 vi_csi_write(chan, portno, TEGRA_VI_CSI_IMAGE_SIZE_WC, word_count); 299 vi_csi_write(chan, portno, TEGRA_VI_CSI_IMAGE_SIZE, 300 (height << IMAGE_SIZE_HEIGHT_OFFSET) | width); 301 return 0; 302 } 303 304 static void tegra_channel_vi_soft_reset(struct tegra_vi_channel *chan, 305 u8 portno) 306 { 307 /* disable clock gating to enable continuous clock */ 308 tegra_vi_write(chan, TEGRA_VI_CFG_CG_CTRL, 0); 309 /* 310 * Soft reset memory client interface, pixel format logic, sensor 311 * control logic, and a shadow copy logic to bring VI to clean state. 312 */ 313 vi_csi_write(chan, portno, TEGRA_VI_CSI_SW_RESET, 0xf); 314 usleep_range(100, 200); 315 vi_csi_write(chan, portno, TEGRA_VI_CSI_SW_RESET, 0x0); 316 317 /* enable back VI clock gating */ 318 tegra_vi_write(chan, TEGRA_VI_CFG_CG_CTRL, VI_CG_2ND_LEVEL_EN); 319 } 320 321 static void tegra_channel_capture_error_recover(struct tegra_vi_channel *chan, 322 u8 portno) 323 { 324 struct v4l2_subdev *subdev; 325 u32 val; 326 327 /* 328 * Recover VI and CSI hardware blocks in case of missing frame start 329 * events due to source not streaming or noisy csi inputs from the 330 * external source or many outstanding frame start or MW_ACK_DONE 331 * events which can cause CSI and VI hardware hang. 332 * This helps to have a clean capture for next frame. 333 */ 334 val = vi_csi_read(chan, portno, TEGRA_VI_CSI_ERROR_STATUS); 335 dev_dbg(&chan->video.dev, "TEGRA_VI_CSI_ERROR_STATUS 0x%08x\n", val); 336 vi_csi_write(chan, portno, TEGRA_VI_CSI_ERROR_STATUS, val); 337 338 val = tegra_vi_read(chan, TEGRA_VI_CFG_VI_INCR_SYNCPT_ERROR); 339 dev_dbg(&chan->video.dev, 340 "TEGRA_VI_CFG_VI_INCR_SYNCPT_ERROR 0x%08x\n", val); 341 tegra_vi_write(chan, TEGRA_VI_CFG_VI_INCR_SYNCPT_ERROR, val); 342 343 /* recover VI by issuing software reset and re-setup for capture */ 344 tegra_channel_vi_soft_reset(chan, portno); 345 tegra_channel_capture_setup(chan, portno); 346 347 /* recover CSI block */ 348 subdev = tegra_channel_get_remote_csi_subdev(chan); 349 tegra_csi_error_recover(subdev); 350 } 351 352 static struct tegra_channel_buffer * 353 dequeue_buf_done(struct tegra_vi_channel *chan) 354 { 355 struct tegra_channel_buffer *buf = NULL; 356 357 spin_lock(&chan->done_lock); 358 if (list_empty(&chan->done)) { 359 spin_unlock(&chan->done_lock); 360 return NULL; 361 } 362 363 buf = list_first_entry(&chan->done, 364 struct tegra_channel_buffer, queue); 365 list_del_init(&buf->queue); 366 spin_unlock(&chan->done_lock); 367 368 return buf; 369 } 370 371 static void release_buffer(struct tegra_vi_channel *chan, 372 struct tegra_channel_buffer *buf, 373 enum vb2_buffer_state state) 374 { 375 struct vb2_v4l2_buffer *vb = &buf->buf; 376 377 vb->sequence = chan->sequence++; 378 vb->field = V4L2_FIELD_NONE; 379 vb->vb2_buf.timestamp = ktime_get_ns(); 380 vb2_buffer_done(&vb->vb2_buf, state); 381 } 382 383 static void tegra_channel_vi_buffer_setup(struct tegra_vi_channel *chan, 384 u8 portno, u32 buf_offset, 385 struct tegra_channel_buffer *buf) 386 { 387 int bytesperline = chan->format.bytesperline; 388 u32 sizeimage = chan->format.sizeimage; 389 390 /* program buffer address by using surface 0 */ 391 vi_csi_write(chan, portno, TEGRA_VI_CSI_SURFACE0_OFFSET_MSB, 392 ((u64)buf->addr + buf_offset) >> 32); 393 vi_csi_write(chan, portno, TEGRA_VI_CSI_SURFACE0_OFFSET_LSB, 394 buf->addr + buf_offset); 395 vi_csi_write(chan, portno, TEGRA_VI_CSI_SURFACE0_STRIDE, bytesperline); 396 397 if (chan->fmtinfo->fourcc != V4L2_PIX_FMT_NV16) 398 return; 399 /* 400 * Program surface 1 for UV plane with offset sizeimage from Y plane. 401 */ 402 vi_csi_write(chan, portno, TEGRA_VI_CSI_SURFACE1_OFFSET_MSB, 403 (((u64)buf->addr + sizeimage / 2) + buf_offset) >> 32); 404 vi_csi_write(chan, portno, TEGRA_VI_CSI_SURFACE1_OFFSET_LSB, 405 buf->addr + sizeimage / 2 + buf_offset); 406 vi_csi_write(chan, portno, TEGRA_VI_CSI_SURFACE1_STRIDE, bytesperline); 407 } 408 409 static int tegra_channel_capture_frame(struct tegra_vi_channel *chan, 410 struct tegra_channel_buffer *buf) 411 { 412 u32 thresh, value, frame_start, mw_ack_done; 413 u32 fs_thresh[GANG_PORTS_MAX]; 414 u8 *portnos = chan->portnos; 415 int gang_bpl = (chan->format.width >> 1) * chan->fmtinfo->bpp; 416 u32 buf_offset; 417 bool capture_timedout = false; 418 int err, i; 419 420 for (i = 0; i < chan->numgangports; i++) { 421 /* 422 * Align buffers side-by-side for all consecutive x4 ports 423 * in gang ports using bytes per line based on source split 424 * width. 425 */ 426 buf_offset = i * roundup(gang_bpl, SURFACE_ALIGN_BYTES); 427 tegra_channel_vi_buffer_setup(chan, portnos[i], buf_offset, 428 buf); 429 430 /* 431 * Tegra VI block interacts with host1x syncpt to synchronize 432 * programmed condition and hardware operation for capture. 433 * Frame start and Memory write acknowledge syncpts has their 434 * own FIFO of depth 2. 435 * 436 * Syncpoint trigger conditions set through VI_INCR_SYNCPT 437 * register are added to HW syncpt FIFO and when HW triggers, 438 * syncpt condition is removed from the FIFO and counter at 439 * syncpoint index will be incremented by the hardware and 440 * software can wait for counter to reach threshold to 441 * synchronize capturing frame with hardware capture events. 442 */ 443 444 /* increase channel syncpoint threshold for FRAME_START */ 445 thresh = host1x_syncpt_incr_max(chan->frame_start_sp[i], 1); 446 fs_thresh[i] = thresh; 447 448 /* Program FRAME_START trigger condition syncpt request */ 449 frame_start = VI_CSI_PP_FRAME_START(portnos[i]); 450 value = VI_CFG_VI_INCR_SYNCPT_COND(frame_start) | 451 host1x_syncpt_id(chan->frame_start_sp[i]); 452 tegra_vi_write(chan, TEGRA_VI_CFG_VI_INCR_SYNCPT, value); 453 454 /* increase channel syncpoint threshold for MW_ACK_DONE */ 455 thresh = host1x_syncpt_incr_max(chan->mw_ack_sp[i], 1); 456 buf->mw_ack_sp_thresh[i] = thresh; 457 458 /* Program MW_ACK_DONE trigger condition syncpt request */ 459 mw_ack_done = VI_CSI_MW_ACK_DONE(portnos[i]); 460 value = VI_CFG_VI_INCR_SYNCPT_COND(mw_ack_done) | 461 host1x_syncpt_id(chan->mw_ack_sp[i]); 462 tegra_vi_write(chan, TEGRA_VI_CFG_VI_INCR_SYNCPT, value); 463 } 464 465 /* enable single shot capture after all ganged ports are ready */ 466 for (i = 0; i < chan->numgangports; i++) 467 vi_csi_write(chan, portnos[i], TEGRA_VI_CSI_SINGLE_SHOT, 468 SINGLE_SHOT_CAPTURE); 469 470 for (i = 0; i < chan->numgangports; i++) { 471 /* 472 * Wait for syncpt counter to reach frame start event threshold 473 */ 474 err = host1x_syncpt_wait(chan->frame_start_sp[i], fs_thresh[i], 475 TEGRA_VI_SYNCPT_WAIT_TIMEOUT, &value); 476 if (err) { 477 capture_timedout = true; 478 /* increment syncpoint counter for timedout events */ 479 host1x_syncpt_incr(chan->frame_start_sp[i]); 480 spin_lock(&chan->sp_incr_lock[i]); 481 host1x_syncpt_incr(chan->mw_ack_sp[i]); 482 spin_unlock(&chan->sp_incr_lock[i]); 483 /* clear errors and recover */ 484 tegra_channel_capture_error_recover(chan, portnos[i]); 485 } 486 } 487 488 if (capture_timedout) { 489 dev_err_ratelimited(&chan->video.dev, 490 "frame start syncpt timeout: %d\n", err); 491 release_buffer(chan, buf, VB2_BUF_STATE_ERROR); 492 return err; 493 } 494 495 /* move buffer to capture done queue */ 496 spin_lock(&chan->done_lock); 497 list_add_tail(&buf->queue, &chan->done); 498 spin_unlock(&chan->done_lock); 499 500 /* wait up kthread for capture done */ 501 wake_up_interruptible(&chan->done_wait); 502 503 return 0; 504 } 505 506 static void tegra_channel_capture_done(struct tegra_vi_channel *chan, 507 struct tegra_channel_buffer *buf) 508 { 509 enum vb2_buffer_state state = VB2_BUF_STATE_DONE; 510 u32 value; 511 bool capture_timedout = false; 512 int ret, i; 513 514 for (i = 0; i < chan->numgangports; i++) { 515 /* 516 * Wait for syncpt counter to reach MW_ACK_DONE event threshold 517 */ 518 ret = host1x_syncpt_wait(chan->mw_ack_sp[i], 519 buf->mw_ack_sp_thresh[i], 520 TEGRA_VI_SYNCPT_WAIT_TIMEOUT, &value); 521 if (ret) { 522 capture_timedout = true; 523 state = VB2_BUF_STATE_ERROR; 524 /* increment syncpoint counter for timedout event */ 525 spin_lock(&chan->sp_incr_lock[i]); 526 host1x_syncpt_incr(chan->mw_ack_sp[i]); 527 spin_unlock(&chan->sp_incr_lock[i]); 528 } 529 } 530 531 if (capture_timedout) 532 dev_err_ratelimited(&chan->video.dev, 533 "MW_ACK_DONE syncpt timeout: %d\n", ret); 534 release_buffer(chan, buf, state); 535 } 536 537 static int chan_capture_kthread_start(void *data) 538 { 539 struct tegra_vi_channel *chan = data; 540 struct tegra_channel_buffer *buf; 541 unsigned int retries = 0; 542 int err = 0; 543 544 while (1) { 545 /* 546 * Source is not streaming if error is non-zero. 547 * So, do not dequeue buffers on error and let the thread sleep 548 * till kthread stop signal is received. 549 */ 550 wait_event_interruptible(chan->start_wait, 551 kthread_should_stop() || 552 (!list_empty(&chan->capture) && 553 !err)); 554 555 if (kthread_should_stop()) 556 break; 557 558 /* dequeue the buffer and start capture */ 559 spin_lock(&chan->start_lock); 560 if (list_empty(&chan->capture)) { 561 spin_unlock(&chan->start_lock); 562 continue; 563 } 564 565 buf = list_first_entry(&chan->capture, 566 struct tegra_channel_buffer, queue); 567 list_del_init(&buf->queue); 568 spin_unlock(&chan->start_lock); 569 570 err = tegra_channel_capture_frame(chan, buf); 571 if (!err) { 572 retries = 0; 573 continue; 574 } 575 576 if (retries++ > chan->syncpt_timeout_retry) 577 vb2_queue_error(&chan->queue); 578 else 579 err = 0; 580 } 581 582 return 0; 583 } 584 585 static int chan_capture_kthread_finish(void *data) 586 { 587 struct tegra_vi_channel *chan = data; 588 struct tegra_channel_buffer *buf; 589 590 while (1) { 591 wait_event_interruptible(chan->done_wait, 592 !list_empty(&chan->done) || 593 kthread_should_stop()); 594 595 /* dequeue buffers and finish capture */ 596 buf = dequeue_buf_done(chan); 597 while (buf) { 598 tegra_channel_capture_done(chan, buf); 599 buf = dequeue_buf_done(chan); 600 } 601 602 if (kthread_should_stop()) 603 break; 604 } 605 606 return 0; 607 } 608 609 static int tegra210_vi_start_streaming(struct vb2_queue *vq, u32 count) 610 { 611 struct tegra_vi_channel *chan = vb2_get_drv_priv(vq); 612 struct media_pipeline *pipe = &chan->video.pipe; 613 u32 val; 614 u8 *portnos = chan->portnos; 615 int ret, i; 616 617 tegra_vi_write(chan, TEGRA_VI_CFG_CG_CTRL, VI_CG_2ND_LEVEL_EN); 618 619 /* clear syncpt errors */ 620 val = tegra_vi_read(chan, TEGRA_VI_CFG_VI_INCR_SYNCPT_ERROR); 621 tegra_vi_write(chan, TEGRA_VI_CFG_VI_INCR_SYNCPT_ERROR, val); 622 623 /* 624 * Sync point FIFO full stalls the host interface. 625 * Setting NO_STALL will drop INCR_SYNCPT methods when fifos are 626 * full and the corresponding condition bits in INCR_SYNCPT_ERROR 627 * register will be set. 628 * This allows SW to process error recovery. 629 */ 630 tegra_vi_write(chan, TEGRA_VI_CFG_VI_INCR_SYNCPT_CNTRL, 631 VI_INCR_SYNCPT_NO_STALL); 632 633 /* start the pipeline */ 634 ret = video_device_pipeline_start(&chan->video, pipe); 635 if (ret < 0) 636 goto error_pipeline_start; 637 638 /* clear csi errors and do capture setup for all ports in gang mode */ 639 for (i = 0; i < chan->numgangports; i++) { 640 val = vi_csi_read(chan, portnos[i], TEGRA_VI_CSI_ERROR_STATUS); 641 vi_csi_write(chan, portnos[i], TEGRA_VI_CSI_ERROR_STATUS, val); 642 643 tegra_channel_capture_setup(chan, portnos[i]); 644 } 645 646 ret = tegra_channel_set_stream(chan, true); 647 if (ret < 0) 648 goto error_set_stream; 649 650 chan->sequence = 0; 651 652 /* start kthreads to capture data to buffer and return them */ 653 chan->kthread_start_capture = kthread_run(chan_capture_kthread_start, 654 chan, "%s:0", 655 chan->video.name); 656 if (IS_ERR(chan->kthread_start_capture)) { 657 ret = PTR_ERR(chan->kthread_start_capture); 658 chan->kthread_start_capture = NULL; 659 dev_err(&chan->video.dev, 660 "failed to run capture start kthread: %d\n", ret); 661 goto error_kthread_start; 662 } 663 664 chan->kthread_finish_capture = kthread_run(chan_capture_kthread_finish, 665 chan, "%s:1", 666 chan->video.name); 667 if (IS_ERR(chan->kthread_finish_capture)) { 668 ret = PTR_ERR(chan->kthread_finish_capture); 669 chan->kthread_finish_capture = NULL; 670 dev_err(&chan->video.dev, 671 "failed to run capture finish kthread: %d\n", ret); 672 goto error_kthread_done; 673 } 674 675 return 0; 676 677 error_kthread_done: 678 kthread_stop(chan->kthread_start_capture); 679 error_kthread_start: 680 tegra_channel_set_stream(chan, false); 681 error_set_stream: 682 video_device_pipeline_stop(&chan->video); 683 error_pipeline_start: 684 tegra_channel_release_buffers(chan, VB2_BUF_STATE_QUEUED); 685 return ret; 686 } 687 688 static void tegra210_vi_stop_streaming(struct vb2_queue *vq) 689 { 690 struct tegra_vi_channel *chan = vb2_get_drv_priv(vq); 691 692 if (chan->kthread_start_capture) { 693 kthread_stop(chan->kthread_start_capture); 694 chan->kthread_start_capture = NULL; 695 } 696 697 if (chan->kthread_finish_capture) { 698 kthread_stop(chan->kthread_finish_capture); 699 chan->kthread_finish_capture = NULL; 700 } 701 702 tegra_channel_release_buffers(chan, VB2_BUF_STATE_ERROR); 703 tegra_channel_set_stream(chan, false); 704 video_device_pipeline_stop(&chan->video); 705 } 706 707 /* 708 * Tegra210 VI Pixel memory format enum. 709 * These format enum value gets programmed into corresponding Tegra VI 710 * channel register bits. 711 */ 712 enum tegra210_image_format { 713 TEGRA210_IMAGE_FORMAT_T_L8 = 16, 714 715 TEGRA210_IMAGE_FORMAT_T_R16_I = 32, 716 TEGRA210_IMAGE_FORMAT_T_B5G6R5, 717 TEGRA210_IMAGE_FORMAT_T_R5G6B5, 718 TEGRA210_IMAGE_FORMAT_T_A1B5G5R5, 719 TEGRA210_IMAGE_FORMAT_T_A1R5G5B5, 720 TEGRA210_IMAGE_FORMAT_T_B5G5R5A1, 721 TEGRA210_IMAGE_FORMAT_T_R5G5B5A1, 722 TEGRA210_IMAGE_FORMAT_T_A4B4G4R4, 723 TEGRA210_IMAGE_FORMAT_T_A4R4G4B4, 724 TEGRA210_IMAGE_FORMAT_T_B4G4R4A4, 725 TEGRA210_IMAGE_FORMAT_T_R4G4B4A4, 726 727 TEGRA210_IMAGE_FORMAT_T_A8B8G8R8 = 64, 728 TEGRA210_IMAGE_FORMAT_T_A8R8G8B8, 729 TEGRA210_IMAGE_FORMAT_T_B8G8R8A8, 730 TEGRA210_IMAGE_FORMAT_T_R8G8B8A8, 731 TEGRA210_IMAGE_FORMAT_T_A2B10G10R10, 732 TEGRA210_IMAGE_FORMAT_T_A2R10G10B10, 733 TEGRA210_IMAGE_FORMAT_T_B10G10R10A2, 734 TEGRA210_IMAGE_FORMAT_T_R10G10B10A2, 735 736 TEGRA210_IMAGE_FORMAT_T_A8Y8U8V8 = 193, 737 TEGRA210_IMAGE_FORMAT_T_V8U8Y8A8, 738 739 TEGRA210_IMAGE_FORMAT_T_A2Y10U10V10 = 197, 740 TEGRA210_IMAGE_FORMAT_T_V10U10Y10A2, 741 TEGRA210_IMAGE_FORMAT_T_Y8_U8__Y8_V8, 742 TEGRA210_IMAGE_FORMAT_T_Y8_V8__Y8_U8, 743 TEGRA210_IMAGE_FORMAT_T_U8_Y8__V8_Y8, 744 TEGRA210_IMAGE_FORMAT_T_V8_Y8__U8_Y8, 745 746 TEGRA210_IMAGE_FORMAT_T_Y8__U8__V8_N444 = 224, 747 TEGRA210_IMAGE_FORMAT_T_Y8__U8V8_N444, 748 TEGRA210_IMAGE_FORMAT_T_Y8__V8U8_N444, 749 TEGRA210_IMAGE_FORMAT_T_Y8__U8__V8_N422, 750 TEGRA210_IMAGE_FORMAT_T_Y8__U8V8_N422, 751 TEGRA210_IMAGE_FORMAT_T_Y8__V8U8_N422, 752 TEGRA210_IMAGE_FORMAT_T_Y8__U8__V8_N420, 753 TEGRA210_IMAGE_FORMAT_T_Y8__U8V8_N420, 754 TEGRA210_IMAGE_FORMAT_T_Y8__V8U8_N420, 755 TEGRA210_IMAGE_FORMAT_T_X2LC10LB10LA10, 756 TEGRA210_IMAGE_FORMAT_T_A2R6R6R6R6R6, 757 }; 758 759 #define TEGRA210_VIDEO_FMT(DATA_TYPE, BIT_WIDTH, MBUS_CODE, BPP, \ 760 FORMAT, FOURCC) \ 761 { \ 762 TEGRA_IMAGE_DT_##DATA_TYPE, \ 763 BIT_WIDTH, \ 764 MEDIA_BUS_FMT_##MBUS_CODE, \ 765 BPP, \ 766 TEGRA210_IMAGE_FORMAT_##FORMAT, \ 767 V4L2_PIX_FMT_##FOURCC, \ 768 } 769 770 /* Tegra210 supported video formats */ 771 static const struct tegra_video_format tegra210_video_formats[] = { 772 /* RAW 8 */ 773 TEGRA210_VIDEO_FMT(RAW8, 8, SRGGB8_1X8, 1, T_L8, SRGGB8), 774 TEGRA210_VIDEO_FMT(RAW8, 8, SGRBG8_1X8, 1, T_L8, SGRBG8), 775 TEGRA210_VIDEO_FMT(RAW8, 8, SGBRG8_1X8, 1, T_L8, SGBRG8), 776 TEGRA210_VIDEO_FMT(RAW8, 8, SBGGR8_1X8, 1, T_L8, SBGGR8), 777 /* RAW 10 */ 778 TEGRA210_VIDEO_FMT(RAW10, 10, SRGGB10_1X10, 2, T_R16_I, SRGGB10), 779 TEGRA210_VIDEO_FMT(RAW10, 10, SGRBG10_1X10, 2, T_R16_I, SGRBG10), 780 TEGRA210_VIDEO_FMT(RAW10, 10, SGBRG10_1X10, 2, T_R16_I, SGBRG10), 781 TEGRA210_VIDEO_FMT(RAW10, 10, SBGGR10_1X10, 2, T_R16_I, SBGGR10), 782 /* RAW 12 */ 783 TEGRA210_VIDEO_FMT(RAW12, 12, SRGGB12_1X12, 2, T_R16_I, SRGGB12), 784 TEGRA210_VIDEO_FMT(RAW12, 12, SGRBG12_1X12, 2, T_R16_I, SGRBG12), 785 TEGRA210_VIDEO_FMT(RAW12, 12, SGBRG12_1X12, 2, T_R16_I, SGBRG12), 786 TEGRA210_VIDEO_FMT(RAW12, 12, SBGGR12_1X12, 2, T_R16_I, SBGGR12), 787 /* RGB888 */ 788 TEGRA210_VIDEO_FMT(RGB888, 24, RGB888_1X24, 4, T_A8R8G8B8, XBGR32), 789 TEGRA210_VIDEO_FMT(RGB888, 24, RGB888_1X32_PADHI, 4, T_A8B8G8R8, 790 RGBX32), 791 /* YUV422 */ 792 TEGRA210_VIDEO_FMT(YUV422_8, 16, UYVY8_1X16, 2, T_U8_Y8__V8_Y8, YVYU), 793 TEGRA210_VIDEO_FMT(YUV422_8, 16, VYUY8_1X16, 2, T_V8_Y8__U8_Y8, YUYV), 794 TEGRA210_VIDEO_FMT(YUV422_8, 16, YUYV8_1X16, 2, T_Y8_U8__Y8_V8, VYUY), 795 TEGRA210_VIDEO_FMT(YUV422_8, 16, YVYU8_1X16, 2, T_Y8_V8__Y8_U8, UYVY), 796 TEGRA210_VIDEO_FMT(YUV422_8, 16, UYVY8_1X16, 1, T_Y8__V8U8_N422, NV16), 797 TEGRA210_VIDEO_FMT(YUV422_8, 16, UYVY8_2X8, 2, T_U8_Y8__V8_Y8, YVYU), 798 TEGRA210_VIDEO_FMT(YUV422_8, 16, VYUY8_2X8, 2, T_V8_Y8__U8_Y8, YUYV), 799 TEGRA210_VIDEO_FMT(YUV422_8, 16, YUYV8_2X8, 2, T_Y8_U8__Y8_V8, VYUY), 800 TEGRA210_VIDEO_FMT(YUV422_8, 16, YVYU8_2X8, 2, T_Y8_V8__Y8_U8, UYVY), 801 }; 802 803 /* Tegra210 VI operations */ 804 static const struct tegra_vi_ops tegra210_vi_ops = { 805 .channel_host1x_syncpt_init = tegra210_channel_host1x_syncpt_init, 806 .channel_host1x_syncpt_free = tegra210_channel_host1x_syncpt_free, 807 .vi_fmt_align = tegra210_fmt_align, 808 .vi_start_streaming = tegra210_vi_start_streaming, 809 .vi_stop_streaming = tegra210_vi_stop_streaming, 810 }; 811 812 /* Tegra210 VI SoC data */ 813 const struct tegra_vi_soc tegra210_vi_soc = { 814 .video_formats = tegra210_video_formats, 815 .nformats = ARRAY_SIZE(tegra210_video_formats), 816 .ops = &tegra210_vi_ops, 817 .hw_revision = 3, 818 .vi_max_channels = 6, 819 #if IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG) 820 .default_video_format = &tegra210_video_formats[0], 821 .vi_max_clk_hz = 499200000, 822 #else 823 .default_video_format = &tegra210_video_formats[4], 824 .vi_max_clk_hz = 998400000, 825 #endif 826 }; 827 828 /* Tegra210 CSI PHY registers accessors */ 829 static void csi_write(struct tegra_csi *csi, u8 portno, unsigned int addr, 830 u32 val) 831 { 832 void __iomem *csi_pp_base; 833 834 csi_pp_base = csi->iomem + CSI_PP_OFFSET(portno >> 1); 835 836 writel_relaxed(val, csi_pp_base + addr); 837 } 838 839 /* Tegra210 CSI Pixel parser registers accessors */ 840 static void pp_write(struct tegra_csi *csi, u8 portno, u32 addr, u32 val) 841 { 842 void __iomem *csi_pp_base; 843 unsigned int offset; 844 845 csi_pp_base = csi->iomem + CSI_PP_OFFSET(portno >> 1); 846 offset = (portno % CSI_PORTS_PER_BRICK) * TEGRA210_CSI_PORT_OFFSET; 847 848 writel_relaxed(val, csi_pp_base + offset + addr); 849 } 850 851 static u32 pp_read(struct tegra_csi *csi, u8 portno, u32 addr) 852 { 853 void __iomem *csi_pp_base; 854 unsigned int offset; 855 856 csi_pp_base = csi->iomem + CSI_PP_OFFSET(portno >> 1); 857 offset = (portno % CSI_PORTS_PER_BRICK) * TEGRA210_CSI_PORT_OFFSET; 858 859 return readl_relaxed(csi_pp_base + offset + addr); 860 } 861 862 /* Tegra210 CSI CIL A/B port registers accessors */ 863 static void cil_write(struct tegra_csi *csi, u8 portno, u32 addr, u32 val) 864 { 865 void __iomem *csi_cil_base; 866 unsigned int offset; 867 868 csi_cil_base = csi->iomem + CSI_PP_OFFSET(portno >> 1) + 869 TEGRA210_CSI_CIL_OFFSET; 870 offset = (portno % CSI_PORTS_PER_BRICK) * TEGRA210_CSI_PORT_OFFSET; 871 872 writel_relaxed(val, csi_cil_base + offset + addr); 873 } 874 875 static u32 cil_read(struct tegra_csi *csi, u8 portno, u32 addr) 876 { 877 void __iomem *csi_cil_base; 878 unsigned int offset; 879 880 csi_cil_base = csi->iomem + CSI_PP_OFFSET(portno >> 1) + 881 TEGRA210_CSI_CIL_OFFSET; 882 offset = (portno % CSI_PORTS_PER_BRICK) * TEGRA210_CSI_PORT_OFFSET; 883 884 return readl_relaxed(csi_cil_base + offset + addr); 885 } 886 887 /* Tegra210 CSI Test pattern generator registers accessor */ 888 static void tpg_write(struct tegra_csi *csi, u8 portno, unsigned int addr, 889 u32 val) 890 { 891 void __iomem *csi_pp_base; 892 unsigned int offset; 893 894 csi_pp_base = csi->iomem + CSI_PP_OFFSET(portno >> 1); 895 offset = (portno % CSI_PORTS_PER_BRICK) * TEGRA210_CSI_PORT_OFFSET + 896 TEGRA210_CSI_TPG_OFFSET; 897 898 writel_relaxed(val, csi_pp_base + offset + addr); 899 } 900 901 /* 902 * Tegra210 CSI operations 903 */ 904 static void tegra210_csi_port_recover(struct tegra_csi_channel *csi_chan, 905 u8 portno) 906 { 907 struct tegra_csi *csi = csi_chan->csi; 908 u32 val; 909 910 /* 911 * Recover CSI hardware in case of capture errors by issuing 912 * software reset to CSICIL sensor, pixel parser, and clear errors 913 * to have clean capture on next streaming. 914 */ 915 val = pp_read(csi, portno, TEGRA_CSI_PIXEL_PARSER_STATUS); 916 dev_dbg(csi->dev, "TEGRA_CSI_PIXEL_PARSER_STATUS 0x%08x\n", val); 917 918 val = cil_read(csi, portno, TEGRA_CSI_CIL_STATUS); 919 dev_dbg(csi->dev, "TEGRA_CSI_CIL_STATUS 0x%08x\n", val); 920 921 val = cil_read(csi, portno, TEGRA_CSI_CILX_STATUS); 922 dev_dbg(csi->dev, "TEGRA_CSI_CILX_STATUS 0x%08x\n", val); 923 924 if (csi_chan->numlanes == 4) { 925 /* reset CSI CIL sensor */ 926 cil_write(csi, portno, TEGRA_CSI_CIL_SW_SENSOR_RESET, 0x1); 927 cil_write(csi, portno + 1, TEGRA_CSI_CIL_SW_SENSOR_RESET, 0x1); 928 /* 929 * SW_STATUS_RESET resets all status bits of PPA, PPB, CILA, 930 * CILB status registers and debug counters. 931 * So, SW_STATUS_RESET can be used only when CSI brick is in 932 * x4 mode. 933 */ 934 csi_write(csi, portno, TEGRA_CSI_CSI_SW_STATUS_RESET, 0x1); 935 936 /* sleep for 20 clock cycles to drain the FIFO */ 937 usleep_range(10, 20); 938 939 cil_write(csi, portno + 1, TEGRA_CSI_CIL_SW_SENSOR_RESET, 0x0); 940 cil_write(csi, portno, TEGRA_CSI_CIL_SW_SENSOR_RESET, 0x0); 941 csi_write(csi, portno, TEGRA_CSI_CSI_SW_STATUS_RESET, 0x0); 942 } else { 943 /* reset CSICIL sensor */ 944 cil_write(csi, portno, TEGRA_CSI_CIL_SW_SENSOR_RESET, 0x1); 945 usleep_range(10, 20); 946 cil_write(csi, portno, TEGRA_CSI_CIL_SW_SENSOR_RESET, 0x0); 947 948 /* clear the errors */ 949 pp_write(csi, portno, TEGRA_CSI_PIXEL_PARSER_STATUS, 950 0xffffffff); 951 cil_write(csi, portno, TEGRA_CSI_CIL_STATUS, 0xffffffff); 952 cil_write(csi, portno, TEGRA_CSI_CILX_STATUS, 0xffffffff); 953 } 954 } 955 956 static void tegra210_csi_error_recover(struct tegra_csi_channel *csi_chan) 957 { 958 u8 *portnos = csi_chan->csi_port_nums; 959 int i; 960 961 for (i = 0; i < csi_chan->numgangports; i++) 962 tegra210_csi_port_recover(csi_chan, portnos[i]); 963 } 964 965 static int 966 tegra210_csi_port_start_streaming(struct tegra_csi_channel *csi_chan, 967 u8 portno) 968 { 969 struct tegra_csi *csi = csi_chan->csi; 970 u8 clk_settle_time = 0; 971 u8 ths_settle_time = 10; 972 u32 val; 973 974 if (!csi_chan->pg_mode) 975 tegra_csi_calc_settle_time(csi_chan, portno, &clk_settle_time, 976 &ths_settle_time); 977 978 csi_write(csi, portno, TEGRA_CSI_CLKEN_OVERRIDE, 0); 979 980 /* clean up status */ 981 pp_write(csi, portno, TEGRA_CSI_PIXEL_PARSER_STATUS, 0xffffffff); 982 cil_write(csi, portno, TEGRA_CSI_CIL_STATUS, 0xffffffff); 983 cil_write(csi, portno, TEGRA_CSI_CILX_STATUS, 0xffffffff); 984 cil_write(csi, portno, TEGRA_CSI_CIL_INTERRUPT_MASK, 0x0); 985 986 /* CIL PHY registers setup */ 987 cil_write(csi, portno, TEGRA_CSI_CIL_PAD_CONFIG0, 0x0); 988 cil_write(csi, portno, TEGRA_CSI_CIL_PHY_CONTROL, 989 FIELD_PREP(CLK_SETTLE_MASK, clk_settle_time) | 990 FIELD_PREP(THS_SETTLE_MASK, ths_settle_time)); 991 992 /* 993 * The CSI unit provides for connection of up to six cameras in 994 * the system and is organized as three identical instances of 995 * two MIPI support blocks, each with a separate 4-lane 996 * interface that can be configured as a single camera with 4 997 * lanes or as a dual camera with 2 lanes available for each 998 * camera. 999 */ 1000 if (csi_chan->numlanes == 4) { 1001 cil_write(csi, portno + 1, TEGRA_CSI_CIL_STATUS, 0xffffffff); 1002 cil_write(csi, portno + 1, TEGRA_CSI_CILX_STATUS, 0xffffffff); 1003 cil_write(csi, portno + 1, TEGRA_CSI_CIL_INTERRUPT_MASK, 0x0); 1004 1005 cil_write(csi, portno, TEGRA_CSI_CIL_PAD_CONFIG0, 1006 BRICK_CLOCK_A_4X); 1007 cil_write(csi, portno + 1, TEGRA_CSI_CIL_PAD_CONFIG0, 0x0); 1008 cil_write(csi, portno + 1, TEGRA_CSI_CIL_INTERRUPT_MASK, 0x0); 1009 cil_write(csi, portno + 1, TEGRA_CSI_CIL_PHY_CONTROL, 1010 FIELD_PREP(CLK_SETTLE_MASK, clk_settle_time) | 1011 FIELD_PREP(THS_SETTLE_MASK, ths_settle_time)); 1012 csi_write(csi, portno, TEGRA_CSI_PHY_CIL_COMMAND, 1013 CSI_A_PHY_CIL_ENABLE | CSI_B_PHY_CIL_ENABLE); 1014 } else { 1015 val = ((portno & 1) == PORT_A) ? 1016 CSI_A_PHY_CIL_ENABLE | CSI_B_PHY_CIL_NOP : 1017 CSI_B_PHY_CIL_ENABLE | CSI_A_PHY_CIL_NOP; 1018 csi_write(csi, portno, TEGRA_CSI_PHY_CIL_COMMAND, val); 1019 } 1020 1021 /* CSI pixel parser registers setup */ 1022 pp_write(csi, portno, TEGRA_CSI_PIXEL_STREAM_PP_COMMAND, 1023 (0xf << CSI_PP_START_MARKER_FRAME_MAX_OFFSET) | 1024 CSI_PP_SINGLE_SHOT_ENABLE | CSI_PP_RST); 1025 pp_write(csi, portno, TEGRA_CSI_PIXEL_PARSER_INTERRUPT_MASK, 0x0); 1026 pp_write(csi, portno, TEGRA_CSI_PIXEL_STREAM_CONTROL0, 1027 CSI_PP_PACKET_HEADER_SENT | 1028 CSI_PP_DATA_IDENTIFIER_ENABLE | 1029 CSI_PP_WORD_COUNT_SELECT_HEADER | 1030 CSI_PP_CRC_CHECK_ENABLE | CSI_PP_WC_CHECK | 1031 CSI_PP_OUTPUT_FORMAT_STORE | CSI_PPA_PAD_LINE_NOPAD | 1032 CSI_PP_HEADER_EC_DISABLE | CSI_PPA_PAD_FRAME_NOPAD | 1033 (portno & 1)); 1034 pp_write(csi, portno, TEGRA_CSI_PIXEL_STREAM_CONTROL1, 1035 (0x1 << CSI_PP_TOP_FIELD_FRAME_OFFSET) | 1036 (0x1 << CSI_PP_TOP_FIELD_FRAME_MASK_OFFSET)); 1037 pp_write(csi, portno, TEGRA_CSI_PIXEL_STREAM_GAP, 1038 0x14 << PP_FRAME_MIN_GAP_OFFSET); 1039 pp_write(csi, portno, TEGRA_CSI_PIXEL_STREAM_EXPECTED_FRAME, 0x0); 1040 pp_write(csi, portno, TEGRA_CSI_INPUT_STREAM_CONTROL, 1041 (0x3f << CSI_SKIP_PACKET_THRESHOLD_OFFSET) | 1042 (csi_chan->numlanes - 1)); 1043 1044 /* TPG setup */ 1045 if (csi_chan->pg_mode) { 1046 tpg_write(csi, portno, TEGRA_CSI_PATTERN_GENERATOR_CTRL, 1047 ((csi_chan->pg_mode - 1) << PG_MODE_OFFSET) | 1048 PG_ENABLE); 1049 tpg_write(csi, portno, TEGRA_CSI_PG_BLANK, 1050 csi_chan->v_blank << PG_VBLANK_OFFSET | 1051 csi_chan->h_blank); 1052 tpg_write(csi, portno, TEGRA_CSI_PG_PHASE, 0x0); 1053 tpg_write(csi, portno, TEGRA_CSI_PG_RED_FREQ, 1054 (0x10 << PG_RED_VERT_INIT_FREQ_OFFSET) | 1055 (0x10 << PG_RED_HOR_INIT_FREQ_OFFSET)); 1056 tpg_write(csi, portno, TEGRA_CSI_PG_RED_FREQ_RATE, 0x0); 1057 tpg_write(csi, portno, TEGRA_CSI_PG_GREEN_FREQ, 1058 (0x10 << PG_GREEN_VERT_INIT_FREQ_OFFSET) | 1059 (0x10 << PG_GREEN_HOR_INIT_FREQ_OFFSET)); 1060 tpg_write(csi, portno, TEGRA_CSI_PG_GREEN_FREQ_RATE, 0x0); 1061 tpg_write(csi, portno, TEGRA_CSI_PG_BLUE_FREQ, 1062 (0x10 << PG_BLUE_VERT_INIT_FREQ_OFFSET) | 1063 (0x10 << PG_BLUE_HOR_INIT_FREQ_OFFSET)); 1064 tpg_write(csi, portno, TEGRA_CSI_PG_BLUE_FREQ_RATE, 0x0); 1065 } 1066 1067 pp_write(csi, portno, TEGRA_CSI_PIXEL_STREAM_PP_COMMAND, 1068 (0xf << CSI_PP_START_MARKER_FRAME_MAX_OFFSET) | 1069 CSI_PP_SINGLE_SHOT_ENABLE | CSI_PP_ENABLE); 1070 1071 return 0; 1072 } 1073 1074 static void 1075 tegra210_csi_port_stop_streaming(struct tegra_csi_channel *csi_chan, u8 portno) 1076 { 1077 struct tegra_csi *csi = csi_chan->csi; 1078 u32 val; 1079 1080 val = pp_read(csi, portno, TEGRA_CSI_PIXEL_PARSER_STATUS); 1081 1082 dev_dbg(csi->dev, "TEGRA_CSI_PIXEL_PARSER_STATUS 0x%08x\n", val); 1083 pp_write(csi, portno, TEGRA_CSI_PIXEL_PARSER_STATUS, val); 1084 1085 val = cil_read(csi, portno, TEGRA_CSI_CIL_STATUS); 1086 dev_dbg(csi->dev, "TEGRA_CSI_CIL_STATUS 0x%08x\n", val); 1087 cil_write(csi, portno, TEGRA_CSI_CIL_STATUS, val); 1088 1089 val = cil_read(csi, portno, TEGRA_CSI_CILX_STATUS); 1090 dev_dbg(csi->dev, "TEGRA_CSI_CILX_STATUS 0x%08x\n", val); 1091 cil_write(csi, portno, TEGRA_CSI_CILX_STATUS, val); 1092 1093 pp_write(csi, portno, TEGRA_CSI_PIXEL_STREAM_PP_COMMAND, 1094 (0xf << CSI_PP_START_MARKER_FRAME_MAX_OFFSET) | 1095 CSI_PP_DISABLE); 1096 1097 if (csi_chan->pg_mode) { 1098 tpg_write(csi, portno, TEGRA_CSI_PATTERN_GENERATOR_CTRL, 1099 PG_DISABLE); 1100 return; 1101 } 1102 1103 if (csi_chan->numlanes == 4) { 1104 csi_write(csi, portno, TEGRA_CSI_PHY_CIL_COMMAND, 1105 CSI_A_PHY_CIL_DISABLE | 1106 CSI_B_PHY_CIL_DISABLE); 1107 } else { 1108 val = ((portno & 1) == PORT_A) ? 1109 CSI_A_PHY_CIL_DISABLE | CSI_B_PHY_CIL_NOP : 1110 CSI_B_PHY_CIL_DISABLE | CSI_A_PHY_CIL_NOP; 1111 csi_write(csi, portno, TEGRA_CSI_PHY_CIL_COMMAND, val); 1112 } 1113 } 1114 1115 static int tegra210_csi_start_streaming(struct tegra_csi_channel *csi_chan) 1116 { 1117 u8 *portnos = csi_chan->csi_port_nums; 1118 int ret, i; 1119 1120 for (i = 0; i < csi_chan->numgangports; i++) { 1121 ret = tegra210_csi_port_start_streaming(csi_chan, portnos[i]); 1122 if (ret) 1123 goto stream_start_fail; 1124 } 1125 1126 return 0; 1127 1128 stream_start_fail: 1129 for (i = i - 1; i >= 0; i--) 1130 tegra210_csi_port_stop_streaming(csi_chan, portnos[i]); 1131 1132 return ret; 1133 } 1134 1135 static void tegra210_csi_stop_streaming(struct tegra_csi_channel *csi_chan) 1136 { 1137 u8 *portnos = csi_chan->csi_port_nums; 1138 int i; 1139 1140 for (i = 0; i < csi_chan->numgangports; i++) 1141 tegra210_csi_port_stop_streaming(csi_chan, portnos[i]); 1142 } 1143 1144 /* 1145 * Tegra210 CSI TPG frame rate table with horizontal and vertical 1146 * blanking intervals for corresponding format and resolution. 1147 * Blanking intervals are tuned values from design team for max TPG 1148 * clock rate. 1149 */ 1150 static const struct tpg_framerate tegra210_tpg_frmrate_table[] = { 1151 { 1152 .frmsize = { 1280, 720 }, 1153 .code = MEDIA_BUS_FMT_SRGGB10_1X10, 1154 .framerate = 120, 1155 .h_blank = 512, 1156 .v_blank = 8, 1157 }, 1158 { 1159 .frmsize = { 1920, 1080 }, 1160 .code = MEDIA_BUS_FMT_SRGGB10_1X10, 1161 .framerate = 60, 1162 .h_blank = 512, 1163 .v_blank = 8, 1164 }, 1165 { 1166 .frmsize = { 3840, 2160 }, 1167 .code = MEDIA_BUS_FMT_SRGGB10_1X10, 1168 .framerate = 20, 1169 .h_blank = 8, 1170 .v_blank = 8, 1171 }, 1172 { 1173 .frmsize = { 1280, 720 }, 1174 .code = MEDIA_BUS_FMT_RGB888_1X32_PADHI, 1175 .framerate = 60, 1176 .h_blank = 512, 1177 .v_blank = 8, 1178 }, 1179 { 1180 .frmsize = { 1920, 1080 }, 1181 .code = MEDIA_BUS_FMT_RGB888_1X32_PADHI, 1182 .framerate = 30, 1183 .h_blank = 512, 1184 .v_blank = 8, 1185 }, 1186 { 1187 .frmsize = { 3840, 2160 }, 1188 .code = MEDIA_BUS_FMT_RGB888_1X32_PADHI, 1189 .framerate = 8, 1190 .h_blank = 8, 1191 .v_blank = 8, 1192 }, 1193 }; 1194 1195 static const char * const tegra210_csi_cil_clks[] = { 1196 "csi", 1197 "cilab", 1198 "cilcd", 1199 "cile", 1200 #if IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG) 1201 "csi_tpg", 1202 #endif 1203 }; 1204 1205 /* Tegra210 CSI operations */ 1206 static const struct tegra_csi_ops tegra210_csi_ops = { 1207 .csi_start_streaming = tegra210_csi_start_streaming, 1208 .csi_stop_streaming = tegra210_csi_stop_streaming, 1209 .csi_err_recover = tegra210_csi_error_recover, 1210 }; 1211 1212 /* Tegra210 CSI SoC data */ 1213 const struct tegra_csi_soc tegra210_csi_soc = { 1214 .ops = &tegra210_csi_ops, 1215 .csi_max_channels = 6, 1216 .clk_names = tegra210_csi_cil_clks, 1217 .num_clks = ARRAY_SIZE(tegra210_csi_cil_clks), 1218 .tpg_frmrate_table = tegra210_tpg_frmrate_table, 1219 .tpg_frmrate_table_size = ARRAY_SIZE(tegra210_tpg_frmrate_table), 1220 }; 1221