1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 /* 7 * CMN PLL block expects the reference clock from on-board Wi-Fi block, 8 * and supplies fixed rate clocks as output to the networking hardware 9 * blocks and to GCC. The networking related blocks include PPE (packet 10 * process engine), the externally connected PHY or switch devices, and 11 * the PCS. 12 * 13 * On the IPQ9574 SoC, there are three clocks with 50 MHZ and one clock 14 * with 25 MHZ which are output from the CMN PLL to Ethernet PHY (or switch), 15 * and one clock with 353 MHZ to PPE. The other fixed rate output clocks 16 * are supplied to GCC (24 MHZ as XO and 32 KHZ as sleep clock), and to PCS 17 * with 31.25 MHZ. 18 * 19 * On the IPQ5424 SoC, there is an output clock from CMN PLL to PPE at 375 MHZ, 20 * and an output clock to NSS (network subsystem) at 300 MHZ. The other output 21 * clocks from CMN PLL on IPQ5424 are the same as IPQ9574. 22 * 23 * On the IPQ5332 SoC, the CMN PLL provides a single 50 MHZ clock output to 24 * the Ethernet PHY (or switch) via the UNIPHY (PCS). It also supplies a 200 25 * MHZ clock to the PPE. The remaining fixed-rate clocks to the GCC and PCS 26 * are the same as those in the IPQ9574 SoC. 27 * 28 * +---------+ 29 * | GCC | 30 * +--+---+--+ 31 * AHB CLK| |SYS CLK 32 * V V 33 * +-------+---+------+ 34 * | +-------------> eth0-50mhz 35 * REF CLK | IPQ9574 | 36 * -------->+ +-------------> eth1-50mhz 37 * | CMN PLL block | 38 * | +-------------> eth2-50mhz 39 * | | 40 * +----+----+----+---+-------------> eth-25mhz 41 * | | | 42 * V V V 43 * GCC PCS NSS/PPE 44 */ 45 46 #include <linux/bitfield.h> 47 #include <linux/bitops.h> 48 #include <linux/clk-provider.h> 49 #include <linux/delay.h> 50 #include <linux/err.h> 51 #include <linux/module.h> 52 #include <linux/platform_device.h> 53 #include <linux/pm_clock.h> 54 #include <linux/pm_runtime.h> 55 #include <linux/regmap.h> 56 57 #include <dt-bindings/clock/qcom,ipq-cmn-pll.h> 58 #include <dt-bindings/clock/qcom,ipq5018-cmn-pll.h> 59 #include <dt-bindings/clock/qcom,ipq5210-cmn-pll.h> 60 #include <dt-bindings/clock/qcom,ipq5332-cmn-pll.h> 61 #include <dt-bindings/clock/qcom,ipq5424-cmn-pll.h> 62 #include <dt-bindings/clock/qcom,ipq6018-cmn-pll.h> 63 #include <dt-bindings/clock/qcom,ipq8074-cmn-pll.h> 64 65 #include "clk-regmap.h" 66 #include "clk-regmap-divider.h" 67 68 #define CMN_PLL_REFCLK_SRC_SELECTION 0x28 69 #define CMN_PLL_REFCLK_SRC_DIV GENMASK(9, 8) 70 71 #define CMN_PLL_LOCKED 0x64 72 #define CMN_PLL_CLKS_LOCKED BIT(8) 73 74 #define CMN_PLL_NSS_PPE_FREQ_CTRL 0x98 75 #define CMN_PLL_NSS_CLK_SEL GENMASK(13, 8) 76 #define CMN_PLL_PPE_CLK_SEL GENMASK(5, 0) 77 78 #define CMN_PLL_PON_CONFIG 0x42c 79 #define CMN_PLL_PON_MODE_SEL BIT(9) 80 #define CMN_PLL_PON_EN BIT(8) 81 #define CMN_PLL_PON_DIV_CTRL GENMASK(7, 0) 82 #define CMN_PLL_GEPHY_312P5M_125M_SEL BIT(10) 83 84 #define CMN_PLL_POWER_ON_AND_RESET 0x780 85 #define CMN_ANA_EN_SW_RSTN BIT(6) 86 87 #define CMN_PLL_REFCLK_CONFIG 0x784 88 #define CMN_PLL_REFCLK_EXTERNAL BIT(9) 89 #define CMN_PLL_REFCLK_DIV GENMASK(8, 4) 90 #define CMN_PLL_REFCLK_INDEX GENMASK(3, 0) 91 92 #define CMN_PLL_CTRL 0x78c 93 #define CMN_PLL_CTRL_LOCK_DETECT_EN BIT(15) 94 95 #define CMN_PLL_DIVIDER_CTRL 0x794 96 #define CMN_PLL_DIVIDER_CTRL_FACTOR GENMASK(9, 0) 97 98 /* Clock gate enable bits. */ 99 #define CMN_PLL_OUTPUT_RELATED_1 0x79c 100 #define CLK25M_EN_BIT 15 101 #define CLK50M_EN_BIT3 14 102 /* Documented as CLK250M_EN in the register description; gates ephy-50mhz. */ 103 #define CLK250M_EN_BIT 13 104 #define CLK31P25M_EN_BIT 12 105 #define CLK50M_EN_BIT1 11 106 #define CLK50M_EN_BIT2 10 107 108 /** 109 * enum cmn_pll_clk_type - CMN PLL output clock registration type 110 * @CMN_PLL_CLK_FIXED_RATE: plain fixed rate clock 111 * @CMN_PLL_CLK_FIXED_GATE: fixed rate clock with a hardware gate 112 * @CMN_PLL_CLK_NSS: NSS clock with configurable divider 113 * @CMN_PLL_CLK_PPE: PPE clock with configurable divider 114 * @CMN_PLL_CLK_PON: PON reference clock 115 * @CMN_PLL_CLK_EPHY_RAW: EPHY-RAW clock 116 */ 117 enum cmn_pll_clk_type { 118 CMN_PLL_CLK_FIXED_RATE, 119 CMN_PLL_CLK_FIXED_GATE, 120 CMN_PLL_CLK_NSS, 121 CMN_PLL_CLK_PPE, 122 CMN_PLL_CLK_PON, 123 CMN_PLL_CLK_EPHY_RAW, 124 }; 125 126 /** 127 * struct cmn_pll_fixed_output_clk - CMN PLL output clocks information 128 * @id: Clock specifier to be supplied 129 * @name: Clock name to be registered 130 * @type: Clock registration type 131 * @rate: Clock rate 132 * @enable_bit: Enable bit in CMN_PLL_OUTPUT_RELATED_1 for gate clock, 133 * -1 for non-gated clocks. 134 */ 135 struct cmn_pll_fixed_output_clk { 136 unsigned int id; 137 const char *name; 138 enum cmn_pll_clk_type type; 139 unsigned long rate; 140 int enable_bit; 141 }; 142 143 /** 144 * struct clk_cmn_pll - CMN PLL hardware specific data 145 * @regmap: hardware regmap. 146 * @hw: handle between common and hardware-specific interfaces 147 * @div2_hw: fixed /2 clock derived from the CMN PLL output; present on 148 * every supported SoC. 149 */ 150 struct clk_cmn_pll { 151 struct regmap *regmap; 152 struct clk_hw hw; 153 struct clk_hw *div2_hw; 154 }; 155 156 /** 157 * struct clk_fixed_gate - fixed rate clock with a hardware gate 158 * @clkr: handle between common and hardware-specific interfaces; its 159 * enable_reg/enable_mask are set to CMN_PLL_OUTPUT_RELATED_1 and 160 * this clock's gate bit, and reused via clk_enable_regmap() and 161 * friends. That register is shared across multiple gate clocks, 162 * but regmap already serializes read-modify-write access to a 163 * given register, so no additional locking is needed here. 164 * @rate: fixed clock rate. 165 */ 166 struct clk_fixed_gate { 167 struct clk_regmap clkr; 168 unsigned long rate; 169 }; 170 171 #define CLK_PLL_OUTPUT_RAW(_id, _name, _type, _rate, _bit) { \ 172 .id = _id, \ 173 .name = _name, \ 174 .type = _type, \ 175 .rate = _rate, \ 176 .enable_bit = _bit, \ 177 } 178 179 #define CLK_PLL_OUTPUT(_id, _name, _rate) \ 180 CLK_PLL_OUTPUT_RAW(_id, _name, CMN_PLL_CLK_FIXED_RATE, _rate, -1) 181 182 #define CLK_PLL_GATE(_id, _name, _rate, _bit) \ 183 CLK_PLL_OUTPUT_RAW(_id, _name, CMN_PLL_CLK_FIXED_GATE, _rate, _bit) 184 185 #define CLK_PLL_NSS(_id, _name) \ 186 CLK_PLL_OUTPUT_RAW(_id, _name, CMN_PLL_CLK_NSS, 0, -1) 187 188 #define CLK_PLL_PPE(_id, _name) \ 189 CLK_PLL_OUTPUT_RAW(_id, _name, CMN_PLL_CLK_PPE, 0, -1) 190 191 #define CLK_PLL_PON(_id, _name) \ 192 CLK_PLL_OUTPUT_RAW(_id, _name, CMN_PLL_CLK_PON, 0, -1) 193 194 #define CLK_PLL_EPHY_RAW(_id, _name) \ 195 CLK_PLL_OUTPUT_RAW(_id, _name, CMN_PLL_CLK_EPHY_RAW, 0, -1) 196 197 #define to_clk_cmn_pll(_hw) container_of(_hw, struct clk_cmn_pll, hw) 198 199 #define to_clk_fixed_gate(_hw) \ 200 container_of(to_clk_regmap(_hw), struct clk_fixed_gate, clkr) 201 202 static const struct regmap_config ipq_cmn_pll_regmap_config = { 203 .reg_bits = 32, 204 .reg_stride = 4, 205 .val_bits = 32, 206 .max_register = 0x7fc, 207 }; 208 209 static const struct cmn_pll_fixed_output_clk ipq5018_output_clks[] = { 210 CLK_PLL_OUTPUT(IPQ5018_XO_24MHZ_CLK, "xo-24mhz", 24000000UL), 211 CLK_PLL_OUTPUT(IPQ5018_SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL), 212 CLK_PLL_OUTPUT(IPQ5018_ETH_50MHZ_CLK, "eth-50mhz", 50000000UL), 213 { /* Sentinel */ } 214 }; 215 216 static const struct cmn_pll_fixed_output_clk ipq5210_output_clks[] = { 217 CLK_PLL_OUTPUT(IPQ5210_XO_24MHZ_CLK, "xo-24mhz", 24000000UL), 218 CLK_PLL_OUTPUT(IPQ5210_SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL), 219 CLK_PLL_GATE(IPQ5210_PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL, CLK31P25M_EN_BIT), 220 CLK_PLL_GATE(IPQ5210_ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL, CLK50M_EN_BIT1), 221 CLK_PLL_GATE(IPQ5210_ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL, CLK50M_EN_BIT2), 222 CLK_PLL_GATE(IPQ5210_ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL, CLK50M_EN_BIT3), 223 CLK_PLL_GATE(IPQ5210_EPHY_50MHZ_CLK, "ephy-50mhz", 50000000UL, CLK250M_EN_BIT), 224 CLK_PLL_GATE(IPQ5210_ETH_25MHZ_CLK, "eth-25mhz", 25000000UL, CLK25M_EN_BIT), 225 CLK_PLL_NSS(IPQ5210_NSS_CLK, "nss"), 226 CLK_PLL_PPE(IPQ5210_PPE_CLK, "ppe"), 227 CLK_PLL_PON(IPQ5210_PON_CLK, "pon"), 228 CLK_PLL_EPHY_RAW(IPQ5210_EPHY_RAW_CLK, "ephy-raw"), 229 { /* Sentinel */ } 230 }; 231 232 static const struct cmn_pll_fixed_output_clk ipq6018_output_clks[] = { 233 CLK_PLL_OUTPUT(IPQ6018_BIAS_PLL_CC_CLK, "bias_pll_cc_clk", 300000000UL), 234 CLK_PLL_OUTPUT(IPQ6018_BIAS_PLL_NSS_NOC_CLK, "bias_pll_nss_noc_clk", 416500000UL), 235 { /* Sentinel */ } 236 }; 237 238 static const struct cmn_pll_fixed_output_clk ipq8074_output_clks[] = { 239 CLK_PLL_OUTPUT(IPQ8074_BIAS_PLL_CC_CLK, "bias_pll_cc_clk", 300000000UL), 240 CLK_PLL_OUTPUT(IPQ8074_BIAS_PLL_NSS_NOC_CLK, "bias_pll_nss_noc_clk", 416500000UL), 241 { /* Sentinel */ } 242 }; 243 244 static const struct cmn_pll_fixed_output_clk ipq5332_output_clks[] = { 245 CLK_PLL_OUTPUT(IPQ5332_XO_24MHZ_CLK, "xo-24mhz", 24000000UL), 246 CLK_PLL_OUTPUT(IPQ5332_SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL), 247 CLK_PLL_OUTPUT(IPQ5332_PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL), 248 CLK_PLL_OUTPUT(IPQ5332_NSS_300MHZ_CLK, "nss-300mhz", 300000000UL), 249 CLK_PLL_OUTPUT(IPQ5332_PPE_200MHZ_CLK, "ppe-200mhz", 200000000UL), 250 CLK_PLL_OUTPUT(IPQ5332_ETH_50MHZ_CLK, "eth-50mhz", 50000000UL), 251 { /* Sentinel */ } 252 }; 253 254 static const struct cmn_pll_fixed_output_clk ipq5424_output_clks[] = { 255 CLK_PLL_OUTPUT(IPQ5424_XO_24MHZ_CLK, "xo-24mhz", 24000000UL), 256 CLK_PLL_OUTPUT(IPQ5424_SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL), 257 CLK_PLL_OUTPUT(IPQ5424_PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL), 258 CLK_PLL_OUTPUT(IPQ5424_NSS_300MHZ_CLK, "nss-300mhz", 300000000UL), 259 CLK_PLL_OUTPUT(IPQ5424_PPE_375MHZ_CLK, "ppe-375mhz", 375000000UL), 260 CLK_PLL_OUTPUT(IPQ5424_ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL), 261 CLK_PLL_OUTPUT(IPQ5424_ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL), 262 CLK_PLL_OUTPUT(IPQ5424_ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL), 263 CLK_PLL_OUTPUT(IPQ5424_ETH_25MHZ_CLK, "eth-25mhz", 25000000UL), 264 { /* Sentinel */ } 265 }; 266 267 static const struct cmn_pll_fixed_output_clk ipq9574_output_clks[] = { 268 CLK_PLL_OUTPUT(XO_24MHZ_CLK, "xo-24mhz", 24000000UL), 269 CLK_PLL_OUTPUT(SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL), 270 CLK_PLL_OUTPUT(PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL), 271 CLK_PLL_OUTPUT(NSS_1200MHZ_CLK, "nss-1200mhz", 1200000000UL), 272 CLK_PLL_OUTPUT(PPE_353MHZ_CLK, "ppe-353mhz", 353000000UL), 273 CLK_PLL_OUTPUT(ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL), 274 CLK_PLL_OUTPUT(ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL), 275 CLK_PLL_OUTPUT(ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL), 276 CLK_PLL_OUTPUT(ETH_25MHZ_CLK, "eth-25mhz", 25000000UL), 277 { /* Sentinel */ } 278 }; 279 280 /* 281 * CMN PLL has the single parent clock, which supports the several 282 * possible parent clock rates, each parent clock rate is reflected 283 * by the specific reference index value in the hardware. 284 */ 285 static int ipq_cmn_pll_find_freq_index(unsigned long parent_rate) 286 { 287 int index = -EINVAL; 288 289 switch (parent_rate) { 290 case 25000000: 291 index = 3; 292 break; 293 case 31250000: 294 index = 4; 295 break; 296 case 40000000: 297 index = 6; 298 break; 299 case 48000000: 300 case 96000000: 301 /* 302 * Parent clock rate 48 MHZ and 96 MHZ take the same value 303 * of reference clock index. 96 MHZ needs the source clock 304 * divider to be programmed as 2. 305 */ 306 index = 7; 307 break; 308 case 50000000: 309 index = 8; 310 break; 311 default: 312 break; 313 } 314 315 return index; 316 } 317 318 static unsigned long clk_cmn_pll_recalc_rate(struct clk_hw *hw, 319 unsigned long parent_rate) 320 { 321 struct clk_cmn_pll *cmn_pll = to_clk_cmn_pll(hw); 322 u32 val, factor, ref_div; 323 324 /* 325 * The value of CMN_PLL_DIVIDER_CTRL_FACTOR is automatically adjusted 326 * by HW according to the parent clock rate. 327 */ 328 regmap_read(cmn_pll->regmap, CMN_PLL_DIVIDER_CTRL, &val); 329 factor = FIELD_GET(CMN_PLL_DIVIDER_CTRL_FACTOR, val); 330 if (WARN_ON(factor == 0)) 331 factor = 1; 332 333 regmap_read(cmn_pll->regmap, CMN_PLL_REFCLK_CONFIG, &val); 334 ref_div = FIELD_GET(CMN_PLL_REFCLK_DIV, val); 335 if (WARN_ON(ref_div == 0)) 336 ref_div = 1; 337 338 return div_u64((u64)parent_rate * 2 * factor, ref_div); 339 } 340 341 static int clk_cmn_pll_determine_rate(struct clk_hw *hw, 342 struct clk_rate_request *req) 343 { 344 int ret; 345 346 /* Validate the rate of the single parent clock. */ 347 ret = ipq_cmn_pll_find_freq_index(req->best_parent_rate); 348 349 return ret < 0 ? ret : 0; 350 } 351 352 /* 353 * This function is used to initialize the CMN PLL to enable the fixed 354 * rate output clocks. It is expected to be configured once. 355 */ 356 static int clk_cmn_pll_set_rate(struct clk_hw *hw, unsigned long rate, 357 unsigned long parent_rate) 358 { 359 struct clk_cmn_pll *cmn_pll = to_clk_cmn_pll(hw); 360 int ret, index; 361 u32 val; 362 363 /* 364 * Configure the reference input clock selection as per the given 365 * parent clock. The output clock rates are always of fixed value. 366 */ 367 index = ipq_cmn_pll_find_freq_index(parent_rate); 368 if (index < 0) 369 return index; 370 371 ret = regmap_update_bits(cmn_pll->regmap, CMN_PLL_REFCLK_CONFIG, 372 CMN_PLL_REFCLK_INDEX, 373 FIELD_PREP(CMN_PLL_REFCLK_INDEX, index)); 374 if (ret) 375 return ret; 376 377 /* 378 * Update the source clock rate selection and source clock 379 * divider as 2 when the parent clock rate is 96 MHZ. 380 */ 381 if (parent_rate == 96000000) { 382 ret = regmap_update_bits(cmn_pll->regmap, CMN_PLL_REFCLK_CONFIG, 383 CMN_PLL_REFCLK_DIV, 384 FIELD_PREP(CMN_PLL_REFCLK_DIV, 2)); 385 if (ret) 386 return ret; 387 388 ret = regmap_update_bits(cmn_pll->regmap, CMN_PLL_REFCLK_SRC_SELECTION, 389 CMN_PLL_REFCLK_SRC_DIV, 390 FIELD_PREP(CMN_PLL_REFCLK_SRC_DIV, 0)); 391 if (ret) 392 return ret; 393 } 394 395 /* Enable PLL locked detect. */ 396 ret = regmap_set_bits(cmn_pll->regmap, CMN_PLL_CTRL, 397 CMN_PLL_CTRL_LOCK_DETECT_EN); 398 if (ret) 399 return ret; 400 401 /* 402 * Reset the CMN PLL block to ensure the updated configurations 403 * take effect. 404 */ 405 ret = regmap_clear_bits(cmn_pll->regmap, CMN_PLL_POWER_ON_AND_RESET, 406 CMN_ANA_EN_SW_RSTN); 407 if (ret) 408 return ret; 409 410 usleep_range(1000, 1200); 411 ret = regmap_set_bits(cmn_pll->regmap, CMN_PLL_POWER_ON_AND_RESET, 412 CMN_ANA_EN_SW_RSTN); 413 if (ret) 414 return ret; 415 416 /* Stability check of CMN PLL output clocks. */ 417 return regmap_read_poll_timeout(cmn_pll->regmap, CMN_PLL_LOCKED, val, 418 (val & CMN_PLL_CLKS_LOCKED), 419 100, 100 * USEC_PER_MSEC); 420 } 421 422 static const struct clk_ops clk_cmn_pll_ops = { 423 .recalc_rate = clk_cmn_pll_recalc_rate, 424 .determine_rate = clk_cmn_pll_determine_rate, 425 .set_rate = clk_cmn_pll_set_rate, 426 }; 427 428 static struct clk_hw *ipq_cmn_pll_clk_hw_register(struct platform_device *pdev) 429 { 430 struct clk_parent_data pdata = { .index = 0 }; 431 struct device *dev = &pdev->dev; 432 struct clk_init_data init = {}; 433 struct clk_cmn_pll *cmn_pll; 434 struct regmap *regmap; 435 void __iomem *base; 436 int ret; 437 438 base = devm_platform_ioremap_resource(pdev, 0); 439 if (IS_ERR(base)) 440 return ERR_CAST(base); 441 442 regmap = devm_regmap_init_mmio(dev, base, &ipq_cmn_pll_regmap_config); 443 if (IS_ERR(regmap)) 444 return ERR_CAST(regmap); 445 446 cmn_pll = devm_kzalloc(dev, sizeof(*cmn_pll), GFP_KERNEL); 447 if (!cmn_pll) 448 return ERR_PTR(-ENOMEM); 449 450 init.name = "cmn_pll"; 451 init.parent_data = &pdata; 452 init.num_parents = 1; 453 init.ops = &clk_cmn_pll_ops; 454 455 cmn_pll->hw.init = &init; 456 cmn_pll->regmap = regmap; 457 458 ret = devm_clk_hw_register(dev, &cmn_pll->hw); 459 if (ret) 460 return ERR_PTR(ret); 461 462 return &cmn_pll->hw; 463 } 464 465 static struct clk_hw *ipq_cmn_pll_regmap_div_register(struct device *dev, 466 const char *name, 467 struct clk_hw *parent_hw, 468 u32 field_mask) 469 { 470 struct clk_parent_data pdata = { .hw = parent_hw }; 471 struct clk_regmap_div *div_clk; 472 int ret; 473 474 div_clk = devm_kzalloc(dev, sizeof(*div_clk), GFP_KERNEL); 475 if (!div_clk) 476 return ERR_PTR(-ENOMEM); 477 478 div_clk->reg = CMN_PLL_NSS_PPE_FREQ_CTRL; 479 div_clk->shift = __ffs(field_mask); 480 div_clk->width = hweight32(field_mask); 481 /* 482 * CMN_PLL_NSS_CLK_SEL / CMN_PLL_PPE_CLK_SEL reset to a valid, non-zero 483 * divider in hardware. CLK_DIVIDER_ALLOW_ZERO is deliberately not set: 484 * a divider field read back as 0 is genuinely invalid and should trip 485 * the core clk-divider's zero-divisor WARN rather than be silently 486 * tolerated. 487 */ 488 div_clk->flags = CLK_DIVIDER_ONE_BASED; 489 div_clk->clkr.hw.init = &(struct clk_init_data){ 490 .name = name, 491 .parent_data = &pdata, 492 .num_parents = 1, 493 .ops = &clk_regmap_div_ops, 494 }; 495 496 ret = devm_clk_register_regmap(dev, &div_clk->clkr); 497 if (ret) 498 return ERR_PTR(ret); 499 500 return &div_clk->clkr.hw; 501 } 502 503 /* 504 * PON (Passive Optical Network) reference clock operations. 505 * The PON refclk's parent is cmn_pll_div2 (CMN PLL rate / 2); it is 506 * then divided by a configurable 8-bit divider (1-255). 507 */ 508 static unsigned long clk_pon_clk_recalc_rate(struct clk_hw *hw, 509 unsigned long parent_rate) 510 { 511 struct clk_regmap *pon_clk = to_clk_regmap(hw); 512 u32 val, div; 513 int ret; 514 515 ret = regmap_read(pon_clk->regmap, CMN_PLL_PON_CONFIG, &val); 516 if (ret) 517 return 0; 518 519 /* Check if in UNIPHY mode (bit 9 = 0) - fixed 31.25 MHz */ 520 if (!(val & CMN_PLL_PON_MODE_SEL)) 521 return 31250000UL; 522 523 /* PON mode: calculate from divider */ 524 div = FIELD_GET(CMN_PLL_PON_DIV_CTRL, val); 525 if (!div) 526 return 0; 527 528 return DIV_ROUND_CLOSEST_ULL((u64)parent_rate, div); 529 } 530 531 static int clk_pon_clk_determine_rate(struct clk_hw *hw, 532 struct clk_rate_request *req) 533 { 534 unsigned long div, pon_rate, uniphy_rate = 31250000UL; 535 bool uniphy_rate_valid, pon_rate_valid; 536 537 if (!req->rate || !req->best_parent_rate) 538 return -EINVAL; 539 540 div = DIV64_U64_ROUND_CLOSEST((u64)req->best_parent_rate, req->rate); 541 542 /* Clamp to valid range (1-255) */ 543 div = clamp_t(unsigned long, div, 1, 255); 544 545 pon_rate = DIV_ROUND_CLOSEST_ULL((u64)req->best_parent_rate, div); 546 547 uniphy_rate_valid = uniphy_rate >= req->min_rate && 548 uniphy_rate <= req->max_rate; 549 pon_rate_valid = pon_rate >= req->min_rate && 550 pon_rate <= req->max_rate; 551 552 if (!uniphy_rate_valid && !pon_rate_valid) 553 return -EINVAL; 554 555 /* Pick whichever mode gets closer to the requested rate */ 556 if (uniphy_rate_valid && pon_rate_valid) { 557 unsigned long diff_uniphy, diff_pon; 558 559 diff_uniphy = abs_diff(req->rate, uniphy_rate); 560 diff_pon = abs_diff(req->rate, pon_rate); 561 req->rate = diff_uniphy < diff_pon ? uniphy_rate : pon_rate; 562 } else { 563 req->rate = uniphy_rate_valid ? uniphy_rate : pon_rate; 564 } 565 566 return 0; 567 } 568 569 static int clk_pon_clk_set_rate(struct clk_hw *hw, unsigned long rate, 570 unsigned long parent_rate) 571 { 572 struct clk_regmap *pon_clk = to_clk_regmap(hw); 573 unsigned long div; 574 575 if (rate == 0) 576 return -EINVAL; 577 578 /* 579 * An exact request for 31.25 MHz is always satisfiable by UNIPHY 580 * mode, even though PON mode with a suitable divider can produce 581 * the same frequency for some parent rates. Preferring UNIPHY here 582 * is safe: this function is only ever called with a rate produced 583 * by clk_pon_clk_determine_rate() through the standard 584 * clk_set_rate() path, and either mode yields the identical output 585 * rate for this value. 586 */ 587 if (rate == 31250000UL) 588 return regmap_clear_bits(pon_clk->regmap, CMN_PLL_PON_CONFIG, 589 CMN_PLL_PON_MODE_SEL); 590 591 div = DIV64_U64_ROUND_CLOSEST((u64)parent_rate, rate); 592 if (div == 0 || div > 255) 593 return -EINVAL; 594 595 /* Switch to PON mode and program the divider in a single write */ 596 return regmap_update_bits(pon_clk->regmap, CMN_PLL_PON_CONFIG, 597 CMN_PLL_PON_MODE_SEL | CMN_PLL_PON_DIV_CTRL, 598 CMN_PLL_PON_MODE_SEL | 599 FIELD_PREP(CMN_PLL_PON_DIV_CTRL, div)); 600 } 601 602 static const struct clk_ops clk_pon_clk_ops = { 603 .enable = clk_enable_regmap, 604 .disable = clk_disable_regmap, 605 .is_enabled = clk_is_enabled_regmap, 606 .recalc_rate = clk_pon_clk_recalc_rate, 607 .determine_rate = clk_pon_clk_determine_rate, 608 .set_rate = clk_pon_clk_set_rate, 609 }; 610 611 static struct clk_hw *ipq_cmn_pll_pon_clk_register(struct device *dev, 612 const char *name, 613 struct clk_hw *parent_hw) 614 { 615 struct clk_parent_data pdata = { .hw = parent_hw }; 616 struct clk_init_data init = {}; 617 struct clk_regmap *pon_clk; 618 int ret; 619 620 pon_clk = devm_kzalloc(dev, sizeof(*pon_clk), GFP_KERNEL); 621 if (!pon_clk) 622 return ERR_PTR(-ENOMEM); 623 624 init.name = name; 625 init.parent_data = &pdata; 626 init.num_parents = 1; 627 init.ops = &clk_pon_clk_ops; 628 /* 629 * The PON reference clock may already be enabled by bootloader 630 * or consumed by hardware without an in-kernel client driver. 631 * Add CLK_IGNORE_UNUSED so the clock framework does not disable 632 * it when no consumer has claimed it. 633 */ 634 init.flags = CLK_IGNORE_UNUSED; 635 636 pon_clk->hw.init = &init; 637 pon_clk->enable_reg = CMN_PLL_PON_CONFIG; 638 pon_clk->enable_mask = CMN_PLL_PON_EN; 639 640 ret = devm_clk_register_regmap(dev, pon_clk); 641 if (ret) 642 return ERR_PTR(ret); 643 644 return &pon_clk->hw; 645 } 646 647 /* 648 * EPHY-RAW clock operations for IPQ5210. 649 * The output clock rate is selected via bit 10 of CMN_PLL_PON_CONFIG: 650 * 0: 125 MHz (for 1G link speed) 651 * 1: 312.5 MHz (for 2.5G link speed) 652 */ 653 static unsigned long clk_ephy_raw_recalc_rate(struct clk_hw *hw, 654 unsigned long parent_rate) 655 { 656 struct clk_regmap *ephy_raw_clk = to_clk_regmap(hw); 657 u32 val; 658 int ret; 659 660 ret = regmap_read(ephy_raw_clk->regmap, CMN_PLL_PON_CONFIG, &val); 661 if (WARN_ON_ONCE(ret)) 662 return 0; 663 664 if (val & CMN_PLL_GEPHY_312P5M_125M_SEL) 665 return 312500000UL; 666 667 return 125000000UL; 668 } 669 670 static int clk_ephy_raw_determine_rate(struct clk_hw *hw, 671 struct clk_rate_request *req) 672 { 673 unsigned long rate_125m = 125000000UL, rate_312p5m = 312500000UL; 674 bool rate_125m_valid, rate_312p5m_valid; 675 676 rate_125m_valid = rate_125m >= req->min_rate && 677 rate_125m <= req->max_rate; 678 rate_312p5m_valid = rate_312p5m >= req->min_rate && 679 rate_312p5m <= req->max_rate; 680 681 if (!rate_125m_valid && !rate_312p5m_valid) 682 return -EINVAL; 683 684 /* Pick whichever of the two supported rates is closer to the request */ 685 if (rate_125m_valid && rate_312p5m_valid) { 686 unsigned long diff_125m, diff_312p5m; 687 688 diff_125m = abs_diff(req->rate, rate_125m); 689 diff_312p5m = abs_diff(req->rate, rate_312p5m); 690 req->rate = diff_125m < diff_312p5m ? rate_125m : rate_312p5m; 691 } else { 692 req->rate = rate_125m_valid ? rate_125m : rate_312p5m; 693 } 694 695 return 0; 696 } 697 698 static int clk_ephy_raw_set_rate(struct clk_hw *hw, unsigned long rate, 699 unsigned long parent_rate) 700 { 701 struct clk_regmap *ephy_raw_clk = to_clk_regmap(hw); 702 703 if (rate == 125000000UL) 704 return regmap_clear_bits(ephy_raw_clk->regmap, 705 CMN_PLL_PON_CONFIG, 706 CMN_PLL_GEPHY_312P5M_125M_SEL); 707 708 if (rate == 312500000UL) 709 return regmap_set_bits(ephy_raw_clk->regmap, 710 CMN_PLL_PON_CONFIG, 711 CMN_PLL_GEPHY_312P5M_125M_SEL); 712 713 return -EINVAL; 714 } 715 716 static const struct clk_ops clk_ephy_raw_ops = { 717 .recalc_rate = clk_ephy_raw_recalc_rate, 718 .determine_rate = clk_ephy_raw_determine_rate, 719 .set_rate = clk_ephy_raw_set_rate, 720 }; 721 722 static struct clk_hw *ipq_cmn_pll_ephy_raw_register(struct device *dev, 723 const char *name, 724 struct clk_hw *parent_hw) 725 { 726 struct clk_parent_data pdata = { .hw = parent_hw }; 727 struct clk_regmap *ephy_raw_clk; 728 struct clk_init_data init = {}; 729 int ret; 730 731 ephy_raw_clk = devm_kzalloc(dev, sizeof(*ephy_raw_clk), GFP_KERNEL); 732 if (!ephy_raw_clk) 733 return ERR_PTR(-ENOMEM); 734 735 init.name = name; 736 init.parent_data = &pdata; 737 init.num_parents = 1; 738 init.ops = &clk_ephy_raw_ops; 739 740 ephy_raw_clk->hw.init = &init; 741 742 ret = devm_clk_register_regmap(dev, ephy_raw_clk); 743 if (ret) 744 return ERR_PTR(ret); 745 746 return &ephy_raw_clk->hw; 747 } 748 749 static unsigned long clk_fixed_gate_recalc_rate(struct clk_hw *hw, 750 unsigned long parent_rate) 751 { 752 struct clk_fixed_gate *gate_clk = to_clk_fixed_gate(hw); 753 754 return gate_clk->rate; 755 } 756 757 static const struct clk_ops clk_fixed_gate_ops = { 758 .enable = clk_enable_regmap, 759 .disable = clk_disable_regmap, 760 .is_enabled = clk_is_enabled_regmap, 761 .recalc_rate = clk_fixed_gate_recalc_rate, 762 }; 763 764 static struct clk_hw *ipq_cmn_pll_register_fixed_gate(struct device *dev, 765 const char *name, 766 struct clk_hw *parent_hw, 767 int enable_bit, 768 unsigned long rate) 769 { 770 struct clk_parent_data pdata = { .hw = parent_hw }; 771 struct clk_fixed_gate *gate_clk; 772 struct clk_init_data init = {}; 773 int ret; 774 775 gate_clk = devm_kzalloc(dev, sizeof(*gate_clk), GFP_KERNEL); 776 if (!gate_clk) 777 return ERR_PTR(-ENOMEM); 778 779 init.name = name; 780 init.parent_data = &pdata; 781 init.num_parents = 1; 782 init.ops = &clk_fixed_gate_ops; 783 /* 784 * These gated clocks may be relied on by external hardware or 785 * bootloader-enabled paths without an in-kernel client driver. 786 * Add CLK_IGNORE_UNUSED so the clock framework does not disable 787 * them when no consumer has claimed them. 788 */ 789 init.flags = CLK_IGNORE_UNUSED; 790 791 gate_clk->clkr.hw.init = &init; 792 gate_clk->clkr.enable_reg = CMN_PLL_OUTPUT_RELATED_1; 793 gate_clk->clkr.enable_mask = BIT(enable_bit); 794 gate_clk->rate = rate; 795 796 ret = devm_clk_register_regmap(dev, &gate_clk->clkr); 797 if (ret) 798 return ERR_PTR(ret); 799 800 return &gate_clk->clkr.hw; 801 } 802 803 static int ipq_cmn_pll_register_clks(struct platform_device *pdev) 804 { 805 const struct cmn_pll_fixed_output_clk *p, *fixed_clk; 806 struct clk_hw_onecell_data *hw_data; 807 struct device *dev = &pdev->dev; 808 struct clk_cmn_pll *cmn_pll; 809 struct clk_hw *cmn_pll_hw; 810 unsigned int num_clks; 811 struct clk_hw *hw; 812 int ret, i; 813 814 fixed_clk = device_get_match_data(dev); 815 if (!fixed_clk) 816 return -EINVAL; 817 818 num_clks = 0; 819 for (p = fixed_clk; p->name; p++) 820 num_clks++; 821 822 hw_data = devm_kzalloc(dev, struct_size(hw_data, hws, num_clks + 1), 823 GFP_KERNEL); 824 if (!hw_data) 825 return -ENOMEM; 826 827 hw_data->num = num_clks + 1; 828 829 /* 830 * Register the CMN PLL clock, which is the parent clock of 831 * the fixed rate output clocks. 832 */ 833 cmn_pll_hw = ipq_cmn_pll_clk_hw_register(pdev); 834 if (IS_ERR(cmn_pll_hw)) 835 return PTR_ERR(cmn_pll_hw); 836 837 cmn_pll = to_clk_cmn_pll(cmn_pll_hw); 838 cmn_pll->div2_hw = devm_clk_hw_register_fixed_factor_parent_hw(dev, 839 "cmn_pll_div2", 840 cmn_pll_hw, 841 0, 1, 2); 842 if (IS_ERR(cmn_pll->div2_hw)) 843 return PTR_ERR(cmn_pll->div2_hw); 844 845 /* Register the fixed rate output clocks. */ 846 for (i = 0; i < num_clks; i++) { 847 hw = ERR_PTR(-EINVAL); 848 849 switch (fixed_clk[i].type) { 850 case CMN_PLL_CLK_FIXED_RATE: { 851 struct clk_parent_data pdata = { .hw = cmn_pll_hw }; 852 853 hw = devm_clk_hw_register_fixed_rate_parent_data(dev, 854 fixed_clk[i].name, 855 &pdata, 0, 856 fixed_clk[i].rate); 857 break; 858 } 859 case CMN_PLL_CLK_FIXED_GATE: 860 hw = ipq_cmn_pll_register_fixed_gate(dev, 861 fixed_clk[i].name, 862 cmn_pll->div2_hw, 863 fixed_clk[i].enable_bit, 864 fixed_clk[i].rate); 865 break; 866 case CMN_PLL_CLK_NSS: 867 hw = ipq_cmn_pll_regmap_div_register(dev, 868 fixed_clk[i].name, 869 cmn_pll->div2_hw, 870 CMN_PLL_NSS_CLK_SEL); 871 break; 872 case CMN_PLL_CLK_PPE: 873 hw = ipq_cmn_pll_regmap_div_register(dev, 874 fixed_clk[i].name, 875 cmn_pll->div2_hw, 876 CMN_PLL_PPE_CLK_SEL); 877 break; 878 case CMN_PLL_CLK_PON: 879 hw = ipq_cmn_pll_pon_clk_register(dev, 880 fixed_clk[i].name, 881 cmn_pll->div2_hw); 882 break; 883 case CMN_PLL_CLK_EPHY_RAW: 884 hw = ipq_cmn_pll_ephy_raw_register(dev, 885 fixed_clk[i].name, 886 cmn_pll->div2_hw); 887 break; 888 } 889 890 if (IS_ERR(hw)) 891 return PTR_ERR(hw); 892 893 hw_data->hws[fixed_clk[i].id] = hw; 894 } 895 896 /* 897 * Provide the CMN PLL clock. The clock rate of CMN PLL 898 * is configured to 12 GHZ by DT property assigned-clock-rates-u64. 899 */ 900 hw_data->hws[CMN_PLL_CLK] = cmn_pll_hw; 901 902 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, hw_data); 903 if (ret) 904 return ret; 905 906 platform_set_drvdata(pdev, hw_data); 907 908 return 0; 909 } 910 911 static int ipq_cmn_pll_clk_probe(struct platform_device *pdev) 912 { 913 struct device *dev = &pdev->dev; 914 int ret; 915 916 ret = devm_pm_runtime_enable(dev); 917 if (ret) 918 return ret; 919 920 ret = devm_pm_clk_create(dev); 921 if (ret) 922 return ret; 923 924 /* 925 * To access the CMN PLL registers, the GCC AHB & SYS clocks 926 * of CMN PLL block need to be enabled. 927 */ 928 ret = pm_clk_add(dev, "ahb"); 929 if (ret) 930 return dev_err_probe(dev, ret, "Failed to add AHB clock\n"); 931 932 ret = pm_clk_add(dev, "sys"); 933 if (ret) 934 return dev_err_probe(dev, ret, "Failed to add SYS clock\n"); 935 936 ret = pm_runtime_resume_and_get(dev); 937 if (ret) 938 return ret; 939 940 /* Register CMN PLL clock and fixed rate output clocks. */ 941 ret = ipq_cmn_pll_register_clks(pdev); 942 pm_runtime_put(dev); 943 if (ret) 944 return dev_err_probe(dev, ret, 945 "Failed to register CMN PLL clocks\n"); 946 947 return 0; 948 } 949 950 static const struct dev_pm_ops ipq_cmn_pll_pm_ops = { 951 SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) 952 }; 953 954 static const struct of_device_id ipq_cmn_pll_clk_ids[] = { 955 { .compatible = "qcom,ipq5018-cmn-pll", .data = &ipq5018_output_clks }, 956 { .compatible = "qcom,ipq5210-cmn-pll", .data = &ipq5210_output_clks }, 957 { .compatible = "qcom,ipq5332-cmn-pll", .data = &ipq5332_output_clks }, 958 { .compatible = "qcom,ipq5424-cmn-pll", .data = &ipq5424_output_clks }, 959 { .compatible = "qcom,ipq6018-cmn-pll", .data = &ipq6018_output_clks }, 960 { .compatible = "qcom,ipq8074-cmn-pll", .data = &ipq8074_output_clks }, 961 { .compatible = "qcom,ipq9574-cmn-pll", .data = &ipq9574_output_clks }, 962 { } 963 }; 964 MODULE_DEVICE_TABLE(of, ipq_cmn_pll_clk_ids); 965 966 static struct platform_driver ipq_cmn_pll_clk_driver = { 967 .probe = ipq_cmn_pll_clk_probe, 968 .driver = { 969 .name = "ipq_cmn_pll", 970 .of_match_table = ipq_cmn_pll_clk_ids, 971 .pm = &ipq_cmn_pll_pm_ops, 972 }, 973 }; 974 module_platform_driver(ipq_cmn_pll_clk_driver); 975 976 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. IPQ CMN PLL Driver"); 977 MODULE_LICENSE("GPL"); 978