1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* 3 * Copyright (c) 2023-2025 Rockchip Electronics Co., Ltd. 4 * Author: Finley Xiao <finley.xiao@rock-chips.com> 5 */ 6 7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3506_H 8 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3506_H 9 10 /* cru plls */ 11 #define PLL_GPLL 0 12 #define PLL_V0PLL 1 13 #define PLL_V1PLL 2 14 15 /* cru-clocks indices */ 16 #define ARMCLK 3 17 #define CLK_DDR 4 18 #define XIN24M_GATE 5 19 #define CLK_GPLL_GATE 6 20 #define CLK_V0PLL_GATE 7 21 #define CLK_V1PLL_GATE 8 22 #define CLK_GPLL_DIV 9 23 #define CLK_GPLL_DIV_100M 10 24 #define CLK_V0PLL_DIV 11 25 #define CLK_V1PLL_DIV 12 26 #define CLK_INT_VOICE_MATRIX0 13 27 #define CLK_INT_VOICE_MATRIX1 14 28 #define CLK_INT_VOICE_MATRIX2 15 29 #define CLK_FRAC_UART_MATRIX0_MUX 16 30 #define CLK_FRAC_UART_MATRIX1_MUX 17 31 #define CLK_FRAC_VOICE_MATRIX0_MUX 18 32 #define CLK_FRAC_VOICE_MATRIX1_MUX 19 33 #define CLK_FRAC_COMMON_MATRIX0_MUX 20 34 #define CLK_FRAC_COMMON_MATRIX1_MUX 21 35 #define CLK_FRAC_COMMON_MATRIX2_MUX 22 36 #define CLK_FRAC_UART_MATRIX0 23 37 #define CLK_FRAC_UART_MATRIX1 24 38 #define CLK_FRAC_VOICE_MATRIX0 25 39 #define CLK_FRAC_VOICE_MATRIX1 26 40 #define CLK_FRAC_COMMON_MATRIX0 27 41 #define CLK_FRAC_COMMON_MATRIX1 28 42 #define CLK_FRAC_COMMON_MATRIX2 29 43 #define CLK_REF_USBPHY_TOP 30 44 #define CLK_REF_DPHY_TOP 31 45 #define ACLK_CORE_ROOT 32 46 #define PCLK_CORE_ROOT 33 47 #define PCLK_DBG 34 48 #define PCLK_CORE_GRF 35 49 #define PCLK_CORE_CRU 36 50 #define CLK_CORE_EMA_DETECT 37 51 #define CLK_REF_PVTPLL_CORE 38 52 #define PCLK_GPIO1 39 53 #define DBCLK_GPIO1 40 54 #define ACLK_CORE_PERI_ROOT 41 55 #define HCLK_CORE_PERI_ROOT 42 56 #define PCLK_CORE_PERI_ROOT 43 57 #define CLK_DSMC 44 58 #define ACLK_DSMC 45 59 #define PCLK_DSMC 46 60 #define CLK_FLEXBUS_TX 47 61 #define CLK_FLEXBUS_RX 48 62 #define ACLK_FLEXBUS 49 63 #define HCLK_FLEXBUS 50 64 #define ACLK_DSMC_SLV 51 65 #define HCLK_DSMC_SLV 52 66 #define ACLK_BUS_ROOT 53 67 #define HCLK_BUS_ROOT 54 68 #define PCLK_BUS_ROOT 55 69 #define ACLK_SYSRAM 56 70 #define HCLK_SYSRAM 57 71 #define ACLK_DMAC0 58 72 #define ACLK_DMAC1 59 73 #define HCLK_M0 60 74 #define PCLK_BUS_GRF 61 75 #define PCLK_TIMER 62 76 #define CLK_TIMER0_CH0 63 77 #define CLK_TIMER0_CH1 64 78 #define CLK_TIMER0_CH2 65 79 #define CLK_TIMER0_CH3 66 80 #define CLK_TIMER0_CH4 67 81 #define CLK_TIMER0_CH5 68 82 #define PCLK_WDT0 69 83 #define TCLK_WDT0 70 84 #define PCLK_WDT1 71 85 #define TCLK_WDT1 72 86 #define PCLK_MAILBOX 73 87 #define PCLK_INTMUX 74 88 #define PCLK_SPINLOCK 75 89 #define PCLK_DDRC 76 90 #define HCLK_DDRPHY 77 91 #define PCLK_DDRMON 78 92 #define CLK_DDRMON_OSC 79 93 #define PCLK_STDBY 80 94 #define HCLK_USBOTG0 81 95 #define HCLK_USBOTG0_PMU 82 96 #define CLK_USBOTG0_ADP 83 97 #define HCLK_USBOTG1 84 98 #define HCLK_USBOTG1_PMU 85 99 #define CLK_USBOTG1_ADP 86 100 #define PCLK_USBPHY 87 101 #define ACLK_DMA2DDR 88 102 #define PCLK_DMA2DDR 89 103 #define STCLK_M0 90 104 #define CLK_DDRPHY 91 105 #define CLK_DDRC_SRC 92 106 #define ACLK_DDRC_0 93 107 #define ACLK_DDRC_1 94 108 #define CLK_DDRC 95 109 #define CLK_DDRMON 96 110 #define HCLK_LSPERI_ROOT 97 111 #define PCLK_LSPERI_ROOT 98 112 #define PCLK_UART0 99 113 #define PCLK_UART1 100 114 #define PCLK_UART2 101 115 #define PCLK_UART3 102 116 #define PCLK_UART4 103 117 #define SCLK_UART0 104 118 #define SCLK_UART1 105 119 #define SCLK_UART2 106 120 #define SCLK_UART3 107 121 #define SCLK_UART4 108 122 #define PCLK_I2C0 109 123 #define CLK_I2C0 110 124 #define PCLK_I2C1 111 125 #define CLK_I2C1 112 126 #define PCLK_I2C2 113 127 #define CLK_I2C2 114 128 #define PCLK_PWM1 115 129 #define CLK_PWM1 116 130 #define CLK_OSC_PWM1 117 131 #define CLK_RC_PWM1 118 132 #define CLK_FREQ_PWM1 119 133 #define CLK_COUNTER_PWM1 120 134 #define PCLK_SPI0 121 135 #define CLK_SPI0 122 136 #define PCLK_SPI1 123 137 #define CLK_SPI1 124 138 #define PCLK_GPIO2 125 139 #define DBCLK_GPIO2 126 140 #define PCLK_GPIO3 127 141 #define DBCLK_GPIO3 128 142 #define PCLK_GPIO4 129 143 #define DBCLK_GPIO4 130 144 #define HCLK_CAN0 131 145 #define CLK_CAN0 132 146 #define HCLK_CAN1 133 147 #define CLK_CAN1 134 148 #define HCLK_PDM 135 149 #define MCLK_PDM 136 150 #define CLKOUT_PDM 137 151 #define MCLK_SPDIFTX 138 152 #define HCLK_SPDIFTX 139 153 #define HCLK_SPDIFRX 140 154 #define MCLK_SPDIFRX 141 155 #define MCLK_SAI0 142 156 #define HCLK_SAI0 143 157 #define MCLK_OUT_SAI0 144 158 #define MCLK_SAI1 145 159 #define HCLK_SAI1 146 160 #define MCLK_OUT_SAI1 147 161 #define HCLK_ASRC0 148 162 #define CLK_ASRC0 149 163 #define HCLK_ASRC1 150 164 #define CLK_ASRC1 151 165 #define PCLK_CRU 152 166 #define PCLK_PMU_ROOT 153 167 #define MCLK_ASRC0 154 168 #define MCLK_ASRC1 155 169 #define MCLK_ASRC2 156 170 #define MCLK_ASRC3 157 171 #define LRCK_ASRC0_SRC 158 172 #define LRCK_ASRC0_DST 159 173 #define LRCK_ASRC1_SRC 160 174 #define LRCK_ASRC1_DST 161 175 #define ACLK_HSPERI_ROOT 162 176 #define HCLK_HSPERI_ROOT 163 177 #define PCLK_HSPERI_ROOT 164 178 #define CCLK_SRC_SDMMC 165 179 #define HCLK_SDMMC 166 180 #define HCLK_FSPI 167 181 #define SCLK_FSPI 168 182 #define PCLK_SPI2 169 183 #define ACLK_MAC0 170 184 #define ACLK_MAC1 171 185 #define PCLK_MAC0 172 186 #define PCLK_MAC1 173 187 #define CLK_MAC_ROOT 174 188 #define CLK_MAC0 175 189 #define CLK_MAC1 176 190 #define MCLK_SAI2 177 191 #define HCLK_SAI2 178 192 #define MCLK_OUT_SAI2 179 193 #define MCLK_SAI3_SRC 180 194 #define HCLK_SAI3 181 195 #define MCLK_SAI3 182 196 #define MCLK_OUT_SAI3 183 197 #define MCLK_SAI4_SRC 184 198 #define HCLK_SAI4 185 199 #define MCLK_SAI4 186 200 #define HCLK_DSM 187 201 #define MCLK_DSM 188 202 #define PCLK_AUDIO_ADC 189 203 #define MCLK_AUDIO_ADC 190 204 #define MCLK_AUDIO_ADC_DIV4 191 205 #define PCLK_SARADC 192 206 #define CLK_SARADC 193 207 #define PCLK_OTPC_NS 194 208 #define CLK_SBPI_OTPC_NS 195 209 #define CLK_USER_OTPC_NS 196 210 #define PCLK_UART5 197 211 #define SCLK_UART5 198 212 #define PCLK_GPIO234_IOC 199 213 #define CLK_MAC_PTP_ROOT 200 214 #define CLK_MAC0_PTP 201 215 #define CLK_MAC1_PTP 202 216 #define CLK_SPI2 203 217 #define ACLK_VIO_ROOT 204 218 #define HCLK_VIO_ROOT 205 219 #define PCLK_VIO_ROOT 206 220 #define HCLK_RGA 207 221 #define ACLK_RGA 208 222 #define CLK_CORE_RGA 209 223 #define ACLK_VOP 210 224 #define HCLK_VOP 211 225 #define DCLK_VOP 212 226 #define PCLK_DPHY 213 227 #define PCLK_DSI_HOST 214 228 #define PCLK_TSADC 215 229 #define CLK_TSADC 216 230 #define CLK_TSADC_TSEN 217 231 #define PCLK_GPIO1_IOC 218 232 #define PCLK_OTPC_S 219 233 #define CLK_SBPI_OTPC_S 220 234 #define CLK_USER_OTPC_S 221 235 #define PCLK_OTP_MASK 222 236 #define PCLK_KEYREADER 223 237 #define HCLK_BOOTROM 224 238 #define PCLK_DDR_SERVICE 225 239 #define HCLK_CRYPTO_S 226 240 #define HCLK_KEYLAD 227 241 #define CLK_CORE_CRYPTO 228 242 #define CLK_PKA_CRYPTO 229 243 #define CLK_CORE_CRYPTO_S 230 244 #define CLK_PKA_CRYPTO_S 231 245 #define ACLK_CRYPTO_S 232 246 #define HCLK_RNG_S 233 247 #define CLK_CORE_CRYPTO_NS 234 248 #define CLK_PKA_CRYPTO_NS 235 249 #define ACLK_CRYPTO_NS 236 250 #define HCLK_CRYPTO_NS 237 251 #define HCLK_RNG 238 252 #define CLK_PMU 239 253 #define PCLK_PMU 240 254 #define CLK_PMU_32K 241 255 #define PCLK_PMU_CRU 242 256 #define PCLK_PMU_GRF 243 257 #define PCLK_GPIO0_IOC 244 258 #define PCLK_GPIO0 245 259 #define DBCLK_GPIO0 246 260 #define PCLK_GPIO1_SHADOW 247 261 #define DBCLK_GPIO1_SHADOW 248 262 #define PCLK_PMU_HP_TIMER 249 263 #define CLK_PMU_HP_TIMER 250 264 #define CLK_PMU_HP_TIMER_32K 251 265 #define PCLK_PWM0 252 266 #define CLK_PWM0 253 267 #define CLK_OSC_PWM0 254 268 #define CLK_RC_PWM0 255 269 #define CLK_MAC_OUT 256 270 #define CLK_REF_OUT0 257 271 #define CLK_REF_OUT1 258 272 #define CLK_32K_FRAC 259 273 #define CLK_32K_RC 260 274 #define CLK_32K 261 275 #define CLK_32K_PMU 262 276 #define PCLK_TOUCH_KEY 263 277 #define CLK_TOUCH_KEY 264 278 #define CLK_REF_PHY_PLL 265 279 #define CLK_REF_PHY_PMU_MUX 266 280 #define CLK_WIFI_OUT 267 281 #define CLK_V0PLL_REF 268 282 #define CLK_V1PLL_REF 269 283 #define CLK_32K_FRAC_MUX 270 284 285 #endif 286