1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* 3 * Copyright (c) 2025 Samsung Electronics Co., Ltd. 4 * https://www.samsung.com 5 * Copyright (c) 2025 Axis Communications AB. 6 * https://www.axis.com 7 * 8 * Device Tree binding constants for ARTPEC-8 clock controller. 9 */ 10 11 #ifndef _DT_BINDINGS_CLOCK_ARTPEC8_H 12 #define _DT_BINDINGS_CLOCK_ARTPEC8_H 13 14 /* CMU_CMU */ 15 #define CLK_FOUT_SHARED0_PLL 1 16 #define CLK_DOUT_SHARED0_DIV2 2 17 #define CLK_DOUT_SHARED0_DIV3 3 18 #define CLK_DOUT_SHARED0_DIV4 4 19 #define CLK_FOUT_SHARED1_PLL 5 20 #define CLK_DOUT_SHARED1_DIV2 6 21 #define CLK_DOUT_SHARED1_DIV3 7 22 #define CLK_DOUT_SHARED1_DIV4 8 23 #define CLK_FOUT_AUDIO_PLL 9 24 #define CLK_DOUT_CMU_BUS 10 25 #define CLK_DOUT_CMU_BUS_DLP 11 26 #define CLK_DOUT_CMU_CDC_CORE 12 27 #define CLK_DOUT_CMU_OTP 13 28 #define CLK_DOUT_CMU_CORE_MAIN 14 29 #define CLK_DOUT_CMU_CORE_DLP 15 30 #define CLK_DOUT_CMU_CPUCL_SWITCH 16 31 #define CLK_DOUT_CMU_DLP_CORE 17 32 #define CLK_DOUT_CMU_FSYS_BUS 18 33 #define CLK_DOUT_CMU_FSYS_IP 19 34 #define CLK_DOUT_CMU_FSYS_SCAN0 20 35 #define CLK_DOUT_CMU_FSYS_SCAN1 21 36 #define CLK_DOUT_CMU_GPU_3D 22 37 #define CLK_DOUT_CMU_GPU_2D 23 38 #define CLK_DOUT_CMU_IMEM_ACLK 24 39 #define CLK_DOUT_CMU_IMEM_JPEG 25 40 #define CLK_DOUT_CMU_MIF_SWITCH 26 41 #define CLK_DOUT_CMU_MIF_BUSP 27 42 #define CLK_DOUT_CMU_PERI_DISP 28 43 #define CLK_DOUT_CMU_PERI_IP 29 44 #define CLK_DOUT_CMU_PERI_AUDIO 30 45 #define CLK_DOUT_CMU_RSP_CORE 31 46 #define CLK_DOUT_CMU_TRFM_CORE 32 47 #define CLK_DOUT_CMU_VCA_ACE 33 48 #define CLK_DOUT_CMU_VCA_OD 34 49 #define CLK_DOUT_CMU_VIO_CORE 35 50 #define CLK_DOUT_CMU_VIO_AUDIO 36 51 #define CLK_DOUT_CMU_VIP0_CORE 37 52 #define CLK_DOUT_CMU_VIP1_CORE 38 53 #define CLK_DOUT_CMU_VPP_CORE 39 54 55 /* CMU_BUS */ 56 #define CLK_MOUT_BUS_ACLK_USER 1 57 #define CLK_MOUT_BUS_DLP_USER 2 58 #define CLK_DOUT_BUS_PCLK 3 59 60 /* CMU_CORE */ 61 #define CLK_MOUT_CORE_ACLK_USER 1 62 #define CLK_MOUT_CORE_DLP_USER 2 63 #define CLK_DOUT_CORE_PCLK 3 64 65 /* CMU_CPUCL */ 66 #define CLK_FOUT_CPUCL_PLL 1 67 #define CLK_MOUT_CPUCL_PLL 2 68 #define CLK_MOUT_CPUCL_SWITCH_USER 3 69 #define CLK_DOUT_CPUCL_CPU 4 70 #define CLK_DOUT_CPUCL_CLUSTER_ACLK 5 71 #define CLK_DOUT_CPUCL_CLUSTER_PCLKDBG 6 72 #define CLK_DOUT_CPUCL_CLUSTER_CNTCLK 7 73 #define CLK_DOUT_CPUCL_CLUSTER_ATCLK 8 74 #define CLK_DOUT_CPUCL_PCLK 9 75 #define CLK_DOUT_CPUCL_CMUREF 10 76 #define CLK_DOUT_CPUCL_DBG 11 77 #define CLK_DOUT_CPUCL_PCLKDBG 12 78 #define CLK_GOUT_CPUCL_CLUSTER_CPU 13 79 #define CLK_GOUT_CPUCL_SHORTSTOP 14 80 #define CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_PCLKDBG 15 81 #define CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_ATCLK 16 82 83 /* CMU_FSYS */ 84 #define CLK_FOUT_FSYS_PLL 1 85 #define CLK_MOUT_FSYS_SCAN0_USER 2 86 #define CLK_MOUT_FSYS_SCAN1_USER 3 87 #define CLK_MOUT_FSYS_BUS_USER 4 88 #define CLK_MOUT_FSYS_MMC_USER 5 89 #define CLK_DOUT_FSYS_PCIE_PIPE 6 90 #define CLK_DOUT_FSYS_ADC 7 91 #define CLK_DOUT_FSYS_PCIE_PHY_REFCLK_SYSPLL 8 92 #define CLK_DOUT_FSYS_EQOS_INT125 9 93 #define CLK_DOUT_FSYS_OTP_MEM 10 94 #define CLK_DOUT_FSYS_SCLK_UART 11 95 #define CLK_DOUT_FSYS_EQOS_25 12 96 #define CLK_DOUT_FSYS_EQOS_2p5 13 97 #define CLK_DOUT_FSYS_BUS300 14 98 #define CLK_DOUT_FSYS_BUS_QSPI 15 99 #define CLK_DOUT_FSYS_MMC_CARD0 16 100 #define CLK_DOUT_FSYS_MMC_CARD1 17 101 #define CLK_DOUT_SCAN_CLK_FSYS_125 18 102 #define CLK_DOUT_FSYS_QSPI 19 103 #define CLK_DOUT_FSYS_SFMC_NAND 20 104 #define CLK_DOUT_FSYS_SCAN_CLK_MMC 21 105 #define CLK_GOUT_FSYS_USB20DRD_IPCLKPORT_ACLK_PHYCTRL_20 22 106 #define CLK_GOUT_FSYS_USB20DRD_IPCLKPORT_BUS_CLK_EARLY 23 107 #define CLK_GOUT_FSYS_XHB_USB_IPCLKPORT_CLK 24 108 #define CLK_GOUT_FSYS_XHB_AHBBR_IPCLKPORT_CLK 25 109 #define CLK_GOUT_FSYS_I2C0_IPCLKPORT_I_PCLK 26 110 #define CLK_GOUT_FSYS_I2C1_IPCLKPORT_I_PCLK 27 111 #define CLK_GOUT_FSYS_PWM_IPCLKPORT_I_PCLK_S0 28 112 #define CLK_GOUT_FSYS_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG 29 113 #define CLK_GOUT_FSYS_DWC_PCIE_CTL_INXT_0_SLV_ACLK_UG 30 114 #define CLK_GOUT_FSYS_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG 31 115 #define CLK_GOUT_FSYS_PIPE_PAL_INST_0_I_APB_PCLK 32 116 #define CLK_GOUT_FSYS_EQOS_TOP_IPCLKPORT_ACLK_I 33 117 #define CLK_GOUT_FSYS_EQOS_TOP_IPCLKPORT_CLK_CSR_I 34 118 #define CLK_GOUT_FSYS_EQOS_TOP_IPCLKPORT_I_RGMII_TXCLK_2P5 35 119 #define CLK_GOUT_FSYS_SFMC_IPCLKPORT_I_ACLK_NAND 36 120 #define CLK_GOUT_FSYS_MMC0_IPCLKPORT_SDCLKIN 37 121 #define CLK_GOUT_FSYS_MMC0_IPCLKPORT_I_ACLK 38 122 #define CLK_GOUT_FSYS_MMC1_IPCLKPORT_SDCLKIN 39 123 #define CLK_GOUT_FSYS_MMC1_IPCLKPORT_I_ACLK 40 124 #define CLK_GOUT_FSYS_PCIE_PHY_REFCLK_IN 41 125 #define CLK_GOUT_FSYS_UART0_PCLK 42 126 #define CLK_GOUT_FSYS_UART0_SCLK_UART 43 127 #define CLK_GOUT_FSYS_BUS_QSPI 44 128 #define CLK_GOUT_FSYS_QSPI_IPCLKPORT_HCLK 45 129 #define CLK_GOUT_FSYS_QSPI_IPCLKPORT_SSI_CLK 46 130 131 /* CMU_IMEM */ 132 #define CLK_MOUT_IMEM_ACLK_USER 1 133 #define CLK_MOUT_IMEM_GIC_CA53 2 134 #define CLK_MOUT_IMEM_GIC_CA5 3 135 #define CLK_MOUT_IMEM_JPEG_USER 4 136 #define CLK_GOUT_IMEM_MCT_PCLK 5 137 #define CLK_GOUT_IMEM_PCLK_TMU0_APBIF 6 138 139 /* CMU_PERI */ 140 #define CLK_MOUT_PERI_IP_USER 1 141 #define CLK_MOUT_PERI_AUDIO_USER 2 142 #define CLK_MOUT_PERI_I2S0 3 143 #define CLK_MOUT_PERI_I2S1 4 144 #define CLK_MOUT_PERI_DISP_USER 5 145 #define CLK_DOUT_PERI_SPI 6 146 #define CLK_DOUT_PERI_UART1 7 147 #define CLK_DOUT_PERI_UART2 8 148 #define CLK_DOUT_PERI_PCLK 9 149 #define CLK_DOUT_PERI_I2S0 10 150 #define CLK_DOUT_PERI_I2S1 11 151 #define CLK_DOUT_PERI_DSIM 12 152 #define CLK_GOUT_PERI_UART1_PCLK 13 153 #define CLK_GOUT_PERI_UART1_SCLK_UART 14 154 #define CLK_GOUT_PERI_UART2_PCLK 15 155 #define CLK_GOUT_PERI_UART2_SCLK_UART 16 156 #define CLK_GOUT_PERI_I2C2_IPCLKPORT_I_PCLK 17 157 #define CLK_GOUT_PERI_I2C3_IPCLKPORT_I_PCLK 18 158 #define CLK_GOUT_PERI_SPI0_PCLK 19 159 #define CLK_GOUT_PERI_SPI0_SCLK_SPI 20 160 #define CLK_GOUT_PERI_APB_ASYNC_DSIM_IPCLKPORT_PCLKS 21 161 #define CLK_GOUT_PERI_I2SSC0_IPCLKPORT_CLK_HST 22 162 #define CLK_GOUT_PERI_I2SSC1_IPCLKPORT_CLK_HST 23 163 #define CLK_GOUT_PERI_AUDIO_OUT_IPCLKPORT_CLK 24 164 #define CLK_GOUT_PERI_I2SSC0_IPCLKPORT_CLK 25 165 #define CLK_GOUT_PERI_I2SSC1_IPCLKPORT_CLK 26 166 #define CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_APB_CLK 27 167 #define CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_AXI_CLK 28 168 169 #endif /* _DT_BINDINGS_CLOCK_ARTPEC8_H */ 170