1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2024 Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
4 * Author: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
5 *
6 * Common Clock Framework support for Exynos8895 SoC.
7 */
8
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/of.h>
12 #include <linux/platform_device.h>
13
14 #include <dt-bindings/clock/samsung,exynos8895.h>
15
16 #include "clk.h"
17 #include "clk-exynos-arm64.h"
18
19 /* NOTE: Must be equal to the last clock ID increased by one */
20 #define CLKS_NR_TOP (CLK_GOUT_CMU_VPU_BUS + 1)
21 #define CLKS_NR_FSYS0 (CLK_GOUT_FSYS0_XIU_P_FSYS0_ACLK + 1)
22 #define CLKS_NR_FSYS1 (CLK_GOUT_FSYS1_XIU_P_FSYS1_ACLK + 1)
23 #define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_USI03_I_SCLK_USI + 1)
24 #define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_XIU_P_PERIC1_ACLK + 1)
25 #define CLKS_NR_PERIS (CLK_GOUT_PERIS_XIU_P_PERIS_ACLK + 1)
26
27 /* ---- CMU_TOP ------------------------------------------------------------- */
28
29 /* Register Offset definitions for CMU_TOP (0x15a80000) */
30 #define PLL_LOCKTIME_PLL_SHARED0 0x0000
31 #define PLL_LOCKTIME_PLL_SHARED1 0x0004
32 #define PLL_LOCKTIME_PLL_SHARED2 0x0008
33 #define PLL_LOCKTIME_PLL_SHARED3 0x000c
34 #define PLL_LOCKTIME_PLL_SHARED4 0x0010
35 #define PLL_CON0_MUX_CP2AP_MIF_CLK_USER 0x0100
36 #define PLL_CON2_MUX_CP2AP_MIF_CLK_USER 0x0108
37 #define PLL_CON0_PLL_SHARED0 0x0120
38 #define PLL_CON0_PLL_SHARED1 0x0140
39 #define PLL_CON0_PLL_SHARED2 0x0160
40 #define PLL_CON0_PLL_SHARED3 0x0180
41 #define PLL_CON0_PLL_SHARED4 0x01a0
42 #define CLK_CON_MUX_MUX_CLKCMU_ABOX_CPUABOX 0x1000
43 #define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1004
44 #define CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS 0x1008
45 #define CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS 0x100c
46 #define CLK_CON_MUX_MUX_CLKCMU_BUSC_BUSPHSI2C 0x1010
47 #define CLK_CON_MUX_MUX_CLKCMU_CAM_BUS 0x1014
48 #define CLK_CON_MUX_MUX_CLKCMU_CAM_TPU0 0x1018
49 #define CLK_CON_MUX_MUX_CLKCMU_CAM_TPU1 0x101c
50 #define CLK_CON_MUX_MUX_CLKCMU_CAM_VRA 0x1020
51 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0 0x1024
52 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1 0x1028
53 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2 0x102c
54 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3 0x1030
55 #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1034
56 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x1038
57 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x103c
58 #define CLK_CON_MUX_MUX_CLKCMU_DBG_BUS 0x1040
59 #define CLK_CON_MUX_MUX_CLKCMU_DCAM_BUS 0x1044
60 #define CLK_CON_MUX_MUX_CLKCMU_DCAM_IMGD 0x1048
61 #define CLK_CON_MUX_MUX_CLKCMU_DPU_BUS 0x104c
62 #define CLK_CON_MUX_MUX_CLKCMU_DROOPDETECTOR 0x1050
63 #define CLK_CON_MUX_MUX_CLKCMU_DSP_BUS 0x1054
64 #define CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS 0x1058
65 #define CLK_CON_MUX_MUX_CLKCMU_FSYS0_DPGTC 0x105c
66 #define CLK_CON_MUX_MUX_CLKCMU_FSYS0_MMC_EMBD 0x1060
67 #define CLK_CON_MUX_MUX_CLKCMU_FSYS0_UFS_EMBD 0x1064
68 #define CLK_CON_MUX_MUX_CLKCMU_FSYS0_USBDRD30 0x1068
69 #define CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS 0x106c
70 #define CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD 0x1070
71 #define CLK_CON_MUX_MUX_CLKCMU_FSYS1_PCIE 0x1074
72 #define CLK_CON_MUX_MUX_CLKCMU_FSYS1_UFS_CARD 0x1078
73 #define CLK_CON_MUX_MUX_CLKCMU_G2D_G2D 0x107c
74 #define CLK_CON_MUX_MUX_CLKCMU_G2D_JPEG 0x1080
75 #define CLK_CON_MUX_MUX_CLKCMU_HPM 0x1084
76 #define CLK_CON_MUX_MUX_CLKCMU_IMEM_BUS 0x1088
77 #define CLK_CON_MUX_MUX_CLKCMU_ISPHQ_BUS 0x108c
78 #define CLK_CON_MUX_MUX_CLKCMU_ISPLP_BUS 0x1090
79 #define CLK_CON_MUX_MUX_CLKCMU_IVA_BUS 0x1094
80 #define CLK_CON_MUX_MUX_CLKCMU_MFC_BUS 0x1098
81 #define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x109c
82 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS 0x10a0
83 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_UART_DBG 0x10a4
84 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI00 0x10a8
85 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI01 0x10ac
86 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI02 0x10b0
87 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI03 0x10b4
88 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS 0x10b8
89 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPEEDY2 0x10bc
90 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPI_CAM0 0x10c0
91 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPI_CAM1 0x10c4
92 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_UART_BT 0x10c8
93 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI04 0x10cc
94 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI05 0x10d0
95 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI06 0x10d4
96 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI07 0x10d8
97 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI08 0x10dc
98 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI09 0x10e0
99 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI10 0x10e4
100 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI11 0x10e8
101 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI12 0x10ec
102 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI13 0x10f0
103 #define CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS 0x10f4
104 #define CLK_CON_MUX_MUX_CLKCMU_SRDZ_BUS 0x10f8
105 #define CLK_CON_MUX_MUX_CLKCMU_SRDZ_IMGD 0x10fc
106 #define CLK_CON_MUX_MUX_CLKCMU_VPU_BUS 0x1100
107 #define CLK_CON_MUX_MUX_CLK_CMU_CMUREF 0x1104
108 #define CLK_CON_MUX_MUX_CMU_CMUREF 0x1108
109 #define CLK_CON_DIV_CLKCMU_ABOX_CPUABOX 0x1800
110 #define CLK_CON_DIV_CLKCMU_APM_BUS 0x1804
111 #define CLK_CON_DIV_CLKCMU_BUS1_BUS 0x1808
112 #define CLK_CON_DIV_CLKCMU_BUSC_BUS 0x180c
113 #define CLK_CON_DIV_CLKCMU_BUSC_BUSPHSI2C 0x1810
114 #define CLK_CON_DIV_CLKCMU_CAM_BUS 0x1814
115 #define CLK_CON_DIV_CLKCMU_CAM_TPU0 0x1818
116 #define CLK_CON_DIV_CLKCMU_CAM_TPU1 0x181c
117 #define CLK_CON_DIV_CLKCMU_CAM_VRA 0x1820
118 #define CLK_CON_DIV_CLKCMU_CIS_CLK0 0x1824
119 #define CLK_CON_DIV_CLKCMU_CIS_CLK1 0x1828
120 #define CLK_CON_DIV_CLKCMU_CIS_CLK2 0x182c
121 #define CLK_CON_DIV_CLKCMU_CIS_CLK3 0x1830
122 #define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1834
123 #define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1838
124 #define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x183c
125 #define CLK_CON_DIV_CLKCMU_DBG_BUS 0x1840
126 #define CLK_CON_DIV_CLKCMU_DCAM_BUS 0x1844
127 #define CLK_CON_DIV_CLKCMU_DCAM_IMGD 0x1848
128 #define CLK_CON_DIV_CLKCMU_DPU_BUS 0x184c
129 #define CLK_CON_DIV_CLKCMU_DSP_BUS 0x1850
130 #define CLK_CON_DIV_CLKCMU_FSYS0_BUS 0x1854
131 #define CLK_CON_DIV_CLKCMU_FSYS0_DPGTC 0x1858
132 #define CLK_CON_DIV_CLKCMU_FSYS0_MMC_EMBD 0x185c
133 #define CLK_CON_DIV_CLKCMU_FSYS0_UFS_EMBD 0x1860
134 #define CLK_CON_DIV_CLKCMU_FSYS0_USBDRD30 0x1864
135 #define CLK_CON_DIV_CLKCMU_FSYS1_BUS 0x1868
136 #define CLK_CON_DIV_CLKCMU_FSYS1_MMC_CARD 0x186c
137 #define CLK_CON_DIV_CLKCMU_FSYS1_PCIE 0x1870
138 #define CLK_CON_DIV_CLKCMU_FSYS1_UFS_CARD 0x1874
139 #define CLK_CON_DIV_CLKCMU_G2D_G2D 0x1878
140 #define CLK_CON_DIV_CLKCMU_G2D_JPEG 0x187c
141 #define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x1880
142 #define CLK_CON_DIV_CLKCMU_HPM 0x1884
143 #define CLK_CON_DIV_CLKCMU_IMEM_BUS 0x1888
144 #define CLK_CON_DIV_CLKCMU_ISPHQ_BUS 0x188c
145 #define CLK_CON_DIV_CLKCMU_ISPLP_BUS 0x1890
146 #define CLK_CON_DIV_CLKCMU_IVA_BUS 0x1894
147 #define CLK_CON_DIV_CLKCMU_MFC_BUS 0x1898
148 #define CLK_CON_DIV_CLKCMU_MODEM_SHARED0 0x189c
149 #define CLK_CON_DIV_CLKCMU_MODEM_SHARED1 0x18a0
150 #define CLK_CON_DIV_CLKCMU_OTP 0x18a4
151 #define CLK_CON_DIV_CLKCMU_PERIC0_BUS 0x18a8
152 #define CLK_CON_DIV_CLKCMU_PERIC0_UART_DBG 0x18ac
153 #define CLK_CON_DIV_CLKCMU_PERIC0_USI00 0x18b0
154 #define CLK_CON_DIV_CLKCMU_PERIC0_USI01 0x18b4
155 #define CLK_CON_DIV_CLKCMU_PERIC0_USI02 0x18b8
156 #define CLK_CON_DIV_CLKCMU_PERIC0_USI03 0x18bc
157 #define CLK_CON_DIV_CLKCMU_PERIC1_BUS 0x18c0
158 #define CLK_CON_DIV_CLKCMU_PERIC1_SPEEDY2 0x18c4
159 #define CLK_CON_DIV_CLKCMU_PERIC1_SPI_CAM0 0x18c8
160 #define CLK_CON_DIV_CLKCMU_PERIC1_SPI_CAM1 0x18cc
161 #define CLK_CON_DIV_CLKCMU_PERIC1_UART_BT 0x18d0
162 #define CLK_CON_DIV_CLKCMU_PERIC1_USI04 0x18d4
163 #define CLK_CON_DIV_CLKCMU_PERIC1_USI05 0x18d8
164 #define CLK_CON_DIV_CLKCMU_PERIC1_USI06 0x18dc
165 #define CLK_CON_DIV_CLKCMU_PERIC1_USI07 0x18e0
166 #define CLK_CON_DIV_CLKCMU_PERIC1_USI08 0x18e4
167 #define CLK_CON_DIV_CLKCMU_PERIC1_USI09 0x18e8
168 #define CLK_CON_DIV_CLKCMU_PERIC1_USI10 0x18ec
169 #define CLK_CON_DIV_CLKCMU_PERIC1_USI11 0x18f0
170 #define CLK_CON_DIV_CLKCMU_PERIC1_USI12 0x18f4
171 #define CLK_CON_DIV_CLKCMU_PERIC1_USI13 0x18f8
172 #define CLK_CON_DIV_CLKCMU_PERIS_BUS 0x18fc
173 #define CLK_CON_DIV_CLKCMU_SRDZ_BUS 0x1900
174 #define CLK_CON_DIV_CLKCMU_SRDZ_IMGD 0x1904
175 #define CLK_CON_DIV_CLKCMU_VPU_BUS 0x1908
176 #define CLK_CON_DIV_DIV_CLK_CMU_CMUREF 0x190c
177 #define CLK_CON_DIV_DIV_CP2AP_MIF_CLK_DIV2 0x1910
178 #define CLK_CON_DIV_DIV_PLL_SHARED0_DIV2 0x1914
179 #define CLK_CON_DIV_DIV_PLL_SHARED0_DIV4 0x1918
180 #define CLK_CON_DIV_DIV_PLL_SHARED1_DIV2 0x191c
181 #define CLK_CON_DIV_DIV_PLL_SHARED1_DIV4 0x1920
182 #define CLK_CON_DIV_DIV_PLL_SHARED2_DIV2 0x1924
183 #define CLK_CON_DIV_DIV_PLL_SHARED3_DIV2 0x1928
184 #define CLK_CON_DIV_DIV_PLL_SHARED4_DIV2 0x192c
185 #define CLK_CON_GAT_CLKCMU_DROOPDETECTOR 0x2000
186 #define CLK_CON_GAT_CLKCMU_MIF_SWITCH 0x2004
187 #define CLK_CON_GAT_GATE_CLKCMU_ABOX_CPUABOX 0x2008
188 #define CLK_CON_GAT_GATE_CLKCMU_APM_BUS 0x200c
189 #define CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS 0x2010
190 #define CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS 0x2014
191 #define CLK_CON_GAT_GATE_CLKCMU_BUSC_BUSPHSI2C 0x2018
192 #define CLK_CON_GAT_GATE_CLKCMU_CAM_BUS 0x201c
193 #define CLK_CON_GAT_GATE_CLKCMU_CAM_TPU0 0x2020
194 #define CLK_CON_GAT_GATE_CLKCMU_CAM_TPU1 0x2024
195 #define CLK_CON_GAT_GATE_CLKCMU_CAM_VRA 0x2028
196 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0 0x202c
197 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1 0x2030
198 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2 0x2034
199 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3 0x2038
200 #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x203c
201 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH 0x2040
202 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH 0x2044
203 #define CLK_CON_GAT_GATE_CLKCMU_DBG_BUS 0x2048
204 #define CLK_CON_GAT_GATE_CLKCMU_DCAM_BUS 0x204c
205 #define CLK_CON_GAT_GATE_CLKCMU_DCAM_IMGD 0x2050
206 #define CLK_CON_GAT_GATE_CLKCMU_DPU_BUS 0x2054
207 #define CLK_CON_GAT_GATE_CLKCMU_DSP_BUS 0x2058
208 #define CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS 0x205c
209 #define CLK_CON_GAT_GATE_CLKCMU_FSYS0_DPGTC 0x2060
210 #define CLK_CON_GAT_GATE_CLKCMU_FSYS0_MMC_EMBD 0x2064
211 #define CLK_CON_GAT_GATE_CLKCMU_FSYS0_UFS_EMBD 0x2068
212 #define CLK_CON_GAT_GATE_CLKCMU_FSYS0_USBDRD30 0x206c
213 #define CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS 0x2070
214 #define CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD 0x2074
215 #define CLK_CON_GAT_GATE_CLKCMU_FSYS1_PCIE 0x2078
216 #define CLK_CON_GAT_GATE_CLKCMU_FSYS1_UFS_CARD 0x207c
217 #define CLK_CON_GAT_GATE_CLKCMU_G2D_G2D 0x2080
218 #define CLK_CON_GAT_GATE_CLKCMU_G2D_JPEG 0x2084
219 #define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x2088
220 #define CLK_CON_GAT_GATE_CLKCMU_HPM 0x208c
221 #define CLK_CON_GAT_GATE_CLKCMU_IMEM_BUS 0x2090
222 #define CLK_CON_GAT_GATE_CLKCMU_ISPHQ_BUS 0x2094
223 #define CLK_CON_GAT_GATE_CLKCMU_ISPLP_BUS 0x2098
224 #define CLK_CON_GAT_GATE_CLKCMU_IVA_BUS 0x209c
225 #define CLK_CON_GAT_GATE_CLKCMU_MFC_BUS 0x20a0
226 #define CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0 0x20a4
227 #define CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1 0x20a8
228 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS 0x20ac
229 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_UART_DBG 0x20b0
230 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI00 0x20b4
231 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI01 0x20b8
232 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI02 0x20bc
233 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI03 0x20c0
234 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS 0x20c4
235 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPEEDY2 0x20c8
236 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPI_CAM0 0x20cc
237 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPI_CAM1 0x20d0
238 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_UART_BT 0x20d4
239 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI04 0x20d8
240 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI05 0x20dc
241 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI06 0x20e0
242 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI07 0x20e4
243 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI08 0x20e8
244 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI09 0x20ec
245 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI10 0x20f0
246 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI11 0x20f4
247 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI12 0x20f8
248 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI13 0x20fc
249 #define CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS 0x2100
250 #define CLK_CON_GAT_GATE_CLKCMU_SRDZ_BUS 0x2104
251 #define CLK_CON_GAT_GATE_CLKCMU_SRDZ_IMGD 0x2108
252 #define CLK_CON_GAT_GATE_CLKCMU_VPU_BUS 0x210c
253
254 static const unsigned long top_clk_regs[] __initconst = {
255 PLL_LOCKTIME_PLL_SHARED0,
256 PLL_LOCKTIME_PLL_SHARED1,
257 PLL_LOCKTIME_PLL_SHARED2,
258 PLL_LOCKTIME_PLL_SHARED3,
259 PLL_LOCKTIME_PLL_SHARED4,
260 PLL_CON0_MUX_CP2AP_MIF_CLK_USER,
261 PLL_CON2_MUX_CP2AP_MIF_CLK_USER,
262 PLL_CON0_PLL_SHARED0,
263 PLL_CON0_PLL_SHARED1,
264 PLL_CON0_PLL_SHARED2,
265 PLL_CON0_PLL_SHARED3,
266 PLL_CON0_PLL_SHARED4,
267 CLK_CON_MUX_MUX_CLKCMU_ABOX_CPUABOX,
268 CLK_CON_MUX_MUX_CLKCMU_APM_BUS,
269 CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS,
270 CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS,
271 CLK_CON_MUX_MUX_CLKCMU_BUSC_BUSPHSI2C,
272 CLK_CON_MUX_MUX_CLKCMU_CAM_BUS,
273 CLK_CON_MUX_MUX_CLKCMU_CAM_TPU0,
274 CLK_CON_MUX_MUX_CLKCMU_CAM_TPU1,
275 CLK_CON_MUX_MUX_CLKCMU_CAM_VRA,
276 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0,
277 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1,
278 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2,
279 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3,
280 CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,
281 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
282 CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
283 CLK_CON_MUX_MUX_CLKCMU_DBG_BUS,
284 CLK_CON_MUX_MUX_CLKCMU_DCAM_BUS,
285 CLK_CON_MUX_MUX_CLKCMU_DCAM_IMGD,
286 CLK_CON_MUX_MUX_CLKCMU_DPU_BUS,
287 CLK_CON_MUX_MUX_CLKCMU_DROOPDETECTOR,
288 CLK_CON_MUX_MUX_CLKCMU_DSP_BUS,
289 CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS,
290 CLK_CON_MUX_MUX_CLKCMU_FSYS0_DPGTC,
291 CLK_CON_MUX_MUX_CLKCMU_FSYS0_MMC_EMBD,
292 CLK_CON_MUX_MUX_CLKCMU_FSYS0_UFS_EMBD,
293 CLK_CON_MUX_MUX_CLKCMU_FSYS0_USBDRD30,
294 CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS,
295 CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD,
296 CLK_CON_MUX_MUX_CLKCMU_FSYS1_PCIE,
297 CLK_CON_MUX_MUX_CLKCMU_FSYS1_UFS_CARD,
298 CLK_CON_MUX_MUX_CLKCMU_G2D_G2D,
299 CLK_CON_MUX_MUX_CLKCMU_G2D_JPEG,
300 CLK_CON_MUX_MUX_CLKCMU_HPM,
301 CLK_CON_MUX_MUX_CLKCMU_IMEM_BUS,
302 CLK_CON_MUX_MUX_CLKCMU_ISPHQ_BUS,
303 CLK_CON_MUX_MUX_CLKCMU_ISPLP_BUS,
304 CLK_CON_MUX_MUX_CLKCMU_IVA_BUS,
305 CLK_CON_MUX_MUX_CLKCMU_MFC_BUS,
306 CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH,
307 CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS,
308 CLK_CON_MUX_MUX_CLKCMU_PERIC0_UART_DBG,
309 CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI00,
310 CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI01,
311 CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI02,
312 CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI03,
313 CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS,
314 CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPEEDY2,
315 CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPI_CAM0,
316 CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPI_CAM1,
317 CLK_CON_MUX_MUX_CLKCMU_PERIC1_UART_BT,
318 CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI04,
319 CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI05,
320 CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI06,
321 CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI07,
322 CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI08,
323 CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI09,
324 CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI10,
325 CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI11,
326 CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI12,
327 CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI13,
328 CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS,
329 CLK_CON_MUX_MUX_CLKCMU_SRDZ_BUS,
330 CLK_CON_MUX_MUX_CLKCMU_SRDZ_IMGD,
331 CLK_CON_MUX_MUX_CLKCMU_VPU_BUS,
332 CLK_CON_MUX_MUX_CLK_CMU_CMUREF,
333 CLK_CON_MUX_MUX_CMU_CMUREF,
334 CLK_CON_DIV_CLKCMU_ABOX_CPUABOX,
335 CLK_CON_DIV_CLKCMU_APM_BUS,
336 CLK_CON_DIV_CLKCMU_BUS1_BUS,
337 CLK_CON_DIV_CLKCMU_BUSC_BUS,
338 CLK_CON_DIV_CLKCMU_BUSC_BUSPHSI2C,
339 CLK_CON_DIV_CLKCMU_CAM_BUS,
340 CLK_CON_DIV_CLKCMU_CAM_TPU0,
341 CLK_CON_DIV_CLKCMU_CAM_TPU1,
342 CLK_CON_DIV_CLKCMU_CAM_VRA,
343 CLK_CON_DIV_CLKCMU_CIS_CLK0,
344 CLK_CON_DIV_CLKCMU_CIS_CLK1,
345 CLK_CON_DIV_CLKCMU_CIS_CLK2,
346 CLK_CON_DIV_CLKCMU_CIS_CLK3,
347 CLK_CON_DIV_CLKCMU_CORE_BUS,
348 CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH,
349 CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH,
350 CLK_CON_DIV_CLKCMU_DBG_BUS,
351 CLK_CON_DIV_CLKCMU_DCAM_BUS,
352 CLK_CON_DIV_CLKCMU_DCAM_IMGD,
353 CLK_CON_DIV_CLKCMU_DPU_BUS,
354 CLK_CON_DIV_CLKCMU_DSP_BUS,
355 CLK_CON_DIV_CLKCMU_FSYS0_BUS,
356 CLK_CON_DIV_CLKCMU_FSYS0_DPGTC,
357 CLK_CON_DIV_CLKCMU_FSYS0_MMC_EMBD,
358 CLK_CON_DIV_CLKCMU_FSYS0_UFS_EMBD,
359 CLK_CON_DIV_CLKCMU_FSYS0_USBDRD30,
360 CLK_CON_DIV_CLKCMU_FSYS1_BUS,
361 CLK_CON_DIV_CLKCMU_FSYS1_MMC_CARD,
362 CLK_CON_DIV_CLKCMU_FSYS1_PCIE,
363 CLK_CON_DIV_CLKCMU_FSYS1_UFS_CARD,
364 CLK_CON_DIV_CLKCMU_G2D_G2D,
365 CLK_CON_DIV_CLKCMU_G2D_JPEG,
366 CLK_CON_DIV_CLKCMU_G3D_SWITCH,
367 CLK_CON_DIV_CLKCMU_HPM,
368 CLK_CON_DIV_CLKCMU_IMEM_BUS,
369 CLK_CON_DIV_CLKCMU_ISPHQ_BUS,
370 CLK_CON_DIV_CLKCMU_ISPLP_BUS,
371 CLK_CON_DIV_CLKCMU_IVA_BUS,
372 CLK_CON_DIV_CLKCMU_MFC_BUS,
373 CLK_CON_DIV_CLKCMU_MODEM_SHARED0,
374 CLK_CON_DIV_CLKCMU_MODEM_SHARED1,
375 CLK_CON_DIV_CLKCMU_OTP,
376 CLK_CON_DIV_CLKCMU_PERIC0_BUS,
377 CLK_CON_DIV_CLKCMU_PERIC0_UART_DBG,
378 CLK_CON_DIV_CLKCMU_PERIC0_USI00,
379 CLK_CON_DIV_CLKCMU_PERIC0_USI01,
380 CLK_CON_DIV_CLKCMU_PERIC0_USI02,
381 CLK_CON_DIV_CLKCMU_PERIC0_USI03,
382 CLK_CON_DIV_CLKCMU_PERIC1_BUS,
383 CLK_CON_DIV_CLKCMU_PERIC1_SPEEDY2,
384 CLK_CON_DIV_CLKCMU_PERIC1_SPI_CAM0,
385 CLK_CON_DIV_CLKCMU_PERIC1_SPI_CAM1,
386 CLK_CON_DIV_CLKCMU_PERIC1_UART_BT,
387 CLK_CON_DIV_CLKCMU_PERIC1_USI04,
388 CLK_CON_DIV_CLKCMU_PERIC1_USI05,
389 CLK_CON_DIV_CLKCMU_PERIC1_USI06,
390 CLK_CON_DIV_CLKCMU_PERIC1_USI07,
391 CLK_CON_DIV_CLKCMU_PERIC1_USI08,
392 CLK_CON_DIV_CLKCMU_PERIC1_USI09,
393 CLK_CON_DIV_CLKCMU_PERIC1_USI10,
394 CLK_CON_DIV_CLKCMU_PERIC1_USI11,
395 CLK_CON_DIV_CLKCMU_PERIC1_USI12,
396 CLK_CON_DIV_CLKCMU_PERIC1_USI13,
397 CLK_CON_DIV_CLKCMU_PERIS_BUS,
398 CLK_CON_DIV_CLKCMU_SRDZ_BUS,
399 CLK_CON_DIV_CLKCMU_SRDZ_IMGD,
400 CLK_CON_DIV_CLKCMU_VPU_BUS,
401 CLK_CON_DIV_DIV_CLK_CMU_CMUREF,
402 CLK_CON_DIV_DIV_CP2AP_MIF_CLK_DIV2,
403 CLK_CON_DIV_DIV_PLL_SHARED0_DIV2,
404 CLK_CON_DIV_DIV_PLL_SHARED0_DIV4,
405 CLK_CON_DIV_DIV_PLL_SHARED1_DIV2,
406 CLK_CON_DIV_DIV_PLL_SHARED1_DIV4,
407 CLK_CON_DIV_DIV_PLL_SHARED2_DIV2,
408 CLK_CON_DIV_DIV_PLL_SHARED3_DIV2,
409 CLK_CON_DIV_DIV_PLL_SHARED4_DIV2,
410 CLK_CON_GAT_CLKCMU_DROOPDETECTOR,
411 CLK_CON_GAT_CLKCMU_MIF_SWITCH,
412 CLK_CON_GAT_GATE_CLKCMU_ABOX_CPUABOX,
413 CLK_CON_GAT_GATE_CLKCMU_APM_BUS,
414 CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS,
415 CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS,
416 CLK_CON_GAT_GATE_CLKCMU_BUSC_BUSPHSI2C,
417 CLK_CON_GAT_GATE_CLKCMU_CAM_BUS,
418 CLK_CON_GAT_GATE_CLKCMU_CAM_TPU0,
419 CLK_CON_GAT_GATE_CLKCMU_CAM_TPU1,
420 CLK_CON_GAT_GATE_CLKCMU_CAM_VRA,
421 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0,
422 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1,
423 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2,
424 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3,
425 CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
426 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH,
427 CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH,
428 CLK_CON_GAT_GATE_CLKCMU_DBG_BUS,
429 CLK_CON_GAT_GATE_CLKCMU_DCAM_BUS,
430 CLK_CON_GAT_GATE_CLKCMU_DCAM_IMGD,
431 CLK_CON_GAT_GATE_CLKCMU_DPU_BUS,
432 CLK_CON_GAT_GATE_CLKCMU_DSP_BUS,
433 CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS,
434 CLK_CON_GAT_GATE_CLKCMU_FSYS0_DPGTC,
435 CLK_CON_GAT_GATE_CLKCMU_FSYS0_MMC_EMBD,
436 CLK_CON_GAT_GATE_CLKCMU_FSYS0_UFS_EMBD,
437 CLK_CON_GAT_GATE_CLKCMU_FSYS0_USBDRD30,
438 CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS,
439 CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD,
440 CLK_CON_GAT_GATE_CLKCMU_FSYS1_PCIE,
441 CLK_CON_GAT_GATE_CLKCMU_FSYS1_UFS_CARD,
442 CLK_CON_GAT_GATE_CLKCMU_G2D_G2D,
443 CLK_CON_GAT_GATE_CLKCMU_G2D_JPEG,
444 CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH,
445 CLK_CON_GAT_GATE_CLKCMU_HPM,
446 CLK_CON_GAT_GATE_CLKCMU_IMEM_BUS,
447 CLK_CON_GAT_GATE_CLKCMU_ISPHQ_BUS,
448 CLK_CON_GAT_GATE_CLKCMU_ISPLP_BUS,
449 CLK_CON_GAT_GATE_CLKCMU_IVA_BUS,
450 CLK_CON_GAT_GATE_CLKCMU_MFC_BUS,
451 CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0,
452 CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1,
453 CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS,
454 CLK_CON_GAT_GATE_CLKCMU_PERIC0_UART_DBG,
455 CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI00,
456 CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI01,
457 CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI02,
458 CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI03,
459 CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS,
460 CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPEEDY2,
461 CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPI_CAM0,
462 CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPI_CAM1,
463 CLK_CON_GAT_GATE_CLKCMU_PERIC1_UART_BT,
464 CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI04,
465 CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI05,
466 CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI06,
467 CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI07,
468 CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI08,
469 CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI09,
470 CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI10,
471 CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI11,
472 CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI12,
473 CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI13,
474 CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS,
475 CLK_CON_GAT_GATE_CLKCMU_SRDZ_BUS,
476 CLK_CON_GAT_GATE_CLKCMU_SRDZ_IMGD,
477 CLK_CON_GAT_GATE_CLKCMU_VPU_BUS,
478 };
479
480 static const struct samsung_pll_rate_table pll_shared0_rate_table[] __initconst = {
481 PLL_35XX_RATE(26 * MHZ, 2132000000U, 328, 4, 0),
482 };
483
484 static const struct samsung_pll_rate_table pll_shared1_rate_table[] __initconst = {
485 PLL_35XX_RATE(26 * MHZ, 1865500000U, 287, 4, 0),
486 };
487
488 static const struct samsung_pll_rate_table pll_shared2_rate_table[] __initconst = {
489 PLL_35XX_RATE(26 * MHZ, 800000000U, 400, 13, 0),
490 };
491
492 static const struct samsung_pll_rate_table pll_shared3_rate_table[] __initconst = {
493 PLL_35XX_RATE(26 * MHZ, 630000000U, 315, 13, 0),
494 };
495
496 static const struct samsung_pll_rate_table pll_shared4_rate_table[] __initconst = {
497 PLL_35XX_RATE(26 * MHZ, 667333333U, 154, 6, 0),
498 };
499
500 static const struct samsung_pll_clock top_pll_clks[] __initconst = {
501 /* CMU_TOP_PURECLKCOMP */
502 PLL(pll_1051x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
503 PLL_LOCKTIME_PLL_SHARED0, PLL_CON0_PLL_SHARED0,
504 pll_shared0_rate_table),
505 PLL(pll_1051x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
506 PLL_LOCKTIME_PLL_SHARED1, PLL_CON0_PLL_SHARED1,
507 pll_shared1_rate_table),
508 PLL(pll_1052x, CLK_FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk",
509 PLL_LOCKTIME_PLL_SHARED2, PLL_CON0_PLL_SHARED2,
510 pll_shared2_rate_table),
511 PLL(pll_1052x, CLK_FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk",
512 PLL_LOCKTIME_PLL_SHARED3, PLL_CON0_PLL_SHARED3,
513 pll_shared3_rate_table),
514 PLL(pll_1052x, CLK_FOUT_SHARED4_PLL, "fout_shared4_pll", "oscclk",
515 PLL_LOCKTIME_PLL_SHARED4, PLL_CON0_PLL_SHARED4,
516 pll_shared4_rate_table),
517 };
518
519 /* List of parent clocks for Muxes in CMU_TOP */
520 PNAME(mout_pll_shared0_p) = { "oscclk", "fout_shared0_pll" };
521 PNAME(mout_pll_shared1_p) = { "oscclk", "fout_shared1_pll" };
522 PNAME(mout_pll_shared2_p) = { "oscclk", "fout_shared2_pll" };
523 PNAME(mout_pll_shared3_p) = { "oscclk", "fout_shared3_pll" };
524 PNAME(mout_pll_shared4_p) = { "oscclk", "fout_shared4_pll" };
525 PNAME(mout_cp2ap_mif_clk_user_p) = { "oscclk" };
526 PNAME(mout_cmu_abox_cpuabox_p) = { "dout_cmu_shared0_div2",
527 "dout_cmu_shared1_div2",
528 "fout_shared2_pll",
529 "fout_shared4_pll" };
530 PNAME(mout_cmu_apm_bus_p) = { "dout_cmu_shared0_div4",
531 "dout_cmu_shared2_div2" };
532 PNAME(mout_cmu_bus1_bus_p) = { "fout_shared4_pll",
533 "dout_cmu_shared0_div4",
534 "dout_cmu_shared1_div4",
535 "dout_cmu_shared2_div2" };
536 PNAME(mout_cmu_busc_bus_p) = { "fout_shared4_pll",
537 "dout_cmu_shared0_div4",
538 "dout_cmu_shared1_div4",
539 "dout_cmu_shared2_div2",
540 "dout_cmu_cp2ap_mif_clk_div2",
541 "oscclk", "oscclk", "oscclk" };
542 PNAME(mout_cmu_busc_busphsi2c_p) = { "dout_cmu_shared0_div4",
543 "dout_cmu_shared2_div2",
544 "dout_cmu_cp2ap_mif_clk_div2",
545 "oscclk" };
546 PNAME(mout_cmu_cam_bus_p) = { "dout_cmu_shared0_div4",
547 "dout_cmu_shared1_div4",
548 "dout_cmu_shared2_div2",
549 "dout_cmu_shared4_div2" };
550 PNAME(mout_cmu_cam_tpu0_p) = { "dout_cmu_shared0_div4",
551 "dout_cmu_shared1_div4",
552 "dout_cmu_shared2_div2",
553 "dout_cmu_shared4_div2" };
554 PNAME(mout_cmu_cam_tpu1_p) = { "dout_cmu_shared0_div4",
555 "dout_cmu_shared1_div4",
556 "dout_cmu_shared2_div2",
557 "dout_cmu_shared4_div2" };
558 PNAME(mout_cmu_cam_vra_p) = { "dout_cmu_shared0_div4",
559 "dout_cmu_shared1_div4",
560 "dout_cmu_shared2_div2",
561 "dout_cmu_shared4_div2" };
562 PNAME(mout_cmu_cis_clk0_p) = { "oscclk",
563 "dout_cmu_shared2_div2" };
564 PNAME(mout_cmu_cis_clk1_p) = { "oscclk",
565 "dout_cmu_shared2_div2" };
566 PNAME(mout_cmu_cis_clk2_p) = { "oscclk",
567 "dout_cmu_shared2_div2" };
568 PNAME(mout_cmu_cis_clk3_p) = { "oscclk",
569 "dout_cmu_shared2_div2" };
570 PNAME(mout_core_bus_p) = { "dout_cmu_shared0_div2",
571 "dout_cmu_shared1_div2",
572 "fout_shared2_pll",
573 "fout_shared4_pll",
574 "dout_cmu_shared0_div4",
575 "dout_cmu_shared1_div4",
576 "dout_cmu_shared2_div2",
577 "dout_cmu_cp2ap_mif_clk_div2" };
578 PNAME(mout_cmu_cpucl0_switch_p) = { "dout_cmu_shared0_div2",
579 "dout_cmu_shared1_div2",
580 "fout_shared2_pll",
581 "fout_shared4_pll" };
582 PNAME(mout_cmu_cpucl1_switch_p) = { "dout_cmu_shared0_div2",
583 "dout_cmu_shared1_div2",
584 "fout_shared2_pll",
585 "fout_shared4_pll" };
586 PNAME(mout_cmu_dbg_bus_p) = { "fout_shared2_pll",
587 "fout_shared4_pll",
588 "dout_cmu_shared0_div4",
589 "dout_cmu_shared1_div4" };
590 PNAME(mout_cmu_dcam_bus_p) = { "fout_shared4_pll",
591 "dout_cmu_shared0_div4",
592 "dout_cmu_shared1_div4",
593 "dout_cmu_shared2_div2" };
594 PNAME(mout_cmu_dcam_imgd_p) = { "dout_cmu_shared0_div4",
595 "dout_cmu_shared1_div4",
596 "dout_cmu_shared2_div2",
597 "dout_cmu_shared4_div2" };
598 PNAME(mout_cmu_dpu_bus_p) = { "dout_cmu_shared0_div2",
599 "fout_shared3_pll",
600 "fout_shared4_pll",
601 "dout_cmu_shared1_div4",
602 "dout_cmu_shared2_div2",
603 "oscclk", "oscclk", "oscclk" };
604 PNAME(mout_cmu_droopdetector_p) = { "oscclk", "dout_cmu_shared0_div2",
605 "dout_cmu_shared1_div2",
606 "fout_shared2_pll" };
607 PNAME(mout_cmu_dsp_bus_p) = { "dout_cmu_shared0_div4",
608 "dout_cmu_shared1_div4",
609 "dout_cmu_shared2_div2",
610 "dout_cmu_shared4_div2" };
611 PNAME(mout_fsys0_bus_p) = { "dout_cmu_shared1_div2",
612 "fout_shared2_pll",
613 "fout_shared4_pll",
614 "dout_cmu_shared0_div4" };
615 PNAME(mout_fsys0_dpgtc_p) = { "oscclk", "dout_cmu_shared0_div4",
616 "dout_cmu_shared2_div2",
617 "dout_cmu_shared4_div2" };
618 PNAME(mout_fsys0_mmc_embd_p) = { "oscclk", "fout_shared2_pll",
619 "fout_shared4_pll",
620 "dout_cmu_shared0_div4",
621 "dout_cmu_shared1_div4",
622 "oscclk", "oscclk", "oscclk" };
623 PNAME(mout_fsys0_ufs_embd_p) = { "oscclk", "dout_cmu_shared0_div4",
624 "dout_cmu_shared2_div2",
625 "dout_cmu_shared4_div2" };
626 PNAME(mout_fsys0_usbdrd30_p) = { "oscclk", "dout_cmu_shared0_div4",
627 "dout_cmu_shared2_div2",
628 "dout_cmu_shared4_div2" };
629 PNAME(mout_cmu_fsys1_bus_p) = { "fout_shared2_pll",
630 "dout_cmu_shared0_div4" };
631 PNAME(mout_cmu_fsys1_mmc_card_p) = { "oscclk", "fout_shared2_pll",
632 "fout_shared4_pll",
633 "dout_cmu_shared0_div4",
634 "dout_cmu_shared1_div4",
635 "oscclk", "oscclk", "oscclk" };
636 PNAME(mout_cmu_fsys1_pcie_p) = { "oscclk", "fout_shared2_pll" };
637 PNAME(mout_cmu_fsys1_ufs_card_p) = { "oscclk",
638 "dout_cmu_shared0_div4",
639 "dout_cmu_shared2_div2",
640 "dout_cmu_shared4_div2" };
641 PNAME(mout_cmu_g2d_g2d_p) = { "fout_shared4_pll",
642 "dout_cmu_shared0_div4",
643 "dout_cmu_shared1_div4",
644 "dout_cmu_shared2_div2" };
645 PNAME(mout_cmu_g2d_jpeg_p) = { "dout_cmu_shared0_div4",
646 "dout_cmu_shared1_div4",
647 "dout_cmu_shared2_div2",
648 "dout_cmu_shared4_div2" };
649 PNAME(mout_cmu_hpm_p) = { "oscclk", "dout_cmu_shared0_div4",
650 "dout_cmu_shared1_div4",
651 "dout_cmu_shared2_div2" };
652 PNAME(mout_cmu_imem_bus_p) = { "dout_cmu_shared0_div4",
653 "dout_cmu_shared1_div4",
654 "dout_cmu_shared2_div2",
655 "dout_cmu_shared4_div2" };
656 PNAME(mout_cmu_isphq_bus_p) = { "dout_cmu_shared0_div4",
657 "dout_cmu_shared1_div4",
658 "dout_cmu_shared2_div2",
659 "dout_cmu_shared4_div2" };
660 PNAME(mout_cmu_isplp_bus_p) = { "dout_cmu_shared0_div4",
661 "dout_cmu_shared1_div4",
662 "dout_cmu_shared2_div2",
663 "dout_cmu_shared4_div2" };
664 PNAME(mout_cmu_iva_bus_p) = { "dout_cmu_shared0_div4",
665 "dout_cmu_shared1_div4",
666 "dout_cmu_shared2_div2",
667 "dout_cmu_shared4_div2" };
668 PNAME(mout_cmu_mfc_bus_p) = { "fout_shared4_pll",
669 "dout_cmu_shared0_div4",
670 "dout_cmu_shared1_div4",
671 "dout_cmu_shared2_div2" };
672 PNAME(mout_cmu_mif_switch_p) = { "fout_shared0_pll",
673 "fout_shared1_pll",
674 "dout_cmu_shared0_div2",
675 "dout_cmu_shared1_div2",
676 "fout_shared2_pll",
677 "mout_cp2ap_mif_clk_user",
678 "oscclk", "oscclk" };
679 PNAME(mout_cmu_peric0_bus_p) = { "dout_cmu_shared0_div4",
680 "dout_cmu_shared2_div2" };
681 PNAME(mout_cmu_peric0_uart_dbg_p) = { "oscclk", "dout_cmu_shared0_div4",
682 "dout_cmu_shared2_div2",
683 "dout_cmu_shared4_div2" };
684 PNAME(mout_cmu_peric0_usi00_p) = { "oscclk", "dout_cmu_shared0_div4",
685 "dout_cmu_shared2_div2",
686 "dout_cmu_shared4_div2" };
687 PNAME(mout_cmu_peric0_usi01_p) = { "oscclk", "dout_cmu_shared0_div4",
688 "dout_cmu_shared2_div2",
689 "dout_cmu_shared4_div2" };
690 PNAME(mout_cmu_peric0_usi02_p) = { "oscclk", "dout_cmu_shared0_div4",
691 "dout_cmu_shared2_div2",
692 "dout_cmu_shared4_div2" };
693 PNAME(mout_cmu_peric0_usi03_p) = { "oscclk", "dout_cmu_shared0_div4",
694 "dout_cmu_shared2_div2",
695 "dout_cmu_shared4_div2" };
696 PNAME(mout_cmu_peric1_bus_p) = { "dout_cmu_shared0_div4",
697 "dout_cmu_shared2_div2" };
698 PNAME(mout_cmu_peric1_speedy2_p) = { "oscclk", "dout_cmu_shared0_div4",
699 "dout_cmu_shared2_div2",
700 "oscclk" };
701 PNAME(mout_cmu_peric1_spi_cam0_p) = { "oscclk", "dout_cmu_shared0_div4",
702 "dout_cmu_shared2_div2",
703 "dout_cmu_shared4_div2" };
704 PNAME(mout_cmu_peric1_spi_cam1_p) = { "oscclk", "dout_cmu_shared0_div4",
705 "dout_cmu_shared2_div2",
706 "dout_cmu_shared4_div2" };
707 PNAME(mout_cmu_peric1_uart_bt_p) = { "oscclk", "dout_cmu_shared0_div4",
708 "dout_cmu_shared2_div2",
709 "dout_cmu_shared4_div2" };
710 PNAME(mout_cmu_peric1_usi04_p) = { "oscclk", "dout_cmu_shared0_div4",
711 "dout_cmu_shared2_div2",
712 "dout_cmu_shared4_div2" };
713 PNAME(mout_cmu_peric1_usi05_p) = { "oscclk", "dout_cmu_shared0_div4",
714 "dout_cmu_shared2_div2",
715 "dout_cmu_shared4_div2" };
716 PNAME(mout_cmu_peric1_usi06_p) = { "oscclk", "dout_cmu_shared0_div4",
717 "dout_cmu_shared2_div2",
718 "dout_cmu_shared4_div2" };
719 PNAME(mout_cmu_peric1_usi07_p) = { "oscclk", "dout_cmu_shared0_div4",
720 "dout_cmu_shared2_div2",
721 "dout_cmu_shared4_div2" };
722 PNAME(mout_cmu_peric1_usi08_p) = { "oscclk", "dout_cmu_shared0_div4",
723 "dout_cmu_shared2_div2",
724 "dout_cmu_shared4_div2" };
725 PNAME(mout_cmu_peric1_usi09_p) = { "oscclk", "dout_cmu_shared0_div4",
726 "dout_cmu_shared2_div2",
727 "dout_cmu_shared4_div2" };
728 PNAME(mout_cmu_peric1_usi10_p) = { "oscclk", "dout_cmu_shared0_div4",
729 "dout_cmu_shared2_div2",
730 "dout_cmu_shared4_div2" };
731 PNAME(mout_cmu_peric1_usi11_p) = { "oscclk", "dout_cmu_shared0_div4",
732 "dout_cmu_shared2_div2",
733 "dout_cmu_shared4_div2" };
734 PNAME(mout_cmu_peric1_usi12_p) = { "oscclk", "dout_cmu_shared0_div4",
735 "dout_cmu_shared2_div2",
736 "dout_cmu_shared4_div2" };
737 PNAME(mout_cmu_peric1_usi13_p) = { "oscclk", "dout_cmu_shared0_div4",
738 "dout_cmu_shared2_div2",
739 "dout_cmu_shared4_div2" };
740 PNAME(mout_cmu_peris_bus_p) = { "dout_cmu_shared0_div4",
741 "dout_cmu_shared2_div2" };
742 PNAME(mout_cmu_srdz_bus_p) = { "dout_cmu_shared0_div4",
743 "dout_cmu_shared1_div4",
744 "dout_cmu_shared2_div2",
745 "dout_cmu_shared4_div2" };
746 PNAME(mout_cmu_srdz_imgd_p) = { "dout_cmu_shared0_div4",
747 "dout_cmu_shared1_div4",
748 "dout_cmu_shared2_div2",
749 "dout_cmu_shared4_div2" };
750 PNAME(mout_cmu_vpu_bus_p) = { "dout_cmu_shared0_div4",
751 "dout_cmu_shared1_div4",
752 "dout_cmu_shared2_div2",
753 "dout_cmu_shared4_div2" };
754
755 /*
756 * Register name to clock name mangling strategy used in this file
757 *
758 * Replace PLL_CON0_PLL with CLK_MOUT_PLL and mout_pll
759 * Replace CLK_CON_MUX_MUX_CLKCMU with CLK_MOUT_CMU and mout_cmu
760 * Replace CLK_CON_DIV_CLKCMU with CLK_DOUT_CMU and dout_cmu
761 * Replace CLK_CON_DIV_DIV_CLKCMU with CLK_DOUT_CMU and dout_cmu
762 * Replace CLK_CON_GAT_CLKCMU with CLK_GOUT_CMU and gout_cmu
763 * Replace CLK_CON_GAT_GATE_CLKCMU with CLK_GOUT_CMU and gout_cmu
764 *
765 * For gates remove _UID _BLK _IPCLKPORT and _RSTNSYNC
766 */
767
768 static const struct samsung_mux_clock top_mux_clks[] __initconst = {
769 MUX(CLK_MOUT_PLL_SHARED0, "mout_pll_shared0", mout_pll_shared0_p,
770 PLL_CON0_PLL_SHARED0, 4, 1),
771 MUX(CLK_MOUT_PLL_SHARED1, "mout_pll_shared1", mout_pll_shared1_p,
772 PLL_CON0_PLL_SHARED1, 4, 1),
773 MUX(CLK_MOUT_PLL_SHARED2, "mout_pll_shared2", mout_pll_shared2_p,
774 PLL_CON0_PLL_SHARED2, 4, 1),
775 MUX(CLK_MOUT_PLL_SHARED3, "mout_pll_shared3", mout_pll_shared3_p,
776 PLL_CON0_PLL_SHARED3, 4, 1),
777 MUX(CLK_MOUT_PLL_SHARED4, "mout_pll_shared4", mout_pll_shared4_p,
778 PLL_CON0_PLL_SHARED4, 4, 1),
779 MUX(CLK_MOUT_CP2AP_MIF_CLK_USER, "mout_cp2ap_mif_clk_user",
780 mout_cp2ap_mif_clk_user_p, PLL_CON0_MUX_CP2AP_MIF_CLK_USER, 4, 1),
781 MUX(CLK_MOUT_CMU_ABOX_CPUABOX, "mout_cmu_abox_cpuabox",
782 mout_cmu_abox_cpuabox_p, CLK_CON_MUX_MUX_CLKCMU_ABOX_CPUABOX,
783 0, 2),
784 MUX(CLK_MOUT_CMU_APM_BUS, "mout_cmu_apm_bus", mout_cmu_apm_bus_p,
785 CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 1),
786 MUX(CLK_MOUT_CMU_BUS1_BUS, "mout_cmu_bus1_bus", mout_cmu_bus1_bus_p,
787 CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS, 0, 2),
788 MUX(CLK_MOUT_CMU_BUSC_BUS, "mout_cmu_busc_bus", mout_cmu_busc_bus_p,
789 CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS, 0, 3),
790 MUX(CLK_MOUT_CMU_BUSC_BUSPHSI2C, "mout_cmu_busc_busphsi2c",
791 mout_cmu_busc_busphsi2c_p, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUSPHSI2C,
792 0, 2),
793 MUX(CLK_MOUT_CMU_CAM_BUS, "mout_cmu_cam_bus", mout_cmu_cam_bus_p,
794 CLK_CON_MUX_MUX_CLKCMU_CAM_BUS, 0, 2),
795 MUX(CLK_MOUT_CMU_CAM_TPU0, "mout_cmu_cam_tpu0", mout_cmu_cam_tpu0_p,
796 CLK_CON_MUX_MUX_CLKCMU_CAM_TPU0, 0, 2),
797 MUX(CLK_MOUT_CMU_CAM_TPU1, "mout_cmu_cam_tpu1", mout_cmu_cam_tpu1_p,
798 CLK_CON_MUX_MUX_CLKCMU_CAM_TPU1, 0, 2),
799 MUX(CLK_MOUT_CMU_CAM_VRA, "mout_cmu_cam_vra", mout_cmu_cam_vra_p,
800 CLK_CON_MUX_MUX_CLKCMU_CAM_VRA, 0, 2),
801 MUX(CLK_MOUT_CMU_CIS_CLK0, "mout_cmu_cis_clk0", mout_cmu_cis_clk0_p,
802 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0, 0, 1),
803 MUX(CLK_MOUT_CMU_CIS_CLK1, "mout_cmu_cis_clk1", mout_cmu_cis_clk1_p,
804 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1, 0, 1),
805 MUX(CLK_MOUT_CMU_CIS_CLK2, "mout_cmu_cis_clk2", mout_cmu_cis_clk2_p,
806 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2, 0, 1),
807 MUX(CLK_MOUT_CMU_CIS_CLK3, "mout_cmu_cis_clk3", mout_cmu_cis_clk3_p,
808 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3, 0, 1),
809 MUX(CLK_MOUT_CMU_CORE_BUS, "mout_core_bus", mout_core_bus_p,
810 CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 3),
811 MUX(CLK_MOUT_CMU_CPUCL0_SWITCH, "mout_cmu_cpucl0_switch",
812 mout_cmu_cpucl0_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
813 0, 2),
814 MUX(CLK_MOUT_CMU_CPUCL1_SWITCH, "mout_cmu_cpucl1_switch",
815 mout_cmu_cpucl1_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
816 0, 2),
817 MUX(CLK_MOUT_CMU_DBG_BUS, "mout_cmu_dbg_bus", mout_cmu_dbg_bus_p,
818 CLK_CON_MUX_MUX_CLKCMU_DBG_BUS, 0, 2),
819 MUX(CLK_MOUT_CMU_DCAM_BUS, "mout_cmu_dcam_bus", mout_cmu_dcam_bus_p,
820 CLK_CON_MUX_MUX_CLKCMU_DCAM_BUS, 0, 2),
821 MUX(CLK_MOUT_CMU_DCAM_IMGD, "mout_cmu_dcam_imgd", mout_cmu_dcam_imgd_p,
822 CLK_CON_MUX_MUX_CLKCMU_DCAM_IMGD, 0, 2),
823 MUX(CLK_MOUT_CMU_DPU_BUS, "mout_cmu_dpu_bus", mout_cmu_dpu_bus_p,
824 CLK_CON_MUX_MUX_CLKCMU_DPU_BUS, 0, 3),
825 MUX(CLK_MOUT_CMU_DROOPDETECTOR, "mout_cmu_droopdetector",
826 mout_cmu_droopdetector_p, CLK_CON_MUX_MUX_CLKCMU_DROOPDETECTOR,
827 0, 2),
828 MUX(CLK_MOUT_CMU_DSP_BUS, "mout_cmu_dsp_bus", mout_cmu_dsp_bus_p,
829 CLK_CON_MUX_MUX_CLKCMU_DSP_BUS, 0, 2),
830 MUX(CLK_MOUT_CMU_FSYS0_BUS, "mout_fsys0_bus", mout_fsys0_bus_p,
831 CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS, 0, 2),
832 MUX(CLK_MOUT_CMU_FSYS0_DPGTC, "mout_fsys0_dpgtc", mout_fsys0_dpgtc_p,
833 CLK_CON_MUX_MUX_CLKCMU_FSYS0_DPGTC, 0, 2),
834 MUX(CLK_MOUT_CMU_FSYS0_MMC_EMBD, "mout_fsys0_mmc_embd",
835 mout_fsys0_mmc_embd_p, CLK_CON_MUX_MUX_CLKCMU_FSYS0_MMC_EMBD,
836 0, 3),
837 MUX(CLK_MOUT_CMU_FSYS0_UFS_EMBD, "mout_fsys0_ufs_embd",
838 mout_fsys0_ufs_embd_p, CLK_CON_MUX_MUX_CLKCMU_FSYS0_UFS_EMBD,
839 0, 2),
840 MUX(CLK_MOUT_CMU_FSYS0_USBDRD30, "mout_fsys0_usbdrd30",
841 mout_fsys0_usbdrd30_p, CLK_CON_MUX_MUX_CLKCMU_FSYS0_USBDRD30,
842 0, 2),
843 MUX(CLK_MOUT_CMU_FSYS1_BUS, "mout_cmu_fsys1_bus", mout_cmu_fsys1_bus_p,
844 CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS, 0, 1),
845 MUX(CLK_MOUT_CMU_FSYS1_MMC_CARD, "mout_cmu_fsys1_mmc_card",
846 mout_cmu_fsys1_mmc_card_p, CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD,
847 0, 3),
848 MUX(CLK_MOUT_CMU_FSYS1_PCIE, "mout_cmu_fsys1_pcie",
849 mout_cmu_fsys1_pcie_p, CLK_CON_MUX_MUX_CLKCMU_FSYS1_PCIE, 0, 1),
850 MUX(CLK_MOUT_CMU_FSYS1_UFS_CARD, "mout_cmu_fsys1_ufs_card",
851 mout_cmu_fsys1_ufs_card_p, CLK_CON_MUX_MUX_CLKCMU_FSYS1_UFS_CARD,
852 0, 2),
853 MUX(CLK_MOUT_CMU_G2D_G2D, "mout_cmu_g2d_g2d", mout_cmu_g2d_g2d_p,
854 CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0, 2),
855 MUX(CLK_MOUT_CMU_G2D_JPEG, "mout_cmu_g2d_jpeg", mout_cmu_g2d_jpeg_p,
856 CLK_CON_MUX_MUX_CLKCMU_G2D_JPEG, 0, 2),
857 MUX(CLK_MOUT_CMU_HPM, "mout_cmu_hpm", mout_cmu_hpm_p,
858 CLK_CON_MUX_MUX_CLKCMU_HPM, 0, 2),
859 MUX(CLK_MOUT_CMU_IMEM_BUS, "mout_cmu_imem_bus", mout_cmu_imem_bus_p,
860 CLK_CON_MUX_MUX_CLKCMU_IMEM_BUS, 0, 2),
861 MUX(CLK_MOUT_CMU_ISPHQ_BUS, "mout_cmu_isphq_bus", mout_cmu_isphq_bus_p,
862 CLK_CON_MUX_MUX_CLKCMU_ISPHQ_BUS, 0, 2),
863 MUX(CLK_MOUT_CMU_ISPLP_BUS, "mout_cmu_isplp_bus", mout_cmu_isplp_bus_p,
864 CLK_CON_MUX_MUX_CLKCMU_ISPLP_BUS, 0, 2),
865 MUX(CLK_MOUT_CMU_IVA_BUS, "mout_cmu_iva_bus", mout_cmu_iva_bus_p,
866 CLK_CON_MUX_MUX_CLKCMU_IVA_BUS, 0, 2),
867 MUX(CLK_MOUT_CMU_MFC_BUS, "mout_cmu_mfc_bus", mout_cmu_mfc_bus_p,
868 CLK_CON_MUX_MUX_CLKCMU_MFC_BUS, 0, 2),
869 MUX(CLK_MOUT_CMU_MIF_SWITCH, "mout_cmu_mif_switch",
870 mout_cmu_mif_switch_p, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 3),
871 MUX(CLK_MOUT_CMU_PERIC0_BUS, "mout_cmu_peric0_bus",
872 mout_cmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 1),
873 MUX(CLK_MOUT_CMU_PERIC0_UART_DBG, "mout_cmu_peric0_uart_dbg",
874 mout_cmu_peric0_uart_dbg_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_UART_DBG,
875 0, 2),
876 MUX(CLK_MOUT_CMU_PERIC0_USI00, "mout_cmu_peric0_usi00",
877 mout_cmu_peric0_usi00_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI00,
878 0, 2),
879 MUX(CLK_MOUT_CMU_PERIC0_USI01, "mout_cmu_peric0_usi01",
880 mout_cmu_peric0_usi01_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI01,
881 0, 2),
882 MUX(CLK_MOUT_CMU_PERIC0_USI02, "mout_cmu_peric0_usi02",
883 mout_cmu_peric0_usi02_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI02,
884 0, 2),
885 MUX(CLK_MOUT_CMU_PERIC0_USI03, "mout_cmu_peric0_usi03",
886 mout_cmu_peric0_usi03_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI03,
887 0, 2),
888 MUX(CLK_MOUT_CMU_PERIC1_BUS, "mout_cmu_peric1_bus",
889 mout_cmu_peric1_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS, 0, 1),
890 MUX(CLK_MOUT_CMU_PERIC1_SPEEDY2, "mout_cmu_peric1_speedy2",
891 mout_cmu_peric1_speedy2_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPEEDY2,
892 0, 2),
893 MUX(CLK_MOUT_CMU_PERIC1_SPI_CAM0, "mout_cmu_peric1_spi_cam0",
894 mout_cmu_peric1_spi_cam0_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPI_CAM0,
895 0, 2),
896 MUX(CLK_MOUT_CMU_PERIC1_SPI_CAM1, "mout_cmu_peric1_spi_cam1",
897 mout_cmu_peric1_spi_cam1_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPI_CAM1,
898 0, 2),
899 MUX(CLK_MOUT_CMU_PERIC1_UART_BT, "mout_cmu_peric1_uart_bt",
900 mout_cmu_peric1_uart_bt_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_UART_BT,
901 0, 2),
902 MUX(CLK_MOUT_CMU_PERIC1_USI04, "mout_cmu_peric1_usi04",
903 mout_cmu_peric1_usi04_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI04,
904 0, 2),
905 MUX(CLK_MOUT_CMU_PERIC1_USI05, "mout_cmu_peric1_usi05",
906 mout_cmu_peric1_usi05_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI05,
907 0, 2),
908 MUX(CLK_MOUT_CMU_PERIC1_USI06, "mout_cmu_peric1_usi06",
909 mout_cmu_peric1_usi06_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI06,
910 0, 2),
911 MUX(CLK_MOUT_CMU_PERIC1_USI07, "mout_cmu_peric1_usi07",
912 mout_cmu_peric1_usi07_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI07,
913 0, 2),
914 MUX(CLK_MOUT_CMU_PERIC1_USI08, "mout_cmu_peric1_usi08",
915 mout_cmu_peric1_usi08_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI08,
916 0, 2),
917 MUX(CLK_MOUT_CMU_PERIC1_USI09, "mout_cmu_peric1_usi09",
918 mout_cmu_peric1_usi09_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI09,
919 0, 2),
920 MUX(CLK_MOUT_CMU_PERIC1_USI10, "mout_cmu_peric1_usi10",
921 mout_cmu_peric1_usi10_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI10,
922 0, 2),
923 MUX(CLK_MOUT_CMU_PERIC1_USI11, "mout_cmu_peric1_usi11",
924 mout_cmu_peric1_usi11_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI11,
925 0, 2),
926 MUX(CLK_MOUT_CMU_PERIC1_USI12, "mout_cmu_peric1_usi12",
927 mout_cmu_peric1_usi12_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI12,
928 0, 2),
929 MUX(CLK_MOUT_CMU_PERIC1_USI13, "mout_cmu_peric1_usi13",
930 mout_cmu_peric1_usi13_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI13,
931 0, 2),
932 MUX(CLK_MOUT_CMU_PERIS_BUS, "mout_cmu_peris_bus", mout_cmu_peris_bus_p,
933 CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS, 0, 1),
934 MUX(CLK_MOUT_CMU_SRDZ_BUS, "mout_cmu_srdz_bus", mout_cmu_srdz_bus_p,
935 CLK_CON_MUX_MUX_CLKCMU_SRDZ_BUS, 0, 2),
936 MUX(CLK_MOUT_CMU_SRDZ_IMGD, "mout_cmu_srdz_imgd", mout_cmu_srdz_imgd_p,
937 CLK_CON_MUX_MUX_CLKCMU_SRDZ_IMGD, 0, 2),
938 MUX(CLK_MOUT_CMU_VPU_BUS, "mout_cmu_vpu_bus", mout_cmu_vpu_bus_p,
939 CLK_CON_MUX_MUX_CLKCMU_VPU_BUS, 0, 2),
940 };
941
942 static const struct samsung_div_clock top_div_clks[] __initconst = {
943 DIV(CLK_DOUT_CMU_ABOX_CPUABOX, "dout_cmu_cmu_abox_cpuabox",
944 "gout_cmu_abox_cpuabox", CLK_CON_DIV_CLKCMU_ABOX_CPUABOX, 0, 3),
945 DIV(CLK_DOUT_CMU_APM_BUS, "dout_cmu_apm_bus", "gout_cmu_apm_bus",
946 CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3),
947 DIV(CLK_DOUT_CMU_BUS1_BUS, "dout_cmu_bus1_bus", "gout_cmu_bus1_bus",
948 CLK_CON_DIV_CLKCMU_BUS1_BUS, 0, 4),
949 DIV(CLK_DOUT_CMU_BUSC_BUS, "dout_cmu_busc_bus",
950 "gout_cmu_clkcmu_busc_bus", CLK_CON_DIV_CLKCMU_BUSC_BUS, 0, 4),
951 DIV(CLK_DOUT_CMU_BUSC_BUSPHSI2C, "dout_cmu_busc_busphsi2c",
952 "gout_cmu_busc_busphsi2c", CLK_CON_DIV_CLKCMU_BUSC_BUSPHSI2C,
953 0, 4),
954 DIV(CLK_DOUT_CMU_CAM_BUS, "dout_cmu_cam_bus", "gout_cmu_cam_bus",
955 CLK_CON_DIV_CLKCMU_CAM_BUS, 0, 4),
956 DIV(CLK_DOUT_CMU_CAM_TPU0, "dout_cmu_cam_tpu0", "gout_cmu_cam_tpu0",
957 CLK_CON_DIV_CLKCMU_CAM_TPU0, 0, 4),
958 DIV(CLK_DOUT_CMU_CAM_TPU1, "dout_cmu_cam_tpu1", "gout_cmu_cam_tpu1",
959 CLK_CON_DIV_CLKCMU_CAM_TPU1, 0, 4),
960 DIV(CLK_DOUT_CMU_CAM_VRA, "dout_cmu_cam_vra", "gout_cmu_cam_vra",
961 CLK_CON_DIV_CLKCMU_CAM_VRA, 0, 4),
962 DIV(CLK_DOUT_CMU_CIS_CLK0, "dout_cmu_cis_clk0", "gout_cmu_cis_clk0",
963 CLK_CON_DIV_CLKCMU_CIS_CLK0, 0, 5),
964 DIV(CLK_DOUT_CMU_CIS_CLK1, "dout_cmu_cis_clk1", "gout_cmu_cis_clk1",
965 CLK_CON_DIV_CLKCMU_CIS_CLK1, 0, 5),
966 DIV(CLK_DOUT_CMU_CIS_CLK2, "dout_cmu_cis_clk2", "gout_cmu_cis_clk2",
967 CLK_CON_DIV_CLKCMU_CIS_CLK2, 0, 5),
968 DIV(CLK_DOUT_CMU_CIS_CLK3, "dout_cmu_cis_clk3", "gout_cmu_cis_clk3",
969 CLK_CON_DIV_CLKCMU_CIS_CLK3, 0, 5),
970 DIV(CLK_DOUT_CMU_CORE_BUS, "dout_cmu_core_bus", "gout_cmu_core_bus",
971 CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
972 DIV(CLK_DOUT_CMU_CPUCL0_SWITCH, "dout_cmu_cpucl0_switch",
973 "gout_cmu_cpucl0_switch", CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3),
974 DIV(CLK_DOUT_CMU_CPUCL1_SWITCH, "dout_cmu_cpucl1_switch",
975 "gout_cmu_cpucl1_switch", CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 3),
976 DIV(CLK_DOUT_CMU_DBG_BUS, "dout_cmu_dbg_bus", "gout_cmu_dbg_bus",
977 CLK_CON_DIV_CLKCMU_DBG_BUS, 0, 4),
978 DIV(CLK_DOUT_CMU_DCAM_BUS, "dout_cmu_dcam_bus", "gout_cmu_dcam_bus",
979 CLK_CON_DIV_CLKCMU_DCAM_BUS, 0, 4),
980 DIV(CLK_DOUT_CMU_DCAM_IMGD, "dout_cmu_dcam_imgd", "gout_cmu_dcam_imgd",
981 CLK_CON_DIV_CLKCMU_DCAM_IMGD, 0, 4),
982 DIV(CLK_DOUT_CMU_DPU_BUS, "dout_cmu_dpu_bus", "gout_cmu_dpu_bus",
983 CLK_CON_DIV_CLKCMU_DPU_BUS, 0, 4),
984 DIV(CLK_DOUT_CMU_DSP_BUS, "dout_cmu_dsp_bus", "gout_cmu_dsp_bus",
985 CLK_CON_DIV_CLKCMU_DSP_BUS, 0, 4),
986 DIV(CLK_DOUT_CMU_FSYS0_BUS, "dout_cmu_fsys0_bus", "gout_cmu_fsys0_bus",
987 CLK_CON_DIV_CLKCMU_FSYS0_BUS, 0, 4),
988 DIV(CLK_DOUT_CMU_FSYS0_DPGTC, "dout_cmu_fsys0_dpgtc",
989 "gout_cmu_fsys0_dpgtc", CLK_CON_DIV_CLKCMU_FSYS0_DPGTC, 0, 3),
990 DIV(CLK_DOUT_CMU_FSYS0_MMC_EMBD, "dout_cmu_fsys0_mmc_embd",
991 "gout_cmu_fsys0_mmc_embd", CLK_CON_DIV_CLKCMU_FSYS0_MMC_EMBD,
992 0, 9),
993 DIV(CLK_DOUT_CMU_FSYS0_UFS_EMBD, "dout_cmu_fsys0_ufs_embd",
994 "gout_cmu_fsys0_ufs_embd", CLK_CON_DIV_CLKCMU_FSYS0_UFS_EMBD,
995 0, 3),
996 DIV(CLK_DOUT_CMU_FSYS0_USBDRD30, "dout_cmu_fsys0_usbdrd30",
997 "gout_cmu_fsys0_usbdrd30", CLK_CON_DIV_CLKCMU_FSYS0_USBDRD30,
998 0, 4),
999 DIV(CLK_DOUT_CMU_FSYS1_BUS, "dout_cmu_fsys1_bus", "gout_cmu_fsys1_bus",
1000 CLK_CON_DIV_CLKCMU_FSYS1_BUS, 0, 4),
1001 DIV(CLK_DOUT_CMU_FSYS1_MMC_CARD, "dout_cmu_fsys1_mmc_card",
1002 "gout_cmu_fsys1_mmc_card", CLK_CON_DIV_CLKCMU_FSYS1_MMC_CARD,
1003 0, 9),
1004 DIV(CLK_DOUT_CMU_FSYS1_UFS_CARD, "dout_cmu_fsys1_ufs_card",
1005 "gout_cmu_fsys1_ufs_card", CLK_CON_DIV_CLKCMU_FSYS1_UFS_CARD,
1006 0, 4),
1007 DIV(CLK_DOUT_CMU_G2D_G2D, "dout_cmu_g2d_g2d", "gout_cmu_g2d_g2d",
1008 CLK_CON_DIV_CLKCMU_G2D_G2D, 0, 4),
1009 DIV(CLK_DOUT_CMU_G2D_JPEG, "dout_cmu_g2d_jpeg", "gout_cmu_g2d_jpeg",
1010 CLK_CON_DIV_CLKCMU_G2D_JPEG, 0, 4),
1011 DIV(CLK_DOUT_CMU_G3D_SWITCH, "dout_cmu_g3d_switch",
1012 "gout_cmu_g3d_switch", CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3),
1013 DIV(CLK_DOUT_CMU_HPM, "dout_cmu_hpm", "gout_cmu_hpm",
1014 CLK_CON_DIV_CLKCMU_HPM, 0, 2),
1015 DIV(CLK_DOUT_CMU_IMEM_BUS, "dout_cmu_imem_bus", "gout_cmu_imem_bus",
1016 CLK_CON_DIV_CLKCMU_IMEM_BUS, 0, 4),
1017 DIV(CLK_DOUT_CMU_ISPHQ_BUS, "dout_cmu_isphq_bus", "gout_cmu_isphq_bus",
1018 CLK_CON_DIV_CLKCMU_ISPHQ_BUS, 0, 4),
1019 DIV(CLK_DOUT_CMU_ISPLP_BUS, "dout_cmu_isplp_bus", "gout_cmu_isplp_bus",
1020 CLK_CON_DIV_CLKCMU_ISPLP_BUS, 0, 4),
1021 DIV(CLK_DOUT_CMU_IVA_BUS, "dout_cmu_iva_bus", "gout_cmu_iva_bus",
1022 CLK_CON_DIV_CLKCMU_IVA_BUS, 0, 4),
1023 DIV(CLK_DOUT_CMU_MFC_BUS, "dout_cmu_mfc_bus", "gout_cmu_mfc_bus",
1024 CLK_CON_DIV_CLKCMU_MFC_BUS, 0, 4),
1025 DIV(CLK_DOUT_CMU_MODEM_SHARED0, "dout_cmu_modem_shared0",
1026 "gout_cmu_modem_shared0", CLK_CON_DIV_CLKCMU_MODEM_SHARED0, 0, 3),
1027 DIV(CLK_DOUT_CMU_MODEM_SHARED1, "dout_cmu_modem_shared1",
1028 "gout_cmu_modem_shared1", CLK_CON_DIV_CLKCMU_MODEM_SHARED1, 0, 3),
1029 DIV(CLK_DOUT_CMU_PERIC0_BUS, "dout_cmu_peric0_bus",
1030 "gout_cmu_peric0_bus", CLK_CON_DIV_CLKCMU_PERIC0_BUS, 0, 4),
1031 DIV(CLK_DOUT_CMU_PERIC0_UART_DBG, "dout_cmu_peric0_uart_dbg",
1032 "gout_cmu_peric0_uart_dbg", CLK_CON_DIV_CLKCMU_PERIC0_UART_DBG,
1033 0, 4),
1034 DIV(CLK_DOUT_CMU_PERIC0_USI00, "dout_cmu_peric0_usi00",
1035 "gout_cmu_peric0_usi00", CLK_CON_DIV_CLKCMU_PERIC0_USI00, 0, 4),
1036 DIV(CLK_DOUT_CMU_PERIC0_USI01, "dout_cmu_peric0_usi01",
1037 "gout_cmu_peric0_usi01", CLK_CON_DIV_CLKCMU_PERIC0_USI01, 0, 4),
1038 DIV(CLK_DOUT_CMU_PERIC0_USI02, "dout_cmu_peric0_usi02",
1039 "gout_cmu_peric0_usi02", CLK_CON_DIV_CLKCMU_PERIC0_USI02, 0, 4),
1040 DIV(CLK_DOUT_CMU_PERIC0_USI03, "dout_cmu_peric0_usi03",
1041 "gout_cmu_peric0_usi03", CLK_CON_DIV_CLKCMU_PERIC0_USI03, 0, 4),
1042 DIV(CLK_DOUT_CMU_PERIC1_BUS, "dout_cmu_peric1_bus",
1043 "gout_cmu_peric1_bus", CLK_CON_DIV_CLKCMU_PERIC1_BUS, 0, 4),
1044 DIV(CLK_DOUT_CMU_PERIC1_SPEEDY2, "dout_cmu_peric1_speedy2",
1045 "gout_cmu_peric1_speedy2", CLK_CON_DIV_CLKCMU_PERIC1_SPEEDY2,
1046 0, 4),
1047 DIV(CLK_DOUT_CMU_PERIC1_SPI_CAM0, "dout_cmu_peric1_spi_cam0",
1048 "gout_cmu_peric1_spi_cam0", CLK_CON_DIV_CLKCMU_PERIC1_SPI_CAM0,
1049 0, 4),
1050 DIV(CLK_DOUT_CMU_PERIC1_SPI_CAM1, "dout_cmu_peric1_spi_cam1",
1051 "gout_cmu_peric1_spi_cam1", CLK_CON_DIV_CLKCMU_PERIC1_SPI_CAM1,
1052 0, 4),
1053 DIV(CLK_DOUT_CMU_PERIC1_UART_BT, "dout_cmu_peric1_uart_bt",
1054 "gout_cmu_peric1_uart_bt", CLK_CON_DIV_CLKCMU_PERIC1_UART_BT,
1055 0, 4),
1056 DIV(CLK_DOUT_CMU_PERIC1_USI04, "dout_cmu_peric1_usi04",
1057 "gout_cmu_peric1_usi04", CLK_CON_DIV_CLKCMU_PERIC1_USI04, 0, 4),
1058 DIV(CLK_DOUT_CMU_PERIC1_USI05, "dout_cmu_peric1_usi05",
1059 "gout_cmu_peric1_usi05", CLK_CON_DIV_CLKCMU_PERIC1_USI05, 0, 4),
1060 DIV(CLK_DOUT_CMU_PERIC1_USI06, "dout_cmu_peric1_usi06",
1061 "gout_cmu_peric1_usi06", CLK_CON_DIV_CLKCMU_PERIC1_USI06, 0, 4),
1062 DIV(CLK_DOUT_CMU_PERIC1_USI07, "dout_cmu_peric1_usi07",
1063 "gout_cmu_peric1_usi07", CLK_CON_DIV_CLKCMU_PERIC1_USI07, 0, 4),
1064 DIV(CLK_DOUT_CMU_PERIC1_USI08, "dout_cmu_peric1_usi08",
1065 "gout_cmu_peric1_usi08", CLK_CON_DIV_CLKCMU_PERIC1_USI08, 0, 4),
1066 DIV(CLK_DOUT_CMU_PERIC1_USI09, "dout_cmu_peric1_usi09",
1067 "gout_cmu_peric1_usi09", CLK_CON_DIV_CLKCMU_PERIC1_USI09, 0, 4),
1068 DIV(CLK_DOUT_CMU_PERIC1_USI10, "dout_cmu_peric1_usi10",
1069 "gout_cmu_peric1_usi10", CLK_CON_DIV_CLKCMU_PERIC1_USI10, 0, 4),
1070 DIV(CLK_DOUT_CMU_PERIC1_USI11, "dout_cmu_peric1_usi11",
1071 "gout_cmu_peric1_usi11", CLK_CON_DIV_CLKCMU_PERIC1_USI11, 0, 4),
1072 DIV(CLK_DOUT_CMU_PERIC1_USI12, "dout_cmu_peric1_usi12",
1073 "gout_cmu_peric1_usi12", CLK_CON_DIV_CLKCMU_PERIC1_USI12, 0, 4),
1074 DIV(CLK_DOUT_CMU_PERIC1_USI13, "dout_cmu_peric1_usi13",
1075 "gout_cmu_peric1_usi13", CLK_CON_DIV_CLKCMU_PERIC1_USI13, 0, 4),
1076 DIV(CLK_DOUT_CMU_PERIS_BUS, "dout_cmu_peris_bus", "gout_cmu_peris_bus",
1077 CLK_CON_DIV_CLKCMU_PERIS_BUS, 0, 4),
1078 DIV(CLK_DOUT_CMU_SRDZ_BUS, "dout_cmu_srdz_bus", "gout_cmu_srdz_bus",
1079 CLK_CON_DIV_CLKCMU_SRDZ_BUS, 0, 4),
1080 DIV(CLK_DOUT_CMU_SRDZ_IMGD, "dout_cmu_srdz_imgd", "gout_cmu_srdz_imgd",
1081 CLK_CON_DIV_CLKCMU_SRDZ_IMGD, 0, 4),
1082 DIV(CLK_DOUT_CMU_VPU_BUS, "dout_cmu_vpu_bus", "gout_cmu_vpu_bus",
1083 CLK_CON_DIV_CLKCMU_VPU_BUS, 0, 4),
1084 };
1085
1086 static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = {
1087 FFACTOR(CLK_DOUT_CMU_SHARED0_DIV2, "dout_cmu_shared0_div2",
1088 "mout_pll_shared0", 1, 2, 0),
1089 FFACTOR(CLK_DOUT_CMU_SHARED0_DIV4, "dout_cmu_shared0_div4",
1090 "mout_pll_shared0", 1, 4, 0),
1091 FFACTOR(CLK_DOUT_CMU_SHARED1_DIV2, "dout_cmu_shared1_div2",
1092 "mout_pll_shared1", 1, 2, 0),
1093 FFACTOR(CLK_DOUT_CMU_SHARED1_DIV4, "dout_cmu_shared1_div4",
1094 "mout_pll_shared1", 1, 4, 0),
1095 FFACTOR(CLK_DOUT_CMU_SHARED2_DIV2, "dout_cmu_shared2_div2",
1096 "mout_pll_shared2", 1, 2, 0),
1097 FFACTOR(CLK_DOUT_CMU_SHARED3_DIV2, "dout_cmu_shared3_div2",
1098 "mout_pll_shared3", 1, 2, 0),
1099 FFACTOR(CLK_DOUT_CMU_SHARED4_DIV2, "dout_cmu_shared4_div2",
1100 "mout_pll_shared4", 1, 2, 0),
1101 FFACTOR(CLK_DOUT_CMU_FSYS1_PCIE, "dout_cmu_fsys1_pcie",
1102 "gout_cmu_fsys1_pcie", 1, 8, 0),
1103 FFACTOR(CLK_DOUT_CMU_CP2AP_MIF_CLK_DIV2, "dout_cmu_cp2ap_mif_clk_div2",
1104 "mout_cp2ap_mif_clk_user", 1, 2, 0),
1105 FFACTOR(CLK_DOUT_CMU_CMU_OTP, "dout_cmu_cmu_otp", "oscclk", 1, 8, 0),
1106 };
1107
1108 static const struct samsung_gate_clock top_gate_clks[] __initconst = {
1109 GATE(CLK_GOUT_CMU_DROOPDETECTOR, "gout_droopdetector",
1110 "mout_cmu_droopdetector", CLK_CON_GAT_CLKCMU_DROOPDETECTOR,
1111 21, 0, 0),
1112 GATE(CLK_GOUT_CMU_MIF_SWITCH, "gout_cmu_mif_switch",
1113 "mout_cmu_mif_switch", CLK_CON_GAT_CLKCMU_MIF_SWITCH, 21, 0, 0),
1114 GATE(CLK_GOUT_CMU_ABOX_CPUABOX, "gout_cmu_abox_cpuabox",
1115 "mout_cmu_abox_cpuabox", CLK_CON_GAT_GATE_CLKCMU_ABOX_CPUABOX,
1116 21, 0, 0),
1117 GATE(CLK_GOUT_CMU_APM_BUS, "gout_cmu_apm_bus", "mout_cmu_apm_bus",
1118 CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 21, CLK_IGNORE_UNUSED, 0),
1119 GATE(CLK_GOUT_CMU_BUS1_BUS, "gout_cmu_bus1_bus", "mout_cmu_bus1_bus",
1120 CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS, 21, CLK_IGNORE_UNUSED, 0),
1121 GATE(CLK_GOUT_CMU_BUSC_BUS, "gout_cmu_busc_bus", "mout_cmu_busc_bus",
1122 CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS, 21, CLK_IGNORE_UNUSED, 0),
1123 GATE(CLK_GOUT_CMU_BUSC_BUSPHSI2C, "gout_cmu_busc_busphsi2c",
1124 "mout_cmu_busc_busphsi2c", CLK_CON_GAT_GATE_CLKCMU_BUSC_BUSPHSI2C,
1125 21, CLK_IGNORE_UNUSED, 0),
1126 GATE(CLK_GOUT_CMU_CAM_BUS, "gout_cmu_cam_bus", "mout_cmu_cam_bus",
1127 CLK_CON_GAT_GATE_CLKCMU_CAM_BUS, 21, 0, 0),
1128 GATE(CLK_GOUT_CMU_CAM_TPU0, "gout_cmu_cam_tpu0", "mout_cmu_cam_tpu0",
1129 CLK_CON_GAT_GATE_CLKCMU_CAM_TPU0, 21, 0, 0),
1130 GATE(CLK_GOUT_CMU_CAM_TPU1, "gout_cmu_cam_tpu1", "mout_cmu_cam_tpu1",
1131 CLK_CON_GAT_GATE_CLKCMU_CAM_TPU1, 21, 0, 0),
1132 GATE(CLK_GOUT_CMU_CAM_VRA, "gout_cmu_cam_vra", "mout_cmu_cam_vra",
1133 CLK_CON_GAT_GATE_CLKCMU_CAM_VRA, 21, 0, 0),
1134 GATE(CLK_GOUT_CMU_CIS_CLK0, "gout_cmu_cis_clk0", "mout_cmu_cis_clk0",
1135 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0, 21, 0, 0),
1136 GATE(CLK_GOUT_CMU_CIS_CLK1, "gout_cmu_cis_clk1", "mout_cmu_cis_clk1",
1137 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1, 21, 0, 0),
1138 GATE(CLK_GOUT_CMU_CIS_CLK2, "gout_cmu_cis_clk2", "mout_cmu_cis_clk2",
1139 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2, 21, 0, 0),
1140 GATE(CLK_GOUT_CMU_CIS_CLK3, "gout_cmu_cis_clk3", "mout_cmu_cis_clk3",
1141 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3, 21, 0, 0),
1142 GATE(CLK_GOUT_CMU_CORE_BUS, "gout_cmu_core_bus", "mout_core_bus",
1143 CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, CLK_IGNORE_UNUSED, 0),
1144 GATE(CLK_GOUT_CMU_CPUCL0_SWITCH, "gout_cmu_cpucl0_switch",
1145 "mout_cmu_cpucl0_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH,
1146 21, CLK_IGNORE_UNUSED, 0),
1147 GATE(CLK_GOUT_CMU_CPUCL1_SWITCH, "gout_cmu_cpucl1_switch",
1148 "mout_cmu_cpucl1_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH,
1149 21, CLK_IGNORE_UNUSED, 0),
1150 GATE(CLK_GOUT_CMU_DBG_BUS, "gout_cmu_dbg_bus", "mout_cmu_dbg_bus",
1151 CLK_CON_GAT_GATE_CLKCMU_DBG_BUS, 21, 0, 0),
1152 GATE(CLK_GOUT_CMU_DCAM_BUS, "gout_cmu_dcam_bus", "mout_cmu_dcam_bus",
1153 CLK_CON_GAT_GATE_CLKCMU_DCAM_BUS, 21, 0, 0),
1154 GATE(CLK_GOUT_CMU_DCAM_IMGD, "gout_cmu_dcam_imgd",
1155 "mout_cmu_dcam_imgd", CLK_CON_GAT_GATE_CLKCMU_DCAM_IMGD,
1156 21, 0, 0),
1157 GATE(CLK_GOUT_CMU_DPU_BUS, "gout_cmu_dpu_bus", "mout_cmu_dpu_bus",
1158 CLK_CON_GAT_GATE_CLKCMU_DPU_BUS, 21, CLK_IGNORE_UNUSED, 0),
1159 GATE(CLK_GOUT_CMU_DSP_BUS, "gout_cmu_dsp_bus", "mout_cmu_dsp_bus",
1160 CLK_CON_GAT_GATE_CLKCMU_DSP_BUS, 21, CLK_IGNORE_UNUSED, 0),
1161 GATE(CLK_GOUT_CMU_FSYS0_BUS, "gout_cmu_fsys0_bus", "mout_fsys0_bus",
1162 CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS, 21, 0, 0),
1163 GATE(CLK_GOUT_CMU_FSYS0_DPGTC, "gout_cmu_fsys0_dpgtc",
1164 "mout_fsys0_dpgtc", CLK_CON_GAT_GATE_CLKCMU_FSYS0_DPGTC,
1165 21, 0, 0),
1166 GATE(CLK_GOUT_CMU_FSYS0_MMC_EMBD, "gout_cmu_fsys0_mmc_embd",
1167 "mout_fsys0_mmc_embd", CLK_CON_GAT_GATE_CLKCMU_FSYS0_MMC_EMBD,
1168 21, 0, 0),
1169 GATE(CLK_GOUT_CMU_FSYS0_UFS_EMBD, "gout_cmu_fsys0_ufs_embd",
1170 "mout_fsys0_ufs_embd", CLK_CON_GAT_GATE_CLKCMU_FSYS0_UFS_EMBD,
1171 21, 0, 0),
1172 GATE(CLK_GOUT_CMU_FSYS0_USBDRD30, "gout_cmu_fsys0_usbdrd30",
1173 "mout_fsys0_usbdrd30", CLK_CON_GAT_GATE_CLKCMU_FSYS0_USBDRD30,
1174 21, 0, 0),
1175 GATE(CLK_GOUT_CMU_FSYS1_BUS, "gout_cmu_fsys1_bus",
1176 "mout_cmu_fsys1_bus", CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS,
1177 21, 0, 0),
1178 GATE(CLK_GOUT_CMU_FSYS1_MMC_CARD, "gout_cmu_fsys1_mmc_card",
1179 "mout_cmu_fsys1_mmc_card", CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD,
1180 21, 0, 0),
1181 GATE(CLK_GOUT_CMU_FSYS1_PCIE, "gout_cmu_fsys1_pcie",
1182 "mout_cmu_fsys1_pcie", CLK_CON_GAT_GATE_CLKCMU_FSYS1_PCIE,
1183 21, 0, 0),
1184 GATE(CLK_GOUT_CMU_FSYS1_UFS_CARD, "gout_cmu_fsys1_ufs_card",
1185 "mout_cmu_fsys1_ufs_card", CLK_CON_GAT_GATE_CLKCMU_FSYS1_UFS_CARD,
1186 21, 0, 0),
1187 GATE(CLK_GOUT_CMU_G2D_G2D, "gout_cmu_g2d_g2d", "mout_cmu_g2d_g2d",
1188 CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 21, 0, 0),
1189 GATE(CLK_GOUT_CMU_G2D_JPEG, "gout_cmu_g2d_jpeg", "mout_cmu_g2d_jpeg",
1190 CLK_CON_GAT_GATE_CLKCMU_G2D_JPEG, 21, 0, 0),
1191 GATE(CLK_GOUT_CMU_G3D_SWITCH, "gout_cmu_g3d_switch",
1192 "fout_shared2_pll", CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 21, 0, 0),
1193 GATE(CLK_GOUT_CMU_HPM, "gout_cmu_hpm", "mout_cmu_hpm",
1194 CLK_CON_GAT_GATE_CLKCMU_HPM, 21, 0, 0),
1195 GATE(CLK_GOUT_CMU_IMEM_BUS, "gout_cmu_imem_bus", "mout_cmu_imem_bus",
1196 CLK_CON_GAT_GATE_CLKCMU_IMEM_BUS, 21, 0, 0),
1197 GATE(CLK_GOUT_CMU_ISPHQ_BUS, "gout_cmu_isphq_bus",
1198 "mout_cmu_isphq_bus", CLK_CON_GAT_GATE_CLKCMU_ISPHQ_BUS,
1199 21, 0, 0),
1200 GATE(CLK_GOUT_CMU_ISPLP_BUS, "gout_cmu_isplp_bus",
1201 "mout_cmu_isplp_bus", CLK_CON_GAT_GATE_CLKCMU_ISPLP_BUS,
1202 21, 0, 0),
1203 GATE(CLK_GOUT_CMU_IVA_BUS, "gout_cmu_iva_bus", "mout_cmu_iva_bus",
1204 CLK_CON_GAT_GATE_CLKCMU_IVA_BUS, 21, 0, 0),
1205 GATE(CLK_GOUT_CMU_MFC_BUS, "gout_cmu_mfc_bus", "mout_cmu_mfc_bus",
1206 CLK_CON_GAT_GATE_CLKCMU_MFC_BUS, 21, 0, 0),
1207 GATE(CLK_GOUT_CMU_MODEM_SHARED0, "gout_cmu_modem_shared0",
1208 "dout_cmu_shared0_div2", CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0,
1209 21, 0, 0),
1210 GATE(CLK_GOUT_CMU_MODEM_SHARED1, "gout_cmu_modem_shared1",
1211 "fout_shared2_pll", CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1,
1212 21, 0, 0),
1213 GATE(CLK_GOUT_CMU_PERIC0_BUS, "gout_cmu_peric0_bus",
1214 "mout_cmu_peric0_bus", CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS,
1215 21, 0, 0),
1216 GATE(CLK_GOUT_CMU_PERIC0_UART_DBG, "gout_cmu_peric0_uart_dbg",
1217 "mout_cmu_peric0_uart_dbg",
1218 CLK_CON_GAT_GATE_CLKCMU_PERIC0_UART_DBG, 21, 0, 0),
1219 GATE(CLK_GOUT_CMU_PERIC0_USI00, "gout_cmu_peric0_usi00",
1220 "mout_cmu_peric0_usi00", CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI00,
1221 21, 0, 0),
1222 GATE(CLK_GOUT_CMU_PERIC0_USI01, "gout_cmu_peric0_usi01",
1223 "mout_cmu_peric0_usi01", CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI01,
1224 21, 0, 0),
1225 GATE(CLK_GOUT_CMU_PERIC0_USI02, "gout_cmu_peric0_usi02",
1226 "mout_cmu_peric0_usi02", CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI02,
1227 21, 0, 0),
1228 GATE(CLK_GOUT_CMU_PERIC0_USI03, "gout_cmu_peric0_usi03",
1229 "mout_cmu_peric0_usi03", CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI03,
1230 21, 0, 0),
1231 GATE(CLK_GOUT_CMU_PERIC1_BUS, "gout_cmu_peric1_bus",
1232 "mout_cmu_peric1_bus", CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS,
1233 21, 0, 0),
1234 GATE(CLK_GOUT_CMU_PERIC1_SPEEDY2, "gout_cmu_peric1_speedy2",
1235 "mout_cmu_peric1_speedy2", CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPEEDY2,
1236 21, 0, 0),
1237 GATE(CLK_GOUT_CMU_PERIC1_SPI_CAM0, "gout_cmu_peric1_spi_cam0",
1238 "mout_cmu_peric1_spi_cam0",
1239 CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPI_CAM0, 21, 0, 0),
1240 GATE(CLK_GOUT_CMU_PERIC1_SPI_CAM1, "gout_cmu_peric1_spi_cam1",
1241 "mout_cmu_peric1_spi_cam1",
1242 CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPI_CAM1, 21, 0, 0),
1243 GATE(CLK_GOUT_CMU_PERIC1_UART_BT, "gout_cmu_peric1_uart_bt",
1244 "mout_cmu_peric1_uart_bt", CLK_CON_GAT_GATE_CLKCMU_PERIC1_UART_BT,
1245 21, 0, 0),
1246 GATE(CLK_GOUT_CMU_PERIC1_USI04, "gout_cmu_peric1_usi04",
1247 "mout_cmu_peric1_usi04", CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI04,
1248 21, 0, 0),
1249 GATE(CLK_GOUT_CMU_PERIC1_USI05, "gout_cmu_peric1_usi05",
1250 "mout_cmu_peric1_usi05", CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI05,
1251 21, 0, 0),
1252 GATE(CLK_GOUT_CMU_PERIC1_USI06, "gout_cmu_peric1_usi06",
1253 "mout_cmu_peric1_usi06", CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI06,
1254 21, 0, 0),
1255 GATE(CLK_GOUT_CMU_PERIC1_USI07, "gout_cmu_peric1_usi07",
1256 "mout_cmu_peric1_usi07", CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI07,
1257 21, 0, 0),
1258 GATE(CLK_GOUT_CMU_PERIC1_USI08, "gout_cmu_peric1_usi08",
1259 "mout_cmu_peric1_usi08", CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI08,
1260 21, 0, 0),
1261 GATE(CLK_GOUT_CMU_PERIC1_USI09, "gout_cmu_peric1_usi09",
1262 "mout_cmu_peric1_usi09", CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI09,
1263 21, 0, 0),
1264 GATE(CLK_GOUT_CMU_PERIC1_USI10, "gout_cmu_peric1_usi10",
1265 "mout_cmu_peric1_usi10", CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI10,
1266 21, 0, 0),
1267 GATE(CLK_GOUT_CMU_PERIC1_USI11, "gout_cmu_peric1_usi11",
1268 "mout_cmu_peric1_usi11", CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI11,
1269 21, 0, 0),
1270 GATE(CLK_GOUT_CMU_PERIC1_USI12, "gout_cmu_peric1_usi12",
1271 "mout_cmu_peric1_usi12", CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI12,
1272 21, 0, 0),
1273 GATE(CLK_GOUT_CMU_PERIC1_USI13, "gout_cmu_peric1_usi13",
1274 "mout_cmu_peric1_usi13", CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI13,
1275 21, 0, 0),
1276 GATE(CLK_GOUT_CMU_PERIS_BUS, "gout_cmu_peris_bus",
1277 "mout_cmu_peris_bus", CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS,
1278 21, 0, 0),
1279 GATE(CLK_GOUT_CMU_SRDZ_BUS, "gout_cmu_srdz_bus", "mout_cmu_srdz_bus",
1280 CLK_CON_GAT_GATE_CLKCMU_SRDZ_BUS, 21, 0, 0),
1281 GATE(CLK_GOUT_CMU_SRDZ_IMGD, "gout_cmu_srdz_imgd",
1282 "mout_cmu_srdz_imgd", CLK_CON_GAT_GATE_CLKCMU_SRDZ_IMGD,
1283 21, 0, 0),
1284 GATE(CLK_GOUT_CMU_VPU_BUS, "gout_cmu_vpu_bus", "mout_cmu_vpu_bus",
1285 CLK_CON_GAT_GATE_CLKCMU_VPU_BUS, 21, 0, 0),
1286 };
1287
1288 static const struct samsung_cmu_info top_cmu_info __initconst = {
1289 .pll_clks = top_pll_clks,
1290 .nr_pll_clks = ARRAY_SIZE(top_pll_clks),
1291 .mux_clks = top_mux_clks,
1292 .nr_mux_clks = ARRAY_SIZE(top_mux_clks),
1293 .div_clks = top_div_clks,
1294 .nr_div_clks = ARRAY_SIZE(top_div_clks),
1295 .fixed_factor_clks = top_fixed_factor_clks,
1296 .nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks),
1297 .gate_clks = top_gate_clks,
1298 .nr_gate_clks = ARRAY_SIZE(top_gate_clks),
1299 .nr_clk_ids = CLKS_NR_TOP,
1300 .clk_regs = top_clk_regs,
1301 .nr_clk_regs = ARRAY_SIZE(top_clk_regs),
1302 };
1303
exynos8895_cmu_top_init(struct device_node * np)1304 static void __init exynos8895_cmu_top_init(struct device_node *np)
1305 {
1306 exynos_arm64_register_cmu(NULL, np, &top_cmu_info);
1307 }
1308
1309 /* Register CMU_TOP early, as it's a dependency for other early domains */
1310 CLK_OF_DECLARE(exynos8895_cmu_top, "samsung,exynos8895-cmu-top",
1311 exynos8895_cmu_top_init);
1312
1313 /* ---- CMU_PERIS ----------------------------------------------------------- */
1314
1315 /* Register Offset definitions for CMU_PERIS (0x10010000) */
1316 #define PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER 0x0100
1317 #define PLL_CON2_MUX_CLKCMU_PERIS_BUS_USER 0x0108
1318 #define CLK_CON_MUX_MUX_CLK_PERIS_GIC 0x1000
1319 #define CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK 0x2000
1320 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM 0x2010
1321 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKS 0x2014
1322 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP0_IPCLKPORT_ACLK 0x2018
1323 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP1_IPCLKPORT_ACLK 0x201c
1324 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_BUSIF_TMU_IPCLKPORT_PCLK 0x2020
1325 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK 0x2024
1326 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK 0x2028
1327 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK 0x202c
1328 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK 0x2030
1329 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK 0x2034
1330 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_PMU_PERIS_IPCLKPORT_PCLK 0x2038
1331 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK 0x203c
1332 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK 0x2040
1333 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK 0x2044
1334 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC00_IPCLKPORT_PCLK 0x2048
1335 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC01_IPCLKPORT_PCLK 0x204c
1336 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC02_IPCLKPORT_PCLK 0x2050
1337 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC03_IPCLKPORT_PCLK 0x2054
1338 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC04_IPCLKPORT_PCLK 0x2058
1339 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC05_IPCLKPORT_PCLK 0x205c
1340 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC06_IPCLKPORT_PCLK 0x2060
1341 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC07_IPCLKPORT_PCLK 0x2064
1342 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC08_IPCLKPORT_PCLK 0x2068
1343 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC09_IPCLKPORT_PCLK 0x206c
1344 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC10_IPCLKPORT_PCLK 0x2070
1345 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC11_IPCLKPORT_PCLK 0x2074
1346 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC12_IPCLKPORT_PCLK 0x2078
1347 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC13_IPCLKPORT_PCLK 0x207c
1348 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC14_IPCLKPORT_PCLK 0x2080
1349 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC15_IPCLKPORT_PCLK 0x2084
1350 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK 0x2088
1351 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK 0x208c
1352 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_XIU_P_PERIS_IPCLKPORT_ACLK 0x2090
1353
1354 static const unsigned long peris_clk_regs[] __initconst = {
1355 PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER,
1356 PLL_CON2_MUX_CLKCMU_PERIS_BUS_USER,
1357 CLK_CON_MUX_MUX_CLK_PERIS_GIC,
1358 CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK,
1359 CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM,
1360 CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKS,
1361 CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP0_IPCLKPORT_ACLK,
1362 CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP1_IPCLKPORT_ACLK,
1363 CLK_CON_GAT_GOUT_BLK_PERIS_UID_BUSIF_TMU_IPCLKPORT_PCLK,
1364 CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK,
1365 CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK,
1366 CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK,
1367 CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK,
1368 CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK,
1369 CLK_CON_GAT_GOUT_BLK_PERIS_UID_PMU_PERIS_IPCLKPORT_PCLK,
1370 CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK,
1371 CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK,
1372 CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK,
1373 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC00_IPCLKPORT_PCLK,
1374 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC01_IPCLKPORT_PCLK,
1375 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC02_IPCLKPORT_PCLK,
1376 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC03_IPCLKPORT_PCLK,
1377 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC04_IPCLKPORT_PCLK,
1378 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC05_IPCLKPORT_PCLK,
1379 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC06_IPCLKPORT_PCLK,
1380 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC07_IPCLKPORT_PCLK,
1381 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC08_IPCLKPORT_PCLK,
1382 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC09_IPCLKPORT_PCLK,
1383 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC10_IPCLKPORT_PCLK,
1384 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC11_IPCLKPORT_PCLK,
1385 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC12_IPCLKPORT_PCLK,
1386 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC13_IPCLKPORT_PCLK,
1387 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC14_IPCLKPORT_PCLK,
1388 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC15_IPCLKPORT_PCLK,
1389 CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,
1390 CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK,
1391 CLK_CON_GAT_GOUT_BLK_PERIS_UID_XIU_P_PERIS_IPCLKPORT_ACLK,
1392 };
1393
1394 /* List of parent clocks for Muxes in CMU_PERIS */
1395 PNAME(mout_peris_bus_user_p) = { "oscclk", "dout_cmu_peris_bus" };
1396 PNAME(mout_peris_gic_p) = { "oscclk", "mout_peris_bus_user" };
1397
1398 static const struct samsung_mux_clock peris_mux_clks[] __initconst = {
1399 MUX(CLK_MOUT_PERIS_BUS_USER, "mout_peris_bus_user",
1400 mout_peris_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER, 4, 1),
1401 MUX(CLK_MOUT_PERIS_GIC, "mout_peris_gic",
1402 mout_peris_gic_p, CLK_CON_MUX_MUX_CLK_PERIS_GIC, 0, 5),
1403 };
1404
1405 static const struct samsung_gate_clock peris_gate_clks[] __initconst = {
1406 GATE(CLK_GOUT_PERIS_CMU_PERIS_PCLK, "gout_peris_cmu_peris_pclk",
1407 "mout_peris_bus_user",
1408 CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK,
1409 21, CLK_IS_CRITICAL, 0),
1410 GATE(CLK_GOUT_PERIS_AD_AXI_P_PERIS_ACLKM,
1411 "gout_peris_ad_axi_p_peris_aclkm", "mout_peris_gic",
1412 CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM,
1413 21, CLK_IS_CRITICAL, 0),
1414 GATE(CLK_GOUT_PERIS_AD_AXI_P_PERIS_ACLKS,
1415 "gout_peris_ad_axi_p_peris_aclks", "mout_peris_bus_user",
1416 CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKS,
1417 21, CLK_IS_CRITICAL, 0),
1418 GATE(CLK_GOUT_PERIS_AXI2APB_PERISP0_ACLK,
1419 "gout_peris_axi2apb_perisp0_aclk", "mout_peris_bus_user",
1420 CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP0_IPCLKPORT_ACLK,
1421 21, CLK_IS_CRITICAL, 0),
1422 GATE(CLK_GOUT_PERIS_AXI2APB_PERISP1_ACLK,
1423 "gout_peris_axi2apb_perisp1_aclk", "mout_peris_bus_user",
1424 CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP1_IPCLKPORT_ACLK,
1425 21, CLK_IS_CRITICAL, 0),
1426 GATE(CLK_GOUT_PERIS_BUSIF_TMU_PCLK, "gout_peris_busif_tmu_pclk",
1427 "mout_peris_bus_user",
1428 CLK_CON_GAT_GOUT_BLK_PERIS_UID_BUSIF_TMU_IPCLKPORT_PCLK,
1429 21, 0, 0),
1430 /* GIC (interrupt controller) clock must be always running */
1431 GATE(CLK_GOUT_PERIS_GIC_CLK, "gout_peris_gic_clk",
1432 "mout_peris_gic",
1433 CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK,
1434 21, CLK_IS_CRITICAL, 0),
1435 GATE(CLK_GOUT_PERIS_LHM_AXI_P_PERIS_I_CLK,
1436 "gout_peris_lhm_axi_p_peris_i_clk", "mout_peris_bus_user",
1437 CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK,
1438 21, CLK_IS_CRITICAL, 0),
1439 GATE(CLK_GOUT_PERIS_MCT_PCLK, "gout_peris_mct_pclk",
1440 "mout_peris_bus_user",
1441 CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK, 21, 0, 0),
1442 GATE(CLK_GOUT_PERIS_OTP_CON_BIRA_PCLK, "gout_peris_otp_con_bira_pclk",
1443 "mout_peris_bus_user",
1444 CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK,
1445 21, 0, 0),
1446 GATE(CLK_GOUT_PERIS_OTP_CON_TOP_PCLK, "gout_peris_otp_con_top_pclk",
1447 "mout_peris_bus_user",
1448 CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK,
1449 21, 0, 0),
1450 GATE(CLK_GOUT_PERIS_PMU_PERIS_PCLK, "gout_peris_pmu_peris_pclk",
1451 "mout_peris_bus_user",
1452 CLK_CON_GAT_GOUT_BLK_PERIS_UID_PMU_PERIS_IPCLKPORT_PCLK,
1453 21, 0, 0),
1454 GATE(CLK_GOUT_PERIS_RSTNSYNC_CLK_PERIS_BUSP_CLK,
1455 "gout_peris_rstnsync_clk_peris_busp_clk", "mout_peris_bus_user",
1456 CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK,
1457 21, 0, 0),
1458 GATE(CLK_GOUT_PERIS_RSTNSYNC_CLK_PERIS_GIC_CLK,
1459 "gout_peris_rstnsync_clk_peris_gic_clk", "mout_peris_gic",
1460 CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK,
1461 21, 0, 0),
1462 GATE(CLK_GOUT_PERIS_SYSREG_PERIS_PCLK, "gout_peris_sysreg_peris_pclk",
1463 "mout_peris_bus_user",
1464 CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK,
1465 21, 0, 0),
1466 GATE(CLK_GOUT_PERIS_TZPC00_PCLK, "gout_peris_tzpc00_pclk",
1467 "mout_peris_bus_user",
1468 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC00_IPCLKPORT_PCLK, 21, 0, 0),
1469 GATE(CLK_GOUT_PERIS_TZPC01_PCLK, "gout_peris_tzpc01_pclk",
1470 "mout_peris_bus_user",
1471 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC01_IPCLKPORT_PCLK, 21, 0, 0),
1472 GATE(CLK_GOUT_PERIS_TZPC02_PCLK, "gout_peris_tzpc02_pclk",
1473 "mout_peris_bus_user",
1474 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC02_IPCLKPORT_PCLK, 21, 0, 0),
1475 GATE(CLK_GOUT_PERIS_TZPC03_PCLK, "gout_peris_tzpc03_pclk",
1476 "mout_peris_bus_user",
1477 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC03_IPCLKPORT_PCLK, 21, 0, 0),
1478 GATE(CLK_GOUT_PERIS_TZPC04_PCLK, "gout_peris_tzpc04_pclk",
1479 "mout_peris_bus_user",
1480 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC04_IPCLKPORT_PCLK, 21, 0, 0),
1481 GATE(CLK_GOUT_PERIS_TZPC05_PCLK, "gout_peris_tzpc05_pclk",
1482 "mout_peris_bus_user",
1483 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC05_IPCLKPORT_PCLK, 21, 0, 0),
1484 GATE(CLK_GOUT_PERIS_TZPC06_PCLK, "gout_peris_tzpc06_pclk",
1485 "mout_peris_bus_user",
1486 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC06_IPCLKPORT_PCLK, 21, 0, 0),
1487 GATE(CLK_GOUT_PERIS_TZPC07_PCLK, "gout_peris_tzpc07_pclk",
1488 "mout_peris_bus_user",
1489 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC07_IPCLKPORT_PCLK, 21, 0, 0),
1490 GATE(CLK_GOUT_PERIS_TZPC08_PCLK, "gout_peris_tzpc08_pclk",
1491 "mout_peris_bus_user",
1492 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC08_IPCLKPORT_PCLK, 21, 0, 0),
1493 GATE(CLK_GOUT_PERIS_TZPC09_PCLK, "gout_peris_tzpc09_pclk",
1494 "mout_peris_bus_user",
1495 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC09_IPCLKPORT_PCLK, 21, 0, 0),
1496 GATE(CLK_GOUT_PERIS_TZPC10_PCLK, "gout_peris_tzpc10_pclk",
1497 "mout_peris_bus_user",
1498 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC10_IPCLKPORT_PCLK, 21, 0, 0),
1499 GATE(CLK_GOUT_PERIS_TZPC11_PCLK, "gout_peris_tzpc11_pclk",
1500 "mout_peris_bus_user",
1501 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC11_IPCLKPORT_PCLK, 21, 0, 0),
1502 GATE(CLK_GOUT_PERIS_TZPC12_PCLK, "gout_peris_tzpc12_pclk",
1503 "mout_peris_bus_user",
1504 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC12_IPCLKPORT_PCLK, 21, 0, 0),
1505 GATE(CLK_GOUT_PERIS_TZPC13_PCLK, "gout_peris_tzpc13_pclk",
1506 "mout_peris_bus_user",
1507 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC13_IPCLKPORT_PCLK, 21, 0, 0),
1508 GATE(CLK_GOUT_PERIS_TZPC14_PCLK, "gout_peris_tzpc14_pclk",
1509 "mout_peris_bus_user",
1510 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC14_IPCLKPORT_PCLK, 21, 0, 0),
1511 GATE(CLK_GOUT_PERIS_TZPC15_PCLK, "gout_peris_tzpc15_pclk",
1512 "mout_peris_bus_user",
1513 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC15_IPCLKPORT_PCLK, 21, 0, 0),
1514 GATE(CLK_GOUT_PERIS_WDT_CLUSTER0_PCLK, "gout_peris_wdt_cluster0_pclk",
1515 "mout_peris_bus_user",
1516 CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,
1517 21, 0, 0),
1518 GATE(CLK_GOUT_PERIS_WDT_CLUSTER1_PCLK, "gout_peris_wdt_cluster1_pclk",
1519 "mout_peris_bus_user",
1520 CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK,
1521 21, 0, 0),
1522 GATE(CLK_GOUT_PERIS_XIU_P_PERIS_ACLK, "gout_peris_xiu_p_peris_aclk",
1523 "mout_peris_bus_user",
1524 CLK_CON_GAT_GOUT_BLK_PERIS_UID_XIU_P_PERIS_IPCLKPORT_ACLK,
1525 21, CLK_IGNORE_UNUSED, 0),
1526 };
1527
1528 static const struct samsung_cmu_info peris_cmu_info __initconst = {
1529 .mux_clks = peris_mux_clks,
1530 .nr_mux_clks = ARRAY_SIZE(peris_mux_clks),
1531 .gate_clks = peris_gate_clks,
1532 .nr_gate_clks = ARRAY_SIZE(peris_gate_clks),
1533 .nr_clk_ids = CLKS_NR_PERIS,
1534 .clk_regs = peris_clk_regs,
1535 .nr_clk_regs = ARRAY_SIZE(peris_clk_regs),
1536 .clk_name = "bus",
1537 };
1538
exynos8895_cmu_peris_init(struct device_node * np)1539 static void __init exynos8895_cmu_peris_init(struct device_node *np)
1540 {
1541 exynos_arm64_register_cmu(NULL, np, &peris_cmu_info);
1542 }
1543
1544 /* Register CMU_PERIS early, as it's needed for MCT timer */
1545 CLK_OF_DECLARE(exynos8895_cmu_peris, "samsung,exynos8895-cmu-peris",
1546 exynos8895_cmu_peris_init);
1547
1548 /* ---- CMU_FSYS0 ---------------------------------------------------------- */
1549
1550 /* Register Offset definitions for CMU_FSYS0 (0x11000000) */
1551 #define PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER 0x0100
1552 #define PLL_CON2_MUX_CLKCMU_FSYS0_BUS_USER 0x0108
1553 #define PLL_CON0_MUX_CLKCMU_FSYS0_DPGTC_USER 0x0120
1554 #define PLL_CON2_MUX_CLKCMU_FSYS0_DPGTC_USER 0x0128
1555 #define PLL_CON0_MUX_CLKCMU_FSYS0_MMC_EMBD_USER 0x0140
1556 #define PLL_CON2_MUX_CLKCMU_FSYS0_MMC_EMBD_USER 0x0148
1557 #define PLL_CON0_MUX_CLKCMU_FSYS0_UFS_EMBD_USER 0x0160
1558 #define PLL_CON2_MUX_CLKCMU_FSYS0_UFS_EMBD_USER 0x0168
1559 #define PLL_CON0_MUX_CLKCMU_FSYS0_USBDRD30_USER 0x0180
1560 #define PLL_CON2_MUX_CLKCMU_FSYS0_USBDRD30_USER 0x0188
1561 #define CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK 0x2000
1562 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AHBBR_FSYS0_IPCLKPORT_HCLK 0x2010
1563 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2AHB_FSYS0_IPCLKPORT_ACLK 0x2014
1564 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2AHB_USB_FSYS0_IPCLKPORT_ACLK 0x2018
1565 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2APB_FSYS0_IPCLKPORT_ACLK 0x201c
1566 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BTM_FSYS0_IPCLKPORT_I_ACLK 0x2020
1567 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BTM_FSYS0_IPCLKPORT_I_PCLK 0x2024
1568 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_GTC_EXT_CLK 0x202c
1569 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_PCLK 0x2030
1570 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_ETR_MIU_IPCLKPORT_I_ACLK 0x2034
1571 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_ETR_MIU_IPCLKPORT_I_PCLK 0x2038
1572 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_GPIO_FSYS0_IPCLKPORT_PCLK 0x203c
1573 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_D_USBTV_IPCLKPORT_I_CLK 0x2040
1574 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_G_ETR_IPCLKPORT_I_CLK 0x2044
1575 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_P_FSYS0_IPCLKPORT_I_CLK 0x2048
1576 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHS_ACEL_D_FSYS0_IPCLKPORT_I_CLK 0x204c
1577 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_MMC_EMBD_IPCLKPORT_I_ACLK 0x2050
1578 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_MMC_EMBD_IPCLKPORT_SDCLKIN 0x2054
1579 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PMU_FSYS0_IPCLKPORT_PCLK 0x2058
1580 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BCM_FSYS0_IPCLKPORT_ACLK 0x205c
1581 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BCM_FSYS0_IPCLKPORT_PCLK 0x2060
1582 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_RSTNSYNC_CLK_FSYS0_BUS_IPCLKPORT_CLK 0x2064
1583 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_SYSREG_FSYS0_IPCLKPORT_PCLK 0x2068
1584 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_ACLK 0x206c
1585 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO 0x2070
1586 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK 0x2074
1587 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_ACLK 0x2078
1588 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_REF_CLK 0x207c
1589 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_SUSPEND_CLK 0x2080
1590 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_AHB_CLK 0x2084
1591 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_CORE_CLK 0x2088
1592 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_XIU_CLK 0x208c
1593 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_US_D_FSYS0_USB_IPCLKPORT_ACLK 0x2090
1594 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_D_FSYS0_IPCLKPORT_ACLK 0x2094
1595 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_D_FSYS0_USB_IPCLKPORT_ACLK 0x2098
1596 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_P_FSYS0_IPCLKPORT_ACLK 0x209c
1597
1598 static const unsigned long fsys0_clk_regs[] __initconst = {
1599 PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER,
1600 PLL_CON2_MUX_CLKCMU_FSYS0_BUS_USER,
1601 PLL_CON0_MUX_CLKCMU_FSYS0_DPGTC_USER,
1602 PLL_CON2_MUX_CLKCMU_FSYS0_DPGTC_USER,
1603 PLL_CON0_MUX_CLKCMU_FSYS0_MMC_EMBD_USER,
1604 PLL_CON2_MUX_CLKCMU_FSYS0_MMC_EMBD_USER,
1605 PLL_CON0_MUX_CLKCMU_FSYS0_UFS_EMBD_USER,
1606 PLL_CON2_MUX_CLKCMU_FSYS0_UFS_EMBD_USER,
1607 PLL_CON0_MUX_CLKCMU_FSYS0_USBDRD30_USER,
1608 PLL_CON2_MUX_CLKCMU_FSYS0_USBDRD30_USER,
1609 CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK,
1610 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AHBBR_FSYS0_IPCLKPORT_HCLK,
1611 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2AHB_FSYS0_IPCLKPORT_ACLK,
1612 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2AHB_USB_FSYS0_IPCLKPORT_ACLK,
1613 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2APB_FSYS0_IPCLKPORT_ACLK,
1614 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BTM_FSYS0_IPCLKPORT_I_ACLK,
1615 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BTM_FSYS0_IPCLKPORT_I_PCLK,
1616 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_GTC_EXT_CLK,
1617 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_PCLK,
1618 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_ETR_MIU_IPCLKPORT_I_ACLK,
1619 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_ETR_MIU_IPCLKPORT_I_PCLK,
1620 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_GPIO_FSYS0_IPCLKPORT_PCLK,
1621 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_D_USBTV_IPCLKPORT_I_CLK,
1622 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_G_ETR_IPCLKPORT_I_CLK,
1623 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_P_FSYS0_IPCLKPORT_I_CLK,
1624 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHS_ACEL_D_FSYS0_IPCLKPORT_I_CLK,
1625 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_MMC_EMBD_IPCLKPORT_I_ACLK,
1626 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_MMC_EMBD_IPCLKPORT_SDCLKIN,
1627 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PMU_FSYS0_IPCLKPORT_PCLK,
1628 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BCM_FSYS0_IPCLKPORT_ACLK,
1629 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BCM_FSYS0_IPCLKPORT_PCLK,
1630 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_RSTNSYNC_CLK_FSYS0_BUS_IPCLKPORT_CLK,
1631 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_SYSREG_FSYS0_IPCLKPORT_PCLK,
1632 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_ACLK,
1633 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO,
1634 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK,
1635 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_ACLK,
1636 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_REF_CLK,
1637 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_SUSPEND_CLK,
1638 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_AHB_CLK,
1639 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_CORE_CLK,
1640 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_XIU_CLK,
1641 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_US_D_FSYS0_USB_IPCLKPORT_ACLK,
1642 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_D_FSYS0_IPCLKPORT_ACLK,
1643 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_D_FSYS0_USB_IPCLKPORT_ACLK,
1644 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_P_FSYS0_IPCLKPORT_ACLK,
1645 };
1646
1647 /* List of parent clocks for Muxes in CMU_FSYS0 */
1648 PNAME(mout_fsys0_bus_user_p) = { "oscclk", "dout_cmu_fsys0_bus" };
1649 PNAME(mout_fsys0_dpgtc_user_p) = { "oscclk", "dout_cmu_fsys0_dpgtc" };
1650 PNAME(mout_fsys0_mmc_embd_user_p) = { "oscclk",
1651 "dout_cmu_fsys0_mmc_embd" };
1652 PNAME(mout_fsys0_ufs_embd_user_p) = { "oscclk",
1653 "dout_cmu_fsys0_ufs_embd" };
1654 PNAME(mout_fsys0_usbdrd30_user_p) = { "oscclk",
1655 "dout_cmu_fsys0_usbdrd30" };
1656
1657 static const struct samsung_mux_clock fsys0_mux_clks[] __initconst = {
1658 MUX(CLK_MOUT_FSYS0_BUS_USER, "mout_fsys0_bus_user",
1659 mout_fsys0_bus_user_p, PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER, 4, 1),
1660 MUX(CLK_MOUT_FSYS0_DPGTC_USER, "mout_fsys0_dpgtc_user",
1661 mout_fsys0_dpgtc_user_p, PLL_CON0_MUX_CLKCMU_FSYS0_DPGTC_USER,
1662 4, 1),
1663 MUX_F(CLK_MOUT_FSYS0_MMC_EMBD_USER, "mout_fsys0_mmc_embd_user",
1664 mout_fsys0_mmc_embd_user_p, PLL_CON0_MUX_CLKCMU_FSYS0_MMC_EMBD_USER,
1665 4, 1, CLK_SET_RATE_PARENT, 0),
1666 MUX(CLK_MOUT_FSYS0_UFS_EMBD_USER, "mout_fsys0_ufs_embd_user",
1667 mout_fsys0_ufs_embd_user_p, PLL_CON0_MUX_CLKCMU_FSYS0_UFS_EMBD_USER,
1668 4, 1),
1669 MUX(CLK_MOUT_FSYS0_USBDRD30_USER, "mout_fsys0_usbdrd30_user",
1670 mout_fsys0_usbdrd30_user_p, PLL_CON0_MUX_CLKCMU_FSYS0_USBDRD30_USER,
1671 4, 1),
1672 };
1673
1674 static const struct samsung_gate_clock fsys0_gate_clks[] __initconst = {
1675 /* Disabling this clock makes the system hang. Mark the clock as critical. */
1676 GATE(CLK_GOUT_FSYS0_FSYS0_CMU_FSYS0_PCLK,
1677 "gout_fsys0_fsys0_cmu_fsys0_pclk", "mout_fsys0_bus_user",
1678 CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK,
1679 21, CLK_IS_CRITICAL, 0),
1680 GATE(CLK_GOUT_FSYS0_AHBBR_FSYS0_HCLK, "gout_fsys0_ahbbr_fsys0_hclk",
1681 "mout_fsys0_bus_user",
1682 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AHBBR_FSYS0_IPCLKPORT_HCLK,
1683 21, 0, 0),
1684 GATE(CLK_GOUT_FSYS0_AXI2AHB_FSYS0_ACLK,
1685 "gout_fsys0_axi2ahb_fsys0_aclk", "mout_fsys0_bus_user",
1686 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2AHB_FSYS0_IPCLKPORT_ACLK,
1687 21, CLK_IS_CRITICAL, 0),
1688 GATE(CLK_GOUT_FSYS0_AXI2AHB_USB_FSYS0_ACLK,
1689 "gout_fsys0_axi2ahb_usb_fsys0_aclk", "mout_fsys0_bus_user",
1690 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2AHB_USB_FSYS0_IPCLKPORT_ACLK,
1691 21, CLK_IS_CRITICAL, 0),
1692 GATE(CLK_GOUT_FSYS0_AXI2APB_FSYS0_ACLK,
1693 "gout_fsys0_axi2apb_fsys0_aclk", "mout_fsys0_bus_user",
1694 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2APB_FSYS0_IPCLKPORT_ACLK,
1695 21, CLK_IS_CRITICAL, 0),
1696 GATE(CLK_GOUT_FSYS0_BTM_FSYS0_I_ACLK, "gout_fsys0_btm_fsys0_i_aclk",
1697 "mout_fsys0_bus_user",
1698 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BTM_FSYS0_IPCLKPORT_I_ACLK,
1699 21, 0, 0),
1700 GATE(CLK_GOUT_FSYS0_BTM_FSYS0_I_PCLK, "gout_fsys0_btm_fsys0_i_pclk",
1701 "mout_fsys0_bus_user",
1702 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BTM_FSYS0_IPCLKPORT_I_PCLK,
1703 21, 0, 0),
1704 GATE(CLK_GOUT_FSYS0_DP_LINK_I_GTC_EXT_CLK,
1705 "gout_fsys0_dp_link_i_gtc_ext_clk", "mout_fsys0_dpgtc_user",
1706 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_GTC_EXT_CLK,
1707 21, 0, 0),
1708 GATE(CLK_GOUT_FSYS0_DP_LINK_I_PCLK, "gout_fsys0_dp_link_i_pclk",
1709 "mout_fsys0_bus_user",
1710 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_PCLK,
1711 21, 0, 0),
1712 GATE(CLK_GOUT_FSYS0_ETR_MIU_I_ACLK, "gout_fsys0_etr_miu_i_aclk",
1713 "mout_fsys0_bus_user",
1714 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_ETR_MIU_IPCLKPORT_I_ACLK, 21, 0, 0),
1715 GATE(CLK_GOUT_FSYS0_ETR_MIU_I_PCLK, "gout_fsys0_etr_miu_i_pclk",
1716 "mout_fsys0_bus_user",
1717 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_ETR_MIU_IPCLKPORT_I_PCLK, 21, 0, 0),
1718 GATE(CLK_GOUT_FSYS0_GPIO_FSYS0_PCLK, "gout_fsys0_gpio_fsys0_pclk",
1719 "mout_fsys0_bus_user",
1720 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_GPIO_FSYS0_IPCLKPORT_PCLK,
1721 21, CLK_IGNORE_UNUSED, 0),
1722 GATE(CLK_GOUT_FSYS0_LHM_AXI_D_USBTV_I_CLK,
1723 "gout_fsys0_lhm_axi_d_usbtv_i_clk", "mout_fsys0_bus_user",
1724 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_D_USBTV_IPCLKPORT_I_CLK,
1725 21, 0, 0),
1726 GATE(CLK_GOUT_FSYS0_LHM_AXI_G_ETR_I_CLK,
1727 "gout_fsys0_lhm_axi_g_etr_i_clk", "mout_fsys0_bus_user",
1728 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_G_ETR_IPCLKPORT_I_CLK,
1729 21, 0, 0),
1730 GATE(CLK_GOUT_FSYS0_LHM_AXI_P_FSYS0_I_CLK,
1731 "gout_fsys0_lhm_axi_p_fsys0_i_clk", "mout_fsys0_bus_user",
1732 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_P_FSYS0_IPCLKPORT_I_CLK,
1733 21, CLK_IS_CRITICAL, 0),
1734 GATE(CLK_GOUT_FSYS0_LHS_ACEL_D_FSYS0_I_CLK,
1735 "gout_fsys0_lhs_acel_d_fsys0_i_clk", "mout_fsys0_bus_user",
1736 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHS_ACEL_D_FSYS0_IPCLKPORT_I_CLK,
1737 21, CLK_IS_CRITICAL, 0),
1738 GATE(CLK_GOUT_FSYS0_MMC_EMBD_I_ACLK, "gout_fsys0_mmc_embd_i_aclk",
1739 "mout_fsys0_bus_user",
1740 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_MMC_EMBD_IPCLKPORT_I_ACLK,
1741 21, 0, 0),
1742 GATE(CLK_GOUT_FSYS0_MMC_EMBD_SDCLKIN, "gout_fsys0_mmc_embd_sdclkin",
1743 "mout_fsys0_mmc_embd_user",
1744 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_MMC_EMBD_IPCLKPORT_SDCLKIN,
1745 21, CLK_SET_RATE_PARENT, 0),
1746 GATE(CLK_GOUT_FSYS0_PMU_FSYS0_PCLK, "gout_fsys0_pmu_fsys0_pclk",
1747 "mout_fsys0_bus_user",
1748 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PMU_FSYS0_IPCLKPORT_PCLK, 21, 0, 0),
1749 GATE(CLK_GOUT_FSYS0_BCM_FSYS0_ACLK, "gout_fsys0_bcm_fsys0_aclk",
1750 "mout_fsys0_bus_user",
1751 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BCM_FSYS0_IPCLKPORT_ACLK, 21, 0, 0),
1752 GATE(CLK_GOUT_FSYS0_BCM_FSYS0_PCLK, "gout_fsys0_bcm_fsys0_pclk",
1753 "mout_fsys0_bus_user",
1754 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BCM_FSYS0_IPCLKPORT_PCLK, 21, 0, 0),
1755 GATE(CLK_GOUT_FSYS0_RSTNSYNC_CLK_FSYS0_BUS_CLK,
1756 "gout_fsys0_rstnsync_clk_fsys0_bus_clk", "mout_fsys0_bus_user",
1757 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_RSTNSYNC_CLK_FSYS0_BUS_IPCLKPORT_CLK,
1758 21, 0, 0),
1759 GATE(CLK_GOUT_FSYS0_SYSREG_FSYS0_PCLK, "gout_fsys0_sysreg_fsys0_pclk",
1760 "mout_fsys0_bus_user",
1761 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_SYSREG_FSYS0_IPCLKPORT_PCLK,
1762 21, 0, 0),
1763 GATE(CLK_GOUT_FSYS0_UFS_EMBD_I_ACLK, "gout_fsys0_ufs_embd_i_aclk",
1764 "mout_fsys0_bus_user",
1765 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_ACLK,
1766 21, 0, 0),
1767 GATE(CLK_GOUT_FSYS0_UFS_EMBD_I_CLK_UNIPRO,
1768 "gout_fsys0_ufs_embd_i_clk_unipro", "mout_fsys0_ufs_embd_user",
1769 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO,
1770 21, CLK_IS_CRITICAL, 0),
1771 GATE(CLK_GOUT_FSYS0_UFS_EMBD_I_FMP_CLK,
1772 "gout_fsys0_ufs_embd_i_fmp_clk", "mout_fsys0_bus_user",
1773 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK,
1774 21, 0, 0),
1775 GATE(CLK_GOUT_FSYS0_USBTV_I_USB30DRD_ACLK,
1776 "gout_fsys0_usbtv_i_usb30drd_aclk", "mout_fsys0_bus_user",
1777 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_ACLK,
1778 21, 0, 0),
1779 GATE(CLK_GOUT_FSYS0_USBTV_I_USB30DRD_REF_CLK,
1780 "gout_fsys0_usbtv_i_usb30drd_ref_clk", "mout_fsys0_usbdrd30_user",
1781 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_REF_CLK,
1782 21, 0, 0),
1783 GATE(CLK_GOUT_FSYS0_USBTV_I_USB30DRD_SUSPEND_CLK,
1784 "gout_fsys0_usbtv_i_usb30drd_suspend_clk",
1785 "mout_fsys0_usbdrd30_user",
1786 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_SUSPEND_CLK,
1787 21, 0, 0),
1788 GATE(CLK_GOUT_FSYS0_USBTV_I_USBTVH_AHB_CLK,
1789 "gout_fsys0_usbtv_i_usbtvh_ahb_clk", "mout_fsys0_bus_user",
1790 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_AHB_CLK,
1791 21, 0, 0),
1792 GATE(CLK_GOUT_FSYS0_USBTV_I_USBTVH_CORE_CLK,
1793 "gout_fsys0_usbtv_i_usbtvh_core_clk", "mout_fsys0_bus_user",
1794 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_CORE_CLK,
1795 21, 0, 0),
1796 GATE(CLK_GOUT_FSYS0_USBTV_I_USBTVH_XIU_CLK,
1797 "gout_fsys0_usbtv_i_usbtvh_xiu_clk", "mout_fsys0_bus_user",
1798 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_XIU_CLK,
1799 21, 0, 0),
1800 GATE(CLK_GOUT_FSYS0_US_D_FSYS0_USB_ACLK,
1801 "gout_fsys0_us_d_fsys0_usb_aclk", "mout_fsys0_bus_user",
1802 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_US_D_FSYS0_USB_IPCLKPORT_ACLK,
1803 21, 0, 0),
1804 GATE(CLK_GOUT_FSYS0_XIU_D_FSYS0_ACLK, "gout_fsys0_xiu_d_fsys0_aclk",
1805 "mout_fsys0_bus_user",
1806 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_D_FSYS0_IPCLKPORT_ACLK,
1807 21, CLK_IGNORE_UNUSED, 0),
1808 GATE(CLK_GOUT_FSYS0_XIU_D_FSYS0_USB_ACLK,
1809 "gout_fsys0_xiu_d_fsys0_usb_aclk", "mout_fsys0_bus_user",
1810 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_D_FSYS0_USB_IPCLKPORT_ACLK,
1811 21, CLK_IGNORE_UNUSED, 0),
1812 GATE(CLK_GOUT_FSYS0_XIU_P_FSYS0_ACLK,
1813 "gout_fsys0_xiu_p_fsys0_aclk", "mout_fsys0_bus_user",
1814 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_P_FSYS0_IPCLKPORT_ACLK,
1815 21, CLK_IGNORE_UNUSED, 0),
1816 };
1817
1818 static const struct samsung_cmu_info fsys0_cmu_info __initconst = {
1819 .mux_clks = fsys0_mux_clks,
1820 .nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks),
1821 .gate_clks = fsys0_gate_clks,
1822 .nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks),
1823 .nr_clk_ids = CLKS_NR_FSYS0,
1824 .clk_regs = fsys0_clk_regs,
1825 .nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs),
1826 .clk_name = "bus",
1827 };
1828
1829 /* ---- CMU_FSYS1 ---------------------------------------------------------- */
1830
1831 /* Register Offset definitions for CMU_FSYS1 (0x11400000) */
1832 #define PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER 0x0100
1833 #define PLL_CON2_MUX_CLKCMU_FSYS1_BUS_USER 0x0108
1834 #define PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER 0x0120
1835 #define PLL_CON2_MUX_CLKCMU_FSYS1_MMC_CARD_USER 0x0128
1836 #define PLL_CON0_MUX_CLKCMU_FSYS1_PCIE_USER 0x0140
1837 #define PLL_CON2_MUX_CLKCMU_FSYS1_PCIE_USER 0x0148
1838 #define PLL_CON0_MUX_CLKCMU_FSYS1_UFS_CARD_USER 0x0160
1839 #define PLL_CON2_MUX_CLKCMU_FSYS1_UFS_CARD_USER 0x0168
1840 #define CLK_CON_GAT_CLK_BLK_FSYS1_UID_PCIE_IPCLKPORT_PHY_REF_CLK_IN 0x2000
1841 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM 0x2004
1842 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AHBBR_FSYS1_IPCLKPORT_HCLK 0x2008
1843 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2AHB_FSYS1_IPCLKPORT_ACLK 0x200c
1844 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P0_IPCLKPORT_ACLK 0x2010
1845 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P1_IPCLKPORT_ACLK 0x2014
1846 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_ACLK 0x2018
1847 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_PCLK 0x201c
1848 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK 0x2024
1849 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_GPIO_FSYS1_IPCLKPORT_PCLK 0x2028
1850 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHM_AXI_P_FSYS1_IPCLKPORT_I_CLK 0x202c
1851 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHS_ACEL_D_FSYS1_IPCLKPORT_I_CLK 0x2030
1852 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK 0x2034
1853 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN 0x2038
1854 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_DBI_ACLK_0 0x203c
1855 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_DBI_ACLK_1 0x2040
1856 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIE_PHY_LC_X2_INST_0_I_SCL_APB_PCLK 0x2044
1857 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_MSTR_ACLK_0 0x2048
1858 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_MSTR_ACLK_1 0x204c
1859 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK 0x2050
1860 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PCIE_SUB_CTRL_INST_1_I_DRIVER_APB_CLK 0x2054
1861 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PIPE2_DIGITAL_X2_WRAP_INST_0_I_APB_PCLK_SCL 0x2058
1862 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_SLV_ACLK_0 0x205c
1863 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_SLV_ACLK_1 0x2060
1864 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PMU_FSYS1_IPCLKPORT_PCLK 0x2068
1865 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BCM_FSYS1_IPCLKPORT_ACLK 0x206c
1866 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BCM_FSYS1_IPCLKPORT_PCLK 0x2070
1867 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RSTNSYNC_CLK_FSYS1_BUS_IPCLKPORT_CLK 0x2074
1868 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_ACLK 0x207c
1869 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_PCLK 0x2080
1870 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_ACLK 0x2084
1871 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_PCLK 0x2088
1872 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SYSREG_FSYS1_IPCLKPORT_PCLK 0x2090
1873 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_TOE_WIFI0_IPCLKPORT_I_CLK 0x2094
1874 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_TOE_WIFI1_IPCLKPORT_I_CLK 0x2098
1875 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_ACLK 0x209c
1876 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_CLK_UNIPRO 0x20a0
1877 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_FMP_CLK 0x20a4
1878 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_D_FSYS1_IPCLKPORT_ACLK 0x20a8
1879 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_P_FSYS1_IPCLKPORT_ACLK 0x20ac
1880
1881 static const unsigned long fsys1_clk_regs[] __initconst = {
1882 PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER,
1883 PLL_CON2_MUX_CLKCMU_FSYS1_BUS_USER,
1884 PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER,
1885 PLL_CON2_MUX_CLKCMU_FSYS1_MMC_CARD_USER,
1886 PLL_CON0_MUX_CLKCMU_FSYS1_PCIE_USER,
1887 PLL_CON2_MUX_CLKCMU_FSYS1_PCIE_USER,
1888 PLL_CON0_MUX_CLKCMU_FSYS1_UFS_CARD_USER,
1889 PLL_CON2_MUX_CLKCMU_FSYS1_UFS_CARD_USER,
1890 CLK_CON_GAT_CLK_BLK_FSYS1_UID_PCIE_IPCLKPORT_PHY_REF_CLK_IN,
1891 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM,
1892 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AHBBR_FSYS1_IPCLKPORT_HCLK,
1893 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2AHB_FSYS1_IPCLKPORT_ACLK,
1894 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P0_IPCLKPORT_ACLK,
1895 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P1_IPCLKPORT_ACLK,
1896 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_ACLK,
1897 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_PCLK,
1898 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK,
1899 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_GPIO_FSYS1_IPCLKPORT_PCLK,
1900 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHM_AXI_P_FSYS1_IPCLKPORT_I_CLK,
1901 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHS_ACEL_D_FSYS1_IPCLKPORT_I_CLK,
1902 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK,
1903 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN,
1904 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_DBI_ACLK_0,
1905 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_DBI_ACLK_1,
1906 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIE_PHY_LC_X2_INST_0_I_SCL_APB_PCLK,
1907 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_MSTR_ACLK_0,
1908 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_MSTR_ACLK_1,
1909 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK,
1910 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PCIE_SUB_CTRL_INST_1_I_DRIVER_APB_CLK,
1911 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PIPE2_DIGITAL_X2_WRAP_INST_0_I_APB_PCLK_SCL,
1912 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_SLV_ACLK_0,
1913 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_SLV_ACLK_1,
1914 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PMU_FSYS1_IPCLKPORT_PCLK,
1915 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BCM_FSYS1_IPCLKPORT_ACLK,
1916 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BCM_FSYS1_IPCLKPORT_PCLK,
1917 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RSTNSYNC_CLK_FSYS1_BUS_IPCLKPORT_CLK,
1918 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_ACLK,
1919 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_PCLK,
1920 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_ACLK,
1921 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_PCLK,
1922 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SYSREG_FSYS1_IPCLKPORT_PCLK,
1923 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_TOE_WIFI0_IPCLKPORT_I_CLK,
1924 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_TOE_WIFI1_IPCLKPORT_I_CLK,
1925 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_ACLK,
1926 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_CLK_UNIPRO,
1927 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_FMP_CLK,
1928 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_D_FSYS1_IPCLKPORT_ACLK,
1929 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_P_FSYS1_IPCLKPORT_ACLK,
1930 };
1931
1932 /* List of parent clocks for Muxes in CMU_FSYS1 */
1933 PNAME(mout_fsys1_bus_user_p) = { "oscclk", "dout_cmu_fsys1_bus" };
1934 PNAME(mout_fsys1_mmc_card_user_p) = { "oscclk",
1935 "dout_cmu_fsys1_mmc_card" };
1936 PNAME(mout_fsys1_pcie_user_p) = { "oscclk", "dout_cmu_fsys1_pcie" };
1937 PNAME(mout_fsys1_ufs_card_user_p) = { "oscclk",
1938 "dout_cmu_fsys1_ufs_card" };
1939
1940 static const struct samsung_mux_clock fsys1_mux_clks[] __initconst = {
1941 MUX(CLK_MOUT_FSYS1_BUS_USER, "mout_fsys1_bus_user",
1942 mout_fsys1_bus_user_p, PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER, 4, 1),
1943 MUX_F(CLK_MOUT_FSYS1_MMC_CARD_USER, "mout_fsys1_mmc_card_user",
1944 mout_fsys1_mmc_card_user_p,
1945 PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER,
1946 4, 1, CLK_SET_RATE_PARENT, 0),
1947 MUX(CLK_MOUT_FSYS1_PCIE_USER, "mout_fsys1_pcie_user",
1948 mout_fsys1_pcie_user_p, PLL_CON0_MUX_CLKCMU_FSYS1_PCIE_USER, 4, 1),
1949 MUX(CLK_MOUT_FSYS1_UFS_CARD_USER, "mout_fsys1_ufs_card_user",
1950 mout_fsys1_ufs_card_user_p,
1951 PLL_CON0_MUX_CLKCMU_FSYS1_UFS_CARD_USER, 4, 1),
1952 };
1953
1954 static const struct samsung_gate_clock fsys1_gate_clks[] __initconst = {
1955 GATE(CLK_GOUT_FSYS1_PCIE_PHY_REF_CLK_IN,
1956 "gout_clk_blk_fsys1_pcie_phy_ref_clk_in", "mout_fsys1_pcie_user",
1957 CLK_CON_GAT_CLK_BLK_FSYS1_UID_PCIE_IPCLKPORT_PHY_REF_CLK_IN,
1958 21, 0, 0),
1959 GATE(CLK_GOUT_FSYS1_ADM_AHB_SSS_HCLKM, "gout_fsys1_adm_ahb_sss_hclkm",
1960 "mout_fsys1_bus_user",
1961 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM,
1962 21, 0, 0),
1963 GATE(CLK_GOUT_FSYS1_AHBBR_FSYS1_HCLK, "gout_fsys1_ahbbr_fsys1_hclk",
1964 "mout_fsys1_bus_user",
1965 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AHBBR_FSYS1_IPCLKPORT_HCLK,
1966 21, CLK_IS_CRITICAL, 0),
1967 GATE(CLK_GOUT_FSYS1_AXI2AHB_FSYS1_ACLK,
1968 "gout_fsys1_axi2ahb_fsys1_aclk", "mout_fsys1_bus_user",
1969 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2AHB_FSYS1_IPCLKPORT_ACLK,
1970 21, CLK_IS_CRITICAL, 0),
1971 GATE(CLK_GOUT_FSYS1_AXI2APB_FSYS1P0_ACLK,
1972 "gout_fsys1_axi2apb_fsys1p0_aclk", "mout_fsys1_bus_user",
1973 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P0_IPCLKPORT_ACLK,
1974 21, CLK_IS_CRITICAL, 0),
1975 GATE(CLK_GOUT_FSYS1_AXI2APB_FSYS1P1_ACLK,
1976 "gout_fsys1_axi2apb_fsys1p1_aclk", "mout_fsys1_bus_user",
1977 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P1_IPCLKPORT_ACLK,
1978 21, CLK_IS_CRITICAL, 0),
1979 GATE(CLK_GOUT_FSYS1_BTM_FSYS1_I_ACLK, "gout_fsys1_btm_fsys1_i_aclk",
1980 "mout_fsys1_bus_user",
1981 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_ACLK,
1982 21, 0, 0),
1983 GATE(CLK_GOUT_FSYS1_BTM_FSYS1_I_PCLK, "gout_fsys1_btm_fsys1_i_pclk",
1984 "mout_fsys1_bus_user",
1985 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_PCLK,
1986 21, 0, 0),
1987 GATE(CLK_GOUT_FSYS1_FSYS1_CMU_FSYS1_PCLK,
1988 "gout_fsys1_fsys1_cmu_fsys1_pclk", "mout_fsys1_bus_user",
1989 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK,
1990 21, CLK_IS_CRITICAL, 0),
1991 GATE(CLK_GOUT_FSYS1_GPIO_FSYS1_PCLK, "gout_fsys1_gpio_fsys1_pclk",
1992 "mout_fsys1_bus_user",
1993 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_GPIO_FSYS1_IPCLKPORT_PCLK,
1994 21, CLK_IGNORE_UNUSED, 0),
1995 GATE(CLK_GOUT_FSYS1_LHM_AXI_P_FSYS1_I_CLK,
1996 "gout_fsys1_lhm_axi_p_fsys1_i_clk", "mout_fsys1_bus_user",
1997 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHM_AXI_P_FSYS1_IPCLKPORT_I_CLK,
1998 21, CLK_IS_CRITICAL, 0),
1999 GATE(CLK_GOUT_FSYS1_LHS_ACEL_D_FSYS1_I_CLK,
2000 "gout_fsys1_lhs_acel_d_fsys1_i_clk", "mout_fsys1_bus_user",
2001 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHS_ACEL_D_FSYS1_IPCLKPORT_I_CLK,
2002 21, CLK_IS_CRITICAL, 0),
2003 GATE(CLK_GOUT_FSYS1_MMC_CARD_I_ACLK, "gout_fsys1_mmc_card_i_aclk",
2004 "mout_fsys1_bus_user",
2005 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK,
2006 21, 0, 0),
2007 GATE(CLK_GOUT_FSYS1_MMC_CARD_SDCLKIN, "gout_fsys1_mmc_card_sdclkin",
2008 "mout_fsys1_mmc_card_user",
2009 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN,
2010 21, CLK_SET_RATE_PARENT, 0),
2011 GATE(CLK_GOUT_FSYS1_PCIE_DBI_ACLK_0, "gout_fsys1_pcie_dbi_aclk_0",
2012 "mout_fsys1_bus_user",
2013 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_DBI_ACLK_0,
2014 21, 0, 0),
2015 GATE(CLK_GOUT_FSYS1_PCIE_DBI_ACLK_1, "gout_fsys1_pcie_dbi_aclk_1",
2016 "mout_fsys1_bus_user",
2017 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_DBI_ACLK_1,
2018 21, 0, 0),
2019 GATE(CLK_GOUT_FSYS1_PCIE_IEEE1500_WRAPPER_FOR_PCIE_PHY_LC_X2_INST_0_I_SCL_APB_PCLK,
2020 "gout_fsys1_pcie_ieee1500_wrapper_for_pcie_phy_lc_x2_inst_0_i_scl_apb_pclk",
2021 "mout_fsys1_bus_user",
2022 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIE_PHY_LC_X2_INST_0_I_SCL_APB_PCLK,
2023 21, 0, 0),
2024 GATE(CLK_GOUT_FSYS1_PCIE_MSTR_ACLK_0,
2025 "gout_fsys1_pcie_mstr_aclk_0", "mout_fsys1_bus_user",
2026 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_MSTR_ACLK_0,
2027 21, 0, 0),
2028 GATE(CLK_GOUT_FSYS1_PCIE_MSTR_ACLK_1,
2029 "gout_fsys1_pcie_mstr_aclk_1", "mout_fsys1_bus_user",
2030 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_MSTR_ACLK_1,
2031 21, 0, 0),
2032 GATE(CLK_GOUT_FSYS1_PCIE_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK,
2033 "gout_fsys1_pcie_pcie_sub_ctrl_inst_0_i_driver_apb_clk",
2034 "mout_fsys1_bus_user",
2035 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK,
2036 21, 0, 0),
2037 GATE(CLK_GOUT_FSYS1_PCIE_PCIE_SUB_CTRL_INST_1_I_DRIVER_APB_CLK,
2038 "gout_fsys1_pcie_pcie_sub_ctrl_inst_1_i_driver_apb_clk",
2039 "mout_fsys1_bus_user",
2040 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PCIE_SUB_CTRL_INST_1_I_DRIVER_APB_CLK,
2041 21, 0, 0),
2042 GATE(CLK_GOUT_FSYS1_PCIE_PIPE2_DIGITAL_X2_WRAP_INST_0_I_APB_PCLK_SCL,
2043 "gout_fsys1_pcie_pipe2_digital_x2_wrap_inst_0_i_apb_pclk_scl",
2044 "mout_fsys1_bus_user",
2045 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PIPE2_DIGITAL_X2_WRAP_INST_0_I_APB_PCLK_SCL,
2046 21, 0, 0),
2047 GATE(CLK_GOUT_FSYS1_PCIE_SLV_ACLK_0, "gout_fsys1_pcie_slv_aclk_0",
2048 "mout_fsys1_bus_user",
2049 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_SLV_ACLK_0,
2050 21, 0, 0),
2051 GATE(CLK_GOUT_FSYS1_PCIE_SLV_ACLK_1, "gout_fsys1_pcie_slv_aclk_1",
2052 "mout_fsys1_bus_user",
2053 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_SLV_ACLK_1,
2054 21, 0, 0),
2055 GATE(CLK_GOUT_FSYS1_PMU_FSYS1_PCLK, "gout_fsys1_pmu_fsys1_pclk",
2056 "mout_fsys1_bus_user",
2057 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PMU_FSYS1_IPCLKPORT_PCLK,
2058 21, 0, 0),
2059 GATE(CLK_GOUT_FSYS1_BCM_FSYS1_ACLK, "gout_fsys1_bcm_fsys1_aclk",
2060 "mout_fsys1_bus_user",
2061 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BCM_FSYS1_IPCLKPORT_ACLK,
2062 21, 0, 0),
2063 GATE(CLK_GOUT_FSYS1_BCM_FSYS1_PCLK, "gout_fsys1_bcm_fsys1_pclk",
2064 "mout_fsys1_bus_user",
2065 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BCM_FSYS1_IPCLKPORT_PCLK,
2066 21, 0, 0),
2067 GATE(CLK_GOUT_FSYS1_RSTNSYNC_CLK_FSYS1_BUS_CLK,
2068 "gout_fsys1_rstnsync_clk_fsys1_bus_clk", "mout_fsys1_bus_user",
2069 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RSTNSYNC_CLK_FSYS1_BUS_IPCLKPORT_CLK,
2070 21, 0, 0),
2071 GATE(CLK_GOUT_FSYS1_RTIC_I_ACLK, "gout_fsys1_rtic_i_aclk",
2072 "mout_fsys1_bus_user",
2073 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_ACLK, 21, 0, 0),
2074 GATE(CLK_GOUT_FSYS1_RTIC_I_PCLK, "gout_fsys1_rtic_i_pclk",
2075 "mout_fsys1_bus_user",
2076 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_PCLK, 21, 0, 0),
2077 GATE(CLK_GOUT_FSYS1_SSS_I_ACLK, "gout_fsys1_sss_i_aclk",
2078 "mout_fsys1_bus_user",
2079 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_ACLK, 21, 0, 0),
2080 GATE(CLK_GOUT_FSYS1_SSS_I_PCLK, "gout_fsys1_sss_i_pclk",
2081 "mout_fsys1_bus_user",
2082 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_PCLK, 21, 0, 0),
2083 GATE(CLK_GOUT_FSYS1_SYSREG_FSYS1_PCLK, "gout_fsys1_sysreg_fsys1_pclk",
2084 "mout_fsys1_bus_user",
2085 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SYSREG_FSYS1_IPCLKPORT_PCLK,
2086 21, 0, 0),
2087 GATE(CLK_GOUT_FSYS1_TOE_WIFI0_I_CLK, "gout_fsys1_toe_wifi0_i_clk",
2088 "mout_fsys1_bus_user",
2089 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_TOE_WIFI0_IPCLKPORT_I_CLK,
2090 21, 0, 0),
2091 GATE(CLK_GOUT_FSYS1_TOE_WIFI1_I_CLK, "gout_fsys1_toe_wifi1_i_clk",
2092 "mout_fsys1_bus_user",
2093 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_TOE_WIFI1_IPCLKPORT_I_CLK,
2094 21, 0, 0),
2095 GATE(CLK_GOUT_FSYS1_UFS_CARD_I_ACLK, "gout_fsys1_ufs_card_i_aclk",
2096 "mout_fsys1_bus_user",
2097 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_ACLK,
2098 21, 0, 0),
2099 GATE(CLK_GOUT_FSYS1_UFS_CARD_I_CLK_UNIPRO,
2100 "gout_fsys1_ufs_card_i_clk_unipro", "mout_fsys1_ufs_card_user",
2101 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_CLK_UNIPRO,
2102 21, CLK_IGNORE_UNUSED, 0),
2103 GATE(CLK_GOUT_FSYS1_UFS_CARD_I_FMP_CLK,
2104 "gout_fsys1_ufs_card_i_fmp_clk", "mout_fsys1_bus_user",
2105 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_FMP_CLK,
2106 21, 0, 0),
2107 GATE(CLK_GOUT_FSYS1_XIU_D_FSYS1_ACLK, "gout_fsys1_xiu_d_fsys1_aclk",
2108 "mout_fsys1_bus_user",
2109 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_D_FSYS1_IPCLKPORT_ACLK,
2110 21, CLK_IGNORE_UNUSED, 0),
2111 GATE(CLK_GOUT_FSYS1_XIU_P_FSYS1_ACLK, "gout_fsys1_xiu_p_fsys1_aclk",
2112 "mout_fsys1_bus_user",
2113 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_P_FSYS1_IPCLKPORT_ACLK,
2114 21, CLK_IGNORE_UNUSED, 0),
2115 };
2116
2117 static const struct samsung_cmu_info fsys1_cmu_info __initconst = {
2118 .mux_clks = fsys1_mux_clks,
2119 .nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks),
2120 .gate_clks = fsys1_gate_clks,
2121 .nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks),
2122 .nr_clk_ids = CLKS_NR_FSYS1,
2123 .clk_regs = fsys1_clk_regs,
2124 .nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs),
2125 .clk_name = "bus",
2126 };
2127
2128 /* ---- CMU_PERIC0 ---------------------------------------------------------- */
2129
2130 /* Register Offset definitions for CMU_PERIC0 (0x10400000) */
2131 #define PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER 0x0100
2132 #define PLL_CON2_MUX_CLKCMU_PERIC0_BUS_USER 0x0108
2133 #define PLL_CON0_MUX_CLKCMU_PERIC0_UART_DBG_USER 0x0120
2134 #define PLL_CON2_MUX_CLKCMU_PERIC0_UART_DBG_USER 0x0128
2135 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI00_USER 0x0140
2136 #define PLL_CON2_MUX_CLKCMU_PERIC0_USI00_USER 0x0148
2137 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI01_USER 0x0160
2138 #define PLL_CON2_MUX_CLKCMU_PERIC0_USI01_USER 0x0168
2139 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI02_USER 0x0180
2140 #define PLL_CON2_MUX_CLKCMU_PERIC0_USI02_USER 0x0188
2141 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI03_USER 0x01a0
2142 #define PLL_CON2_MUX_CLKCMU_PERIC0_USI03_USER 0x01a8
2143 #define CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK 0x2000
2144 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0_IPCLKPORT_ACLK 0x2014
2145 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK 0x2018
2146 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK 0x201c
2147 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PMU_PERIC0_IPCLKPORT_PCLK 0x2020
2148 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PWM_IPCLKPORT_I_PCLK_S0 0x2028
2149 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK 0x202c
2150 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SPEEDY2_TSP_IPCLKPORT_CLK 0x2030
2151 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK 0x2034
2152 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_EXT_UCLK 0x2038
2153 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_PCLK 0x203c
2154 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_IPCLKPORT_I_PCLK 0x2040
2155 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_IPCLKPORT_I_SCLK_USI 0x2044
2156 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_IPCLKPORT_I_PCLK 0x2048
2157 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_IPCLKPORT_I_SCLK_USI 0x204c
2158 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_IPCLKPORT_I_PCLK 0x2050
2159 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_IPCLKPORT_I_SCLK_USI 0x2054
2160 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_IPCLKPORT_I_PCLK 0x2058
2161 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_IPCLKPORT_I_SCLK_USI 0x205c
2162
2163 static const unsigned long peric0_clk_regs[] __initconst = {
2164 PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER,
2165 PLL_CON2_MUX_CLKCMU_PERIC0_BUS_USER,
2166 PLL_CON0_MUX_CLKCMU_PERIC0_UART_DBG_USER,
2167 PLL_CON2_MUX_CLKCMU_PERIC0_UART_DBG_USER,
2168 PLL_CON0_MUX_CLKCMU_PERIC0_USI00_USER,
2169 PLL_CON2_MUX_CLKCMU_PERIC0_USI00_USER,
2170 PLL_CON0_MUX_CLKCMU_PERIC0_USI01_USER,
2171 PLL_CON2_MUX_CLKCMU_PERIC0_USI01_USER,
2172 PLL_CON0_MUX_CLKCMU_PERIC0_USI02_USER,
2173 PLL_CON2_MUX_CLKCMU_PERIC0_USI02_USER,
2174 PLL_CON0_MUX_CLKCMU_PERIC0_USI03_USER,
2175 PLL_CON2_MUX_CLKCMU_PERIC0_USI03_USER,
2176 CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK,
2177 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0_IPCLKPORT_ACLK,
2178 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK,
2179 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK,
2180 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PMU_PERIC0_IPCLKPORT_PCLK,
2181 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PWM_IPCLKPORT_I_PCLK_S0,
2182 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK,
2183 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SPEEDY2_TSP_IPCLKPORT_CLK,
2184 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK,
2185 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_EXT_UCLK,
2186 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_PCLK,
2187 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_IPCLKPORT_I_PCLK,
2188 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_IPCLKPORT_I_SCLK_USI,
2189 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_IPCLKPORT_I_PCLK,
2190 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_IPCLKPORT_I_SCLK_USI,
2191 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_IPCLKPORT_I_PCLK,
2192 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_IPCLKPORT_I_SCLK_USI,
2193 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_IPCLKPORT_I_PCLK,
2194 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_IPCLKPORT_I_SCLK_USI,
2195 };
2196
2197 /* List of parent clocks for Muxes in CMU_PERIC0 */
2198 PNAME(mout_peric0_bus_user_p) = { "oscclk", "dout_cmu_peric0_bus" };
2199 PNAME(mout_peric0_uart_dbg_user_p) = { "oscclk",
2200 "dout_cmu_peric0_uart_dbg" };
2201 PNAME(mout_peric0_usi00_user_p) = { "oscclk",
2202 "dout_cmu_peric0_usi00" };
2203 PNAME(mout_peric0_usi01_user_p) = { "oscclk",
2204 "dout_cmu_peric0_usi01" };
2205 PNAME(mout_peric0_usi02_user_p) = { "oscclk",
2206 "dout_cmu_peric0_usi02" };
2207 PNAME(mout_peric0_usi03_user_p) = { "oscclk",
2208 "dout_cmu_peric0_usi03" };
2209
2210 static const struct samsung_mux_clock peric0_mux_clks[] __initconst = {
2211 MUX(CLK_MOUT_PERIC0_BUS_USER, "mout_peric0_bus_user",
2212 mout_peric0_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER, 4, 1),
2213 MUX(CLK_MOUT_PERIC0_UART_DBG_USER, "mout_peric0_uart_dbg_user",
2214 mout_peric0_uart_dbg_user_p,
2215 PLL_CON0_MUX_CLKCMU_PERIC0_UART_DBG_USER, 4, 1),
2216 MUX(CLK_MOUT_PERIC0_USI00_USER, "mout_peric0_usi00_user",
2217 mout_peric0_usi00_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI00_USER,
2218 4, 1),
2219 MUX(CLK_MOUT_PERIC0_USI01_USER, "mout_peric0_usi01_user",
2220 mout_peric0_usi01_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI01_USER,
2221 4, 1),
2222 MUX(CLK_MOUT_PERIC0_USI02_USER, "mout_peric0_usi02_user",
2223 mout_peric0_usi02_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI02_USER,
2224 4, 1),
2225 MUX(CLK_MOUT_PERIC0_USI03_USER, "mout_peric0_usi03_user",
2226 mout_peric0_usi03_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI03_USER,
2227 4, 1),
2228 };
2229
2230 static const struct samsung_gate_clock peric0_gate_clks[] __initconst = {
2231 GATE(CLK_GOUT_PERIC0_PERIC0_CMU_PERIC0_PCLK,
2232 "gout_cperic0_peric0_cmu_peric0_pclk", "mout_peric0_bus_user",
2233 CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK,
2234 21, CLK_IS_CRITICAL, 0),
2235 GATE(CLK_GOUT_PERIC0_AXI2APB_PERIC0_ACLK,
2236 "gout_peric0_axi2apb_peric0_aclk", "mout_peric0_bus_user",
2237 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0_IPCLKPORT_ACLK,
2238 21, CLK_IS_CRITICAL, 0),
2239 GATE(CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK, "gout_peric0_gpio_peric0_pclk",
2240 "mout_peric0_bus_user",
2241 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK,
2242 21, CLK_IGNORE_UNUSED, 0),
2243 GATE(CLK_GOUT_PERIC0_LHM_AXI_P_PERIC0_I_CLK,
2244 "gout_peric0_lhm_axi_p_peric0_i_clk", "mout_peric0_bus_user",
2245 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK,
2246 21, CLK_IS_CRITICAL, 0),
2247 GATE(CLK_GOUT_PERIC0_PMU_PERIC0_PCLK, "gout_peric0_pmu_peric0_pclk",
2248 "mout_peric0_bus_user",
2249 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PMU_PERIC0_IPCLKPORT_PCLK,
2250 21, 0, 0),
2251 GATE(CLK_GOUT_PERIC0_PWM_I_PCLK_S0, "gout_peric0_pwm_i_pclk_s0",
2252 "mout_peric0_bus_user",
2253 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PWM_IPCLKPORT_I_PCLK_S0,
2254 21, 0, 0),
2255 GATE(CLK_GOUT_PERIC0_RSTNSYNC_CLK_PERIC0_BUSP_CLK,
2256 "gout_peric0_rstnsync_clk_peric0_busp_clk",
2257 "mout_peric0_bus_user",
2258 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK,
2259 21, 0, 0),
2260 GATE(CLK_GOUT_PERIC0_SPEEDY2_TSP_CLK, "gout_peric0_speedy2_tsp_clk",
2261 "mout_peric0_bus_user",
2262 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SPEEDY2_TSP_IPCLKPORT_CLK,
2263 21, 0, 0),
2264 GATE(CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK,
2265 "gout_peric0_sysreg_peric0_pclk", "mout_peric0_bus_user",
2266 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK,
2267 21, 0, 0),
2268 GATE(CLK_GOUT_PERIC0_UART_DBG_EXT_UCLK,
2269 "gout_peric0_uart_dbg_ext_uclk", "mout_peric0_uart_dbg_user",
2270 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_EXT_UCLK,
2271 21, 0, 0),
2272 GATE(CLK_GOUT_PERIC0_UART_DBG_PCLK, "gout_peric0_uart_dbg_pclk",
2273 "mout_peric0_bus_user",
2274 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_PCLK,
2275 21, 0, 0),
2276 GATE(CLK_GOUT_PERIC0_USI00_I_PCLK, "gout_peric0_usi00_i_pclk",
2277 "mout_peric0_bus_user",
2278 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_IPCLKPORT_I_PCLK, 21, 0, 0),
2279 GATE(CLK_GOUT_PERIC0_USI00_I_SCLK_USI, "gout_peric0_usi00_i_sclk_usi",
2280 "mout_peric0_usi00_user",
2281 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_IPCLKPORT_I_SCLK_USI,
2282 21, 0, 0),
2283 GATE(CLK_GOUT_PERIC0_USI01_I_PCLK, "gout_peric0_usi01_i_pclk",
2284 "mout_peric0_bus_user",
2285 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_IPCLKPORT_I_PCLK, 21, 0, 0),
2286 GATE(CLK_GOUT_PERIC0_USI01_I_SCLK_USI, "gout_peric0_usi01_i_sclk_usi",
2287 "mout_peric0_usi01_user",
2288 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_IPCLKPORT_I_SCLK_USI,
2289 21, 0, 0),
2290 GATE(CLK_GOUT_PERIC0_USI02_I_PCLK, "gout_peric0_usi02_i_pclk",
2291 "mout_peric0_bus_user",
2292 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_IPCLKPORT_I_PCLK, 21, 0, 0),
2293 GATE(CLK_GOUT_PERIC0_USI02_I_SCLK_USI, "gout_peric0_usi02_i_sclk_usi",
2294 "mout_peric0_usi02_user",
2295 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_IPCLKPORT_I_SCLK_USI,
2296 21, 0, 0),
2297 GATE(CLK_GOUT_PERIC0_USI03_I_PCLK, "gout_peric0_usi03_i_pclk",
2298 "mout_peric0_bus_user",
2299 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_IPCLKPORT_I_PCLK, 21, 0, 0),
2300 GATE(CLK_GOUT_PERIC0_USI03_I_SCLK_USI, "gout_peric0_usi03_i_sclk_usi",
2301 "mout_peric0_usi03_user",
2302 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_IPCLKPORT_I_SCLK_USI,
2303 21, 0, 0),
2304 };
2305
2306 static const struct samsung_cmu_info peric0_cmu_info __initconst = {
2307 .mux_clks = peric0_mux_clks,
2308 .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks),
2309 .gate_clks = peric0_gate_clks,
2310 .nr_gate_clks = ARRAY_SIZE(peric0_gate_clks),
2311 .nr_clk_ids = CLKS_NR_PERIC0,
2312 .clk_regs = peric0_clk_regs,
2313 .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs),
2314 .clk_name = "bus",
2315 };
2316
2317 /* ---- CMU_PERIC1 ---------------------------------------------------------- */
2318
2319 /* Register Offset definitions for CMU_PERIC1 (0x10800000) */
2320 #define PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER 0x0100
2321 #define PLL_CON2_MUX_CLKCMU_PERIC1_BUS_USER 0x0108
2322 #define PLL_CON0_MUX_CLKCMU_PERIC1_SPEEDY2_USER 0x0120
2323 #define PLL_CON2_MUX_CLKCMU_PERIC1_SPEEDY2_USER 0x0128
2324 #define PLL_CON0_MUX_CLKCMU_PERIC1_SPI_CAM0_USER 0x0140
2325 #define PLL_CON2_MUX_CLKCMU_PERIC1_SPI_CAM0_USER 0x0148
2326 #define PLL_CON0_MUX_CLKCMU_PERIC1_SPI_CAM1_USER 0x0160
2327 #define PLL_CON2_MUX_CLKCMU_PERIC1_SPI_CAM1_USER 0x0168
2328 #define PLL_CON0_MUX_CLKCMU_PERIC1_UART_BT_USER 0x0180
2329 #define PLL_CON2_MUX_CLKCMU_PERIC1_UART_BT_USER 0x0188
2330 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI04_USER 0x01a0
2331 #define PLL_CON2_MUX_CLKCMU_PERIC1_USI04_USER 0x01a8
2332 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI05_USER 0x01c0
2333 #define PLL_CON2_MUX_CLKCMU_PERIC1_USI05_USER 0x01c8
2334 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI06_USER 0x01e0
2335 #define PLL_CON2_MUX_CLKCMU_PERIC1_USI06_USER 0x01e8
2336 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI07_USER 0x0200
2337 #define PLL_CON2_MUX_CLKCMU_PERIC1_USI07_USER 0x0208
2338 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI08_USER 0x0220
2339 #define PLL_CON2_MUX_CLKCMU_PERIC1_USI08_USER 0x0228
2340 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI09_USER 0x0240
2341 #define PLL_CON2_MUX_CLKCMU_PERIC1_USI09_USER 0x0248
2342 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USER 0x0260
2343 #define PLL_CON2_MUX_CLKCMU_PERIC1_USI10_USER 0x0268
2344 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USER 0x0280
2345 #define PLL_CON2_MUX_CLKCMU_PERIC1_USI11_USER 0x0288
2346 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USER 0x02a0
2347 #define PLL_CON2_MUX_CLKCMU_PERIC1_USI12_USER 0x02a8
2348 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USER 0x02c0
2349 #define PLL_CON2_MUX_CLKCMU_PERIC1_USI13_USER 0x02c8
2350 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK 0x2000
2351 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_SPEEDY2_IPCLKPORT_CLK 0x200c
2352 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P0_IPCLKPORT_ACLK 0x201c
2353 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P1_IPCLKPORT_ACLK 0x2020
2354 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P2_IPCLKPORT_ACLK 0x2024
2355 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK 0x2028
2356 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM0_IPCLKPORT_IPCLK 0x202c
2357 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM1_IPCLKPORT_IPCLK 0x2030
2358 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM2_IPCLKPORT_IPCLK 0x2034
2359 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM3_IPCLKPORT_IPCLK 0x2038
2360 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK 0x203c
2361 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PMU_PERIC1_IPCLKPORT_PCLK 0x2040
2362 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK 0x2044
2363 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI1_IPCLKPORT_CLK 0x2048
2364 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI1_IPCLKPORT_SCLK 0x204c
2365 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI2_IPCLKPORT_CLK 0x2050
2366 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI2_IPCLKPORT_SCLK 0x2054
2367 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI_IPCLKPORT_CLK 0x2058
2368 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI_IPCLKPORT_SCLK 0x205c
2369 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_TSP1_IPCLKPORT_CLK 0x2060
2370 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_TSP2_IPCLKPORT_CLK 0x2064
2371 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_PCLK 0x2068
2372 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_SPI_EXT_CLK 0x206c
2373 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM1_IPCLKPORT_PCLK 0x2070
2374 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM1_IPCLKPORT_SPI_EXT_CLK 0x2074
2375 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK 0x2078
2376 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_EXT_UCLK 0x207c
2377 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_PCLK 0x2080
2378 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI04_IPCLKPORT_I_PCLK 0x2084
2379 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI04_IPCLKPORT_I_SCLK_USI 0x2088
2380 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI05_IPCLKPORT_I_PCLK 0x208c
2381 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI05_IPCLKPORT_I_SCLK_USI 0x2090
2382 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_IPCLKPORT_I_PCLK 0x2094
2383 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_IPCLKPORT_I_SCLK_USI 0x2098
2384 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_IPCLKPORT_I_PCLK 0x209c
2385 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_IPCLKPORT_I_SCLK_USI 0x20a0
2386 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_IPCLKPORT_I_PCLK 0x20a4
2387 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_IPCLKPORT_I_SCLK_USI 0x20a8
2388 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_IPCLKPORT_I_PCLK 0x20ac
2389 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_IPCLKPORT_I_SCLK_USI 0x20b0
2390 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_IPCLKPORT_I_PCLK 0x20b4
2391 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_IPCLKPORT_I_SCLK_USI 0x20b8
2392 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_IPCLKPORT_I_PCLK 0x20bc
2393 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_IPCLKPORT_I_SCLK_USI 0x20c0
2394 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI12_IPCLKPORT_I_PCLK 0x20c4
2395 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI12_IPCLKPORT_I_SCLK_USI 0x20c8
2396 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI13_IPCLKPORT_I_PCLK 0x20cc
2397 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI13_IPCLKPORT_I_SCLK_USI 0x20d0
2398 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK 0x20d4
2399
2400 static const unsigned long peric1_clk_regs[] __initconst = {
2401 PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER,
2402 PLL_CON2_MUX_CLKCMU_PERIC1_BUS_USER,
2403 PLL_CON0_MUX_CLKCMU_PERIC1_SPEEDY2_USER,
2404 PLL_CON2_MUX_CLKCMU_PERIC1_SPEEDY2_USER,
2405 PLL_CON0_MUX_CLKCMU_PERIC1_SPI_CAM0_USER,
2406 PLL_CON2_MUX_CLKCMU_PERIC1_SPI_CAM0_USER,
2407 PLL_CON0_MUX_CLKCMU_PERIC1_SPI_CAM1_USER,
2408 PLL_CON2_MUX_CLKCMU_PERIC1_SPI_CAM1_USER,
2409 PLL_CON0_MUX_CLKCMU_PERIC1_UART_BT_USER,
2410 PLL_CON2_MUX_CLKCMU_PERIC1_UART_BT_USER,
2411 PLL_CON0_MUX_CLKCMU_PERIC1_USI04_USER,
2412 PLL_CON2_MUX_CLKCMU_PERIC1_USI04_USER,
2413 PLL_CON0_MUX_CLKCMU_PERIC1_USI05_USER,
2414 PLL_CON2_MUX_CLKCMU_PERIC1_USI05_USER,
2415 PLL_CON0_MUX_CLKCMU_PERIC1_USI06_USER,
2416 PLL_CON2_MUX_CLKCMU_PERIC1_USI06_USER,
2417 PLL_CON0_MUX_CLKCMU_PERIC1_USI07_USER,
2418 PLL_CON2_MUX_CLKCMU_PERIC1_USI07_USER,
2419 PLL_CON0_MUX_CLKCMU_PERIC1_USI08_USER,
2420 PLL_CON2_MUX_CLKCMU_PERIC1_USI08_USER,
2421 PLL_CON0_MUX_CLKCMU_PERIC1_USI09_USER,
2422 PLL_CON2_MUX_CLKCMU_PERIC1_USI09_USER,
2423 PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USER,
2424 PLL_CON2_MUX_CLKCMU_PERIC1_USI10_USER,
2425 PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USER,
2426 PLL_CON2_MUX_CLKCMU_PERIC1_USI11_USER,
2427 PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USER,
2428 PLL_CON2_MUX_CLKCMU_PERIC1_USI12_USER,
2429 PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USER,
2430 PLL_CON2_MUX_CLKCMU_PERIC1_USI13_USER,
2431 CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK,
2432 CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_SPEEDY2_IPCLKPORT_CLK,
2433 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P0_IPCLKPORT_ACLK,
2434 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P1_IPCLKPORT_ACLK,
2435 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P2_IPCLKPORT_ACLK,
2436 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK,
2437 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM0_IPCLKPORT_IPCLK,
2438 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM1_IPCLKPORT_IPCLK,
2439 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM2_IPCLKPORT_IPCLK,
2440 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM3_IPCLKPORT_IPCLK,
2441 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK,
2442 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PMU_PERIC1_IPCLKPORT_PCLK,
2443 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK,
2444 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI1_IPCLKPORT_CLK,
2445 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI1_IPCLKPORT_SCLK,
2446 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI2_IPCLKPORT_CLK,
2447 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI2_IPCLKPORT_SCLK,
2448 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI_IPCLKPORT_CLK,
2449 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI_IPCLKPORT_SCLK,
2450 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_TSP1_IPCLKPORT_CLK,
2451 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_TSP2_IPCLKPORT_CLK,
2452 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_PCLK,
2453 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_SPI_EXT_CLK,
2454 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM1_IPCLKPORT_PCLK,
2455 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM1_IPCLKPORT_SPI_EXT_CLK,
2456 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK,
2457 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_EXT_UCLK,
2458 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_PCLK,
2459 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI04_IPCLKPORT_I_PCLK,
2460 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI04_IPCLKPORT_I_SCLK_USI,
2461 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI05_IPCLKPORT_I_PCLK,
2462 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI05_IPCLKPORT_I_SCLK_USI,
2463 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_IPCLKPORT_I_PCLK,
2464 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_IPCLKPORT_I_SCLK_USI,
2465 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_IPCLKPORT_I_PCLK,
2466 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_IPCLKPORT_I_SCLK_USI,
2467 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_IPCLKPORT_I_PCLK,
2468 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_IPCLKPORT_I_SCLK_USI,
2469 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_IPCLKPORT_I_PCLK,
2470 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_IPCLKPORT_I_SCLK_USI,
2471 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_IPCLKPORT_I_PCLK,
2472 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_IPCLKPORT_I_SCLK_USI,
2473 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_IPCLKPORT_I_PCLK,
2474 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_IPCLKPORT_I_SCLK_USI,
2475 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI12_IPCLKPORT_I_PCLK,
2476 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI12_IPCLKPORT_I_SCLK_USI,
2477 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI13_IPCLKPORT_I_PCLK,
2478 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI13_IPCLKPORT_I_SCLK_USI,
2479 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK,
2480 };
2481
2482 /* List of parent clocks for Muxes in CMU_PERIC1 */
2483 PNAME(mout_peric1_bus_user_p) = { "oscclk", "dout_cmu_peric1_bus" };
2484 PNAME(mout_peric1_speedy2_user_p) = { "oscclk",
2485 "dout_cmu_peric1_speedy2" };
2486 PNAME(mout_peric1_spi_cam0_user_p) = { "oscclk",
2487 "dout_cmu_peric1_spi_cam0" };
2488 PNAME(mout_peric1_spi_cam1_user_p) = { "oscclk",
2489 "dout_cmu_peric1_spi_cam1" };
2490 PNAME(mout_peric1_uart_bt_user_p) = { "oscclk",
2491 "dout_cmu_peric1_uart_bt" };
2492 PNAME(mout_peric1_usi04_user_p) = { "oscclk",
2493 "dout_cmu_peric1_usi04" };
2494 PNAME(mout_peric1_usi05_user_p) = { "oscclk",
2495 "dout_cmu_peric1_usi05" };
2496 PNAME(mout_peric1_usi06_user_p) = { "oscclk",
2497 "dout_cmu_peric1_usi06" };
2498 PNAME(mout_peric1_usi07_user_p) = { "oscclk",
2499 "dout_cmu_peric1_usi07" };
2500 PNAME(mout_peric1_usi08_user_p) = { "oscclk",
2501 "dout_cmu_peric1_usi08" };
2502 PNAME(mout_peric1_usi09_user_p) = { "oscclk",
2503 "dout_cmu_peric1_usi09" };
2504 PNAME(mout_peric1_usi10_user_p) = { "oscclk",
2505 "dout_cmu_peric1_usi10" };
2506 PNAME(mout_peric1_usi11_user_p) = { "oscclk",
2507 "dout_cmu_peric1_usi11" };
2508 PNAME(mout_peric1_usi12_user_p) = { "oscclk",
2509 "dout_cmu_peric1_usi12" };
2510 PNAME(mout_peric1_usi13_user_p) = { "oscclk",
2511 "dout_cmu_peric1_usi13" };
2512
2513 static const struct samsung_mux_clock peric1_mux_clks[] __initconst = {
2514 MUX(CLK_MOUT_PERIC1_BUS_USER, "mout_peric1_bus_user",
2515 mout_peric1_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER, 4, 1),
2516 MUX(CLK_MOUT_PERIC1_SPEEDY2_USER, "mout_peric1_speedy2_user",
2517 mout_peric1_speedy2_user_p,
2518 PLL_CON0_MUX_CLKCMU_PERIC1_SPEEDY2_USER, 4, 1),
2519 MUX(CLK_MOUT_PERIC1_SPI_CAM0_USER, "mout_peric1_spi_cam0_user",
2520 mout_peric1_spi_cam0_user_p,
2521 PLL_CON0_MUX_CLKCMU_PERIC1_SPI_CAM0_USER, 4, 1),
2522 MUX(CLK_MOUT_PERIC1_SPI_CAM1_USER, "mout_peric1_spi_cam1_user",
2523 mout_peric1_spi_cam1_user_p,
2524 PLL_CON0_MUX_CLKCMU_PERIC1_SPI_CAM1_USER, 4, 1),
2525 MUX(CLK_MOUT_PERIC1_UART_BT_USER, "mout_peric1_uart_bt_user",
2526 mout_peric1_uart_bt_user_p,
2527 PLL_CON0_MUX_CLKCMU_PERIC1_UART_BT_USER, 4, 1),
2528 MUX(CLK_MOUT_PERIC1_USI04_USER, "mout_peric1_usi04_user",
2529 mout_peric1_usi04_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI04_USER,
2530 4, 1),
2531 MUX(CLK_MOUT_PERIC1_USI05_USER, "mout_peric1_usi05_user",
2532 mout_peric1_usi05_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI05_USER,
2533 4, 1),
2534 MUX(CLK_MOUT_PERIC1_USI06_USER, "mout_peric1_usi06_user",
2535 mout_peric1_usi06_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI06_USER,
2536 4, 1),
2537 MUX(CLK_MOUT_PERIC1_USI07_USER, "mout_peric1_usi07_user",
2538 mout_peric1_usi07_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI07_USER,
2539 4, 1),
2540 MUX(CLK_MOUT_PERIC1_USI08_USER, "mout_peric1_usi08_user",
2541 mout_peric1_usi08_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI08_USER,
2542 4, 1),
2543 MUX(CLK_MOUT_PERIC1_USI09_USER, "mout_peric1_usi09_user",
2544 mout_peric1_usi09_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI09_USER,
2545 4, 1),
2546 MUX(CLK_MOUT_PERIC1_USI10_USER, "mout_peric1_usi10_user",
2547 mout_peric1_usi10_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USER,
2548 4, 1),
2549 MUX(CLK_MOUT_PERIC1_USI11_USER, "mout_peric1_usi11_user",
2550 mout_peric1_usi11_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USER,
2551 4, 1),
2552 MUX(CLK_MOUT_PERIC1_USI12_USER, "mout_peric1_usi12_user",
2553 mout_peric1_usi12_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USER,
2554 4, 1),
2555 MUX(CLK_MOUT_PERIC1_USI13_USER, "mout_peric1_usi13_user",
2556 mout_peric1_usi13_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USER,
2557 4, 1),
2558 };
2559
2560 static const struct samsung_gate_clock peric1_gate_clks[] __initconst = {
2561 GATE(CLK_GOUT_PERIC1_PERIC1_CMU_PERIC1_PCLK,
2562 "gout_peric1_peric1_cmu_peric1_pclk", "mout_peric1_bus_user",
2563 CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK,
2564 21, CLK_IS_CRITICAL, 0),
2565 GATE(CLK_GOUT_PERIC1_RSTNSYNC_CLK_PERIC1_SPEEDY2_CLK,
2566 "gout_peric1_rstnsync_clk_peric1_speedy2_clk",
2567 "mout_peric1_speedy2_user",
2568 CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_SPEEDY2_IPCLKPORT_CLK,
2569 21, 0, 0),
2570 GATE(CLK_GOUT_PERIC1_AXI2APB_PERIC1P0_ACLK,
2571 "gout_peric1_axi2apb_peric1p0_aclk",
2572 "mout_peric1_bus_user",
2573 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P0_IPCLKPORT_ACLK,
2574 21, CLK_IS_CRITICAL, 0),
2575 GATE(CLK_GOUT_PERIC1_AXI2APB_PERIC1P1_ACLK,
2576 "gout_peric1_axi2apb_peric1p1_aclk", "mout_peric1_bus_user",
2577 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P1_IPCLKPORT_ACLK,
2578 21, CLK_IS_CRITICAL, 0),
2579 GATE(CLK_GOUT_PERIC1_AXI2APB_PERIC1P2_ACLK,
2580 "gout_peric1_axi2apb_peric1p2_aclk", "mout_peric1_bus_user",
2581 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P2_IPCLKPORT_ACLK,
2582 21, CLK_IS_CRITICAL, 0),
2583 GATE(CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK,
2584 "gout_peric1_gpio_peric1_pclk", "mout_peric1_bus_user",
2585 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK,
2586 21, CLK_IGNORE_UNUSED, 0),
2587 GATE(CLK_GOUT_PERIC1_HSI2C_CAM0_IPCLK, "gout_peric1_hsi2c_cam0_ipclk",
2588 "mout_peric1_bus_user",
2589 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM0_IPCLKPORT_IPCLK,
2590 21, 0, 0),
2591 GATE(CLK_GOUT_PERIC1_HSI2C_CAM1_IPCLK,
2592 "gout_peric1_hsi2c_cam1_ipclk", "mout_peric1_bus_user",
2593 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM1_IPCLKPORT_IPCLK,
2594 21, 0, 0),
2595 GATE(CLK_GOUT_PERIC1_HSI2C_CAM2_IPCLK,
2596 "gout_peric1_hsi2c_cam2_ipclk", "mout_peric1_bus_user",
2597 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM2_IPCLKPORT_IPCLK,
2598 21, 0, 0),
2599 GATE(CLK_GOUT_PERIC1_HSI2C_CAM3_IPCLK, "gout_peric1_hsi2c_cam3_ipclk",
2600 "mout_peric1_bus_user",
2601 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM3_IPCLKPORT_IPCLK,
2602 21, 0, 0),
2603 GATE(CLK_GOUT_PERIC1_LHM_AXI_P_PERIC1_I_CLK,
2604 "gout_peric1_lhm_axi_p_peric1_i_clk", "mout_peric1_bus_user",
2605 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK,
2606 21, CLK_IS_CRITICAL, 0),
2607 GATE(CLK_GOUT_PERIC1_PMU_PERIC1_PCLK, "gout_peric1_pmu_peric1_pclk",
2608 "mout_peric1_bus_user",
2609 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PMU_PERIC1_IPCLKPORT_PCLK,
2610 21, 0, 0),
2611 GATE(CLK_GOUT_PERIC1_RSTNSYNC_CLK_PERIC1_BUSP_CLK,
2612 "gout_peric1_rstnsync_clk_peric1_busp_clk",
2613 "mout_peric1_bus_user",
2614 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK,
2615 21, 0, 0),
2616 GATE(CLK_GOUT_PERIC1_SPEEDY2_DDI1_CLK, "gout_peric1_speedy2_ddi1_clk",
2617 "mout_peric1_bus_user",
2618 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI1_IPCLKPORT_CLK,
2619 21, 0, 0),
2620 GATE(CLK_GOUT_PERIC1_SPEEDY2_DDI1_SCLK,
2621 "gout_peric1_speedy2_ddi1_sclk", "mout_peric1_speedy2_user",
2622 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI1_IPCLKPORT_SCLK,
2623 21, 0, 0),
2624 GATE(CLK_GOUT_PERIC1_SPEEDY2_DDI2_CLK, "gout_peric1_speedy2_ddi2_clk",
2625 "mout_peric1_bus_user",
2626 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI2_IPCLKPORT_CLK,
2627 21, 0, 0),
2628 GATE(CLK_GOUT_PERIC1_SPEEDY2_DDI2_SCLK,
2629 "gout_peric1_speedy2_ddi2_sclk", "mout_peric1_speedy2_user",
2630 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI2_IPCLKPORT_SCLK,
2631 21, 0, 0),
2632 GATE(CLK_GOUT_PERIC1_SPEEDY2_DDI_CLK, "gout_peric1_speedy2_ddi_clk",
2633 "mout_peric1_bus_user",
2634 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI_IPCLKPORT_CLK,
2635 21, 0, 0),
2636 GATE(CLK_GOUT_PERIC1_SPEEDY2_DDI_SCLK, "gout_peric1_speedy2_ddi_sclk",
2637 "mout_peric1_speedy2_user",
2638 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI_IPCLKPORT_SCLK,
2639 21, 0, 0),
2640 GATE(CLK_GOUT_PERIC1_SPEEDY2_TSP1_CLK, "gout_peric1_speedy2_tsp1_clk",
2641 "mout_peric1_bus_user",
2642 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_TSP1_IPCLKPORT_CLK,
2643 21, 0, 0),
2644 GATE(CLK_GOUT_PERIC1_SPEEDY2_TSP2_CLK, "gout_peric1_speedy2_tsp2_clk",
2645 "mout_peric1_bus_user",
2646 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_TSP2_IPCLKPORT_CLK,
2647 21, 0, 0),
2648 GATE(CLK_GOUT_PERIC1_SPI_CAM0_PCLK, "gout_peric1_spi_cam0_pclk",
2649 "mout_peric1_bus_user",
2650 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_PCLK,
2651 21, 0, 0),
2652 GATE(CLK_GOUT_PERIC1_SPI_CAM0_SPI_EXT_CLK,
2653 "gout_peric1_spi_cam0_spi_ext_clk", "mout_peric1_spi_cam0_user",
2654 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_SPI_EXT_CLK,
2655 21, 0, 0),
2656 GATE(CLK_GOUT_PERIC1_SPI_CAM1_PCLK, "gout_peric1_spi_cam1_pclk",
2657 "mout_peric1_bus_user",
2658 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM1_IPCLKPORT_PCLK,
2659 21, 0, 0),
2660 GATE(CLK_GOUT_PERIC1_SPI_CAM1_SPI_EXT_CLK,
2661 "gout_peric1_spi_cam1_spi_ext_clk", "mout_peric1_spi_cam1_user",
2662 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM1_IPCLKPORT_SPI_EXT_CLK,
2663 21, 0, 0),
2664 GATE(CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK,
2665 "gout_peric1_sysreg_peric1_pclk", "mout_peric1_bus_user",
2666 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK,
2667 21, 0, 0),
2668 GATE(CLK_GOUT_PERIC1_UART_BT_EXT_UCLK, "gout_peric1_uart_bt_ext_uclk",
2669 "mout_peric1_uart_bt_user",
2670 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_EXT_UCLK,
2671 21, 0, 0),
2672 GATE(CLK_GOUT_PERIC1_UART_BT_PCLK, "gout_peric1_uart_bt_pclk",
2673 "mout_peric1_bus_user",
2674 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_PCLK, 21, 0, 0),
2675 GATE(CLK_GOUT_PERIC1_USI04_I_PCLK, "gout_peric1_usi04_i_pclk",
2676 "mout_peric1_bus_user",
2677 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI04_IPCLKPORT_I_PCLK, 21, 0, 0),
2678 GATE(CLK_GOUT_PERIC1_USI04_I_SCLK_USI, "gout_peric1_usi04_i_sclk_usi",
2679 "mout_peric1_usi04_user",
2680 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI04_IPCLKPORT_I_SCLK_USI,
2681 21, 0, 0),
2682 GATE(CLK_GOUT_PERIC1_USI05_I_PCLK, "gout_peric1_usi05_i_pclk",
2683 "mout_peric1_bus_user",
2684 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI05_IPCLKPORT_I_PCLK, 21, 0, 0),
2685 GATE(CLK_GOUT_PERIC1_USI05_I_SCLK_USI, "gout_peric1_usi05_i_sclk_usi",
2686 "mout_peric1_usi05_user",
2687 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI05_IPCLKPORT_I_SCLK_USI,
2688 21, 0, 0),
2689 GATE(CLK_GOUT_PERIC1_USI06_I_PCLK, "gout_peric1_usi06_i_pclk",
2690 "mout_peric1_bus_user",
2691 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_IPCLKPORT_I_PCLK, 21, 0, 0),
2692 GATE(CLK_GOUT_PERIC1_USI06_I_SCLK_USI, "gout_peric1_usi06_i_sclk_usi",
2693 "mout_peric1_usi06_user",
2694 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_IPCLKPORT_I_SCLK_USI,
2695 21, 0, 0),
2696 GATE(CLK_GOUT_PERIC1_USI07_I_PCLK, "gout_peric1_usi07_i_pclk",
2697 "mout_peric1_bus_user",
2698 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_IPCLKPORT_I_PCLK, 21, 0, 0),
2699 GATE(CLK_GOUT_PERIC1_USI07_I_SCLK_USI, "gout_peric1_usi07_i_sclk_usi",
2700 "mout_peric1_usi07_user",
2701 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_IPCLKPORT_I_SCLK_USI,
2702 21, 0, 0),
2703 GATE(CLK_GOUT_PERIC1_USI08_I_PCLK, "gout_peric1_usi08_i_pclk",
2704 "mout_peric1_bus_user",
2705 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_IPCLKPORT_I_PCLK, 21, 0, 0),
2706 GATE(CLK_GOUT_PERIC1_USI08_I_SCLK_USI, "gout_peric1_usi08_i_sclk_usi",
2707 "mout_peric1_usi08_user",
2708 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_IPCLKPORT_I_SCLK_USI,
2709 21, 0, 0),
2710 GATE(CLK_GOUT_PERIC1_USI09_I_PCLK, "gout_peric1_usi09_i_pclk",
2711 "mout_peric1_bus_user",
2712 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_IPCLKPORT_I_PCLK, 21, 0, 0),
2713 GATE(CLK_GOUT_PERIC1_USI09_I_SCLK_USI, "gout_peric1_usi09_i_sclk_usi",
2714 "mout_peric1_usi09_user",
2715 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_IPCLKPORT_I_SCLK_USI,
2716 21, 0, 0),
2717 GATE(CLK_GOUT_PERIC1_USI10_I_PCLK, "gout_peric1_usi10_i_pclk",
2718 "mout_peric1_bus_user",
2719 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_IPCLKPORT_I_PCLK, 21, 0, 0),
2720 GATE(CLK_GOUT_PERIC1_USI10_I_SCLK_USI, "gout_peric1_usi10_i_sclk_usi",
2721 "mout_peric1_usi10_user",
2722 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_IPCLKPORT_I_SCLK_USI,
2723 21, 0, 0),
2724 GATE(CLK_GOUT_PERIC1_USI11_I_PCLK, "gout_peric1_usi11_i_pclk",
2725 "mout_peric1_bus_user",
2726 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_IPCLKPORT_I_PCLK, 21, 0, 0),
2727 GATE(CLK_GOUT_PERIC1_USI11_I_SCLK_USI, "gout_peric1_usi11_i_sclk_usi",
2728 "mout_peric1_usi11_user",
2729 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_IPCLKPORT_I_SCLK_USI,
2730 21, 0, 0),
2731 GATE(CLK_GOUT_PERIC1_USI12_I_PCLK, "gout_peric1_usi12_i_pclk",
2732 "mout_peric1_bus_user",
2733 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI12_IPCLKPORT_I_PCLK, 21, 0, 0),
2734 GATE(CLK_GOUT_PERIC1_USI12_I_SCLK_USI, "gout_peric1_usi12_i_sclk_usi",
2735 "mout_peric1_usi12_user",
2736 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI12_IPCLKPORT_I_SCLK_USI,
2737 21, 0, 0),
2738 GATE(CLK_GOUT_PERIC1_USI13_I_PCLK, "gout_peric1_usi13_i_pclk",
2739 "mout_peric1_bus_user",
2740 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI13_IPCLKPORT_I_PCLK, 21, 0, 0),
2741 GATE(CLK_GOUT_PERIC1_USI13_I_SCLK_USI, "gout_peric1_usi13_i_sclk_usi",
2742 "mout_peric1_usi13_user",
2743 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI13_IPCLKPORT_I_SCLK_USI,
2744 21, 0, 0),
2745 GATE(CLK_GOUT_PERIC1_XIU_P_PERIC1_ACLK,
2746 "gout_peric1_xiu_p_peric1_aclk", "mout_peric1_bus_user",
2747 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK,
2748 21, CLK_IGNORE_UNUSED, 0),
2749 };
2750
2751 static const struct samsung_cmu_info peric1_cmu_info __initconst = {
2752 .mux_clks = peric1_mux_clks,
2753 .nr_mux_clks = ARRAY_SIZE(peric1_mux_clks),
2754 .gate_clks = peric1_gate_clks,
2755 .nr_gate_clks = ARRAY_SIZE(peric1_gate_clks),
2756 .nr_clk_ids = CLKS_NR_PERIC1,
2757 .clk_regs = peric1_clk_regs,
2758 .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs),
2759 .clk_name = "bus",
2760 };
2761
exynos8895_cmu_probe(struct platform_device * pdev)2762 static int __init exynos8895_cmu_probe(struct platform_device *pdev)
2763 {
2764 const struct samsung_cmu_info *info;
2765 struct device *dev = &pdev->dev;
2766
2767 info = of_device_get_match_data(dev);
2768 exynos_arm64_register_cmu(dev, dev->of_node, info);
2769
2770 return 0;
2771 }
2772
2773 static const struct of_device_id exynos8895_cmu_of_match[] = {
2774 {
2775 .compatible = "samsung,exynos8895-cmu-fsys0",
2776 .data = &fsys0_cmu_info,
2777 }, {
2778 .compatible = "samsung,exynos8895-cmu-fsys1",
2779 .data = &fsys1_cmu_info,
2780 }, {
2781 .compatible = "samsung,exynos8895-cmu-peric0",
2782 .data = &peric0_cmu_info,
2783 }, {
2784 .compatible = "samsung,exynos8895-cmu-peric1",
2785 .data = &peric1_cmu_info,
2786 },
2787 { }
2788 };
2789
2790 static struct platform_driver exynos8895_cmu_driver __refdata = {
2791 .driver = {
2792 .name = "exynos8895-cmu",
2793 .of_match_table = exynos8895_cmu_of_match,
2794 .suppress_bind_attrs = true,
2795 },
2796 .probe = exynos8895_cmu_probe,
2797 };
2798
exynos8895_cmu_init(void)2799 static int __init exynos8895_cmu_init(void)
2800 {
2801 return platform_driver_register(&exynos8895_cmu_driver);
2802 }
2803 core_initcall(exynos8895_cmu_init);
2804