1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2021 Linaro Ltd.
4 * Author: Sam Protsenko <semen.protsenko@linaro.org>
5 *
6 * Common Clock Framework support for Exynos850 SoC.
7 */
8
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/of.h>
12 #include <linux/platform_device.h>
13
14 #include <dt-bindings/clock/exynos850.h>
15
16 #include "clk.h"
17 #include "clk-cpu.h"
18 #include "clk-exynos-arm64.h"
19
20 /* NOTE: Must be equal to the last clock ID increased by one */
21 #define CLKS_NR_TOP (CLK_DOUT_CPUCL1_SWITCH + 1)
22 #define CLKS_NR_APM (CLK_GOUT_SYSREG_APM_PCLK + 1)
23 #define CLKS_NR_AUD (CLK_GOUT_AUD_CMU_AUD_PCLK + 1)
24 #define CLKS_NR_CMGP (CLK_GOUT_SYSREG_CMGP_PCLK + 1)
25 #define CLKS_NR_CPUCL0 (CLK_CLUSTER0_SCLK + 1)
26 #define CLKS_NR_CPUCL1 (CLK_CLUSTER1_SCLK + 1)
27 #define CLKS_NR_G3D (CLK_GOUT_G3D_SYSREG_PCLK + 1)
28 #define CLKS_NR_HSI (CLK_GOUT_HSI_CMU_HSI_PCLK + 1)
29 #define CLKS_NR_IS (CLK_GOUT_IS_SYSREG_PCLK + 1)
30 #define CLKS_NR_MFCMSCL (CLK_GOUT_MFCMSCL_SYSREG_PCLK + 1)
31 #define CLKS_NR_PERI (CLK_GOUT_BUSIF_TMU_PCLK + 1)
32 #define CLKS_NR_CORE (CLK_GOUT_SPDMA_CORE_ACLK + 1)
33 #define CLKS_NR_DPU (CLK_GOUT_DPU_SYSREG_PCLK + 1)
34
35 /* ---- CMU_TOP ------------------------------------------------------------- */
36
37 /* Register Offset definitions for CMU_TOP (0x120e0000) */
38 #define PLL_LOCKTIME_PLL_MMC 0x0000
39 #define PLL_LOCKTIME_PLL_SHARED0 0x0004
40 #define PLL_LOCKTIME_PLL_SHARED1 0x0008
41 #define PLL_CON0_PLL_MMC 0x0100
42 #define PLL_CON3_PLL_MMC 0x010c
43 #define PLL_CON0_PLL_SHARED0 0x0140
44 #define PLL_CON3_PLL_SHARED0 0x014c
45 #define PLL_CON0_PLL_SHARED1 0x0180
46 #define PLL_CON3_PLL_SHARED1 0x018c
47 #define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1000
48 #define CLK_CON_MUX_MUX_CLKCMU_AUD 0x1004
49 #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1014
50 #define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018
51 #define CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD 0x101c
52 #define CLK_CON_MUX_MUX_CLKCMU_CORE_SSS 0x1020
53 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG 0x1024
54 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x1028
55 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_DBG 0x102c
56 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x1030
57 #define CLK_CON_MUX_MUX_CLKCMU_DPU 0x1034
58 #define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x1038
59 #define CLK_CON_MUX_MUX_CLKCMU_HSI_BUS 0x103c
60 #define CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD 0x1040
61 #define CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD 0x1044
62 #define CLK_CON_MUX_MUX_CLKCMU_IS_BUS 0x1048
63 #define CLK_CON_MUX_MUX_CLKCMU_IS_GDC 0x104c
64 #define CLK_CON_MUX_MUX_CLKCMU_IS_ITP 0x1050
65 #define CLK_CON_MUX_MUX_CLKCMU_IS_VRA 0x1054
66 #define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_JPEG 0x1058
67 #define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_M2M 0x105c
68 #define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MCSC 0x1060
69 #define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC 0x1064
70 #define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1070
71 #define CLK_CON_MUX_MUX_CLKCMU_PERI_IP 0x1074
72 #define CLK_CON_MUX_MUX_CLKCMU_PERI_UART 0x1078
73 #define CLK_CON_DIV_CLKCMU_APM_BUS 0x180c
74 #define CLK_CON_DIV_CLKCMU_AUD 0x1810
75 #define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1820
76 #define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1824
77 #define CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD 0x1828
78 #define CLK_CON_DIV_CLKCMU_CORE_SSS 0x182c
79 #define CLK_CON_DIV_CLKCMU_CPUCL0_DBG 0x1830
80 #define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1834
81 #define CLK_CON_DIV_CLKCMU_CPUCL1_DBG 0x1838
82 #define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x183c
83 #define CLK_CON_DIV_CLKCMU_DPU 0x1840
84 #define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x1844
85 #define CLK_CON_DIV_CLKCMU_HSI_BUS 0x1848
86 #define CLK_CON_DIV_CLKCMU_HSI_MMC_CARD 0x184c
87 #define CLK_CON_DIV_CLKCMU_HSI_USB20DRD 0x1850
88 #define CLK_CON_DIV_CLKCMU_IS_BUS 0x1854
89 #define CLK_CON_DIV_CLKCMU_IS_GDC 0x1858
90 #define CLK_CON_DIV_CLKCMU_IS_ITP 0x185c
91 #define CLK_CON_DIV_CLKCMU_IS_VRA 0x1860
92 #define CLK_CON_DIV_CLKCMU_MFCMSCL_JPEG 0x1864
93 #define CLK_CON_DIV_CLKCMU_MFCMSCL_M2M 0x1868
94 #define CLK_CON_DIV_CLKCMU_MFCMSCL_MCSC 0x186c
95 #define CLK_CON_DIV_CLKCMU_MFCMSCL_MFC 0x1870
96 #define CLK_CON_DIV_CLKCMU_PERI_BUS 0x187c
97 #define CLK_CON_DIV_CLKCMU_PERI_IP 0x1880
98 #define CLK_CON_DIV_CLKCMU_PERI_UART 0x1884
99 #define CLK_CON_DIV_PLL_SHARED0_DIV2 0x188c
100 #define CLK_CON_DIV_PLL_SHARED0_DIV3 0x1890
101 #define CLK_CON_DIV_PLL_SHARED0_DIV4 0x1894
102 #define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1898
103 #define CLK_CON_DIV_PLL_SHARED1_DIV3 0x189c
104 #define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18a0
105 #define CLK_CON_GAT_GATE_CLKCMU_APM_BUS 0x2008
106 #define CLK_CON_GAT_GATE_CLKCMU_AUD 0x200c
107 #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x201c
108 #define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020
109 #define CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD 0x2024
110 #define CLK_CON_GAT_GATE_CLKCMU_CORE_SSS 0x2028
111 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG 0x202c
112 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH 0x2030
113 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_DBG 0x2034
114 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH 0x2038
115 #define CLK_CON_GAT_GATE_CLKCMU_DPU 0x203c
116 #define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x2040
117 #define CLK_CON_GAT_GATE_CLKCMU_HSI_BUS 0x2044
118 #define CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD 0x2048
119 #define CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD 0x204c
120 #define CLK_CON_GAT_GATE_CLKCMU_IS_BUS 0x2050
121 #define CLK_CON_GAT_GATE_CLKCMU_IS_GDC 0x2054
122 #define CLK_CON_GAT_GATE_CLKCMU_IS_ITP 0x2058
123 #define CLK_CON_GAT_GATE_CLKCMU_IS_VRA 0x205c
124 #define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_JPEG 0x2060
125 #define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_M2M 0x2064
126 #define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MCSC 0x2068
127 #define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC 0x206c
128 #define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x2080
129 #define CLK_CON_GAT_GATE_CLKCMU_PERI_IP 0x2084
130 #define CLK_CON_GAT_GATE_CLKCMU_PERI_UART 0x2088
131
132 static const unsigned long top_clk_regs[] __initconst = {
133 PLL_LOCKTIME_PLL_MMC,
134 PLL_LOCKTIME_PLL_SHARED0,
135 PLL_LOCKTIME_PLL_SHARED1,
136 PLL_CON0_PLL_MMC,
137 PLL_CON3_PLL_MMC,
138 PLL_CON0_PLL_SHARED0,
139 PLL_CON3_PLL_SHARED0,
140 PLL_CON0_PLL_SHARED1,
141 PLL_CON3_PLL_SHARED1,
142 CLK_CON_MUX_MUX_CLKCMU_APM_BUS,
143 CLK_CON_MUX_MUX_CLKCMU_AUD,
144 CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,
145 CLK_CON_MUX_MUX_CLKCMU_CORE_CCI,
146 CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD,
147 CLK_CON_MUX_MUX_CLKCMU_CORE_SSS,
148 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG,
149 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
150 CLK_CON_MUX_MUX_CLKCMU_CPUCL1_DBG,
151 CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
152 CLK_CON_MUX_MUX_CLKCMU_DPU,
153 CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH,
154 CLK_CON_MUX_MUX_CLKCMU_HSI_BUS,
155 CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD,
156 CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD,
157 CLK_CON_MUX_MUX_CLKCMU_IS_BUS,
158 CLK_CON_MUX_MUX_CLKCMU_IS_GDC,
159 CLK_CON_MUX_MUX_CLKCMU_IS_ITP,
160 CLK_CON_MUX_MUX_CLKCMU_IS_VRA,
161 CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_JPEG,
162 CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_M2M,
163 CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MCSC,
164 CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC,
165 CLK_CON_MUX_MUX_CLKCMU_PERI_BUS,
166 CLK_CON_MUX_MUX_CLKCMU_PERI_IP,
167 CLK_CON_MUX_MUX_CLKCMU_PERI_UART,
168 CLK_CON_DIV_CLKCMU_APM_BUS,
169 CLK_CON_DIV_CLKCMU_AUD,
170 CLK_CON_DIV_CLKCMU_CORE_BUS,
171 CLK_CON_DIV_CLKCMU_CORE_CCI,
172 CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD,
173 CLK_CON_DIV_CLKCMU_CORE_SSS,
174 CLK_CON_DIV_CLKCMU_CPUCL0_DBG,
175 CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH,
176 CLK_CON_DIV_CLKCMU_CPUCL1_DBG,
177 CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH,
178 CLK_CON_DIV_CLKCMU_DPU,
179 CLK_CON_DIV_CLKCMU_G3D_SWITCH,
180 CLK_CON_DIV_CLKCMU_HSI_BUS,
181 CLK_CON_DIV_CLKCMU_HSI_MMC_CARD,
182 CLK_CON_DIV_CLKCMU_HSI_USB20DRD,
183 CLK_CON_DIV_CLKCMU_IS_BUS,
184 CLK_CON_DIV_CLKCMU_IS_GDC,
185 CLK_CON_DIV_CLKCMU_IS_ITP,
186 CLK_CON_DIV_CLKCMU_IS_VRA,
187 CLK_CON_DIV_CLKCMU_MFCMSCL_JPEG,
188 CLK_CON_DIV_CLKCMU_MFCMSCL_M2M,
189 CLK_CON_DIV_CLKCMU_MFCMSCL_MCSC,
190 CLK_CON_DIV_CLKCMU_MFCMSCL_MFC,
191 CLK_CON_DIV_CLKCMU_PERI_BUS,
192 CLK_CON_DIV_CLKCMU_PERI_IP,
193 CLK_CON_DIV_CLKCMU_PERI_UART,
194 CLK_CON_DIV_PLL_SHARED0_DIV2,
195 CLK_CON_DIV_PLL_SHARED0_DIV3,
196 CLK_CON_DIV_PLL_SHARED0_DIV4,
197 CLK_CON_DIV_PLL_SHARED1_DIV2,
198 CLK_CON_DIV_PLL_SHARED1_DIV3,
199 CLK_CON_DIV_PLL_SHARED1_DIV4,
200 CLK_CON_GAT_GATE_CLKCMU_APM_BUS,
201 CLK_CON_GAT_GATE_CLKCMU_AUD,
202 CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
203 CLK_CON_GAT_GATE_CLKCMU_CORE_CCI,
204 CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD,
205 CLK_CON_GAT_GATE_CLKCMU_CORE_SSS,
206 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG,
207 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH,
208 CLK_CON_GAT_GATE_CLKCMU_CPUCL1_DBG,
209 CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH,
210 CLK_CON_GAT_GATE_CLKCMU_DPU,
211 CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH,
212 CLK_CON_GAT_GATE_CLKCMU_HSI_BUS,
213 CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD,
214 CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD,
215 CLK_CON_GAT_GATE_CLKCMU_IS_BUS,
216 CLK_CON_GAT_GATE_CLKCMU_IS_GDC,
217 CLK_CON_GAT_GATE_CLKCMU_IS_ITP,
218 CLK_CON_GAT_GATE_CLKCMU_IS_VRA,
219 CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_JPEG,
220 CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_M2M,
221 CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MCSC,
222 CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC,
223 CLK_CON_GAT_GATE_CLKCMU_PERI_BUS,
224 CLK_CON_GAT_GATE_CLKCMU_PERI_IP,
225 CLK_CON_GAT_GATE_CLKCMU_PERI_UART,
226 };
227
228 /*
229 * Do not provide PLL tables to core PLLs, as MANUAL_PLL_CTRL bit is not set
230 * for those PLLs by default, so set_rate operation would fail.
231 */
232 static const struct samsung_pll_clock top_pll_clks[] __initconst = {
233 /* CMU_TOP_PURECLKCOMP */
234 PLL(pll_0822x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
235 PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0,
236 NULL),
237 PLL(pll_0822x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
238 PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1,
239 NULL),
240 PLL(pll_0831x, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "oscclk",
241 PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL),
242 };
243
244 /* List of parent clocks for Muxes in CMU_TOP */
245 PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" };
246 PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" };
247 PNAME(mout_mmc_pll_p) = { "oscclk", "fout_mmc_pll" };
248 /* List of parent clocks for Muxes in CMU_TOP: for CMU_APM */
249 PNAME(mout_clkcmu_apm_bus_p) = { "dout_shared0_div4", "pll_shared1_div4" };
250 /* List of parent clocks for Muxes in CMU_TOP: for CMU_AUD */
251 PNAME(mout_aud_p) = { "fout_shared1_pll", "dout_shared0_div2",
252 "dout_shared1_div2", "dout_shared0_div3" };
253 /* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */
254 PNAME(mout_core_bus_p) = { "dout_shared1_div2", "dout_shared0_div3",
255 "dout_shared1_div3", "dout_shared0_div4" };
256 PNAME(mout_core_cci_p) = { "dout_shared0_div2", "dout_shared1_div2",
257 "dout_shared0_div3", "dout_shared1_div3" };
258 PNAME(mout_core_mmc_embd_p) = { "oscclk", "dout_shared0_div2",
259 "dout_shared1_div2", "dout_shared0_div3",
260 "dout_shared1_div3", "mout_mmc_pll",
261 "oscclk", "oscclk" };
262 PNAME(mout_core_sss_p) = { "dout_shared0_div3", "dout_shared1_div3",
263 "dout_shared0_div4", "dout_shared1_div4" };
264 /* List of parent clocks for Muxes in CMU_TOP: for CMU_CPUCL0 */
265 PNAME(mout_cpucl0_switch_p) = { "fout_shared0_pll", "fout_shared1_pll",
266 "dout_shared0_div2", "dout_shared1_div2" };
267 PNAME(mout_cpucl0_dbg_p) = { "dout_shared0_div4", "dout_shared1_div4" };
268 /* List of parent clocks for Muxes in CMU_TOP: for CMU_CPUCL1 */
269 PNAME(mout_cpucl1_switch_p) = { "fout_shared0_pll", "fout_shared1_pll",
270 "dout_shared0_div2", "dout_shared1_div2" };
271 PNAME(mout_cpucl1_dbg_p) = { "dout_shared0_div4", "dout_shared1_div4" };
272 /* List of parent clocks for Muxes in CMU_TOP: for CMU_G3D */
273 PNAME(mout_g3d_switch_p) = { "dout_shared0_div2", "dout_shared1_div2",
274 "dout_shared0_div3", "dout_shared1_div3" };
275 /* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI */
276 PNAME(mout_hsi_bus_p) = { "dout_shared0_div2", "dout_shared1_div2" };
277 PNAME(mout_hsi_mmc_card_p) = { "oscclk", "dout_shared0_div2",
278 "dout_shared1_div2", "dout_shared0_div3",
279 "dout_shared1_div3", "mout_mmc_pll",
280 "oscclk", "oscclk" };
281 PNAME(mout_hsi_usb20drd_p) = { "oscclk", "dout_shared0_div4",
282 "dout_shared1_div4", "oscclk" };
283 /* List of parent clocks for Muxes in CMU_TOP: for CMU_IS */
284 PNAME(mout_is_bus_p) = { "dout_shared0_div2", "dout_shared1_div2",
285 "dout_shared0_div3", "dout_shared1_div3" };
286 PNAME(mout_is_itp_p) = { "dout_shared0_div2", "dout_shared1_div2",
287 "dout_shared0_div3", "dout_shared1_div3" };
288 PNAME(mout_is_vra_p) = { "dout_shared0_div2", "dout_shared1_div2",
289 "dout_shared0_div3", "dout_shared1_div3" };
290 PNAME(mout_is_gdc_p) = { "dout_shared0_div2", "dout_shared1_div2",
291 "dout_shared0_div3", "dout_shared1_div3" };
292 /* List of parent clocks for Muxes in CMU_TOP: for CMU_MFCMSCL */
293 PNAME(mout_mfcmscl_mfc_p) = { "dout_shared1_div2", "dout_shared0_div3",
294 "dout_shared1_div3", "dout_shared0_div4" };
295 PNAME(mout_mfcmscl_m2m_p) = { "dout_shared1_div2", "dout_shared0_div3",
296 "dout_shared1_div3", "dout_shared0_div4" };
297 PNAME(mout_mfcmscl_mcsc_p) = { "dout_shared1_div2", "dout_shared0_div3",
298 "dout_shared1_div3", "dout_shared0_div4" };
299 PNAME(mout_mfcmscl_jpeg_p) = { "dout_shared0_div3", "dout_shared1_div3",
300 "dout_shared0_div4", "dout_shared1_div4" };
301 /* List of parent clocks for Muxes in CMU_TOP: for CMU_PERI */
302 PNAME(mout_peri_bus_p) = { "dout_shared0_div4", "dout_shared1_div4" };
303 PNAME(mout_peri_uart_p) = { "oscclk", "dout_shared0_div4",
304 "dout_shared1_div4", "oscclk" };
305 PNAME(mout_peri_ip_p) = { "oscclk", "dout_shared0_div4",
306 "dout_shared1_div4", "oscclk" };
307 /* List of parent clocks for Muxes in CMU_TOP: for CMU_DPU */
308 PNAME(mout_dpu_p) = { "dout_shared0_div3", "dout_shared1_div3",
309 "dout_shared0_div4", "dout_shared1_div4" };
310
311 static const struct samsung_mux_clock top_mux_clks[] __initconst = {
312 /* CMU_TOP_PURECLKCOMP */
313 MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p,
314 PLL_CON0_PLL_SHARED0, 4, 1),
315 MUX(CLK_MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p,
316 PLL_CON0_PLL_SHARED1, 4, 1),
317 MUX(CLK_MOUT_MMC_PLL, "mout_mmc_pll", mout_mmc_pll_p,
318 PLL_CON0_PLL_MMC, 4, 1),
319
320 /* APM */
321 MUX(CLK_MOUT_CLKCMU_APM_BUS, "mout_clkcmu_apm_bus",
322 mout_clkcmu_apm_bus_p, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 1),
323
324 /* AUD */
325 MUX(CLK_MOUT_AUD, "mout_aud", mout_aud_p,
326 CLK_CON_MUX_MUX_CLKCMU_AUD, 0, 2),
327
328 /* CORE */
329 MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p,
330 CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
331 MUX(CLK_MOUT_CORE_CCI, "mout_core_cci", mout_core_cci_p,
332 CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 0, 2),
333 MUX(CLK_MOUT_CORE_MMC_EMBD, "mout_core_mmc_embd", mout_core_mmc_embd_p,
334 CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD, 0, 3),
335 MUX(CLK_MOUT_CORE_SSS, "mout_core_sss", mout_core_sss_p,
336 CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, 0, 2),
337
338 /* CPUCL0 */
339 MUX(CLK_MOUT_CPUCL0_DBG, "mout_cpucl0_dbg", mout_cpucl0_dbg_p,
340 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG, 0, 1),
341 MUX(CLK_MOUT_CPUCL0_SWITCH, "mout_cpucl0_switch", mout_cpucl0_switch_p,
342 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, 0, 2),
343
344 /* CPUCL1 */
345 MUX(CLK_MOUT_CPUCL1_DBG, "mout_cpucl1_dbg", mout_cpucl1_dbg_p,
346 CLK_CON_MUX_MUX_CLKCMU_CPUCL1_DBG, 0, 1),
347 MUX(CLK_MOUT_CPUCL1_SWITCH, "mout_cpucl1_switch", mout_cpucl1_switch_p,
348 CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, 0, 2),
349
350 /* DPU */
351 MUX(CLK_MOUT_DPU, "mout_dpu", mout_dpu_p,
352 CLK_CON_MUX_MUX_CLKCMU_DPU, 0, 2),
353
354 /* G3D */
355 MUX(CLK_MOUT_G3D_SWITCH, "mout_g3d_switch", mout_g3d_switch_p,
356 CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0, 2),
357
358 /* HSI */
359 MUX(CLK_MOUT_HSI_BUS, "mout_hsi_bus", mout_hsi_bus_p,
360 CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, 0, 1),
361 MUX(CLK_MOUT_HSI_MMC_CARD, "mout_hsi_mmc_card", mout_hsi_mmc_card_p,
362 CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD, 0, 3),
363 MUX(CLK_MOUT_HSI_USB20DRD, "mout_hsi_usb20drd", mout_hsi_usb20drd_p,
364 CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD, 0, 2),
365
366 /* IS */
367 MUX(CLK_MOUT_IS_BUS, "mout_is_bus", mout_is_bus_p,
368 CLK_CON_MUX_MUX_CLKCMU_IS_BUS, 0, 2),
369 MUX(CLK_MOUT_IS_ITP, "mout_is_itp", mout_is_itp_p,
370 CLK_CON_MUX_MUX_CLKCMU_IS_ITP, 0, 2),
371 MUX(CLK_MOUT_IS_VRA, "mout_is_vra", mout_is_vra_p,
372 CLK_CON_MUX_MUX_CLKCMU_IS_VRA, 0, 2),
373 MUX(CLK_MOUT_IS_GDC, "mout_is_gdc", mout_is_gdc_p,
374 CLK_CON_MUX_MUX_CLKCMU_IS_GDC, 0, 2),
375
376 /* MFCMSCL */
377 MUX(CLK_MOUT_MFCMSCL_MFC, "mout_mfcmscl_mfc", mout_mfcmscl_mfc_p,
378 CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC, 0, 2),
379 MUX(CLK_MOUT_MFCMSCL_M2M, "mout_mfcmscl_m2m", mout_mfcmscl_m2m_p,
380 CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_M2M, 0, 2),
381 MUX(CLK_MOUT_MFCMSCL_MCSC, "mout_mfcmscl_mcsc", mout_mfcmscl_mcsc_p,
382 CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MCSC, 0, 2),
383 MUX(CLK_MOUT_MFCMSCL_JPEG, "mout_mfcmscl_jpeg", mout_mfcmscl_jpeg_p,
384 CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_JPEG, 0, 2),
385
386 /* PERI */
387 MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p,
388 CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1),
389 MUX(CLK_MOUT_PERI_UART, "mout_peri_uart", mout_peri_uart_p,
390 CLK_CON_MUX_MUX_CLKCMU_PERI_UART, 0, 2),
391 MUX(CLK_MOUT_PERI_IP, "mout_peri_ip", mout_peri_ip_p,
392 CLK_CON_MUX_MUX_CLKCMU_PERI_IP, 0, 2),
393 };
394
395 static const struct samsung_div_clock top_div_clks[] __initconst = {
396 /* CMU_TOP_PURECLKCOMP */
397 DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll",
398 CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
399 DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "mout_shared0_pll",
400 CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
401 DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "mout_shared1_pll",
402 CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
403 DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "mout_shared1_pll",
404 CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
405 DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2",
406 CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
407 DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2",
408 CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
409
410 /* APM */
411 DIV(CLK_DOUT_CLKCMU_APM_BUS, "dout_clkcmu_apm_bus",
412 "gout_clkcmu_apm_bus", CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3),
413
414 /* AUD */
415 DIV(CLK_DOUT_AUD, "dout_aud", "gout_aud",
416 CLK_CON_DIV_CLKCMU_AUD, 0, 4),
417
418 /* CORE */
419 DIV(CLK_DOUT_CORE_BUS, "dout_core_bus", "gout_core_bus",
420 CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
421 DIV(CLK_DOUT_CORE_CCI, "dout_core_cci", "gout_core_cci",
422 CLK_CON_DIV_CLKCMU_CORE_CCI, 0, 4),
423 DIV(CLK_DOUT_CORE_MMC_EMBD, "dout_core_mmc_embd", "gout_core_mmc_embd",
424 CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD, 0, 9),
425 DIV(CLK_DOUT_CORE_SSS, "dout_core_sss", "gout_core_sss",
426 CLK_CON_DIV_CLKCMU_CORE_SSS, 0, 4),
427
428 /* CPUCL0 */
429 DIV(CLK_DOUT_CPUCL0_DBG, "dout_cpucl0_dbg", "gout_cpucl0_dbg",
430 CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 3),
431 DIV(CLK_DOUT_CPUCL0_SWITCH, "dout_cpucl0_switch", "gout_cpucl0_switch",
432 CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3),
433
434 /* CPUCL1 */
435 DIV(CLK_DOUT_CPUCL1_DBG, "dout_cpucl1_dbg", "gout_cpucl1_dbg",
436 CLK_CON_DIV_CLKCMU_CPUCL1_DBG, 0, 3),
437 DIV(CLK_DOUT_CPUCL1_SWITCH, "dout_cpucl1_switch", "gout_cpucl1_switch",
438 CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 3),
439
440 /* DPU */
441 DIV(CLK_DOUT_DPU, "dout_dpu", "gout_dpu",
442 CLK_CON_DIV_CLKCMU_DPU, 0, 4),
443
444 /* G3D */
445 DIV(CLK_DOUT_G3D_SWITCH, "dout_g3d_switch", "gout_g3d_switch",
446 CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3),
447
448 /* HSI */
449 DIV(CLK_DOUT_HSI_BUS, "dout_hsi_bus", "gout_hsi_bus",
450 CLK_CON_DIV_CLKCMU_HSI_BUS, 0, 4),
451 DIV(CLK_DOUT_HSI_MMC_CARD, "dout_hsi_mmc_card", "gout_hsi_mmc_card",
452 CLK_CON_DIV_CLKCMU_HSI_MMC_CARD, 0, 9),
453 DIV(CLK_DOUT_HSI_USB20DRD, "dout_hsi_usb20drd", "gout_hsi_usb20drd",
454 CLK_CON_DIV_CLKCMU_HSI_USB20DRD, 0, 4),
455
456 /* IS */
457 DIV(CLK_DOUT_IS_BUS, "dout_is_bus", "gout_is_bus",
458 CLK_CON_DIV_CLKCMU_IS_BUS, 0, 4),
459 DIV(CLK_DOUT_IS_ITP, "dout_is_itp", "gout_is_itp",
460 CLK_CON_DIV_CLKCMU_IS_ITP, 0, 4),
461 DIV(CLK_DOUT_IS_VRA, "dout_is_vra", "gout_is_vra",
462 CLK_CON_DIV_CLKCMU_IS_VRA, 0, 4),
463 DIV(CLK_DOUT_IS_GDC, "dout_is_gdc", "gout_is_gdc",
464 CLK_CON_DIV_CLKCMU_IS_GDC, 0, 4),
465
466 /* MFCMSCL */
467 DIV(CLK_DOUT_MFCMSCL_MFC, "dout_mfcmscl_mfc", "gout_mfcmscl_mfc",
468 CLK_CON_DIV_CLKCMU_MFCMSCL_MFC, 0, 4),
469 DIV(CLK_DOUT_MFCMSCL_M2M, "dout_mfcmscl_m2m", "gout_mfcmscl_m2m",
470 CLK_CON_DIV_CLKCMU_MFCMSCL_M2M, 0, 4),
471 DIV(CLK_DOUT_MFCMSCL_MCSC, "dout_mfcmscl_mcsc", "gout_mfcmscl_mcsc",
472 CLK_CON_DIV_CLKCMU_MFCMSCL_MCSC, 0, 4),
473 DIV(CLK_DOUT_MFCMSCL_JPEG, "dout_mfcmscl_jpeg", "gout_mfcmscl_jpeg",
474 CLK_CON_DIV_CLKCMU_MFCMSCL_JPEG, 0, 4),
475
476 /* PERI */
477 DIV(CLK_DOUT_PERI_BUS, "dout_peri_bus", "gout_peri_bus",
478 CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4),
479 DIV(CLK_DOUT_PERI_UART, "dout_peri_uart", "gout_peri_uart",
480 CLK_CON_DIV_CLKCMU_PERI_UART, 0, 4),
481 DIV(CLK_DOUT_PERI_IP, "dout_peri_ip", "gout_peri_ip",
482 CLK_CON_DIV_CLKCMU_PERI_IP, 0, 4),
483 };
484
485 static const struct samsung_gate_clock top_gate_clks[] __initconst = {
486 /* CORE */
487 GATE(CLK_GOUT_CORE_BUS, "gout_core_bus", "mout_core_bus",
488 CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0),
489 GATE(CLK_GOUT_CORE_CCI, "gout_core_cci", "mout_core_cci",
490 CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 21, 0, 0),
491 GATE(CLK_GOUT_CORE_MMC_EMBD, "gout_core_mmc_embd", "mout_core_mmc_embd",
492 CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD, 21, 0, 0),
493 GATE(CLK_GOUT_CORE_SSS, "gout_core_sss", "mout_core_sss",
494 CLK_CON_GAT_GATE_CLKCMU_CORE_SSS, 21, 0, 0),
495
496 /* APM */
497 GATE(CLK_GOUT_CLKCMU_APM_BUS, "gout_clkcmu_apm_bus",
498 "mout_clkcmu_apm_bus", CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 21, 0, 0),
499
500 /* AUD */
501 GATE(CLK_GOUT_AUD, "gout_aud", "mout_aud",
502 CLK_CON_GAT_GATE_CLKCMU_AUD, 21, 0, 0),
503
504 /* CPUCL0 */
505 GATE(CLK_GOUT_CPUCL0_DBG, "gout_cpucl0_dbg", "mout_cpucl0_dbg",
506 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG, 21, 0, 0),
507 GATE(CLK_GOUT_CPUCL0_SWITCH, "gout_cpucl0_switch", "mout_cpucl0_switch",
508 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 21, 0, 0),
509
510 /* CPUCL1 */
511 GATE(CLK_GOUT_CPUCL1_DBG, "gout_cpucl1_dbg", "mout_cpucl1_dbg",
512 CLK_CON_GAT_GATE_CLKCMU_CPUCL1_DBG, 21, 0, 0),
513 GATE(CLK_GOUT_CPUCL1_SWITCH, "gout_cpucl1_switch", "mout_cpucl1_switch",
514 CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 21, 0, 0),
515
516 /* DPU */
517 GATE(CLK_GOUT_DPU, "gout_dpu", "mout_dpu",
518 CLK_CON_GAT_GATE_CLKCMU_DPU, 21, 0, 0),
519
520 /* G3D */
521 GATE(CLK_GOUT_G3D_SWITCH, "gout_g3d_switch", "mout_g3d_switch",
522 CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 21, 0, 0),
523
524 /* HSI */
525 GATE(CLK_GOUT_HSI_BUS, "gout_hsi_bus", "mout_hsi_bus",
526 CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, 21, 0, 0),
527 GATE(CLK_GOUT_HSI_MMC_CARD, "gout_hsi_mmc_card", "mout_hsi_mmc_card",
528 CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD, 21, 0, 0),
529 GATE(CLK_GOUT_HSI_USB20DRD, "gout_hsi_usb20drd", "mout_hsi_usb20drd",
530 CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD, 21, 0, 0),
531
532 /* IS */
533 /* TODO: These clocks have to be always enabled to access CMU_IS regs */
534 GATE(CLK_GOUT_IS_BUS, "gout_is_bus", "mout_is_bus",
535 CLK_CON_GAT_GATE_CLKCMU_IS_BUS, 21, CLK_IS_CRITICAL, 0),
536 GATE(CLK_GOUT_IS_ITP, "gout_is_itp", "mout_is_itp",
537 CLK_CON_GAT_GATE_CLKCMU_IS_ITP, 21, CLK_IS_CRITICAL, 0),
538 GATE(CLK_GOUT_IS_VRA, "gout_is_vra", "mout_is_vra",
539 CLK_CON_GAT_GATE_CLKCMU_IS_VRA, 21, CLK_IS_CRITICAL, 0),
540 GATE(CLK_GOUT_IS_GDC, "gout_is_gdc", "mout_is_gdc",
541 CLK_CON_GAT_GATE_CLKCMU_IS_GDC, 21, CLK_IS_CRITICAL, 0),
542
543 /* MFCMSCL */
544 /* TODO: These have to be always enabled to access CMU_MFCMSCL regs */
545 GATE(CLK_GOUT_MFCMSCL_MFC, "gout_mfcmscl_mfc", "mout_mfcmscl_mfc",
546 CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC, 21, CLK_IS_CRITICAL, 0),
547 GATE(CLK_GOUT_MFCMSCL_M2M, "gout_mfcmscl_m2m", "mout_mfcmscl_m2m",
548 CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_M2M, 21, CLK_IS_CRITICAL, 0),
549 GATE(CLK_GOUT_MFCMSCL_MCSC, "gout_mfcmscl_mcsc", "mout_mfcmscl_mcsc",
550 CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MCSC, 21, CLK_IS_CRITICAL, 0),
551 GATE(CLK_GOUT_MFCMSCL_JPEG, "gout_mfcmscl_jpeg", "mout_mfcmscl_jpeg",
552 CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_JPEG, 21, CLK_IS_CRITICAL, 0),
553
554 /* PERI */
555 GATE(CLK_GOUT_PERI_BUS, "gout_peri_bus", "mout_peri_bus",
556 CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 21, 0, 0),
557 GATE(CLK_GOUT_PERI_UART, "gout_peri_uart", "mout_peri_uart",
558 CLK_CON_GAT_GATE_CLKCMU_PERI_UART, 21, 0, 0),
559 GATE(CLK_GOUT_PERI_IP, "gout_peri_ip", "mout_peri_ip",
560 CLK_CON_GAT_GATE_CLKCMU_PERI_IP, 21, 0, 0),
561 };
562
563 static const struct samsung_cmu_info top_cmu_info __initconst = {
564 .pll_clks = top_pll_clks,
565 .nr_pll_clks = ARRAY_SIZE(top_pll_clks),
566 .mux_clks = top_mux_clks,
567 .nr_mux_clks = ARRAY_SIZE(top_mux_clks),
568 .div_clks = top_div_clks,
569 .nr_div_clks = ARRAY_SIZE(top_div_clks),
570 .gate_clks = top_gate_clks,
571 .nr_gate_clks = ARRAY_SIZE(top_gate_clks),
572 .nr_clk_ids = CLKS_NR_TOP,
573 .clk_regs = top_clk_regs,
574 .nr_clk_regs = ARRAY_SIZE(top_clk_regs),
575 };
576
exynos850_cmu_top_init(struct device_node * np)577 static void __init exynos850_cmu_top_init(struct device_node *np)
578 {
579 exynos_arm64_register_cmu(NULL, np, &top_cmu_info);
580 }
581
582 /* Register CMU_TOP early, as it's a dependency for other early domains */
583 CLK_OF_DECLARE(exynos850_cmu_top, "samsung,exynos850-cmu-top",
584 exynos850_cmu_top_init);
585
586 /* ---- CMU_APM ------------------------------------------------------------- */
587
588 /* Register Offset definitions for CMU_APM (0x11800000) */
589 #define PLL_CON0_MUX_CLKCMU_APM_BUS_USER 0x0600
590 #define PLL_CON0_MUX_CLK_RCO_APM_I3C_USER 0x0610
591 #define PLL_CON0_MUX_CLK_RCO_APM_USER 0x0620
592 #define PLL_CON0_MUX_DLL_USER 0x0630
593 #define CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS 0x1000
594 #define CLK_CON_MUX_MUX_CLK_APM_BUS 0x1004
595 #define CLK_CON_MUX_MUX_CLK_APM_I3C 0x1008
596 #define CLK_CON_DIV_CLKCMU_CHUB_BUS 0x1800
597 #define CLK_CON_DIV_DIV_CLK_APM_BUS 0x1804
598 #define CLK_CON_DIV_DIV_CLK_APM_I3C 0x1808
599 #define CLK_CON_GAT_CLKCMU_CMGP_BUS 0x2000
600 #define CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS 0x2014
601 #define CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK 0x2018
602 #define CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK 0x2020
603 #define CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK 0x2024
604 #define CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK 0x2028
605 #define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK 0x2034
606 #define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK 0x2038
607 #define CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK 0x20bc
608 #define CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK 0x20c0
609
610 static const unsigned long apm_clk_regs[] __initconst = {
611 PLL_CON0_MUX_CLKCMU_APM_BUS_USER,
612 PLL_CON0_MUX_CLK_RCO_APM_I3C_USER,
613 PLL_CON0_MUX_CLK_RCO_APM_USER,
614 PLL_CON0_MUX_DLL_USER,
615 CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS,
616 CLK_CON_MUX_MUX_CLK_APM_BUS,
617 CLK_CON_MUX_MUX_CLK_APM_I3C,
618 CLK_CON_DIV_CLKCMU_CHUB_BUS,
619 CLK_CON_DIV_DIV_CLK_APM_BUS,
620 CLK_CON_DIV_DIV_CLK_APM_I3C,
621 CLK_CON_GAT_CLKCMU_CMGP_BUS,
622 CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS,
623 CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK,
624 CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK,
625 CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK,
626 CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK,
627 CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK,
628 CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK,
629 CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK,
630 CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK,
631 };
632
633 /* List of parent clocks for Muxes in CMU_APM */
634 PNAME(mout_apm_bus_user_p) = { "oscclk_rco_apm", "dout_clkcmu_apm_bus" };
635 PNAME(mout_rco_apm_i3c_user_p) = { "oscclk_rco_apm", "clk_rco_i3c_pmic" };
636 PNAME(mout_rco_apm_user_p) = { "oscclk_rco_apm", "clk_rco_apm__alv" };
637 PNAME(mout_dll_user_p) = { "oscclk_rco_apm", "clk_dll_dco" };
638 PNAME(mout_clkcmu_chub_bus_p) = { "mout_apm_bus_user", "mout_dll_user" };
639 PNAME(mout_apm_bus_p) = { "mout_rco_apm_user", "mout_apm_bus_user",
640 "mout_dll_user", "oscclk_rco_apm" };
641 PNAME(mout_apm_i3c_p) = { "dout_apm_i3c", "mout_rco_apm_i3c_user" };
642
643 static const struct samsung_fixed_rate_clock apm_fixed_clks[] __initconst = {
644 FRATE(CLK_RCO_I3C_PMIC, "clk_rco_i3c_pmic", NULL, 0, 491520000),
645 FRATE(OSCCLK_RCO_APM, "oscclk_rco_apm", NULL, 0, 24576000),
646 FRATE(CLK_RCO_APM__ALV, "clk_rco_apm__alv", NULL, 0, 49152000),
647 FRATE(CLK_DLL_DCO, "clk_dll_dco", NULL, 0, 360000000),
648 };
649
650 static const struct samsung_mux_clock apm_mux_clks[] __initconst = {
651 MUX(CLK_MOUT_APM_BUS_USER, "mout_apm_bus_user", mout_apm_bus_user_p,
652 PLL_CON0_MUX_CLKCMU_APM_BUS_USER, 4, 1),
653 MUX(CLK_MOUT_RCO_APM_I3C_USER, "mout_rco_apm_i3c_user",
654 mout_rco_apm_i3c_user_p, PLL_CON0_MUX_CLK_RCO_APM_I3C_USER, 4, 1),
655 MUX(CLK_MOUT_RCO_APM_USER, "mout_rco_apm_user", mout_rco_apm_user_p,
656 PLL_CON0_MUX_CLK_RCO_APM_USER, 4, 1),
657 MUX(CLK_MOUT_DLL_USER, "mout_dll_user", mout_dll_user_p,
658 PLL_CON0_MUX_DLL_USER, 4, 1),
659 MUX(CLK_MOUT_CLKCMU_CHUB_BUS, "mout_clkcmu_chub_bus",
660 mout_clkcmu_chub_bus_p, CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS, 0, 1),
661 MUX(CLK_MOUT_APM_BUS, "mout_apm_bus", mout_apm_bus_p,
662 CLK_CON_MUX_MUX_CLK_APM_BUS, 0, 2),
663 MUX(CLK_MOUT_APM_I3C, "mout_apm_i3c", mout_apm_i3c_p,
664 CLK_CON_MUX_MUX_CLK_APM_I3C, 0, 1),
665 };
666
667 static const struct samsung_div_clock apm_div_clks[] __initconst = {
668 DIV(CLK_DOUT_CLKCMU_CHUB_BUS, "dout_clkcmu_chub_bus",
669 "gout_clkcmu_chub_bus",
670 CLK_CON_DIV_CLKCMU_CHUB_BUS, 0, 3),
671 DIV(CLK_DOUT_APM_BUS, "dout_apm_bus", "mout_apm_bus",
672 CLK_CON_DIV_DIV_CLK_APM_BUS, 0, 3),
673 DIV(CLK_DOUT_APM_I3C, "dout_apm_i3c", "mout_apm_bus",
674 CLK_CON_DIV_DIV_CLK_APM_I3C, 0, 3),
675 };
676
677 static const struct samsung_gate_clock apm_gate_clks[] __initconst = {
678 GATE(CLK_GOUT_CLKCMU_CMGP_BUS, "gout_clkcmu_cmgp_bus", "dout_apm_bus",
679 CLK_CON_GAT_CLKCMU_CMGP_BUS, 21, CLK_SET_RATE_PARENT, 0),
680 GATE(CLK_GOUT_CLKCMU_CHUB_BUS, "gout_clkcmu_chub_bus",
681 "mout_clkcmu_chub_bus",
682 CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS, 21, 0, 0),
683 GATE(CLK_GOUT_RTC_PCLK, "gout_rtc_pclk", "dout_apm_bus",
684 CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK, 21, 0, 0),
685 GATE(CLK_GOUT_TOP_RTC_PCLK, "gout_top_rtc_pclk", "dout_apm_bus",
686 CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK, 21, 0, 0),
687 GATE(CLK_GOUT_I3C_PCLK, "gout_i3c_pclk", "dout_apm_bus",
688 CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK, 21, 0, 0),
689 GATE(CLK_GOUT_I3C_SCLK, "gout_i3c_sclk", "mout_apm_i3c",
690 CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK, 21, 0, 0),
691 GATE(CLK_GOUT_SPEEDY_PCLK, "gout_speedy_pclk", "dout_apm_bus",
692 CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK, 21, 0, 0),
693 /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
694 GATE(CLK_GOUT_GPIO_ALIVE_PCLK, "gout_gpio_alive_pclk", "dout_apm_bus",
695 CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK, 21, CLK_IGNORE_UNUSED,
696 0),
697 GATE(CLK_GOUT_PMU_ALIVE_PCLK, "gout_pmu_alive_pclk", "dout_apm_bus",
698 CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK, 21, CLK_IS_CRITICAL, 0),
699 GATE(CLK_GOUT_SYSREG_APM_PCLK, "gout_sysreg_apm_pclk", "dout_apm_bus",
700 CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK, 21, 0, 0),
701 };
702
703 static const struct samsung_cmu_info apm_cmu_info __initconst = {
704 .mux_clks = apm_mux_clks,
705 .nr_mux_clks = ARRAY_SIZE(apm_mux_clks),
706 .div_clks = apm_div_clks,
707 .nr_div_clks = ARRAY_SIZE(apm_div_clks),
708 .gate_clks = apm_gate_clks,
709 .nr_gate_clks = ARRAY_SIZE(apm_gate_clks),
710 .fixed_clks = apm_fixed_clks,
711 .nr_fixed_clks = ARRAY_SIZE(apm_fixed_clks),
712 .nr_clk_ids = CLKS_NR_APM,
713 .clk_regs = apm_clk_regs,
714 .nr_clk_regs = ARRAY_SIZE(apm_clk_regs),
715 .clk_name = "dout_clkcmu_apm_bus",
716 };
717
718 /* ---- CMU_AUD ------------------------------------------------------------- */
719
720 #define PLL_LOCKTIME_PLL_AUD 0x0000
721 #define PLL_CON0_PLL_AUD 0x0100
722 #define PLL_CON3_PLL_AUD 0x010c
723 #define PLL_CON0_MUX_CLKCMU_AUD_CPU_USER 0x0600
724 #define PLL_CON0_MUX_TICK_USB_USER 0x0610
725 #define CLK_CON_MUX_MUX_CLK_AUD_CPU 0x1000
726 #define CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH 0x1004
727 #define CLK_CON_MUX_MUX_CLK_AUD_FM 0x1008
728 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF0 0x100c
729 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF1 0x1010
730 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF2 0x1014
731 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF3 0x1018
732 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF4 0x101c
733 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF5 0x1020
734 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF6 0x1024
735 #define CLK_CON_DIV_DIV_CLK_AUD_MCLK 0x1800
736 #define CLK_CON_DIV_DIV_CLK_AUD_AUDIF 0x1804
737 #define CLK_CON_DIV_DIV_CLK_AUD_BUSD 0x1808
738 #define CLK_CON_DIV_DIV_CLK_AUD_BUSP 0x180c
739 #define CLK_CON_DIV_DIV_CLK_AUD_CNT 0x1810
740 #define CLK_CON_DIV_DIV_CLK_AUD_CPU 0x1814
741 #define CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK 0x1818
742 #define CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG 0x181c
743 #define CLK_CON_DIV_DIV_CLK_AUD_FM 0x1820
744 #define CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY 0x1824
745 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF0 0x1828
746 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF1 0x182c
747 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF2 0x1830
748 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF3 0x1834
749 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF4 0x1838
750 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF5 0x183c
751 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF6 0x1840
752 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT 0x2000
753 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0 0x2004
754 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1 0x2008
755 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2 0x200c
756 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3 0x2010
757 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4 0x2014
758 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5 0x2018
759 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6 0x201c
760 #define CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK 0x2020
761 #define CLK_CON_GAT_GOUT_AUD_ABOX_ACLK 0x2048
762 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY 0x204c
763 #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB 0x2050
764 #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32 0x2054
765 #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP 0x2058
766 #define CLK_CON_GAT_GOUT_AUD_CODEC_MCLK 0x206c
767 #define CLK_CON_GAT_GOUT_AUD_TZPC_PCLK 0x2070
768 #define CLK_CON_GAT_GOUT_AUD_GPIO_PCLK 0x2074
769 #define CLK_CON_GAT_GOUT_AUD_PPMU_ACLK 0x2088
770 #define CLK_CON_GAT_GOUT_AUD_PPMU_PCLK 0x208c
771 #define CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1 0x20b4
772 #define CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK 0x20b8
773 #define CLK_CON_GAT_GOUT_AUD_WDT_PCLK 0x20bc
774
775 static const unsigned long aud_clk_regs[] __initconst = {
776 PLL_LOCKTIME_PLL_AUD,
777 PLL_CON0_PLL_AUD,
778 PLL_CON3_PLL_AUD,
779 PLL_CON0_MUX_CLKCMU_AUD_CPU_USER,
780 PLL_CON0_MUX_TICK_USB_USER,
781 CLK_CON_MUX_MUX_CLK_AUD_CPU,
782 CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH,
783 CLK_CON_MUX_MUX_CLK_AUD_FM,
784 CLK_CON_MUX_MUX_CLK_AUD_UAIF0,
785 CLK_CON_MUX_MUX_CLK_AUD_UAIF1,
786 CLK_CON_MUX_MUX_CLK_AUD_UAIF2,
787 CLK_CON_MUX_MUX_CLK_AUD_UAIF3,
788 CLK_CON_MUX_MUX_CLK_AUD_UAIF4,
789 CLK_CON_MUX_MUX_CLK_AUD_UAIF5,
790 CLK_CON_MUX_MUX_CLK_AUD_UAIF6,
791 CLK_CON_DIV_DIV_CLK_AUD_MCLK,
792 CLK_CON_DIV_DIV_CLK_AUD_AUDIF,
793 CLK_CON_DIV_DIV_CLK_AUD_BUSD,
794 CLK_CON_DIV_DIV_CLK_AUD_BUSP,
795 CLK_CON_DIV_DIV_CLK_AUD_CNT,
796 CLK_CON_DIV_DIV_CLK_AUD_CPU,
797 CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK,
798 CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG,
799 CLK_CON_DIV_DIV_CLK_AUD_FM,
800 CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY,
801 CLK_CON_DIV_DIV_CLK_AUD_UAIF0,
802 CLK_CON_DIV_DIV_CLK_AUD_UAIF1,
803 CLK_CON_DIV_DIV_CLK_AUD_UAIF2,
804 CLK_CON_DIV_DIV_CLK_AUD_UAIF3,
805 CLK_CON_DIV_DIV_CLK_AUD_UAIF4,
806 CLK_CON_DIV_DIV_CLK_AUD_UAIF5,
807 CLK_CON_DIV_DIV_CLK_AUD_UAIF6,
808 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT,
809 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0,
810 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1,
811 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2,
812 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3,
813 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4,
814 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5,
815 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6,
816 CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK,
817 CLK_CON_GAT_GOUT_AUD_ABOX_ACLK,
818 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY,
819 CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB,
820 CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32,
821 CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP,
822 CLK_CON_GAT_GOUT_AUD_CODEC_MCLK,
823 CLK_CON_GAT_GOUT_AUD_TZPC_PCLK,
824 CLK_CON_GAT_GOUT_AUD_GPIO_PCLK,
825 CLK_CON_GAT_GOUT_AUD_PPMU_ACLK,
826 CLK_CON_GAT_GOUT_AUD_PPMU_PCLK,
827 CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1,
828 CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK,
829 CLK_CON_GAT_GOUT_AUD_WDT_PCLK,
830 };
831
832 /* List of parent clocks for Muxes in CMU_AUD */
833 PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll" };
834 PNAME(mout_aud_cpu_user_p) = { "oscclk", "dout_aud" };
835 PNAME(mout_aud_cpu_p) = { "dout_aud_cpu", "mout_aud_cpu_user" };
836 PNAME(mout_aud_cpu_hch_p) = { "mout_aud_cpu", "oscclk" };
837 PNAME(mout_aud_uaif0_p) = { "dout_aud_uaif0", "ioclk_audiocdclk0" };
838 PNAME(mout_aud_uaif1_p) = { "dout_aud_uaif1", "ioclk_audiocdclk1" };
839 PNAME(mout_aud_uaif2_p) = { "dout_aud_uaif2", "ioclk_audiocdclk2" };
840 PNAME(mout_aud_uaif3_p) = { "dout_aud_uaif3", "ioclk_audiocdclk3" };
841 PNAME(mout_aud_uaif4_p) = { "dout_aud_uaif4", "ioclk_audiocdclk4" };
842 PNAME(mout_aud_uaif5_p) = { "dout_aud_uaif5", "ioclk_audiocdclk5" };
843 PNAME(mout_aud_uaif6_p) = { "dout_aud_uaif6", "ioclk_audiocdclk6" };
844 PNAME(mout_aud_tick_usb_user_p) = { "oscclk", "tick_usb" };
845 PNAME(mout_aud_fm_p) = { "oscclk", "dout_aud_fm_spdy" };
846
847 /*
848 * Do not provide PLL table to PLL_AUD, as MANUAL_PLL_CTRL bit is not set
849 * for that PLL by default, so set_rate operation would fail.
850 */
851 static const struct samsung_pll_clock aud_pll_clks[] __initconst = {
852 PLL(pll_0831x, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk",
853 PLL_LOCKTIME_PLL_AUD, PLL_CON3_PLL_AUD, NULL),
854 };
855
856 static const struct samsung_fixed_rate_clock aud_fixed_clks[] __initconst = {
857 FRATE(IOCLK_AUDIOCDCLK0, "ioclk_audiocdclk0", NULL, 0, 25000000),
858 FRATE(IOCLK_AUDIOCDCLK1, "ioclk_audiocdclk1", NULL, 0, 25000000),
859 FRATE(IOCLK_AUDIOCDCLK2, "ioclk_audiocdclk2", NULL, 0, 25000000),
860 FRATE(IOCLK_AUDIOCDCLK3, "ioclk_audiocdclk3", NULL, 0, 25000000),
861 FRATE(IOCLK_AUDIOCDCLK4, "ioclk_audiocdclk4", NULL, 0, 25000000),
862 FRATE(IOCLK_AUDIOCDCLK5, "ioclk_audiocdclk5", NULL, 0, 25000000),
863 FRATE(IOCLK_AUDIOCDCLK6, "ioclk_audiocdclk6", NULL, 0, 25000000),
864 FRATE(TICK_USB, "tick_usb", NULL, 0, 60000000),
865 };
866
867 static const struct samsung_mux_clock aud_mux_clks[] __initconst = {
868 MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p,
869 PLL_CON0_PLL_AUD, 4, 1),
870 MUX(CLK_MOUT_AUD_CPU_USER, "mout_aud_cpu_user", mout_aud_cpu_user_p,
871 PLL_CON0_MUX_CLKCMU_AUD_CPU_USER, 4, 1),
872 MUX(CLK_MOUT_AUD_TICK_USB_USER, "mout_aud_tick_usb_user",
873 mout_aud_tick_usb_user_p,
874 PLL_CON0_MUX_TICK_USB_USER, 4, 1),
875 MUX(CLK_MOUT_AUD_CPU, "mout_aud_cpu", mout_aud_cpu_p,
876 CLK_CON_MUX_MUX_CLK_AUD_CPU, 0, 1),
877 MUX(CLK_MOUT_AUD_CPU_HCH, "mout_aud_cpu_hch", mout_aud_cpu_hch_p,
878 CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH, 0, 1),
879 MUX(CLK_MOUT_AUD_UAIF0, "mout_aud_uaif0", mout_aud_uaif0_p,
880 CLK_CON_MUX_MUX_CLK_AUD_UAIF0, 0, 1),
881 MUX(CLK_MOUT_AUD_UAIF1, "mout_aud_uaif1", mout_aud_uaif1_p,
882 CLK_CON_MUX_MUX_CLK_AUD_UAIF1, 0, 1),
883 MUX(CLK_MOUT_AUD_UAIF2, "mout_aud_uaif2", mout_aud_uaif2_p,
884 CLK_CON_MUX_MUX_CLK_AUD_UAIF2, 0, 1),
885 MUX(CLK_MOUT_AUD_UAIF3, "mout_aud_uaif3", mout_aud_uaif3_p,
886 CLK_CON_MUX_MUX_CLK_AUD_UAIF3, 0, 1),
887 MUX(CLK_MOUT_AUD_UAIF4, "mout_aud_uaif4", mout_aud_uaif4_p,
888 CLK_CON_MUX_MUX_CLK_AUD_UAIF4, 0, 1),
889 MUX(CLK_MOUT_AUD_UAIF5, "mout_aud_uaif5", mout_aud_uaif5_p,
890 CLK_CON_MUX_MUX_CLK_AUD_UAIF5, 0, 1),
891 MUX(CLK_MOUT_AUD_UAIF6, "mout_aud_uaif6", mout_aud_uaif6_p,
892 CLK_CON_MUX_MUX_CLK_AUD_UAIF6, 0, 1),
893 MUX(CLK_MOUT_AUD_FM, "mout_aud_fm", mout_aud_fm_p,
894 CLK_CON_MUX_MUX_CLK_AUD_FM, 0, 1),
895 };
896
897 static const struct samsung_div_clock aud_div_clks[] __initconst = {
898 DIV(CLK_DOUT_AUD_CPU, "dout_aud_cpu", "mout_aud_pll",
899 CLK_CON_DIV_DIV_CLK_AUD_CPU, 0, 4),
900 DIV(CLK_DOUT_AUD_BUSD, "dout_aud_busd", "mout_aud_pll",
901 CLK_CON_DIV_DIV_CLK_AUD_BUSD, 0, 4),
902 DIV(CLK_DOUT_AUD_BUSP, "dout_aud_busp", "mout_aud_pll",
903 CLK_CON_DIV_DIV_CLK_AUD_BUSP, 0, 4),
904 DIV(CLK_DOUT_AUD_AUDIF, "dout_aud_audif", "mout_aud_pll",
905 CLK_CON_DIV_DIV_CLK_AUD_AUDIF, 0, 9),
906 DIV(CLK_DOUT_AUD_CPU_ACLK, "dout_aud_cpu_aclk", "mout_aud_cpu_hch",
907 CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK, 0, 3),
908 DIV(CLK_DOUT_AUD_CPU_PCLKDBG, "dout_aud_cpu_pclkdbg",
909 "mout_aud_cpu_hch",
910 CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG, 0, 3),
911 DIV(CLK_DOUT_AUD_MCLK, "dout_aud_mclk", "dout_aud_audif",
912 CLK_CON_DIV_DIV_CLK_AUD_MCLK, 0, 2),
913 DIV(CLK_DOUT_AUD_CNT, "dout_aud_cnt", "dout_aud_audif",
914 CLK_CON_DIV_DIV_CLK_AUD_CNT, 0, 10),
915 DIV(CLK_DOUT_AUD_UAIF0, "dout_aud_uaif0", "dout_aud_audif",
916 CLK_CON_DIV_DIV_CLK_AUD_UAIF0, 0, 10),
917 DIV(CLK_DOUT_AUD_UAIF1, "dout_aud_uaif1", "dout_aud_audif",
918 CLK_CON_DIV_DIV_CLK_AUD_UAIF1, 0, 10),
919 DIV(CLK_DOUT_AUD_UAIF2, "dout_aud_uaif2", "dout_aud_audif",
920 CLK_CON_DIV_DIV_CLK_AUD_UAIF2, 0, 10),
921 DIV(CLK_DOUT_AUD_UAIF3, "dout_aud_uaif3", "dout_aud_audif",
922 CLK_CON_DIV_DIV_CLK_AUD_UAIF3, 0, 10),
923 DIV(CLK_DOUT_AUD_UAIF4, "dout_aud_uaif4", "dout_aud_audif",
924 CLK_CON_DIV_DIV_CLK_AUD_UAIF4, 0, 10),
925 DIV(CLK_DOUT_AUD_UAIF5, "dout_aud_uaif5", "dout_aud_audif",
926 CLK_CON_DIV_DIV_CLK_AUD_UAIF5, 0, 10),
927 DIV(CLK_DOUT_AUD_UAIF6, "dout_aud_uaif6", "dout_aud_audif",
928 CLK_CON_DIV_DIV_CLK_AUD_UAIF6, 0, 10),
929 DIV(CLK_DOUT_AUD_FM_SPDY, "dout_aud_fm_spdy", "mout_aud_tick_usb_user",
930 CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY, 0, 1),
931 DIV(CLK_DOUT_AUD_FM, "dout_aud_fm", "mout_aud_fm",
932 CLK_CON_DIV_DIV_CLK_AUD_FM, 0, 10),
933 };
934
935 static const struct samsung_gate_clock aud_gate_clks[] __initconst = {
936 GATE(CLK_GOUT_AUD_CMU_AUD_PCLK, "gout_aud_cmu_aud_pclk",
937 "dout_aud_busd",
938 CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK, 21, CLK_IGNORE_UNUSED, 0),
939 GATE(CLK_GOUT_AUD_CA32_CCLK, "gout_aud_ca32_cclk", "mout_aud_cpu_hch",
940 CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32, 21, 0, 0),
941 GATE(CLK_GOUT_AUD_ASB_CCLK, "gout_aud_asb_cclk", "dout_aud_cpu_aclk",
942 CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB, 21, 0, 0),
943 GATE(CLK_GOUT_AUD_DAP_CCLK, "gout_aud_dap_cclk", "dout_aud_cpu_pclkdbg",
944 CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP, 21, 0, 0),
945 /* TODO: Should be enabled in ABOX driver (or made CLK_IS_CRITICAL) */
946 GATE(CLK_GOUT_AUD_ABOX_ACLK, "gout_aud_abox_aclk", "dout_aud_busd",
947 CLK_CON_GAT_GOUT_AUD_ABOX_ACLK, 21, CLK_IGNORE_UNUSED, 0),
948 GATE(CLK_GOUT_AUD_GPIO_PCLK, "gout_aud_gpio_pclk", "dout_aud_busd",
949 CLK_CON_GAT_GOUT_AUD_GPIO_PCLK, 21, 0, 0),
950 GATE(CLK_GOUT_AUD_PPMU_ACLK, "gout_aud_ppmu_aclk", "dout_aud_busd",
951 CLK_CON_GAT_GOUT_AUD_PPMU_ACLK, 21, 0, 0),
952 GATE(CLK_GOUT_AUD_PPMU_PCLK, "gout_aud_ppmu_pclk", "dout_aud_busd",
953 CLK_CON_GAT_GOUT_AUD_PPMU_PCLK, 21, 0, 0),
954 GATE(CLK_GOUT_AUD_SYSMMU_CLK, "gout_aud_sysmmu_clk", "dout_aud_busd",
955 CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1, 21, 0, 0),
956 GATE(CLK_GOUT_AUD_SYSREG_PCLK, "gout_aud_sysreg_pclk", "dout_aud_busd",
957 CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK, 21, 0, 0),
958 GATE(CLK_GOUT_AUD_WDT_PCLK, "gout_aud_wdt_pclk", "dout_aud_busd",
959 CLK_CON_GAT_GOUT_AUD_WDT_PCLK, 21, 0, 0),
960 GATE(CLK_GOUT_AUD_TZPC_PCLK, "gout_aud_tzpc_pclk", "dout_aud_busp",
961 CLK_CON_GAT_GOUT_AUD_TZPC_PCLK, 21, 0, 0),
962 GATE(CLK_GOUT_AUD_CODEC_MCLK, "gout_aud_codec_mclk", "dout_aud_mclk",
963 CLK_CON_GAT_GOUT_AUD_CODEC_MCLK, 21, 0, 0),
964 GATE(CLK_GOUT_AUD_CNT_BCLK, "gout_aud_cnt_bclk", "dout_aud_cnt",
965 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT, 21, 0, 0),
966 GATE(CLK_GOUT_AUD_UAIF0_BCLK, "gout_aud_uaif0_bclk", "mout_aud_uaif0",
967 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0, 21, 0, 0),
968 GATE(CLK_GOUT_AUD_UAIF1_BCLK, "gout_aud_uaif1_bclk", "mout_aud_uaif1",
969 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1, 21, 0, 0),
970 GATE(CLK_GOUT_AUD_UAIF2_BCLK, "gout_aud_uaif2_bclk", "mout_aud_uaif2",
971 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2, 21, 0, 0),
972 GATE(CLK_GOUT_AUD_UAIF3_BCLK, "gout_aud_uaif3_bclk", "mout_aud_uaif3",
973 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3, 21, 0, 0),
974 GATE(CLK_GOUT_AUD_UAIF4_BCLK, "gout_aud_uaif4_bclk", "mout_aud_uaif4",
975 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4, 21, 0, 0),
976 GATE(CLK_GOUT_AUD_UAIF5_BCLK, "gout_aud_uaif5_bclk", "mout_aud_uaif5",
977 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5, 21, 0, 0),
978 GATE(CLK_GOUT_AUD_UAIF6_BCLK, "gout_aud_uaif6_bclk", "mout_aud_uaif6",
979 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6, 21, 0, 0),
980 GATE(CLK_GOUT_AUD_SPDY_BCLK, "gout_aud_spdy_bclk", "dout_aud_fm",
981 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY, 21, 0, 0),
982 };
983
984 static const struct samsung_cmu_info aud_cmu_info __initconst = {
985 .pll_clks = aud_pll_clks,
986 .nr_pll_clks = ARRAY_SIZE(aud_pll_clks),
987 .mux_clks = aud_mux_clks,
988 .nr_mux_clks = ARRAY_SIZE(aud_mux_clks),
989 .div_clks = aud_div_clks,
990 .nr_div_clks = ARRAY_SIZE(aud_div_clks),
991 .gate_clks = aud_gate_clks,
992 .nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
993 .fixed_clks = aud_fixed_clks,
994 .nr_fixed_clks = ARRAY_SIZE(aud_fixed_clks),
995 .nr_clk_ids = CLKS_NR_AUD,
996 .clk_regs = aud_clk_regs,
997 .nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
998 .clk_name = "dout_aud",
999 };
1000
1001 /* ---- CMU_CMGP ------------------------------------------------------------ */
1002
1003 /* Register Offset definitions for CMU_CMGP (0x11c00000) */
1004 #define CLK_CON_MUX_CLK_CMGP_ADC 0x1000
1005 #define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0 0x1004
1006 #define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1 0x1008
1007 #define CLK_CON_DIV_DIV_CLK_CMGP_ADC 0x1800
1008 #define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0 0x1804
1009 #define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1 0x1808
1010 #define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0 0x200c
1011 #define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1 0x2010
1012 #define CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK 0x2018
1013 #define CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK 0x2040
1014 #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK 0x2044
1015 #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK 0x2048
1016 #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK 0x204c
1017 #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK 0x2050
1018
1019 static const unsigned long cmgp_clk_regs[] __initconst = {
1020 CLK_CON_MUX_CLK_CMGP_ADC,
1021 CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0,
1022 CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1,
1023 CLK_CON_DIV_DIV_CLK_CMGP_ADC,
1024 CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0,
1025 CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1,
1026 CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0,
1027 CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1,
1028 CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK,
1029 CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK,
1030 CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK,
1031 CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK,
1032 CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK,
1033 CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK,
1034 };
1035
1036 /* List of parent clocks for Muxes in CMU_CMGP */
1037 PNAME(mout_cmgp_usi0_p) = { "clk_rco_cmgp", "gout_clkcmu_cmgp_bus" };
1038 PNAME(mout_cmgp_usi1_p) = { "clk_rco_cmgp", "gout_clkcmu_cmgp_bus" };
1039 PNAME(mout_cmgp_adc_p) = { "oscclk", "dout_cmgp_adc" };
1040
1041 static const struct samsung_fixed_rate_clock cmgp_fixed_clks[] __initconst = {
1042 FRATE(CLK_RCO_CMGP, "clk_rco_cmgp", NULL, 0, 49152000),
1043 };
1044
1045 static const struct samsung_mux_clock cmgp_mux_clks[] __initconst = {
1046 MUX(CLK_MOUT_CMGP_ADC, "mout_cmgp_adc", mout_cmgp_adc_p,
1047 CLK_CON_MUX_CLK_CMGP_ADC, 0, 1),
1048 MUX_F(CLK_MOUT_CMGP_USI0, "mout_cmgp_usi0", mout_cmgp_usi0_p,
1049 CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0, 0, 1, CLK_SET_RATE_PARENT, 0),
1050 MUX_F(CLK_MOUT_CMGP_USI1, "mout_cmgp_usi1", mout_cmgp_usi1_p,
1051 CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1, 0, 1, CLK_SET_RATE_PARENT, 0),
1052 };
1053
1054 static const struct samsung_div_clock cmgp_div_clks[] __initconst = {
1055 DIV(CLK_DOUT_CMGP_ADC, "dout_cmgp_adc", "gout_clkcmu_cmgp_bus",
1056 CLK_CON_DIV_DIV_CLK_CMGP_ADC, 0, 4),
1057 DIV_F(CLK_DOUT_CMGP_USI0, "dout_cmgp_usi0", "mout_cmgp_usi0",
1058 CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0, 0, 5, CLK_SET_RATE_PARENT, 0),
1059 DIV_F(CLK_DOUT_CMGP_USI1, "dout_cmgp_usi1", "mout_cmgp_usi1",
1060 CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1, 0, 5, CLK_SET_RATE_PARENT, 0),
1061 };
1062
1063 static const struct samsung_gate_clock cmgp_gate_clks[] __initconst = {
1064 GATE(CLK_GOUT_CMGP_ADC_S0_PCLK, "gout_adc_s0_pclk",
1065 "gout_clkcmu_cmgp_bus",
1066 CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0, 21, 0, 0),
1067 GATE(CLK_GOUT_CMGP_ADC_S1_PCLK, "gout_adc_s1_pclk",
1068 "gout_clkcmu_cmgp_bus",
1069 CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1, 21, 0, 0),
1070 /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
1071 GATE(CLK_GOUT_CMGP_GPIO_PCLK, "gout_gpio_cmgp_pclk",
1072 "gout_clkcmu_cmgp_bus",
1073 CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1074 GATE(CLK_GOUT_CMGP_USI0_IPCLK, "gout_cmgp_usi0_ipclk", "dout_cmgp_usi0",
1075 CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK, 21, CLK_SET_RATE_PARENT, 0),
1076 GATE(CLK_GOUT_CMGP_USI0_PCLK, "gout_cmgp_usi0_pclk",
1077 "gout_clkcmu_cmgp_bus",
1078 CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK, 21, 0, 0),
1079 GATE(CLK_GOUT_CMGP_USI1_IPCLK, "gout_cmgp_usi1_ipclk", "dout_cmgp_usi1",
1080 CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK, 21, CLK_SET_RATE_PARENT, 0),
1081 GATE(CLK_GOUT_CMGP_USI1_PCLK, "gout_cmgp_usi1_pclk",
1082 "gout_clkcmu_cmgp_bus",
1083 CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK, 21, 0, 0),
1084 GATE(CLK_GOUT_SYSREG_CMGP_PCLK, "gout_sysreg_cmgp_pclk",
1085 "gout_clkcmu_cmgp_bus",
1086 CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK, 21, 0, 0),
1087 };
1088
1089 static const struct samsung_cmu_info cmgp_cmu_info __initconst = {
1090 .mux_clks = cmgp_mux_clks,
1091 .nr_mux_clks = ARRAY_SIZE(cmgp_mux_clks),
1092 .div_clks = cmgp_div_clks,
1093 .nr_div_clks = ARRAY_SIZE(cmgp_div_clks),
1094 .gate_clks = cmgp_gate_clks,
1095 .nr_gate_clks = ARRAY_SIZE(cmgp_gate_clks),
1096 .fixed_clks = cmgp_fixed_clks,
1097 .nr_fixed_clks = ARRAY_SIZE(cmgp_fixed_clks),
1098 .nr_clk_ids = CLKS_NR_CMGP,
1099 .clk_regs = cmgp_clk_regs,
1100 .nr_clk_regs = ARRAY_SIZE(cmgp_clk_regs),
1101 .clk_name = "gout_clkcmu_cmgp_bus",
1102 };
1103
1104 /* ---- CMU_CPUCL0 ---------------------------------------------------------- */
1105
1106 /* Register Offset definitions for CMU_CPUCL0 (0x10900000) */
1107 #define PLL_LOCKTIME_PLL_CPUCL0 0x0000
1108 #define PLL_CON0_PLL_CPUCL0 0x0100
1109 #define PLL_CON1_PLL_CPUCL0 0x0104
1110 #define PLL_CON3_PLL_CPUCL0 0x010c
1111 #define PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER 0x0600
1112 #define PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER 0x0610
1113 #define CLK_CON_MUX_MUX_CLK_CPUCL0_PLL 0x100c
1114 #define CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK 0x1800
1115 #define CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK 0x1808
1116 #define CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG 0x180c
1117 #define CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK 0x1810
1118 #define CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF 0x1814
1119 #define CLK_CON_DIV_DIV_CLK_CPUCL0_CPU 0x1818
1120 #define CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK 0x181c
1121 #define CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_ATCLK 0x2000
1122 #define CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_PCLK 0x2004
1123 #define CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_PERIPHCLK 0x2008
1124 #define CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_SCLK 0x200c
1125 #define CLK_CON_GAT_CLK_CPUCL0_CMU_CPUCL0_PCLK 0x2010
1126 #define CLK_CON_GAT_GATE_CLK_CPUCL0_CPU 0x2020
1127
1128 static const unsigned long cpucl0_clk_regs[] __initconst = {
1129 PLL_LOCKTIME_PLL_CPUCL0,
1130 PLL_CON0_PLL_CPUCL0,
1131 PLL_CON1_PLL_CPUCL0,
1132 PLL_CON3_PLL_CPUCL0,
1133 PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER,
1134 PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER,
1135 CLK_CON_MUX_MUX_CLK_CPUCL0_PLL,
1136 CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK,
1137 CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK,
1138 CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG,
1139 CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK,
1140 CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF,
1141 CLK_CON_DIV_DIV_CLK_CPUCL0_CPU,
1142 CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK,
1143 CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_ATCLK,
1144 CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_PCLK,
1145 CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_PERIPHCLK,
1146 CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_SCLK,
1147 CLK_CON_GAT_CLK_CPUCL0_CMU_CPUCL0_PCLK,
1148 CLK_CON_GAT_GATE_CLK_CPUCL0_CPU,
1149 };
1150
1151 /* List of parent clocks for Muxes in CMU_CPUCL0 */
1152 PNAME(mout_pll_cpucl0_p) = { "oscclk", "fout_cpucl0_pll" };
1153 PNAME(mout_cpucl0_switch_user_p) = { "oscclk", "dout_cpucl0_switch" };
1154 PNAME(mout_cpucl0_dbg_user_p) = { "oscclk", "dout_cpucl0_dbg" };
1155 PNAME(mout_cpucl0_pll_p) = { "mout_pll_cpucl0",
1156 "mout_cpucl0_switch_user" };
1157
1158 static const struct samsung_pll_rate_table cpu_pll_rates[] __initconst = {
1159 PLL_35XX_RATE(26 * MHZ, 2210000000U, 255, 3, 0),
1160 PLL_35XX_RATE(26 * MHZ, 2106000000U, 243, 3, 0),
1161 PLL_35XX_RATE(26 * MHZ, 2002000000U, 231, 3, 0),
1162 PLL_35XX_RATE(26 * MHZ, 1846000000U, 213, 3, 0),
1163 PLL_35XX_RATE(26 * MHZ, 1742000000U, 201, 3, 0),
1164 PLL_35XX_RATE(26 * MHZ, 1586000000U, 183, 3, 0),
1165 PLL_35XX_RATE(26 * MHZ, 1456000000U, 168, 3, 0),
1166 PLL_35XX_RATE(26 * MHZ, 1300000000U, 150, 3, 0),
1167 PLL_35XX_RATE(26 * MHZ, 1157000000U, 267, 3, 1),
1168 PLL_35XX_RATE(26 * MHZ, 1053000000U, 243, 3, 1),
1169 PLL_35XX_RATE(26 * MHZ, 949000000U, 219, 3, 1),
1170 PLL_35XX_RATE(26 * MHZ, 806000000U, 186, 3, 1),
1171 PLL_35XX_RATE(26 * MHZ, 650000000U, 150, 3, 1),
1172 PLL_35XX_RATE(26 * MHZ, 546000000U, 252, 3, 2),
1173 PLL_35XX_RATE(26 * MHZ, 442000000U, 204, 3, 2),
1174 PLL_35XX_RATE(26 * MHZ, 351000000U, 162, 3, 2),
1175 PLL_35XX_RATE(26 * MHZ, 247000000U, 114, 3, 2),
1176 PLL_35XX_RATE(26 * MHZ, 182000000U, 168, 3, 3),
1177 PLL_35XX_RATE(26 * MHZ, 130000000U, 120, 3, 3),
1178 };
1179
1180 static const struct samsung_pll_clock cpucl0_pll_clks[] __initconst = {
1181 PLL(pll_0822x, CLK_FOUT_CPUCL0_PLL, "fout_cpucl0_pll", "oscclk",
1182 PLL_LOCKTIME_PLL_CPUCL0, PLL_CON3_PLL_CPUCL0, cpu_pll_rates),
1183 };
1184
1185 static const struct samsung_mux_clock cpucl0_mux_clks[] __initconst = {
1186 MUX_F(CLK_MOUT_PLL_CPUCL0, "mout_pll_cpucl0", mout_pll_cpucl0_p,
1187 PLL_CON0_PLL_CPUCL0, 4, 1,
1188 CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
1189 MUX_F(CLK_MOUT_CPUCL0_SWITCH_USER, "mout_cpucl0_switch_user",
1190 mout_cpucl0_switch_user_p,
1191 PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER, 4, 1,
1192 CLK_SET_RATE_PARENT, 0),
1193 MUX(CLK_MOUT_CPUCL0_DBG_USER, "mout_cpucl0_dbg_user",
1194 mout_cpucl0_dbg_user_p,
1195 PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER, 4, 1),
1196 MUX_F(CLK_MOUT_CPUCL0_PLL, "mout_cpucl0_pll", mout_cpucl0_pll_p,
1197 CLK_CON_MUX_MUX_CLK_CPUCL0_PLL, 0, 1, CLK_SET_RATE_PARENT, 0),
1198 };
1199
1200 static const struct samsung_div_clock cpucl0_div_clks[] __initconst = {
1201 DIV_F(CLK_DOUT_CPUCL0_CPU, "dout_cpucl0_cpu", "mout_cpucl0_pll",
1202 CLK_CON_DIV_DIV_CLK_CPUCL0_CPU, 0, 1,
1203 CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
1204 DIV_F(CLK_DOUT_CPUCL0_CMUREF, "dout_cpucl0_cmuref", "dout_cpucl0_cpu",
1205 CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF, 0, 3,
1206 CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
1207 DIV_F(CLK_DOUT_CPUCL0_PCLK, "dout_cpucl0_pclk", "dout_cpucl0_cpu",
1208 CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK, 0, 4,
1209 CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
1210
1211 /* EMBEDDED_CMU_CPUCL0 */
1212 DIV_F(CLK_DOUT_CLUSTER0_ACLK, "dout_cluster0_aclk", "gout_cluster0_cpu",
1213 CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK, 0, 4,
1214 CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
1215 DIV_F(CLK_DOUT_CLUSTER0_ATCLK, "dout_cluster0_atclk",
1216 "gout_cluster0_cpu", CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK, 0, 4,
1217 CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
1218 DIV_F(CLK_DOUT_CLUSTER0_PCLKDBG, "dout_cluster0_pclkdbg",
1219 "gout_cluster0_cpu", CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG, 0, 4,
1220 CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
1221 DIV_F(CLK_DOUT_CLUSTER0_PERIPHCLK, "dout_cluster0_periphclk",
1222 "gout_cluster0_cpu", CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK, 0, 4,
1223 CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
1224 };
1225
1226 static const struct samsung_gate_clock cpucl0_gate_clks[] __initconst = {
1227 GATE(CLK_GOUT_CPUCL0_CMU_CPUCL0_PCLK, "gout_cpucl0_cmu_cpucl0_pclk",
1228 "dout_cpucl0_pclk",
1229 CLK_CON_GAT_CLK_CPUCL0_CMU_CPUCL0_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1230
1231 /* EMBEDDED_CMU_CPUCL0 */
1232 GATE(CLK_GOUT_CLUSTER0_CPU, "gout_cluster0_cpu", "dout_cpucl0_cpu",
1233 CLK_CON_GAT_GATE_CLK_CPUCL0_CPU, 21, CLK_IGNORE_UNUSED, 0),
1234 GATE(CLK_GOUT_CLUSTER0_SCLK, "gout_cluster0_sclk", "gout_cluster0_cpu",
1235 CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_SCLK, 21, CLK_IGNORE_UNUSED, 0),
1236 GATE(CLK_GOUT_CLUSTER0_ATCLK, "gout_cluster0_atclk",
1237 "dout_cluster0_atclk",
1238 CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_ATCLK, 21, CLK_IGNORE_UNUSED, 0),
1239 GATE(CLK_GOUT_CLUSTER0_PERIPHCLK, "gout_cluster0_periphclk",
1240 "dout_cluster0_periphclk",
1241 CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_PERIPHCLK, 21,
1242 CLK_IGNORE_UNUSED, 0),
1243 GATE(CLK_GOUT_CLUSTER0_PCLK, "gout_cluster0_pclk",
1244 "dout_cluster0_pclkdbg",
1245 CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1246 };
1247
1248 /*
1249 * Each parameter is going to be written into the corresponding DIV register. So
1250 * the actual divider value for each parameter will be 1/(param+1). All these
1251 * parameters must be in the range of 0..15, as the divider range for all of
1252 * these DIV clocks is 1..16. The default values for these dividers is
1253 * (1, 3, 3, 1).
1254 */
1255 #define E850_CPU_DIV0(aclk, atclk, pclkdbg, periphclk) \
1256 (((aclk) << 16) | ((atclk) << 12) | ((pclkdbg) << 8) | \
1257 ((periphclk) << 4))
1258
1259 static const struct exynos_cpuclk_cfg_data exynos850_cluster_clk_d[] __initconst
1260 = {
1261 { 2210000, E850_CPU_DIV0(1, 3, 3, 1) },
1262 { 2106000, E850_CPU_DIV0(1, 3, 3, 1) },
1263 { 2002000, E850_CPU_DIV0(1, 3, 3, 1) },
1264 { 1846000, E850_CPU_DIV0(1, 3, 3, 1) },
1265 { 1742000, E850_CPU_DIV0(1, 3, 3, 1) },
1266 { 1586000, E850_CPU_DIV0(1, 3, 3, 1) },
1267 { 1456000, E850_CPU_DIV0(1, 3, 3, 1) },
1268 { 1300000, E850_CPU_DIV0(1, 3, 3, 1) },
1269 { 1157000, E850_CPU_DIV0(1, 3, 3, 1) },
1270 { 1053000, E850_CPU_DIV0(1, 3, 3, 1) },
1271 { 949000, E850_CPU_DIV0(1, 3, 3, 1) },
1272 { 806000, E850_CPU_DIV0(1, 3, 3, 1) },
1273 { 650000, E850_CPU_DIV0(1, 3, 3, 1) },
1274 { 546000, E850_CPU_DIV0(1, 3, 3, 1) },
1275 { 442000, E850_CPU_DIV0(1, 3, 3, 1) },
1276 { 351000, E850_CPU_DIV0(1, 3, 3, 1) },
1277 { 247000, E850_CPU_DIV0(1, 3, 3, 1) },
1278 { 182000, E850_CPU_DIV0(1, 3, 3, 1) },
1279 { 130000, E850_CPU_DIV0(1, 3, 3, 1) },
1280 { 0 }
1281 };
1282
1283 static const struct samsung_cpu_clock cpucl0_cpu_clks[] __initconst = {
1284 CPU_CLK(CLK_CLUSTER0_SCLK, "cluster0_clk", CLK_MOUT_PLL_CPUCL0,
1285 CLK_MOUT_CPUCL0_SWITCH_USER, 0, 0x0, CPUCLK_LAYOUT_E850_CL0,
1286 exynos850_cluster_clk_d),
1287 };
1288
1289 static const struct samsung_cmu_info cpucl0_cmu_info __initconst = {
1290 .pll_clks = cpucl0_pll_clks,
1291 .nr_pll_clks = ARRAY_SIZE(cpucl0_pll_clks),
1292 .mux_clks = cpucl0_mux_clks,
1293 .nr_mux_clks = ARRAY_SIZE(cpucl0_mux_clks),
1294 .div_clks = cpucl0_div_clks,
1295 .nr_div_clks = ARRAY_SIZE(cpucl0_div_clks),
1296 .gate_clks = cpucl0_gate_clks,
1297 .nr_gate_clks = ARRAY_SIZE(cpucl0_gate_clks),
1298 .cpu_clks = cpucl0_cpu_clks,
1299 .nr_cpu_clks = ARRAY_SIZE(cpucl0_cpu_clks),
1300 .nr_clk_ids = CLKS_NR_CPUCL0,
1301 .clk_regs = cpucl0_clk_regs,
1302 .nr_clk_regs = ARRAY_SIZE(cpucl0_clk_regs),
1303 .clk_name = "dout_cpucl0_switch",
1304 .manual_plls = true,
1305 };
1306
exynos850_cmu_cpucl0_init(struct device_node * np)1307 static void __init exynos850_cmu_cpucl0_init(struct device_node *np)
1308 {
1309 exynos_arm64_register_cmu(NULL, np, &cpucl0_cmu_info);
1310 }
1311
1312 /* Register CMU_CPUCL0 early, as CPU clocks should be available ASAP */
1313 CLK_OF_DECLARE(exynos850_cmu_cpucl0, "samsung,exynos850-cmu-cpucl0",
1314 exynos850_cmu_cpucl0_init);
1315
1316 /* ---- CMU_CPUCL1 ---------------------------------------------------------- */
1317
1318 /* Register Offset definitions for CMU_CPUCL1 (0x10800000) */
1319 #define PLL_LOCKTIME_PLL_CPUCL1 0x0000
1320 #define PLL_CON0_PLL_CPUCL1 0x0100
1321 #define PLL_CON1_PLL_CPUCL1 0x0104
1322 #define PLL_CON3_PLL_CPUCL1 0x010c
1323 #define PLL_CON0_MUX_CLKCMU_CPUCL1_DBG_USER 0x0600
1324 #define PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER 0x0610
1325 #define CLK_CON_MUX_MUX_CLK_CPUCL1_PLL 0x1000
1326 #define CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK 0x1800
1327 #define CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK 0x1808
1328 #define CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLKDBG 0x180c
1329 #define CLK_CON_DIV_DIV_CLK_CLUSTER1_PERIPHCLK 0x1810
1330 #define CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF 0x1814
1331 #define CLK_CON_DIV_DIV_CLK_CPUCL1_CPU 0x1818
1332 #define CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK 0x181c
1333 #define CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_ATCLK 0x2000
1334 #define CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_PCLK 0x2004
1335 #define CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_PERIPHCLK 0x2008
1336 #define CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_SCLK 0x200c
1337 #define CLK_CON_GAT_CLK_CPUCL1_CMU_CPUCL1_PCLK 0x2010
1338 #define CLK_CON_GAT_GATE_CLK_CPUCL1_CPU 0x2020
1339
1340 static const unsigned long cpucl1_clk_regs[] __initconst = {
1341 PLL_LOCKTIME_PLL_CPUCL1,
1342 PLL_CON0_PLL_CPUCL1,
1343 PLL_CON1_PLL_CPUCL1,
1344 PLL_CON3_PLL_CPUCL1,
1345 PLL_CON0_MUX_CLKCMU_CPUCL1_DBG_USER,
1346 PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER,
1347 CLK_CON_MUX_MUX_CLK_CPUCL1_PLL,
1348 CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK,
1349 CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK,
1350 CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLKDBG,
1351 CLK_CON_DIV_DIV_CLK_CLUSTER1_PERIPHCLK,
1352 CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF,
1353 CLK_CON_DIV_DIV_CLK_CPUCL1_CPU,
1354 CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK,
1355 CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_ATCLK,
1356 CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_PCLK,
1357 CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_PERIPHCLK,
1358 CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_SCLK,
1359 CLK_CON_GAT_CLK_CPUCL1_CMU_CPUCL1_PCLK,
1360 CLK_CON_GAT_GATE_CLK_CPUCL1_CPU,
1361 };
1362
1363 /* List of parent clocks for Muxes in CMU_CPUCL0 */
1364 PNAME(mout_pll_cpucl1_p) = { "oscclk", "fout_cpucl1_pll" };
1365 PNAME(mout_cpucl1_switch_user_p) = { "oscclk", "dout_cpucl1_switch" };
1366 PNAME(mout_cpucl1_dbg_user_p) = { "oscclk", "dout_cpucl1_dbg" };
1367 PNAME(mout_cpucl1_pll_p) = { "mout_pll_cpucl1",
1368 "mout_cpucl1_switch_user" };
1369
1370 static const struct samsung_pll_clock cpucl1_pll_clks[] __initconst = {
1371 PLL(pll_0822x, CLK_FOUT_CPUCL1_PLL, "fout_cpucl1_pll", "oscclk",
1372 PLL_LOCKTIME_PLL_CPUCL1, PLL_CON3_PLL_CPUCL1, cpu_pll_rates),
1373 };
1374
1375 static const struct samsung_mux_clock cpucl1_mux_clks[] __initconst = {
1376 MUX_F(CLK_MOUT_PLL_CPUCL1, "mout_pll_cpucl1", mout_pll_cpucl1_p,
1377 PLL_CON0_PLL_CPUCL1, 4, 1,
1378 CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
1379 MUX_F(CLK_MOUT_CPUCL1_SWITCH_USER, "mout_cpucl1_switch_user",
1380 mout_cpucl1_switch_user_p,
1381 PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER, 4, 1,
1382 CLK_SET_RATE_PARENT, 0),
1383 MUX(CLK_MOUT_CPUCL1_DBG_USER, "mout_cpucl1_dbg_user",
1384 mout_cpucl1_dbg_user_p,
1385 PLL_CON0_MUX_CLKCMU_CPUCL1_DBG_USER, 4, 1),
1386 MUX_F(CLK_MOUT_CPUCL1_PLL, "mout_cpucl1_pll", mout_cpucl1_pll_p,
1387 CLK_CON_MUX_MUX_CLK_CPUCL1_PLL, 0, 1, CLK_SET_RATE_PARENT, 0),
1388 };
1389
1390 static const struct samsung_div_clock cpucl1_div_clks[] __initconst = {
1391 DIV_F(CLK_DOUT_CPUCL1_CPU, "dout_cpucl1_cpu", "mout_cpucl1_pll",
1392 CLK_CON_DIV_DIV_CLK_CPUCL1_CPU, 0, 1,
1393 CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
1394 DIV_F(CLK_DOUT_CPUCL1_CMUREF, "dout_cpucl1_cmuref", "dout_cpucl1_cpu",
1395 CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF, 0, 3,
1396 CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
1397 DIV_F(CLK_DOUT_CPUCL1_PCLK, "dout_cpucl1_pclk", "dout_cpucl1_cpu",
1398 CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK, 0, 4,
1399 CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
1400
1401 /* EMBEDDED_CMU_CPUCL1 */
1402 DIV_F(CLK_DOUT_CLUSTER1_ACLK, "dout_cluster1_aclk", "gout_cluster1_cpu",
1403 CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK, 0, 4,
1404 CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
1405 DIV_F(CLK_DOUT_CLUSTER1_ATCLK, "dout_cluster1_atclk",
1406 "gout_cluster1_cpu", CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK, 0, 4,
1407 CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
1408 DIV_F(CLK_DOUT_CLUSTER1_PCLKDBG, "dout_cluster1_pclkdbg",
1409 "gout_cluster1_cpu", CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLKDBG, 0, 4,
1410 CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
1411 DIV_F(CLK_DOUT_CLUSTER1_PERIPHCLK, "dout_cluster1_periphclk",
1412 "gout_cluster1_cpu", CLK_CON_DIV_DIV_CLK_CLUSTER1_PERIPHCLK, 0, 4,
1413 CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
1414 };
1415
1416 static const struct samsung_gate_clock cpucl1_gate_clks[] __initconst = {
1417 GATE(CLK_GOUT_CPUCL1_CMU_CPUCL1_PCLK, "gout_cpucl1_cmu_cpucl1_pclk",
1418 "dout_cpucl1_pclk",
1419 CLK_CON_GAT_CLK_CPUCL1_CMU_CPUCL1_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1420
1421 /* EMBEDDED_CMU_CPUCL1 */
1422 GATE(CLK_GOUT_CLUSTER1_CPU, "gout_cluster1_cpu", "dout_cpucl1_cpu",
1423 CLK_CON_GAT_GATE_CLK_CPUCL1_CPU, 21, CLK_IGNORE_UNUSED, 0),
1424 GATE(CLK_GOUT_CLUSTER1_SCLK, "gout_cluster1_sclk", "gout_cluster1_cpu",
1425 CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_SCLK, 21, CLK_IGNORE_UNUSED, 0),
1426 GATE(CLK_GOUT_CLUSTER1_ATCLK, "gout_cluster1_atclk",
1427 "dout_cluster1_atclk",
1428 CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_ATCLK, 21, CLK_IGNORE_UNUSED, 0),
1429 GATE(CLK_GOUT_CLUSTER1_PERIPHCLK, "gout_cluster1_periphclk",
1430 "dout_cluster1_periphclk",
1431 CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_PERIPHCLK, 21,
1432 CLK_IGNORE_UNUSED, 0),
1433 GATE(CLK_GOUT_CLUSTER1_PCLK, "gout_cluster1_pclk",
1434 "dout_cluster1_pclkdbg",
1435 CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1436 };
1437
1438 static const struct samsung_cpu_clock cpucl1_cpu_clks[] __initconst = {
1439 CPU_CLK(CLK_CLUSTER1_SCLK, "cluster1_clk", CLK_MOUT_PLL_CPUCL1,
1440 CLK_MOUT_CPUCL1_SWITCH_USER, 0, 0x0, CPUCLK_LAYOUT_E850_CL1,
1441 exynos850_cluster_clk_d),
1442 };
1443
1444 static const struct samsung_cmu_info cpucl1_cmu_info __initconst = {
1445 .pll_clks = cpucl1_pll_clks,
1446 .nr_pll_clks = ARRAY_SIZE(cpucl1_pll_clks),
1447 .mux_clks = cpucl1_mux_clks,
1448 .nr_mux_clks = ARRAY_SIZE(cpucl1_mux_clks),
1449 .div_clks = cpucl1_div_clks,
1450 .nr_div_clks = ARRAY_SIZE(cpucl1_div_clks),
1451 .gate_clks = cpucl1_gate_clks,
1452 .nr_gate_clks = ARRAY_SIZE(cpucl1_gate_clks),
1453 .cpu_clks = cpucl1_cpu_clks,
1454 .nr_cpu_clks = ARRAY_SIZE(cpucl1_cpu_clks),
1455 .nr_clk_ids = CLKS_NR_CPUCL1,
1456 .clk_regs = cpucl1_clk_regs,
1457 .nr_clk_regs = ARRAY_SIZE(cpucl1_clk_regs),
1458 .clk_name = "dout_cpucl1_switch",
1459 .manual_plls = true,
1460 };
1461
exynos850_cmu_cpucl1_init(struct device_node * np)1462 static void __init exynos850_cmu_cpucl1_init(struct device_node *np)
1463 {
1464 exynos_arm64_register_cmu(NULL, np, &cpucl1_cmu_info);
1465 }
1466
1467 /* Register CMU_CPUCL1 early, as CPU clocks should be available ASAP */
1468 CLK_OF_DECLARE(exynos850_cmu_cpucl1, "samsung,exynos850-cmu-cpucl1",
1469 exynos850_cmu_cpucl1_init);
1470
1471 /* ---- CMU_G3D ------------------------------------------------------------- */
1472
1473 /* Register Offset definitions for CMU_G3D (0x11400000) */
1474 #define PLL_LOCKTIME_PLL_G3D 0x0000
1475 #define PLL_CON0_PLL_G3D 0x0100
1476 #define PLL_CON3_PLL_G3D 0x010c
1477 #define PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER 0x0600
1478 #define CLK_CON_MUX_MUX_CLK_G3D_BUSD 0x1000
1479 #define CLK_CON_DIV_DIV_CLK_G3D_BUSP 0x1804
1480 #define CLK_CON_GAT_CLK_G3D_CMU_G3D_PCLK 0x2000
1481 #define CLK_CON_GAT_CLK_G3D_GPU_CLK 0x2004
1482 #define CLK_CON_GAT_GOUT_G3D_TZPC_PCLK 0x200c
1483 #define CLK_CON_GAT_GOUT_G3D_GRAY2BIN_CLK 0x2010
1484 #define CLK_CON_GAT_GOUT_G3D_BUSD_CLK 0x2024
1485 #define CLK_CON_GAT_GOUT_G3D_BUSP_CLK 0x2028
1486 #define CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK 0x202c
1487
1488 static const unsigned long g3d_clk_regs[] __initconst = {
1489 PLL_LOCKTIME_PLL_G3D,
1490 PLL_CON0_PLL_G3D,
1491 PLL_CON3_PLL_G3D,
1492 PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER,
1493 CLK_CON_MUX_MUX_CLK_G3D_BUSD,
1494 CLK_CON_DIV_DIV_CLK_G3D_BUSP,
1495 CLK_CON_GAT_CLK_G3D_CMU_G3D_PCLK,
1496 CLK_CON_GAT_CLK_G3D_GPU_CLK,
1497 CLK_CON_GAT_GOUT_G3D_TZPC_PCLK,
1498 CLK_CON_GAT_GOUT_G3D_GRAY2BIN_CLK,
1499 CLK_CON_GAT_GOUT_G3D_BUSD_CLK,
1500 CLK_CON_GAT_GOUT_G3D_BUSP_CLK,
1501 CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK,
1502 };
1503
1504 /* List of parent clocks for Muxes in CMU_G3D */
1505 PNAME(mout_g3d_pll_p) = { "oscclk", "fout_g3d_pll" };
1506 PNAME(mout_g3d_switch_user_p) = { "oscclk", "dout_g3d_switch" };
1507 PNAME(mout_g3d_busd_p) = { "mout_g3d_pll", "mout_g3d_switch_user" };
1508
1509 /*
1510 * Do not provide PLL table to PLL_G3D, as MANUAL_PLL_CTRL bit is not set
1511 * for that PLL by default, so set_rate operation would fail.
1512 */
1513 static const struct samsung_pll_clock g3d_pll_clks[] __initconst = {
1514 PLL(pll_0818x, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk",
1515 PLL_LOCKTIME_PLL_G3D, PLL_CON3_PLL_G3D, NULL),
1516 };
1517
1518 static const struct samsung_mux_clock g3d_mux_clks[] __initconst = {
1519 MUX(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p,
1520 PLL_CON0_PLL_G3D, 4, 1),
1521 MUX(CLK_MOUT_G3D_SWITCH_USER, "mout_g3d_switch_user",
1522 mout_g3d_switch_user_p,
1523 PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER, 4, 1),
1524 MUX(CLK_MOUT_G3D_BUSD, "mout_g3d_busd", mout_g3d_busd_p,
1525 CLK_CON_MUX_MUX_CLK_G3D_BUSD, 0, 1),
1526 };
1527
1528 static const struct samsung_div_clock g3d_div_clks[] __initconst = {
1529 DIV(CLK_DOUT_G3D_BUSP, "dout_g3d_busp", "mout_g3d_busd",
1530 CLK_CON_DIV_DIV_CLK_G3D_BUSP, 0, 3),
1531 };
1532
1533 static const struct samsung_gate_clock g3d_gate_clks[] __initconst = {
1534 GATE(CLK_GOUT_G3D_CMU_G3D_PCLK, "gout_g3d_cmu_g3d_pclk",
1535 "dout_g3d_busp",
1536 CLK_CON_GAT_CLK_G3D_CMU_G3D_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1537 GATE(CLK_GOUT_G3D_GPU_CLK, "gout_g3d_gpu_clk", "mout_g3d_busd",
1538 CLK_CON_GAT_CLK_G3D_GPU_CLK, 21, 0, 0),
1539 GATE(CLK_GOUT_G3D_TZPC_PCLK, "gout_g3d_tzpc_pclk", "dout_g3d_busp",
1540 CLK_CON_GAT_GOUT_G3D_TZPC_PCLK, 21, 0, 0),
1541 GATE(CLK_GOUT_G3D_GRAY2BIN_CLK, "gout_g3d_gray2bin_clk",
1542 "mout_g3d_busd",
1543 CLK_CON_GAT_GOUT_G3D_GRAY2BIN_CLK, 21, 0, 0),
1544 GATE(CLK_GOUT_G3D_BUSD_CLK, "gout_g3d_busd_clk", "mout_g3d_busd",
1545 CLK_CON_GAT_GOUT_G3D_BUSD_CLK, 21, 0, 0),
1546 GATE(CLK_GOUT_G3D_BUSP_CLK, "gout_g3d_busp_clk", "dout_g3d_busp",
1547 CLK_CON_GAT_GOUT_G3D_BUSP_CLK, 21, 0, 0),
1548 GATE(CLK_GOUT_G3D_SYSREG_PCLK, "gout_g3d_sysreg_pclk", "dout_g3d_busp",
1549 CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK, 21, 0, 0),
1550 };
1551
1552 static const struct samsung_cmu_info g3d_cmu_info __initconst = {
1553 .pll_clks = g3d_pll_clks,
1554 .nr_pll_clks = ARRAY_SIZE(g3d_pll_clks),
1555 .mux_clks = g3d_mux_clks,
1556 .nr_mux_clks = ARRAY_SIZE(g3d_mux_clks),
1557 .div_clks = g3d_div_clks,
1558 .nr_div_clks = ARRAY_SIZE(g3d_div_clks),
1559 .gate_clks = g3d_gate_clks,
1560 .nr_gate_clks = ARRAY_SIZE(g3d_gate_clks),
1561 .nr_clk_ids = CLKS_NR_G3D,
1562 .clk_regs = g3d_clk_regs,
1563 .nr_clk_regs = ARRAY_SIZE(g3d_clk_regs),
1564 .clk_name = "dout_g3d_switch",
1565 };
1566
1567 /* ---- CMU_HSI ------------------------------------------------------------- */
1568
1569 /* Register Offset definitions for CMU_HSI (0x13400000) */
1570 #define PLL_CON0_MUX_CLKCMU_HSI_BUS_USER 0x0600
1571 #define PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER 0x0610
1572 #define PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER 0x0620
1573 #define CLK_CON_MUX_MUX_CLK_HSI_RTC 0x1000
1574 #define CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK 0x2000
1575 #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV 0x2008
1576 #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50 0x200c
1577 #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26 0x2010
1578 #define CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK 0x2018
1579 #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK 0x2024
1580 #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN 0x2028
1581 #define CLK_CON_GAT_GOUT_HSI_PPMU_ACLK 0x202c
1582 #define CLK_CON_GAT_GOUT_HSI_PPMU_PCLK 0x2030
1583 #define CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK 0x2038
1584 #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20 0x203c
1585 #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY 0x2040
1586
1587 static const unsigned long hsi_clk_regs[] __initconst = {
1588 PLL_CON0_MUX_CLKCMU_HSI_BUS_USER,
1589 PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER,
1590 PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER,
1591 CLK_CON_MUX_MUX_CLK_HSI_RTC,
1592 CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK,
1593 CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV,
1594 CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50,
1595 CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26,
1596 CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK,
1597 CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK,
1598 CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN,
1599 CLK_CON_GAT_GOUT_HSI_PPMU_ACLK,
1600 CLK_CON_GAT_GOUT_HSI_PPMU_PCLK,
1601 CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK,
1602 CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20,
1603 CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY,
1604 };
1605
1606 /* List of parent clocks for Muxes in CMU_HSI */
1607 PNAME(mout_hsi_bus_user_p) = { "oscclk", "dout_hsi_bus" };
1608 PNAME(mout_hsi_mmc_card_user_p) = { "oscclk", "dout_hsi_mmc_card" };
1609 PNAME(mout_hsi_usb20drd_user_p) = { "oscclk", "dout_hsi_usb20drd" };
1610 PNAME(mout_hsi_rtc_p) = { "rtcclk", "oscclk" };
1611
1612 static const struct samsung_mux_clock hsi_mux_clks[] __initconst = {
1613 MUX(CLK_MOUT_HSI_BUS_USER, "mout_hsi_bus_user", mout_hsi_bus_user_p,
1614 PLL_CON0_MUX_CLKCMU_HSI_BUS_USER, 4, 1),
1615 MUX_F(CLK_MOUT_HSI_MMC_CARD_USER, "mout_hsi_mmc_card_user",
1616 mout_hsi_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER,
1617 4, 1, CLK_SET_RATE_PARENT, 0),
1618 MUX(CLK_MOUT_HSI_USB20DRD_USER, "mout_hsi_usb20drd_user",
1619 mout_hsi_usb20drd_user_p, PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER,
1620 4, 1),
1621 MUX(CLK_MOUT_HSI_RTC, "mout_hsi_rtc", mout_hsi_rtc_p,
1622 CLK_CON_MUX_MUX_CLK_HSI_RTC, 0, 1),
1623 };
1624
1625 static const struct samsung_gate_clock hsi_gate_clks[] __initconst = {
1626 /* TODO: Should be enabled in corresponding driver */
1627 GATE(CLK_GOUT_HSI_CMU_HSI_PCLK, "gout_hsi_cmu_hsi_pclk",
1628 "mout_hsi_bus_user",
1629 CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1630 GATE(CLK_GOUT_USB_RTC_CLK, "gout_usb_rtc", "mout_hsi_rtc",
1631 CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, 21, 0, 0),
1632 GATE(CLK_GOUT_USB_REF_CLK, "gout_usb_ref", "mout_hsi_usb20drd_user",
1633 CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50, 21, 0, 0),
1634 GATE(CLK_GOUT_USB_PHY_REF_CLK, "gout_usb_phy_ref", "oscclk",
1635 CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26, 21, 0, 0),
1636 /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
1637 GATE(CLK_GOUT_GPIO_HSI_PCLK, "gout_gpio_hsi_pclk", "mout_hsi_bus_user",
1638 CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1639 GATE(CLK_GOUT_MMC_CARD_ACLK, "gout_mmc_card_aclk", "mout_hsi_bus_user",
1640 CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK, 21, 0, 0),
1641 GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin",
1642 "mout_hsi_mmc_card_user",
1643 CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, 21, CLK_SET_RATE_PARENT, 0),
1644 GATE(CLK_GOUT_HSI_PPMU_ACLK, "gout_hsi_ppmu_aclk", "mout_hsi_bus_user",
1645 CLK_CON_GAT_GOUT_HSI_PPMU_ACLK, 21, 0, 0),
1646 GATE(CLK_GOUT_HSI_PPMU_PCLK, "gout_hsi_ppmu_pclk", "mout_hsi_bus_user",
1647 CLK_CON_GAT_GOUT_HSI_PPMU_PCLK, 21, 0, 0),
1648 GATE(CLK_GOUT_SYSREG_HSI_PCLK, "gout_sysreg_hsi_pclk",
1649 "mout_hsi_bus_user",
1650 CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, 21, 0, 0),
1651 GATE(CLK_GOUT_USB_PHY_ACLK, "gout_usb_phy_aclk", "mout_hsi_bus_user",
1652 CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20, 21, 0, 0),
1653 GATE(CLK_GOUT_USB_BUS_EARLY_CLK, "gout_usb_bus_early",
1654 "mout_hsi_bus_user",
1655 CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY, 21, 0, 0),
1656 };
1657
1658 static const struct samsung_cmu_info hsi_cmu_info __initconst = {
1659 .mux_clks = hsi_mux_clks,
1660 .nr_mux_clks = ARRAY_SIZE(hsi_mux_clks),
1661 .gate_clks = hsi_gate_clks,
1662 .nr_gate_clks = ARRAY_SIZE(hsi_gate_clks),
1663 .nr_clk_ids = CLKS_NR_HSI,
1664 .clk_regs = hsi_clk_regs,
1665 .nr_clk_regs = ARRAY_SIZE(hsi_clk_regs),
1666 .clk_name = "dout_hsi_bus",
1667 };
1668
1669 /* ---- CMU_IS -------------------------------------------------------------- */
1670
1671 #define PLL_CON0_MUX_CLKCMU_IS_BUS_USER 0x0600
1672 #define PLL_CON0_MUX_CLKCMU_IS_GDC_USER 0x0610
1673 #define PLL_CON0_MUX_CLKCMU_IS_ITP_USER 0x0620
1674 #define PLL_CON0_MUX_CLKCMU_IS_VRA_USER 0x0630
1675 #define CLK_CON_DIV_DIV_CLK_IS_BUSP 0x1800
1676 #define CLK_CON_GAT_CLK_IS_CMU_IS_PCLK 0x2000
1677 #define CLK_CON_GAT_GOUT_IS_CSIS0_ACLK 0x2040
1678 #define CLK_CON_GAT_GOUT_IS_CSIS1_ACLK 0x2044
1679 #define CLK_CON_GAT_GOUT_IS_CSIS2_ACLK 0x2048
1680 #define CLK_CON_GAT_GOUT_IS_TZPC_PCLK 0x204c
1681 #define CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA 0x2050
1682 #define CLK_CON_GAT_GOUT_IS_CLK_GDC 0x2054
1683 #define CLK_CON_GAT_GOUT_IS_CLK_IPP 0x2058
1684 #define CLK_CON_GAT_GOUT_IS_CLK_ITP 0x205c
1685 #define CLK_CON_GAT_GOUT_IS_CLK_MCSC 0x2060
1686 #define CLK_CON_GAT_GOUT_IS_CLK_VRA 0x2064
1687 #define CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK 0x2074
1688 #define CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK 0x2078
1689 #define CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK 0x207c
1690 #define CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK 0x2080
1691 #define CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1 0x2098
1692 #define CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1 0x209c
1693 #define CLK_CON_GAT_GOUT_IS_SYSREG_PCLK 0x20a0
1694
1695 static const unsigned long is_clk_regs[] __initconst = {
1696 PLL_CON0_MUX_CLKCMU_IS_BUS_USER,
1697 PLL_CON0_MUX_CLKCMU_IS_GDC_USER,
1698 PLL_CON0_MUX_CLKCMU_IS_ITP_USER,
1699 PLL_CON0_MUX_CLKCMU_IS_VRA_USER,
1700 CLK_CON_DIV_DIV_CLK_IS_BUSP,
1701 CLK_CON_GAT_CLK_IS_CMU_IS_PCLK,
1702 CLK_CON_GAT_GOUT_IS_CSIS0_ACLK,
1703 CLK_CON_GAT_GOUT_IS_CSIS1_ACLK,
1704 CLK_CON_GAT_GOUT_IS_CSIS2_ACLK,
1705 CLK_CON_GAT_GOUT_IS_TZPC_PCLK,
1706 CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA,
1707 CLK_CON_GAT_GOUT_IS_CLK_GDC,
1708 CLK_CON_GAT_GOUT_IS_CLK_IPP,
1709 CLK_CON_GAT_GOUT_IS_CLK_ITP,
1710 CLK_CON_GAT_GOUT_IS_CLK_MCSC,
1711 CLK_CON_GAT_GOUT_IS_CLK_VRA,
1712 CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK,
1713 CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK,
1714 CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK,
1715 CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK,
1716 CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1,
1717 CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1,
1718 CLK_CON_GAT_GOUT_IS_SYSREG_PCLK,
1719 };
1720
1721 /* List of parent clocks for Muxes in CMU_IS */
1722 PNAME(mout_is_bus_user_p) = { "oscclk", "dout_is_bus" };
1723 PNAME(mout_is_itp_user_p) = { "oscclk", "dout_is_itp" };
1724 PNAME(mout_is_vra_user_p) = { "oscclk", "dout_is_vra" };
1725 PNAME(mout_is_gdc_user_p) = { "oscclk", "dout_is_gdc" };
1726
1727 static const struct samsung_mux_clock is_mux_clks[] __initconst = {
1728 MUX(CLK_MOUT_IS_BUS_USER, "mout_is_bus_user", mout_is_bus_user_p,
1729 PLL_CON0_MUX_CLKCMU_IS_BUS_USER, 4, 1),
1730 MUX(CLK_MOUT_IS_ITP_USER, "mout_is_itp_user", mout_is_itp_user_p,
1731 PLL_CON0_MUX_CLKCMU_IS_ITP_USER, 4, 1),
1732 MUX(CLK_MOUT_IS_VRA_USER, "mout_is_vra_user", mout_is_vra_user_p,
1733 PLL_CON0_MUX_CLKCMU_IS_VRA_USER, 4, 1),
1734 MUX(CLK_MOUT_IS_GDC_USER, "mout_is_gdc_user", mout_is_gdc_user_p,
1735 PLL_CON0_MUX_CLKCMU_IS_GDC_USER, 4, 1),
1736 };
1737
1738 static const struct samsung_div_clock is_div_clks[] __initconst = {
1739 DIV(CLK_DOUT_IS_BUSP, "dout_is_busp", "mout_is_bus_user",
1740 CLK_CON_DIV_DIV_CLK_IS_BUSP, 0, 2),
1741 };
1742
1743 static const struct samsung_gate_clock is_gate_clks[] __initconst = {
1744 /* TODO: Should be enabled in IS driver */
1745 GATE(CLK_GOUT_IS_CMU_IS_PCLK, "gout_is_cmu_is_pclk", "dout_is_busp",
1746 CLK_CON_GAT_CLK_IS_CMU_IS_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1747 GATE(CLK_GOUT_IS_CSIS0_ACLK, "gout_is_csis0_aclk", "mout_is_bus_user",
1748 CLK_CON_GAT_GOUT_IS_CSIS0_ACLK, 21, 0, 0),
1749 GATE(CLK_GOUT_IS_CSIS1_ACLK, "gout_is_csis1_aclk", "mout_is_bus_user",
1750 CLK_CON_GAT_GOUT_IS_CSIS1_ACLK, 21, 0, 0),
1751 GATE(CLK_GOUT_IS_CSIS2_ACLK, "gout_is_csis2_aclk", "mout_is_bus_user",
1752 CLK_CON_GAT_GOUT_IS_CSIS2_ACLK, 21, 0, 0),
1753 GATE(CLK_GOUT_IS_TZPC_PCLK, "gout_is_tzpc_pclk", "dout_is_busp",
1754 CLK_CON_GAT_GOUT_IS_TZPC_PCLK, 21, 0, 0),
1755 GATE(CLK_GOUT_IS_CSIS_DMA_CLK, "gout_is_csis_dma_clk",
1756 "mout_is_bus_user",
1757 CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA, 21, 0, 0),
1758 GATE(CLK_GOUT_IS_GDC_CLK, "gout_is_gdc_clk", "mout_is_gdc_user",
1759 CLK_CON_GAT_GOUT_IS_CLK_GDC, 21, 0, 0),
1760 GATE(CLK_GOUT_IS_IPP_CLK, "gout_is_ipp_clk", "mout_is_bus_user",
1761 CLK_CON_GAT_GOUT_IS_CLK_IPP, 21, 0, 0),
1762 GATE(CLK_GOUT_IS_ITP_CLK, "gout_is_itp_clk", "mout_is_itp_user",
1763 CLK_CON_GAT_GOUT_IS_CLK_ITP, 21, 0, 0),
1764 GATE(CLK_GOUT_IS_MCSC_CLK, "gout_is_mcsc_clk", "mout_is_itp_user",
1765 CLK_CON_GAT_GOUT_IS_CLK_MCSC, 21, 0, 0),
1766 GATE(CLK_GOUT_IS_VRA_CLK, "gout_is_vra_clk", "mout_is_vra_user",
1767 CLK_CON_GAT_GOUT_IS_CLK_VRA, 21, 0, 0),
1768 GATE(CLK_GOUT_IS_PPMU_IS0_ACLK, "gout_is_ppmu_is0_aclk",
1769 "mout_is_bus_user",
1770 CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK, 21, 0, 0),
1771 GATE(CLK_GOUT_IS_PPMU_IS0_PCLK, "gout_is_ppmu_is0_pclk", "dout_is_busp",
1772 CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK, 21, 0, 0),
1773 GATE(CLK_GOUT_IS_PPMU_IS1_ACLK, "gout_is_ppmu_is1_aclk",
1774 "mout_is_itp_user",
1775 CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK, 21, 0, 0),
1776 GATE(CLK_GOUT_IS_PPMU_IS1_PCLK, "gout_is_ppmu_is1_pclk", "dout_is_busp",
1777 CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK, 21, 0, 0),
1778 GATE(CLK_GOUT_IS_SYSMMU_IS0_CLK, "gout_is_sysmmu_is0_clk",
1779 "mout_is_bus_user",
1780 CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1, 21, 0, 0),
1781 GATE(CLK_GOUT_IS_SYSMMU_IS1_CLK, "gout_is_sysmmu_is1_clk",
1782 "mout_is_itp_user",
1783 CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1, 21, 0, 0),
1784 GATE(CLK_GOUT_IS_SYSREG_PCLK, "gout_is_sysreg_pclk", "dout_is_busp",
1785 CLK_CON_GAT_GOUT_IS_SYSREG_PCLK, 21, 0, 0),
1786 };
1787
1788 static const struct samsung_cmu_info is_cmu_info __initconst = {
1789 .mux_clks = is_mux_clks,
1790 .nr_mux_clks = ARRAY_SIZE(is_mux_clks),
1791 .div_clks = is_div_clks,
1792 .nr_div_clks = ARRAY_SIZE(is_div_clks),
1793 .gate_clks = is_gate_clks,
1794 .nr_gate_clks = ARRAY_SIZE(is_gate_clks),
1795 .nr_clk_ids = CLKS_NR_IS,
1796 .clk_regs = is_clk_regs,
1797 .nr_clk_regs = ARRAY_SIZE(is_clk_regs),
1798 .clk_name = "dout_is_bus",
1799 };
1800
1801 /* ---- CMU_MFCMSCL --------------------------------------------------------- */
1802
1803 #define PLL_CON0_MUX_CLKCMU_MFCMSCL_JPEG_USER 0x0600
1804 #define PLL_CON0_MUX_CLKCMU_MFCMSCL_M2M_USER 0x0610
1805 #define PLL_CON0_MUX_CLKCMU_MFCMSCL_MCSC_USER 0x0620
1806 #define PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER 0x0630
1807 #define CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP 0x1800
1808 #define CLK_CON_GAT_CLK_MFCMSCL_CMU_MFCMSCL_PCLK 0x2000
1809 #define CLK_CON_GAT_GOUT_MFCMSCL_TZPC_PCLK 0x2038
1810 #define CLK_CON_GAT_GOUT_MFCMSCL_JPEG_ACLK 0x203c
1811 #define CLK_CON_GAT_GOUT_MFCMSCL_M2M_ACLK 0x2048
1812 #define CLK_CON_GAT_GOUT_MFCMSCL_MCSC_I_CLK 0x204c
1813 #define CLK_CON_GAT_GOUT_MFCMSCL_MFC_ACLK 0x2050
1814 #define CLK_CON_GAT_GOUT_MFCMSCL_PPMU_ACLK 0x2054
1815 #define CLK_CON_GAT_GOUT_MFCMSCL_PPMU_PCLK 0x2058
1816 #define CLK_CON_GAT_GOUT_MFCMSCL_SYSMMU_CLK_S1 0x2074
1817 #define CLK_CON_GAT_GOUT_MFCMSCL_SYSREG_PCLK 0x2078
1818
1819 static const unsigned long mfcmscl_clk_regs[] __initconst = {
1820 PLL_CON0_MUX_CLKCMU_MFCMSCL_JPEG_USER,
1821 PLL_CON0_MUX_CLKCMU_MFCMSCL_M2M_USER,
1822 PLL_CON0_MUX_CLKCMU_MFCMSCL_MCSC_USER,
1823 PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER,
1824 CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP,
1825 CLK_CON_GAT_CLK_MFCMSCL_CMU_MFCMSCL_PCLK,
1826 CLK_CON_GAT_GOUT_MFCMSCL_TZPC_PCLK,
1827 CLK_CON_GAT_GOUT_MFCMSCL_JPEG_ACLK,
1828 CLK_CON_GAT_GOUT_MFCMSCL_M2M_ACLK,
1829 CLK_CON_GAT_GOUT_MFCMSCL_MCSC_I_CLK,
1830 CLK_CON_GAT_GOUT_MFCMSCL_MFC_ACLK,
1831 CLK_CON_GAT_GOUT_MFCMSCL_PPMU_ACLK,
1832 CLK_CON_GAT_GOUT_MFCMSCL_PPMU_PCLK,
1833 CLK_CON_GAT_GOUT_MFCMSCL_SYSMMU_CLK_S1,
1834 CLK_CON_GAT_GOUT_MFCMSCL_SYSREG_PCLK,
1835 };
1836
1837 /* List of parent clocks for Muxes in CMU_MFCMSCL */
1838 PNAME(mout_mfcmscl_mfc_user_p) = { "oscclk", "dout_mfcmscl_mfc" };
1839 PNAME(mout_mfcmscl_m2m_user_p) = { "oscclk", "dout_mfcmscl_m2m" };
1840 PNAME(mout_mfcmscl_mcsc_user_p) = { "oscclk", "dout_mfcmscl_mcsc" };
1841 PNAME(mout_mfcmscl_jpeg_user_p) = { "oscclk", "dout_mfcmscl_jpeg" };
1842
1843 static const struct samsung_mux_clock mfcmscl_mux_clks[] __initconst = {
1844 MUX(CLK_MOUT_MFCMSCL_MFC_USER, "mout_mfcmscl_mfc_user",
1845 mout_mfcmscl_mfc_user_p,
1846 PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER, 4, 1),
1847 MUX(CLK_MOUT_MFCMSCL_M2M_USER, "mout_mfcmscl_m2m_user",
1848 mout_mfcmscl_m2m_user_p,
1849 PLL_CON0_MUX_CLKCMU_MFCMSCL_M2M_USER, 4, 1),
1850 MUX(CLK_MOUT_MFCMSCL_MCSC_USER, "mout_mfcmscl_mcsc_user",
1851 mout_mfcmscl_mcsc_user_p,
1852 PLL_CON0_MUX_CLKCMU_MFCMSCL_MCSC_USER, 4, 1),
1853 MUX(CLK_MOUT_MFCMSCL_JPEG_USER, "mout_mfcmscl_jpeg_user",
1854 mout_mfcmscl_jpeg_user_p,
1855 PLL_CON0_MUX_CLKCMU_MFCMSCL_JPEG_USER, 4, 1),
1856 };
1857
1858 static const struct samsung_div_clock mfcmscl_div_clks[] __initconst = {
1859 DIV(CLK_DOUT_MFCMSCL_BUSP, "dout_mfcmscl_busp", "mout_mfcmscl_mfc_user",
1860 CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP, 0, 3),
1861 };
1862
1863 static const struct samsung_gate_clock mfcmscl_gate_clks[] __initconst = {
1864 /* TODO: Should be enabled in MFC driver */
1865 GATE(CLK_GOUT_MFCMSCL_CMU_MFCMSCL_PCLK, "gout_mfcmscl_cmu_mfcmscl_pclk",
1866 "dout_mfcmscl_busp", CLK_CON_GAT_CLK_MFCMSCL_CMU_MFCMSCL_PCLK,
1867 21, CLK_IGNORE_UNUSED, 0),
1868 GATE(CLK_GOUT_MFCMSCL_TZPC_PCLK, "gout_mfcmscl_tzpc_pclk",
1869 "dout_mfcmscl_busp", CLK_CON_GAT_GOUT_MFCMSCL_TZPC_PCLK,
1870 21, 0, 0),
1871 GATE(CLK_GOUT_MFCMSCL_JPEG_ACLK, "gout_mfcmscl_jpeg_aclk",
1872 "mout_mfcmscl_jpeg_user", CLK_CON_GAT_GOUT_MFCMSCL_JPEG_ACLK,
1873 21, 0, 0),
1874 GATE(CLK_GOUT_MFCMSCL_M2M_ACLK, "gout_mfcmscl_m2m_aclk",
1875 "mout_mfcmscl_m2m_user", CLK_CON_GAT_GOUT_MFCMSCL_M2M_ACLK,
1876 21, 0, 0),
1877 GATE(CLK_GOUT_MFCMSCL_MCSC_CLK, "gout_mfcmscl_mcsc_clk",
1878 "mout_mfcmscl_mcsc_user", CLK_CON_GAT_GOUT_MFCMSCL_MCSC_I_CLK,
1879 21, 0, 0),
1880 GATE(CLK_GOUT_MFCMSCL_MFC_ACLK, "gout_mfcmscl_mfc_aclk",
1881 "mout_mfcmscl_mfc_user", CLK_CON_GAT_GOUT_MFCMSCL_MFC_ACLK,
1882 21, 0, 0),
1883 GATE(CLK_GOUT_MFCMSCL_PPMU_ACLK, "gout_mfcmscl_ppmu_aclk",
1884 "mout_mfcmscl_mfc_user", CLK_CON_GAT_GOUT_MFCMSCL_PPMU_ACLK,
1885 21, 0, 0),
1886 GATE(CLK_GOUT_MFCMSCL_PPMU_PCLK, "gout_mfcmscl_ppmu_pclk",
1887 "dout_mfcmscl_busp", CLK_CON_GAT_GOUT_MFCMSCL_PPMU_PCLK,
1888 21, 0, 0),
1889 GATE(CLK_GOUT_MFCMSCL_SYSMMU_CLK, "gout_mfcmscl_sysmmu_clk",
1890 "mout_mfcmscl_mfc_user", CLK_CON_GAT_GOUT_MFCMSCL_SYSMMU_CLK_S1,
1891 21, 0, 0),
1892 GATE(CLK_GOUT_MFCMSCL_SYSREG_PCLK, "gout_mfcmscl_sysreg_pclk",
1893 "dout_mfcmscl_busp", CLK_CON_GAT_GOUT_MFCMSCL_SYSREG_PCLK,
1894 21, 0, 0),
1895 };
1896
1897 static const struct samsung_cmu_info mfcmscl_cmu_info __initconst = {
1898 .mux_clks = mfcmscl_mux_clks,
1899 .nr_mux_clks = ARRAY_SIZE(mfcmscl_mux_clks),
1900 .div_clks = mfcmscl_div_clks,
1901 .nr_div_clks = ARRAY_SIZE(mfcmscl_div_clks),
1902 .gate_clks = mfcmscl_gate_clks,
1903 .nr_gate_clks = ARRAY_SIZE(mfcmscl_gate_clks),
1904 .nr_clk_ids = CLKS_NR_MFCMSCL,
1905 .clk_regs = mfcmscl_clk_regs,
1906 .nr_clk_regs = ARRAY_SIZE(mfcmscl_clk_regs),
1907 .clk_name = "dout_mfcmscl_mfc",
1908 };
1909
1910 /* ---- CMU_PERI ------------------------------------------------------------ */
1911
1912 /* Register Offset definitions for CMU_PERI (0x10030000) */
1913 #define PLL_CON0_MUX_CLKCMU_PERI_BUS_USER 0x0600
1914 #define PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER 0x0610
1915 #define PLL_CON0_MUX_CLKCMU_PERI_SPI_USER 0x0620
1916 #define PLL_CON0_MUX_CLKCMU_PERI_UART_USER 0x0630
1917 #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0 0x1800
1918 #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1 0x1804
1919 #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2 0x1808
1920 #define CLK_CON_DIV_DIV_CLK_PERI_SPI_0 0x180c
1921 #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0 0x200c
1922 #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1 0x2010
1923 #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2 0x2014
1924 #define CLK_CON_GAT_GOUT_PERI_BUSIF_TMU_PCLK 0x2018
1925 #define CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK 0x2020
1926 #define CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK 0x2024
1927 #define CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK 0x2028
1928 #define CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK 0x202c
1929 #define CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK 0x2030
1930 #define CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK 0x2034
1931 #define CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK 0x2038
1932 #define CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK 0x203c
1933 #define CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK 0x2040
1934 #define CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK 0x2044
1935 #define CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK 0x2048
1936 #define CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK 0x204c
1937 #define CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK 0x2050
1938 #define CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK 0x2054
1939 #define CLK_CON_GAT_GOUT_PERI_MCT_PCLK 0x205c
1940 #define CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK 0x2064
1941 #define CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK 0x209c
1942 #define CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK 0x20a0
1943 #define CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK 0x20a4
1944 #define CLK_CON_GAT_GOUT_PERI_UART_IPCLK 0x20a8
1945 #define CLK_CON_GAT_GOUT_PERI_UART_PCLK 0x20ac
1946 #define CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK 0x20b0
1947 #define CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK 0x20b4
1948
1949 static const unsigned long peri_clk_regs[] __initconst = {
1950 PLL_CON0_MUX_CLKCMU_PERI_BUS_USER,
1951 PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER,
1952 PLL_CON0_MUX_CLKCMU_PERI_SPI_USER,
1953 PLL_CON0_MUX_CLKCMU_PERI_UART_USER,
1954 CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0,
1955 CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1,
1956 CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2,
1957 CLK_CON_DIV_DIV_CLK_PERI_SPI_0,
1958 CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0,
1959 CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1,
1960 CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2,
1961 CLK_CON_GAT_GOUT_PERI_BUSIF_TMU_PCLK,
1962 CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK,
1963 CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK,
1964 CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK,
1965 CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK,
1966 CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK,
1967 CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK,
1968 CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK,
1969 CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK,
1970 CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK,
1971 CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK,
1972 CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK,
1973 CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK,
1974 CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK,
1975 CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK,
1976 CLK_CON_GAT_GOUT_PERI_MCT_PCLK,
1977 CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK,
1978 CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK,
1979 CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK,
1980 CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK,
1981 CLK_CON_GAT_GOUT_PERI_UART_IPCLK,
1982 CLK_CON_GAT_GOUT_PERI_UART_PCLK,
1983 CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK,
1984 CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK,
1985 };
1986
1987 /* List of parent clocks for Muxes in CMU_PERI */
1988 PNAME(mout_peri_bus_user_p) = { "oscclk", "dout_peri_bus" };
1989 PNAME(mout_peri_uart_user_p) = { "oscclk", "dout_peri_uart" };
1990 PNAME(mout_peri_hsi2c_user_p) = { "oscclk", "dout_peri_ip" };
1991 PNAME(mout_peri_spi_user_p) = { "oscclk", "dout_peri_ip" };
1992
1993 static const struct samsung_mux_clock peri_mux_clks[] __initconst = {
1994 MUX(CLK_MOUT_PERI_BUS_USER, "mout_peri_bus_user", mout_peri_bus_user_p,
1995 PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 4, 1),
1996 MUX(CLK_MOUT_PERI_UART_USER, "mout_peri_uart_user",
1997 mout_peri_uart_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART_USER, 4, 1),
1998 MUX(CLK_MOUT_PERI_HSI2C_USER, "mout_peri_hsi2c_user",
1999 mout_peri_hsi2c_user_p, PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER, 4, 1),
2000 MUX_F(CLK_MOUT_PERI_SPI_USER, "mout_peri_spi_user",
2001 mout_peri_spi_user_p, PLL_CON0_MUX_CLKCMU_PERI_SPI_USER, 4, 1,
2002 CLK_SET_RATE_PARENT, 0),
2003 };
2004
2005 static const struct samsung_div_clock peri_div_clks[] __initconst = {
2006 DIV(CLK_DOUT_PERI_HSI2C0, "dout_peri_hsi2c0", "gout_peri_hsi2c0",
2007 CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0, 0, 5),
2008 DIV(CLK_DOUT_PERI_HSI2C1, "dout_peri_hsi2c1", "gout_peri_hsi2c1",
2009 CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1, 0, 5),
2010 DIV(CLK_DOUT_PERI_HSI2C2, "dout_peri_hsi2c2", "gout_peri_hsi2c2",
2011 CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2, 0, 5),
2012 DIV_F(CLK_DOUT_PERI_SPI0, "dout_peri_spi0", "mout_peri_spi_user",
2013 CLK_CON_DIV_DIV_CLK_PERI_SPI_0, 0, 5, CLK_SET_RATE_PARENT, 0),
2014 };
2015
2016 static const struct samsung_gate_clock peri_gate_clks[] __initconst = {
2017 GATE(CLK_GOUT_PERI_HSI2C0, "gout_peri_hsi2c0", "mout_peri_hsi2c_user",
2018 CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0, 21, 0, 0),
2019 GATE(CLK_GOUT_PERI_HSI2C1, "gout_peri_hsi2c1", "mout_peri_hsi2c_user",
2020 CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1, 21, 0, 0),
2021 GATE(CLK_GOUT_PERI_HSI2C2, "gout_peri_hsi2c2", "mout_peri_hsi2c_user",
2022 CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2, 21, 0, 0),
2023 GATE(CLK_GOUT_HSI2C0_IPCLK, "gout_hsi2c0_ipclk", "dout_peri_hsi2c0",
2024 CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK, 21, 0, 0),
2025 GATE(CLK_GOUT_HSI2C0_PCLK, "gout_hsi2c0_pclk", "mout_peri_bus_user",
2026 CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK, 21, 0, 0),
2027 GATE(CLK_GOUT_HSI2C1_IPCLK, "gout_hsi2c1_ipclk", "dout_peri_hsi2c1",
2028 CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK, 21, 0, 0),
2029 GATE(CLK_GOUT_HSI2C1_PCLK, "gout_hsi2c1_pclk", "mout_peri_bus_user",
2030 CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK, 21, 0, 0),
2031 GATE(CLK_GOUT_HSI2C2_IPCLK, "gout_hsi2c2_ipclk", "dout_peri_hsi2c2",
2032 CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK, 21, 0, 0),
2033 GATE(CLK_GOUT_HSI2C2_PCLK, "gout_hsi2c2_pclk", "mout_peri_bus_user",
2034 CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK, 21, 0, 0),
2035 GATE(CLK_GOUT_I2C0_PCLK, "gout_i2c0_pclk", "mout_peri_bus_user",
2036 CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, 21, 0, 0),
2037 GATE(CLK_GOUT_I2C1_PCLK, "gout_i2c1_pclk", "mout_peri_bus_user",
2038 CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, 21, 0, 0),
2039 GATE(CLK_GOUT_I2C2_PCLK, "gout_i2c2_pclk", "mout_peri_bus_user",
2040 CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, 21, 0, 0),
2041 GATE(CLK_GOUT_I2C3_PCLK, "gout_i2c3_pclk", "mout_peri_bus_user",
2042 CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, 21, 0, 0),
2043 GATE(CLK_GOUT_I2C4_PCLK, "gout_i2c4_pclk", "mout_peri_bus_user",
2044 CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, 21, 0, 0),
2045 GATE(CLK_GOUT_I2C5_PCLK, "gout_i2c5_pclk", "mout_peri_bus_user",
2046 CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, 21, 0, 0),
2047 GATE(CLK_GOUT_I2C6_PCLK, "gout_i2c6_pclk", "mout_peri_bus_user",
2048 CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, 21, 0, 0),
2049 GATE(CLK_GOUT_MCT_PCLK, "gout_mct_pclk", "mout_peri_bus_user",
2050 CLK_CON_GAT_GOUT_PERI_MCT_PCLK, 21, 0, 0),
2051 GATE(CLK_GOUT_PWM_MOTOR_PCLK, "gout_pwm_motor_pclk",
2052 "mout_peri_bus_user",
2053 CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, 21, 0, 0),
2054 GATE(CLK_GOUT_SPI0_IPCLK, "gout_spi0_ipclk", "dout_peri_spi0",
2055 CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK, 21, CLK_SET_RATE_PARENT, 0),
2056 GATE(CLK_GOUT_SPI0_PCLK, "gout_spi0_pclk", "mout_peri_bus_user",
2057 CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 21, 0, 0),
2058 GATE(CLK_GOUT_SYSREG_PERI_PCLK, "gout_sysreg_peri_pclk",
2059 "mout_peri_bus_user",
2060 CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK, 21, 0, 0),
2061 GATE(CLK_GOUT_UART_IPCLK, "gout_uart_ipclk", "mout_peri_uart_user",
2062 CLK_CON_GAT_GOUT_PERI_UART_IPCLK, 21, 0, 0),
2063 GATE(CLK_GOUT_UART_PCLK, "gout_uart_pclk", "mout_peri_bus_user",
2064 CLK_CON_GAT_GOUT_PERI_UART_PCLK, 21, 0, 0),
2065 GATE(CLK_GOUT_WDT0_PCLK, "gout_wdt0_pclk", "mout_peri_bus_user",
2066 CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK, 21, 0, 0),
2067 GATE(CLK_GOUT_WDT1_PCLK, "gout_wdt1_pclk", "mout_peri_bus_user",
2068 CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK, 21, 0, 0),
2069 /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
2070 GATE(CLK_GOUT_GPIO_PERI_PCLK, "gout_gpio_peri_pclk",
2071 "mout_peri_bus_user",
2072 CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK, 21, CLK_IGNORE_UNUSED, 0),
2073 GATE(CLK_GOUT_BUSIF_TMU_PCLK, "gout_busif_tmu_pclk",
2074 "mout_peri_bus_user",
2075 CLK_CON_GAT_GOUT_PERI_BUSIF_TMU_PCLK, 21, 0, 0),
2076 };
2077
2078 static const struct samsung_cmu_info peri_cmu_info __initconst = {
2079 .mux_clks = peri_mux_clks,
2080 .nr_mux_clks = ARRAY_SIZE(peri_mux_clks),
2081 .div_clks = peri_div_clks,
2082 .nr_div_clks = ARRAY_SIZE(peri_div_clks),
2083 .gate_clks = peri_gate_clks,
2084 .nr_gate_clks = ARRAY_SIZE(peri_gate_clks),
2085 .nr_clk_ids = CLKS_NR_PERI,
2086 .clk_regs = peri_clk_regs,
2087 .nr_clk_regs = ARRAY_SIZE(peri_clk_regs),
2088 .clk_name = "dout_peri_bus",
2089 };
2090
exynos850_cmu_peri_init(struct device_node * np)2091 static void __init exynos850_cmu_peri_init(struct device_node *np)
2092 {
2093 exynos_arm64_register_cmu(NULL, np, &peri_cmu_info);
2094 }
2095
2096 /* Register CMU_PERI early, as it's needed for MCT timer */
2097 CLK_OF_DECLARE(exynos850_cmu_peri, "samsung,exynos850-cmu-peri",
2098 exynos850_cmu_peri_init);
2099
2100 /* ---- CMU_CORE ------------------------------------------------------------ */
2101
2102 /* Register Offset definitions for CMU_CORE (0x12000000) */
2103 #define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER 0x0600
2104 #define PLL_CON0_MUX_CLKCMU_CORE_CCI_USER 0x0610
2105 #define PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER 0x0620
2106 #define PLL_CON0_MUX_CLKCMU_CORE_SSS_USER 0x0630
2107 #define CLK_CON_MUX_MUX_CLK_CORE_GIC 0x1000
2108 #define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800
2109 #define CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK 0x2038
2110 #define CLK_CON_GAT_GOUT_CORE_GIC_CLK 0x2040
2111 #define CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK 0x2044
2112 #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK 0x20e8
2113 #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN 0x20ec
2114 #define CLK_CON_GAT_GOUT_CORE_PDMA_ACLK 0x20f0
2115 #define CLK_CON_GAT_GOUT_CORE_SPDMA_ACLK 0x2124
2116 #define CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK 0x2128
2117 #define CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK 0x212c
2118 #define CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK 0x2130
2119
2120 static const unsigned long core_clk_regs[] __initconst = {
2121 PLL_CON0_MUX_CLKCMU_CORE_BUS_USER,
2122 PLL_CON0_MUX_CLKCMU_CORE_CCI_USER,
2123 PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER,
2124 PLL_CON0_MUX_CLKCMU_CORE_SSS_USER,
2125 CLK_CON_MUX_MUX_CLK_CORE_GIC,
2126 CLK_CON_DIV_DIV_CLK_CORE_BUSP,
2127 CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK,
2128 CLK_CON_GAT_GOUT_CORE_GIC_CLK,
2129 CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK,
2130 CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK,
2131 CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN,
2132 CLK_CON_GAT_GOUT_CORE_PDMA_ACLK,
2133 CLK_CON_GAT_GOUT_CORE_SPDMA_ACLK,
2134 CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK,
2135 CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK,
2136 CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK,
2137 };
2138
2139 /* List of parent clocks for Muxes in CMU_CORE */
2140 PNAME(mout_core_bus_user_p) = { "oscclk", "dout_core_bus" };
2141 PNAME(mout_core_cci_user_p) = { "oscclk", "dout_core_cci" };
2142 PNAME(mout_core_mmc_embd_user_p) = { "oscclk", "dout_core_mmc_embd" };
2143 PNAME(mout_core_sss_user_p) = { "oscclk", "dout_core_sss" };
2144 PNAME(mout_core_gic_p) = { "dout_core_busp", "oscclk" };
2145
2146 static const struct samsung_mux_clock core_mux_clks[] __initconst = {
2147 MUX(CLK_MOUT_CORE_BUS_USER, "mout_core_bus_user", mout_core_bus_user_p,
2148 PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 4, 1),
2149 MUX(CLK_MOUT_CORE_CCI_USER, "mout_core_cci_user", mout_core_cci_user_p,
2150 PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, 4, 1),
2151 MUX_F(CLK_MOUT_CORE_MMC_EMBD_USER, "mout_core_mmc_embd_user",
2152 mout_core_mmc_embd_user_p, PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER,
2153 4, 1, CLK_SET_RATE_PARENT, 0),
2154 MUX(CLK_MOUT_CORE_SSS_USER, "mout_core_sss_user", mout_core_sss_user_p,
2155 PLL_CON0_MUX_CLKCMU_CORE_SSS_USER, 4, 1),
2156 MUX(CLK_MOUT_CORE_GIC, "mout_core_gic", mout_core_gic_p,
2157 CLK_CON_MUX_MUX_CLK_CORE_GIC, 0, 1),
2158 };
2159
2160 static const struct samsung_div_clock core_div_clks[] __initconst = {
2161 DIV(CLK_DOUT_CORE_BUSP, "dout_core_busp", "mout_core_bus_user",
2162 CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 2),
2163 };
2164
2165 static const struct samsung_gate_clock core_gate_clks[] __initconst = {
2166 /* CCI (interconnect) clock must be always running */
2167 GATE(CLK_GOUT_CCI_ACLK, "gout_cci_aclk", "mout_core_cci_user",
2168 CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 21, CLK_IS_CRITICAL, 0),
2169 /* GIC (interrupt controller) clock must be always running */
2170 GATE(CLK_GOUT_GIC_CLK, "gout_gic_clk", "mout_core_gic",
2171 CLK_CON_GAT_GOUT_CORE_GIC_CLK, 21, CLK_IS_CRITICAL, 0),
2172 GATE(CLK_GOUT_MMC_EMBD_ACLK, "gout_mmc_embd_aclk", "dout_core_busp",
2173 CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK, 21, 0, 0),
2174 GATE(CLK_GOUT_MMC_EMBD_SDCLKIN, "gout_mmc_embd_sdclkin",
2175 "mout_core_mmc_embd_user", CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN,
2176 21, CLK_SET_RATE_PARENT, 0),
2177 GATE(CLK_GOUT_PDMA_CORE_ACLK, "gout_pdma_core_aclk",
2178 "mout_core_bus_user", CLK_CON_GAT_GOUT_CORE_PDMA_ACLK, 21, 0, 0),
2179 GATE(CLK_GOUT_SPDMA_CORE_ACLK, "gout_spdma_core_aclk",
2180 "mout_core_bus_user", CLK_CON_GAT_GOUT_CORE_SPDMA_ACLK, 21, 0, 0),
2181 GATE(CLK_GOUT_SSS_ACLK, "gout_sss_aclk", "mout_core_sss_user",
2182 CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK, 21, 0, 0),
2183 GATE(CLK_GOUT_SSS_PCLK, "gout_sss_pclk", "dout_core_busp",
2184 CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK, 21, 0, 0),
2185 /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
2186 GATE(CLK_GOUT_GPIO_CORE_PCLK, "gout_gpio_core_pclk", "dout_core_busp",
2187 CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK, 21, CLK_IGNORE_UNUSED, 0),
2188 GATE(CLK_GOUT_SYSREG_CORE_PCLK, "gout_sysreg_core_pclk",
2189 "dout_core_busp",
2190 CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK, 21, 0, 0),
2191 };
2192
2193 static const struct samsung_cmu_info core_cmu_info __initconst = {
2194 .mux_clks = core_mux_clks,
2195 .nr_mux_clks = ARRAY_SIZE(core_mux_clks),
2196 .div_clks = core_div_clks,
2197 .nr_div_clks = ARRAY_SIZE(core_div_clks),
2198 .gate_clks = core_gate_clks,
2199 .nr_gate_clks = ARRAY_SIZE(core_gate_clks),
2200 .nr_clk_ids = CLKS_NR_CORE,
2201 .clk_regs = core_clk_regs,
2202 .nr_clk_regs = ARRAY_SIZE(core_clk_regs),
2203 .clk_name = "dout_core_bus",
2204 };
2205
2206 /* ---- CMU_DPU ------------------------------------------------------------- */
2207
2208 /* Register Offset definitions for CMU_DPU (0x13000000) */
2209 #define PLL_CON0_MUX_CLKCMU_DPU_USER 0x0600
2210 #define CLK_CON_DIV_DIV_CLK_DPU_BUSP 0x1800
2211 #define CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK 0x2004
2212 #define CLK_CON_GAT_GOUT_DPU_ACLK_DECON0 0x2010
2213 #define CLK_CON_GAT_GOUT_DPU_ACLK_DMA 0x2014
2214 #define CLK_CON_GAT_GOUT_DPU_ACLK_DPP 0x2018
2215 #define CLK_CON_GAT_GOUT_DPU_PPMU_ACLK 0x2028
2216 #define CLK_CON_GAT_GOUT_DPU_PPMU_PCLK 0x202c
2217 #define CLK_CON_GAT_GOUT_DPU_SMMU_CLK 0x2038
2218 #define CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK 0x203c
2219
2220 static const unsigned long dpu_clk_regs[] __initconst = {
2221 PLL_CON0_MUX_CLKCMU_DPU_USER,
2222 CLK_CON_DIV_DIV_CLK_DPU_BUSP,
2223 CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK,
2224 CLK_CON_GAT_GOUT_DPU_ACLK_DECON0,
2225 CLK_CON_GAT_GOUT_DPU_ACLK_DMA,
2226 CLK_CON_GAT_GOUT_DPU_ACLK_DPP,
2227 CLK_CON_GAT_GOUT_DPU_PPMU_ACLK,
2228 CLK_CON_GAT_GOUT_DPU_PPMU_PCLK,
2229 CLK_CON_GAT_GOUT_DPU_SMMU_CLK,
2230 CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK,
2231 };
2232
2233 /* List of parent clocks for Muxes in CMU_DPU */
2234 PNAME(mout_dpu_user_p) = { "oscclk", "dout_dpu" };
2235
2236 static const struct samsung_mux_clock dpu_mux_clks[] __initconst = {
2237 MUX(CLK_MOUT_DPU_USER, "mout_dpu_user", mout_dpu_user_p,
2238 PLL_CON0_MUX_CLKCMU_DPU_USER, 4, 1),
2239 };
2240
2241 static const struct samsung_div_clock dpu_div_clks[] __initconst = {
2242 DIV(CLK_DOUT_DPU_BUSP, "dout_dpu_busp", "mout_dpu_user",
2243 CLK_CON_DIV_DIV_CLK_DPU_BUSP, 0, 3),
2244 };
2245
2246 static const struct samsung_gate_clock dpu_gate_clks[] __initconst = {
2247 /* TODO: Should be enabled in DSIM driver */
2248 GATE(CLK_GOUT_DPU_CMU_DPU_PCLK, "gout_dpu_cmu_dpu_pclk",
2249 "dout_dpu_busp",
2250 CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK, 21, CLK_IGNORE_UNUSED, 0),
2251 GATE(CLK_GOUT_DPU_DECON0_ACLK, "gout_dpu_decon0_aclk", "mout_dpu_user",
2252 CLK_CON_GAT_GOUT_DPU_ACLK_DECON0, 21, 0, 0),
2253 GATE(CLK_GOUT_DPU_DMA_ACLK, "gout_dpu_dma_aclk", "mout_dpu_user",
2254 CLK_CON_GAT_GOUT_DPU_ACLK_DMA, 21, 0, 0),
2255 GATE(CLK_GOUT_DPU_DPP_ACLK, "gout_dpu_dpp_aclk", "mout_dpu_user",
2256 CLK_CON_GAT_GOUT_DPU_ACLK_DPP, 21, 0, 0),
2257 GATE(CLK_GOUT_DPU_PPMU_ACLK, "gout_dpu_ppmu_aclk", "mout_dpu_user",
2258 CLK_CON_GAT_GOUT_DPU_PPMU_ACLK, 21, 0, 0),
2259 GATE(CLK_GOUT_DPU_PPMU_PCLK, "gout_dpu_ppmu_pclk", "dout_dpu_busp",
2260 CLK_CON_GAT_GOUT_DPU_PPMU_PCLK, 21, 0, 0),
2261 GATE(CLK_GOUT_DPU_SMMU_CLK, "gout_dpu_smmu_clk", "mout_dpu_user",
2262 CLK_CON_GAT_GOUT_DPU_SMMU_CLK, 21, 0, 0),
2263 GATE(CLK_GOUT_DPU_SYSREG_PCLK, "gout_dpu_sysreg_pclk", "dout_dpu_busp",
2264 CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK, 21, 0, 0),
2265 };
2266
2267 static const struct samsung_cmu_info dpu_cmu_info __initconst = {
2268 .mux_clks = dpu_mux_clks,
2269 .nr_mux_clks = ARRAY_SIZE(dpu_mux_clks),
2270 .div_clks = dpu_div_clks,
2271 .nr_div_clks = ARRAY_SIZE(dpu_div_clks),
2272 .gate_clks = dpu_gate_clks,
2273 .nr_gate_clks = ARRAY_SIZE(dpu_gate_clks),
2274 .nr_clk_ids = CLKS_NR_DPU,
2275 .clk_regs = dpu_clk_regs,
2276 .nr_clk_regs = ARRAY_SIZE(dpu_clk_regs),
2277 .clk_name = "dout_dpu",
2278 };
2279
2280 /* ---- platform_driver ----------------------------------------------------- */
2281
exynos850_cmu_probe(struct platform_device * pdev)2282 static int __init exynos850_cmu_probe(struct platform_device *pdev)
2283 {
2284 const struct samsung_cmu_info *info;
2285 struct device *dev = &pdev->dev;
2286
2287 info = of_device_get_match_data(dev);
2288 exynos_arm64_register_cmu(dev, dev->of_node, info);
2289
2290 return 0;
2291 }
2292
2293 static const struct of_device_id exynos850_cmu_of_match[] = {
2294 {
2295 .compatible = "samsung,exynos850-cmu-apm",
2296 .data = &apm_cmu_info,
2297 }, {
2298 .compatible = "samsung,exynos850-cmu-aud",
2299 .data = &aud_cmu_info,
2300 }, {
2301 .compatible = "samsung,exynos850-cmu-cmgp",
2302 .data = &cmgp_cmu_info,
2303 }, {
2304 .compatible = "samsung,exynos850-cmu-g3d",
2305 .data = &g3d_cmu_info,
2306 }, {
2307 .compatible = "samsung,exynos850-cmu-hsi",
2308 .data = &hsi_cmu_info,
2309 }, {
2310 .compatible = "samsung,exynos850-cmu-is",
2311 .data = &is_cmu_info,
2312 }, {
2313 .compatible = "samsung,exynos850-cmu-mfcmscl",
2314 .data = &mfcmscl_cmu_info,
2315 }, {
2316 .compatible = "samsung,exynos850-cmu-core",
2317 .data = &core_cmu_info,
2318 }, {
2319 .compatible = "samsung,exynos850-cmu-dpu",
2320 .data = &dpu_cmu_info,
2321 }, {
2322 },
2323 };
2324
2325 static struct platform_driver exynos850_cmu_driver __refdata = {
2326 .driver = {
2327 .name = "exynos850-cmu",
2328 .of_match_table = exynos850_cmu_of_match,
2329 .suppress_bind_attrs = true,
2330 },
2331 .probe = exynos850_cmu_probe,
2332 };
2333
exynos850_cmu_init(void)2334 static int __init exynos850_cmu_init(void)
2335 {
2336 return platform_driver_register(&exynos850_cmu_driver);
2337 }
2338 core_initcall(exynos850_cmu_init);
2339