xref: /linux/include/dt-bindings/clock/sprd,sc9860-clk.h (revision c1144d29f405ce1f4e6ede6482beb3d0d09750c6)
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 //
3 // Spreadtrum SC9860 platform clocks
4 //
5 // Copyright (C) 2017, Spreadtrum Communications Inc.
6 
7 #ifndef _DT_BINDINGS_CLK_SC9860_H_
8 #define _DT_BINDINGS_CLK_SC9860_H_
9 
10 #define	CLK_FAC_4M		0
11 #define	CLK_FAC_2M		1
12 #define	CLK_FAC_1M		2
13 #define	CLK_FAC_250K		3
14 #define	CLK_FAC_RPLL0_26M	4
15 #define	CLK_FAC_RPLL1_26M	5
16 #define	CLK_FAC_RCO25M		6
17 #define	CLK_FAC_RCO4M		7
18 #define	CLK_FAC_RCO2M		8
19 #define	CLK_FAC_3K2		9
20 #define	CLK_FAC_1K		10
21 #define	CLK_MPLL0_GATE		11
22 #define	CLK_MPLL1_GATE		12
23 #define	CLK_DPLL0_GATE		13
24 #define	CLK_DPLL1_GATE		14
25 #define	CLK_LTEPLL0_GATE	15
26 #define	CLK_TWPLL_GATE		16
27 #define	CLK_LTEPLL1_GATE	17
28 #define	CLK_RPLL0_GATE		18
29 #define	CLK_RPLL1_GATE		19
30 #define	CLK_CPPLL_GATE		20
31 #define	CLK_GPLL_GATE		21
32 #define CLK_PMU_GATE_NUM	(CLK_GPLL_GATE + 1)
33 
34 #define	CLK_MPLL0		0
35 #define	CLK_MPLL1		1
36 #define	CLK_DPLL0		2
37 #define	CLK_DPLL1		3
38 #define	CLK_RPLL0		4
39 #define	CLK_RPLL1		5
40 #define	CLK_TWPLL		6
41 #define	CLK_LTEPLL0		7
42 #define	CLK_LTEPLL1		8
43 #define	CLK_GPLL		9
44 #define	CLK_CPPLL		10
45 #define	CLK_GPLL_42M5		11
46 #define	CLK_TWPLL_768M		12
47 #define	CLK_TWPLL_384M		13
48 #define	CLK_TWPLL_192M		14
49 #define	CLK_TWPLL_96M		15
50 #define	CLK_TWPLL_48M		16
51 #define	CLK_TWPLL_24M		17
52 #define	CLK_TWPLL_12M		18
53 #define	CLK_TWPLL_512M		19
54 #define	CLK_TWPLL_256M		20
55 #define	CLK_TWPLL_128M		21
56 #define	CLK_TWPLL_64M		22
57 #define	CLK_TWPLL_307M2		23
58 #define	CLK_TWPLL_153M6		24
59 #define	CLK_TWPLL_76M8		25
60 #define	CLK_TWPLL_51M2		26
61 #define	CLK_TWPLL_38M4		27
62 #define	CLK_TWPLL_19M2		28
63 #define	CLK_L0_614M4		29
64 #define	CLK_L0_409M6		30
65 #define	CLK_L0_38M		31
66 #define	CLK_L1_38M		32
67 #define	CLK_RPLL0_192M		33
68 #define	CLK_RPLL0_96M		34
69 #define	CLK_RPLL0_48M		35
70 #define	CLK_RPLL1_468M		36
71 #define	CLK_RPLL1_192M		37
72 #define	CLK_RPLL1_96M		38
73 #define	CLK_RPLL1_64M		39
74 #define	CLK_RPLL1_48M		40
75 #define	CLK_DPLL0_50M		41
76 #define	CLK_DPLL1_50M		42
77 #define	CLK_CPPLL_50M		43
78 #define	CLK_M0_39M		44
79 #define	CLK_M1_63M		45
80 #define CLK_PLL_NUM		(CLK_M1_63M + 1)
81 
82 
83 #define	CLK_AP_APB		0
84 #define	CLK_AP_USB3		1
85 #define	CLK_UART0		2
86 #define	CLK_UART1		3
87 #define	CLK_UART2		4
88 #define	CLK_UART3		5
89 #define	CLK_UART4		6
90 #define	CLK_I2C0		7
91 #define	CLK_I2C1		8
92 #define	CLK_I2C2		9
93 #define	CLK_I2C3		10
94 #define	CLK_I2C4		11
95 #define	CLK_I2C5		12
96 #define	CLK_SPI0		13
97 #define	CLK_SPI1		14
98 #define	CLK_SPI2		15
99 #define	CLK_SPI3		16
100 #define	CLK_IIS0		17
101 #define	CLK_IIS1		18
102 #define	CLK_IIS2		19
103 #define	CLK_IIS3		20
104 #define CLK_AP_CLK_NUM		(CLK_IIS3 + 1)
105 
106 #define	CLK_AON_APB		0
107 #define	CLK_AUX0		1
108 #define	CLK_AUX1		2
109 #define	CLK_AUX2		3
110 #define	CLK_PROBE		4
111 #define	CLK_SP_AHB		5
112 #define	CLK_CCI			6
113 #define	CLK_GIC			7
114 #define	CLK_CSSYS		8
115 #define	CLK_SDIO0_2X		9
116 #define	CLK_SDIO1_2X		10
117 #define	CLK_SDIO2_2X		11
118 #define	CLK_EMMC_2X		12
119 #define	CLK_SDIO0_1X		13
120 #define	CLK_SDIO1_1X		14
121 #define	CLK_SDIO2_1X		15
122 #define	CLK_EMMC_1X		16
123 #define	CLK_ADI			17
124 #define	CLK_PWM0		18
125 #define	CLK_PWM1		19
126 #define	CLK_PWM2		20
127 #define	CLK_PWM3		21
128 #define	CLK_EFUSE		22
129 #define	CLK_CM3_UART0		23
130 #define	CLK_CM3_UART1		24
131 #define	CLK_THM			25
132 #define	CLK_CM3_I2C0		26
133 #define	CLK_CM3_I2C1		27
134 #define	CLK_CM4_SPI		28
135 #define	CLK_AON_I2C		29
136 #define	CLK_AVS			30
137 #define	CLK_CA53_DAP		31
138 #define	CLK_CA53_TS		32
139 #define	CLK_DJTAG_TCK		33
140 #define	CLK_PMU			34
141 #define	CLK_PMU_26M		35
142 #define	CLK_DEBOUNCE		36
143 #define	CLK_OTG2_REF		37
144 #define	CLK_USB3_REF		38
145 #define	CLK_AP_AXI		39
146 #define CLK_AON_PREDIV_NUM	(CLK_AP_AXI + 1)
147 
148 #define	CLK_USB3_EB		0
149 #define	CLK_USB3_SUSPEND_EB	1
150 #define	CLK_USB3_REF_EB		2
151 #define	CLK_DMA_EB		3
152 #define	CLK_SDIO0_EB		4
153 #define	CLK_SDIO1_EB		5
154 #define	CLK_SDIO2_EB		6
155 #define	CLK_EMMC_EB		7
156 #define	CLK_ROM_EB		8
157 #define	CLK_BUSMON_EB		9
158 #define	CLK_CC63S_EB		10
159 #define	CLK_CC63P_EB		11
160 #define	CLK_CE0_EB		12
161 #define	CLK_CE1_EB		13
162 #define CLK_APAHB_GATE_NUM	(CLK_CE1_EB + 1)
163 
164 #define	CLK_AVS_LIT_EB		0
165 #define	CLK_AVS_BIG_EB		1
166 #define	CLK_AP_INTC5_EB		2
167 #define	CLK_GPIO_EB		3
168 #define	CLK_PWM0_EB		4
169 #define	CLK_PWM1_EB		5
170 #define	CLK_PWM2_EB		6
171 #define	CLK_PWM3_EB		7
172 #define	CLK_KPD_EB		8
173 #define	CLK_AON_SYS_EB		9
174 #define	CLK_AP_SYS_EB		10
175 #define	CLK_AON_TMR_EB		11
176 #define	CLK_AP_TMR0_EB		12
177 #define	CLK_EFUSE_EB		13
178 #define	CLK_EIC_EB		14
179 #define	CLK_PUB1_REG_EB		15
180 #define	CLK_ADI_EB		16
181 #define	CLK_AP_INTC0_EB		17
182 #define	CLK_AP_INTC1_EB		18
183 #define	CLK_AP_INTC2_EB		19
184 #define	CLK_AP_INTC3_EB		20
185 #define	CLK_AP_INTC4_EB		21
186 #define	CLK_SPLK_EB		22
187 #define	CLK_MSPI_EB		23
188 #define	CLK_PUB0_REG_EB		24
189 #define	CLK_PIN_EB		25
190 #define	CLK_AON_CKG_EB		26
191 #define	CLK_GPU_EB		27
192 #define	CLK_APCPU_TS0_EB	28
193 #define	CLK_APCPU_TS1_EB	29
194 #define	CLK_DAP_EB		30
195 #define	CLK_I2C_EB		31
196 #define	CLK_PMU_EB		32
197 #define	CLK_THM_EB		33
198 #define	CLK_AUX0_EB		34
199 #define	CLK_AUX1_EB		35
200 #define	CLK_AUX2_EB		36
201 #define	CLK_PROBE_EB		37
202 #define	CLK_GPU0_AVS_EB		38
203 #define	CLK_GPU1_AVS_EB		39
204 #define	CLK_APCPU_WDG_EB	40
205 #define	CLK_AP_TMR1_EB		41
206 #define	CLK_AP_TMR2_EB		42
207 #define	CLK_DISP_EMC_EB		43
208 #define	CLK_ZIP_EMC_EB		44
209 #define	CLK_GSP_EMC_EB		45
210 #define	CLK_OSC_AON_EB		46
211 #define	CLK_LVDS_TRX_EB		47
212 #define	CLK_LVDS_TCXO_EB	48
213 #define	CLK_MDAR_EB		49
214 #define	CLK_RTC4M0_CAL_EB	50
215 #define	CLK_RCT100M_CAL_EB	51
216 #define	CLK_DJTAG_EB		52
217 #define	CLK_MBOX_EB		53
218 #define	CLK_AON_DMA_EB		54
219 #define	CLK_DBG_EMC_EB		55
220 #define	CLK_LVDS_PLL_DIV_EN	56
221 #define	CLK_DEF_EB		57
222 #define	CLK_AON_APB_RSV0	58
223 #define	CLK_ORP_JTAG_EB		59
224 #define	CLK_VSP_EB		60
225 #define	CLK_CAM_EB		61
226 #define	CLK_DISP_EB		62
227 #define	CLK_DBG_AXI_IF_EB	63
228 #define	CLK_SDIO0_2X_EN		64
229 #define	CLK_SDIO1_2X_EN		65
230 #define	CLK_SDIO2_2X_EN		66
231 #define	CLK_EMMC_2X_EN		67
232 #define	CLK_ARCH_RTC_EB		68
233 #define	CLK_KPB_RTC_EB		69
234 #define	CLK_AON_SYST_RTC_EB	70
235 #define	CLK_AP_SYST_RTC_EB	71
236 #define	CLK_AON_TMR_RTC_EB	72
237 #define	CLK_AP_TMR0_RTC_EB	73
238 #define	CLK_EIC_RTC_EB		74
239 #define	CLK_EIC_RTCDV5_EB	75
240 #define	CLK_AP_WDG_RTC_EB	76
241 #define	CLK_AP_TMR1_RTC_EB	77
242 #define	CLK_AP_TMR2_RTC_EB	78
243 #define	CLK_DCXO_TMR_RTC_EB	79
244 #define	CLK_BB_CAL_RTC_EB	80
245 #define	CLK_AVS_BIG_RTC_EB	81
246 #define	CLK_AVS_LIT_RTC_EB	82
247 #define	CLK_AVS_GPU0_RTC_EB	83
248 #define	CLK_AVS_GPU1_RTC_EB	84
249 #define	CLK_GPU_TS_EB		85
250 #define	CLK_RTCDV10_EB		86
251 #define	CLK_AON_GATE_NUM	(CLK_RTCDV10_EB + 1)
252 
253 #define	CLK_LIT_MCU		0
254 #define	CLK_BIG_MCU		1
255 #define CLK_AONSECURE_NUM	(CLK_BIG_MCU + 1)
256 
257 #define	CLK_AGCP_IIS0_EB	0
258 #define	CLK_AGCP_IIS1_EB	1
259 #define	CLK_AGCP_IIS2_EB	2
260 #define	CLK_AGCP_IIS3_EB	3
261 #define	CLK_AGCP_UART_EB	4
262 #define	CLK_AGCP_DMACP_EB	5
263 #define	CLK_AGCP_DMAAP_EB	6
264 #define	CLK_AGCP_ARC48K_EB	7
265 #define	CLK_AGCP_SRC44P1K_EB	8
266 #define	CLK_AGCP_MCDT_EB	9
267 #define	CLK_AGCP_VBCIFD_EB	10
268 #define	CLK_AGCP_VBC_EB		11
269 #define	CLK_AGCP_SPINLOCK_EB	12
270 #define	CLK_AGCP_ICU_EB		13
271 #define	CLK_AGCP_AP_ASHB_EB	14
272 #define	CLK_AGCP_CP_ASHB_EB	15
273 #define	CLK_AGCP_AUD_EB		16
274 #define	CLK_AGCP_AUDIF_EB	17
275 #define CLK_AGCP_GATE_NUM	(CLK_AGCP_AUDIF_EB + 1)
276 
277 #define	CLK_GPU			0
278 #define CLK_GPU_NUM		(CLK_GPU + 1)
279 
280 #define	CLK_AHB_VSP		0
281 #define	CLK_VSP			1
282 #define	CLK_VSP_ENC		2
283 #define	CLK_VPP			3
284 #define	CLK_VSP_26M		4
285 #define CLK_VSP_NUM		(CLK_VSP_26M + 1)
286 
287 #define	CLK_VSP_DEC_EB		0
288 #define	CLK_VSP_CKG_EB		1
289 #define	CLK_VSP_MMU_EB		2
290 #define	CLK_VSP_ENC_EB		3
291 #define	CLK_VPP_EB		4
292 #define	CLK_VSP_26M_EB		5
293 #define	CLK_VSP_AXI_GATE	6
294 #define	CLK_VSP_ENC_GATE	7
295 #define	CLK_VPP_AXI_GATE	8
296 #define	CLK_VSP_BM_GATE		9
297 #define	CLK_VSP_ENC_BM_GATE	10
298 #define	CLK_VPP_BM_GATE		11
299 #define CLK_VSP_GATE_NUM	(CLK_VPP_BM_GATE + 1)
300 
301 #define	CLK_AHB_CAM		0
302 #define	CLK_SENSOR0		1
303 #define	CLK_SENSOR1		2
304 #define	CLK_SENSOR2		3
305 #define	CLK_MIPI_CSI0_EB	4
306 #define	CLK_MIPI_CSI1_EB	5
307 #define CLK_CAM_NUM		(CLK_MIPI_CSI1_EB + 1)
308 
309 #define	CLK_DCAM0_EB		0
310 #define	CLK_DCAM1_EB		1
311 #define	CLK_ISP0_EB		2
312 #define	CLK_CSI0_EB		3
313 #define	CLK_CSI1_EB		4
314 #define	CLK_JPG0_EB		5
315 #define	CLK_JPG1_EB		6
316 #define	CLK_CAM_CKG_EB		7
317 #define	CLK_CAM_MMU_EB		8
318 #define	CLK_ISP1_EB		9
319 #define	CLK_CPP_EB		10
320 #define	CLK_MMU_PF_EB		11
321 #define	CLK_ISP2_EB		12
322 #define	CLK_DCAM2ISP_IF_EB	13
323 #define	CLK_ISP2DCAM_IF_EB	14
324 #define	CLK_ISP_LCLK_EB		15
325 #define	CLK_ISP_ICLK_EB		16
326 #define	CLK_ISP_MCLK_EB		17
327 #define	CLK_ISP_PCLK_EB		18
328 #define	CLK_ISP_ISP2DCAM_EB	19
329 #define	CLK_DCAM0_IF_EB		20
330 #define	CLK_CLK26M_IF_EB	21
331 #define	CLK_CPHY0_GATE		22
332 #define	CLK_MIPI_CSI0_GATE	23
333 #define	CLK_CPHY1_GATE		24
334 #define	CLK_MIPI_CSI1		25
335 #define	CLK_DCAM0_AXI_GATE	26
336 #define	CLK_DCAM1_AXI_GATE	27
337 #define	CLK_SENSOR0_GATE	28
338 #define	CLK_SENSOR1_GATE	29
339 #define	CLK_JPG0_AXI_GATE	30
340 #define	CLK_GPG1_AXI_GATE	31
341 #define	CLK_ISP0_AXI_GATE	32
342 #define	CLK_ISP1_AXI_GATE	33
343 #define	CLK_ISP2_AXI_GATE	34
344 #define	CLK_CPP_AXI_GATE	35
345 #define	CLK_D0_IF_AXI_GATE	36
346 #define	CLK_D2I_IF_AXI_GATE	37
347 #define	CLK_I2D_IF_AXI_GATE	38
348 #define	CLK_SPARE_AXI_GATE	39
349 #define	CLK_SENSOR2_GATE	40
350 #define	CLK_D0IF_IN_D_EN	41
351 #define	CLK_D1IF_IN_D_EN	42
352 #define	CLK_D0IF_IN_D2I_EN	43
353 #define	CLK_D1IF_IN_D2I_EN	44
354 #define	CLK_IA_IN_D2I_EN	45
355 #define	CLK_IB_IN_D2I_EN	46
356 #define	CLK_IC_IN_D2I_EN	47
357 #define	CLK_IA_IN_I_EN		48
358 #define	CLK_IB_IN_I_EN		49
359 #define	CLK_IC_IN_I_EN		50
360 #define CLK_CAM_GATE_NUM	(CLK_IC_IN_I_EN + 1)
361 
362 #define	CLK_AHB_DISP		0
363 #define	CLK_DISPC0_DPI		1
364 #define	CLK_DISPC1_DPI		2
365 #define CLK_DISP_NUM		(CLK_DISPC1_DPI + 1)
366 
367 #define	CLK_DISPC0_EB		0
368 #define	CLK_DISPC1_EB		1
369 #define	CLK_DISPC_MMU_EB	2
370 #define	CLK_GSP0_EB		3
371 #define	CLK_GSP1_EB		4
372 #define	CLK_GSP0_MMU_EB		5
373 #define	CLK_GSP1_MMU_EB		6
374 #define	CLK_DSI0_EB		7
375 #define	CLK_DSI1_EB		8
376 #define	CLK_DISP_CKG_EB		9
377 #define	CLK_DISP_GPU_EB		10
378 #define	CLK_GPU_MTX_EB		11
379 #define	CLK_GSP_MTX_EB		12
380 #define	CLK_TMC_MTX_EB		13
381 #define	CLK_DISPC_MTX_EB	14
382 #define	CLK_DPHY0_GATE		15
383 #define	CLK_DPHY1_GATE		16
384 #define	CLK_GSP0_A_GATE		17
385 #define	CLK_GSP1_A_GATE		18
386 #define	CLK_GSP0_F_GATE		19
387 #define	CLK_GSP1_F_GATE		20
388 #define	CLK_D_MTX_F_GATE	21
389 #define	CLK_D_MTX_A_GATE	22
390 #define	CLK_D_NOC_F_GATE	23
391 #define	CLK_D_NOC_A_GATE	24
392 #define	CLK_GSP_MTX_F_GATE	25
393 #define	CLK_GSP_MTX_A_GATE	26
394 #define	CLK_GSP_NOC_F_GATE	27
395 #define	CLK_GSP_NOC_A_GATE	28
396 #define	CLK_DISPM0IDLE_GATE	29
397 #define	CLK_GSPM0IDLE_GATE	30
398 #define CLK_DISP_GATE_NUM	(CLK_GSPM0IDLE_GATE + 1)
399 
400 #define	CLK_SIM0_EB		0
401 #define	CLK_IIS0_EB		1
402 #define	CLK_IIS1_EB		2
403 #define	CLK_IIS2_EB		3
404 #define	CLK_IIS3_EB		4
405 #define	CLK_SPI0_EB		5
406 #define	CLK_SPI1_EB		6
407 #define	CLK_SPI2_EB		7
408 #define	CLK_I2C0_EB		8
409 #define	CLK_I2C1_EB		9
410 #define	CLK_I2C2_EB		10
411 #define	CLK_I2C3_EB		11
412 #define	CLK_I2C4_EB		12
413 #define	CLK_I2C5_EB		13
414 #define	CLK_UART0_EB		14
415 #define	CLK_UART1_EB		15
416 #define	CLK_UART2_EB		16
417 #define	CLK_UART3_EB		17
418 #define	CLK_UART4_EB		18
419 #define	CLK_AP_CKG_EB		19
420 #define	CLK_SPI3_EB		20
421 #define CLK_APAPB_GATE_NUM	(CLK_SPI3_EB + 1)
422 
423 #endif /* _DT_BINDINGS_CLK_SC9860_H_ */
424