1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Helper routines for R-Car sound ADG. 4 // 5 // Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 6 #include <linux/clk-provider.h> 7 #include <linux/clkdev.h> 8 #include "rsnd.h" 9 10 #define CLKA 0 11 #define CLKB 1 12 #define CLKC 2 13 #define CLKI 3 14 #define CLKINMAX 4 15 16 #define CLKOUT 0 17 #define CLKOUT1 1 18 #define CLKOUT2 2 19 #define CLKOUT3 3 20 #define CLKOUTMAX 4 21 22 /* Maximum SSI count for per-SSI clocks */ 23 #define ADG_SSI_MAX 10 24 25 #define BRGCKR_31 (1 << 31) 26 #define BRRx_MASK(x) (0x3FF & x) 27 28 static struct rsnd_mod_ops adg_ops = { 29 .name = "adg", 30 }; 31 32 #define ADG_HZ_441 0 33 #define ADG_HZ_48 1 34 #define ADG_HZ_SIZE 2 35 36 struct rsnd_adg { 37 struct clk *adg; 38 struct clk *clkin[CLKINMAX]; 39 struct clk *clkout[CLKOUTMAX]; 40 /* RZ/G3E: per-SSI ADG clocks (adg-ssi-0 through adg-ssi-9) */ 41 struct clk *clk_adg_ssi[ADG_SSI_MAX]; 42 struct clk *clk_ssif_supply; 43 struct clk *null_clk; 44 struct clk_onecell_data onecell; 45 struct rsnd_mod mod; 46 int clkin_rate[CLKINMAX]; 47 bool ssi_clk_prepared; 48 int clkin_size; 49 int clkout_size; 50 u32 ckr; 51 u32 brga; 52 u32 brgb; 53 54 int brg_rate[ADG_HZ_SIZE]; /* BRGA / BRGB */ 55 }; 56 57 #define for_each_rsnd_clkin(pos, adg, i) \ 58 for (i = 0; \ 59 (i < adg->clkin_size) && \ 60 ((pos) = adg->clkin[i]); \ 61 i++) 62 #define for_each_rsnd_clkout(pos, adg, i) \ 63 for (i = 0; \ 64 (i < adg->clkout_size) && \ 65 ((pos) = adg->clkout[i]); \ 66 i++) 67 #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg) 68 69 static const char * const clkin_name_gen4[] = { 70 [CLKA] = "clkin", 71 }; 72 73 static const char * const clkin_name_gen2[] = { 74 [CLKA] = "clk_a", 75 [CLKB] = "clk_b", 76 [CLKC] = "clk_c", 77 [CLKI] = "clk_i", 78 }; 79 80 static const char * const clkin_name_rzg3e[] = { 81 [CLKA] = "audio-clka", 82 [CLKB] = "audio-clkb", 83 [CLKC] = "audio-clkc", 84 [CLKI] = "audio-clki", 85 }; 86 87 static const char * const clkout_name_gen2[] = { 88 [CLKOUT] = "audio_clkout", 89 [CLKOUT1] = "audio_clkout1", 90 [CLKOUT2] = "audio_clkout2", 91 [CLKOUT3] = "audio_clkout3", 92 }; 93 94 static u32 rsnd_adg_calculate_brgx(unsigned long div) 95 { 96 int i; 97 98 if (!div) 99 return 0; 100 101 for (i = 3; i >= 0; i--) { 102 int ratio = 2 << (i * 2); 103 if (0 == (div % ratio)) 104 return (u32)((i << 8) | ((div / ratio) - 1)); 105 } 106 107 return ~0; 108 } 109 110 static u32 rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream *io) 111 { 112 struct rsnd_mod *ssi_mod = rsnd_io_to_mod_ssi(io); 113 int id = rsnd_mod_id(ssi_mod); 114 int ws = id; 115 116 if (rsnd_ssi_is_pin_sharing(io)) { 117 switch (id) { 118 case 1: 119 case 2: 120 case 9: 121 ws = 0; 122 break; 123 case 4: 124 ws = 3; 125 break; 126 case 8: 127 ws = 7; 128 break; 129 } 130 } else { 131 /* 132 * SSI8 is not connected to ADG. 133 * Thus SSI9 is using ws = 8 134 */ 135 if (id == 9) 136 ws = 8; 137 } 138 139 return (0x6 + ws) << 8; 140 } 141 142 static void __rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv, 143 struct rsnd_dai_stream *io, 144 unsigned int target_rate, 145 unsigned int *target_val, 146 unsigned int *target_en) 147 { 148 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 149 struct device *dev = rsnd_priv_to_dev(priv); 150 int sel; 151 unsigned int val, en; 152 unsigned int min, diff; 153 unsigned int sel_rate[] = { 154 adg->clkin_rate[CLKA], /* 0000: CLKA */ 155 adg->clkin_rate[CLKB], /* 0001: CLKB */ 156 adg->clkin_rate[CLKC], /* 0010: CLKC */ 157 adg->brg_rate[ADG_HZ_441], /* 0011: BRGA */ 158 adg->brg_rate[ADG_HZ_48], /* 0100: BRGB */ 159 }; 160 161 min = ~0; 162 val = 0; 163 en = 0; 164 for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) { 165 int idx = 0; 166 int step = 2; 167 int div; 168 169 if (!sel_rate[sel]) 170 continue; 171 172 for (div = 2; div <= 98304; div += step) { 173 diff = abs(target_rate - sel_rate[sel] / div); 174 if (min > diff) { 175 val = (sel << 8) | idx; 176 min = diff; 177 en = 1 << (sel + 1); /* fixme */ 178 } 179 180 /* 181 * step of 0_0000 / 0_0001 / 0_1101 182 * are out of order 183 */ 184 if ((idx > 2) && (idx % 2)) 185 step *= 2; 186 if (idx == 0x1c) { 187 div += step; 188 step *= 2; 189 } 190 idx++; 191 } 192 } 193 194 if (min == ~0) { 195 dev_err(dev, "no Input clock\n"); 196 return; 197 } 198 199 *target_val = val; 200 if (target_en) 201 *target_en = en; 202 } 203 204 static void rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv, 205 struct rsnd_dai_stream *io, 206 unsigned int in_rate, 207 unsigned int out_rate, 208 u32 *in, u32 *out, u32 *en) 209 { 210 struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io); 211 unsigned int target_rate; 212 u32 *target_val; 213 u32 _in; 214 u32 _out; 215 u32 _en; 216 217 /* default = SSI WS */ 218 _in = 219 _out = rsnd_adg_ssi_ws_timing_gen2(io); 220 221 target_rate = 0; 222 target_val = NULL; 223 _en = 0; 224 if (runtime->rate != in_rate) { 225 target_rate = out_rate; 226 target_val = &_out; 227 } else if (runtime->rate != out_rate) { 228 target_rate = in_rate; 229 target_val = &_in; 230 } 231 232 if (target_rate) 233 __rsnd_adg_get_timesel_ratio(priv, io, 234 target_rate, 235 target_val, &_en); 236 237 if (in) 238 *in = _in; 239 if (out) 240 *out = _out; 241 if (en) 242 *en = _en; 243 } 244 245 int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod *cmd_mod, 246 struct rsnd_dai_stream *io) 247 { 248 struct rsnd_priv *priv = rsnd_mod_to_priv(cmd_mod); 249 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 250 struct rsnd_mod *adg_mod = rsnd_mod_get(adg); 251 int id = rsnd_mod_id(cmd_mod); 252 int shift = (id % 2) ? 16 : 0; 253 u32 mask, val; 254 255 rsnd_adg_get_timesel_ratio(priv, io, 256 rsnd_src_get_in_rate(priv, io), 257 rsnd_src_get_out_rate(priv, io), 258 NULL, &val, NULL); 259 260 val = val << shift; 261 mask = 0x0f1f << shift; 262 263 rsnd_mod_bset(adg_mod, CMDOUT_TIMSEL, mask, val); 264 265 return 0; 266 } 267 268 int rsnd_adg_set_src_timesel_gen2(struct rsnd_mod *src_mod, 269 struct rsnd_dai_stream *io, 270 unsigned int in_rate, 271 unsigned int out_rate) 272 { 273 struct rsnd_priv *priv = rsnd_mod_to_priv(src_mod); 274 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 275 struct rsnd_mod *adg_mod = rsnd_mod_get(adg); 276 u32 in, out; 277 u32 mask, en; 278 int id = rsnd_mod_id(src_mod); 279 int shift = (id % 2) ? 16 : 0; 280 281 rsnd_mod_make_sure(src_mod, RSND_MOD_SRC); 282 283 rsnd_adg_get_timesel_ratio(priv, io, 284 in_rate, out_rate, 285 &in, &out, &en); 286 287 in = in << shift; 288 out = out << shift; 289 mask = 0x0f1f << shift; 290 291 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL(id / 2), mask, in); 292 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL(id / 2), mask, out); 293 294 if (en) 295 rsnd_mod_bset(adg_mod, DIV_EN, en, en); 296 297 return 0; 298 } 299 300 static void rsnd_adg_set_ssi_clk(struct rsnd_mod *ssi_mod, u32 val) 301 { 302 struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod); 303 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 304 struct rsnd_mod *adg_mod = rsnd_mod_get(adg); 305 struct device *dev = rsnd_priv_to_dev(priv); 306 int id = rsnd_mod_id(ssi_mod); 307 int shift = (id % 4) * 8; 308 u32 mask = 0xFF << shift; 309 310 rsnd_mod_make_sure(ssi_mod, RSND_MOD_SSI); 311 312 val = val << shift; 313 314 /* 315 * SSI 8 is not connected to ADG. 316 * it works with SSI 7 317 */ 318 if (id == 8) 319 return; 320 321 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL(id / 4), mask, val); 322 323 dev_dbg(dev, "AUDIO_CLK_SEL is 0x%x\n", val); 324 } 325 326 int rsnd_adg_clk_query(struct rsnd_priv *priv, unsigned int rate) 327 { 328 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 329 struct clk *clk; 330 int i; 331 int sel_table[] = { 332 [CLKA] = 0x1, 333 [CLKB] = 0x2, 334 [CLKC] = 0x3, 335 [CLKI] = 0x0, 336 }; 337 338 /* 339 * find suitable clock from 340 * AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI. 341 */ 342 for_each_rsnd_clkin(clk, adg, i) 343 if (rate == adg->clkin_rate[i]) 344 return sel_table[i]; 345 346 /* 347 * find divided clock from BRGA/BRGB 348 */ 349 if (rate == adg->brg_rate[ADG_HZ_441]) 350 return 0x10; 351 352 if (rate == adg->brg_rate[ADG_HZ_48]) 353 return 0x20; 354 355 return -EIO; 356 } 357 358 int rsnd_adg_ssi_clk_stop(struct rsnd_mod *ssi_mod) 359 { 360 struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod); 361 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 362 int id = rsnd_mod_id(ssi_mod); 363 364 rsnd_adg_set_ssi_clk(ssi_mod, 0); 365 366 /* RZ/G3E: only disable here, unprepare is done in hw_free */ 367 clk_disable(adg->clk_adg_ssi[id]); 368 clk_disable(adg->clk_ssif_supply); 369 370 return 0; 371 } 372 373 int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mod, unsigned int rate) 374 { 375 struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod); 376 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 377 struct device *dev = rsnd_priv_to_dev(priv); 378 struct rsnd_mod *adg_mod = rsnd_mod_get(adg); 379 int id = rsnd_mod_id(ssi_mod); 380 int ret, data; 381 u32 ckr = 0; 382 383 data = rsnd_adg_clk_query(priv, rate); 384 if (data < 0) 385 return data; 386 387 rsnd_adg_set_ssi_clk(ssi_mod, data); 388 389 ckr = adg->ckr & ~BRGCKR_31; 390 if (0 == (rate % 8000)) 391 ckr |= BRGCKR_31; /* use BRGB output = 48kHz */ 392 if (ckr != adg->ckr) { 393 rsnd_mod_bset(adg_mod, BRGCKR, 0x80770000, adg->ckr); 394 adg->ckr = ckr; 395 } 396 397 dev_dbg(dev, "CLKOUT is based on BRG%c (= %dHz)\n", 398 (ckr) ? 'B' : 'A', 399 (ckr) ? adg->brg_rate[ADG_HZ_48] : 400 adg->brg_rate[ADG_HZ_441]); 401 402 /* 403 * RZ/G3E: enable per-SSI and supply clocks 404 */ 405 ret = clk_enable(adg->clk_adg_ssi[id]); 406 if (ret) { 407 dev_err(dev, "Cannot enable adg-ssi-%d ADG clock\n", id); 408 return ret; 409 } 410 411 ret = clk_enable(adg->clk_ssif_supply); 412 if (ret) { 413 dev_err(dev, "Cannot enable SSIF supply clock\n"); 414 clk_disable(adg->clk_adg_ssi[id]); 415 return ret; 416 } 417 418 return 0; 419 } 420 421 static int rsnd_adg_ssi_clk_prepare(struct rsnd_adg *adg) 422 { 423 int i, ret; 424 425 if (adg->ssi_clk_prepared) 426 return 0; 427 428 for (i = 0; i < ADG_SSI_MAX; i++) { 429 ret = clk_prepare(adg->clk_adg_ssi[i]); 430 if (ret) 431 goto unwind; 432 } 433 ret = clk_prepare(adg->clk_ssif_supply); 434 if (ret) 435 goto unwind; 436 437 adg->ssi_clk_prepared = true; 438 return 0; 439 440 unwind: 441 while (i--) 442 clk_unprepare(adg->clk_adg_ssi[i]); 443 return ret; 444 } 445 446 static void rsnd_adg_ssi_clk_unprepare(struct rsnd_adg *adg) 447 { 448 int i; 449 450 if (!adg->ssi_clk_prepared) 451 return; 452 adg->ssi_clk_prepared = false; 453 454 clk_unprepare(adg->clk_ssif_supply); 455 for (i = 0; i < ADG_SSI_MAX; i++) 456 clk_unprepare(adg->clk_adg_ssi[i]); 457 } 458 459 int rsnd_adg_clk_control(struct rsnd_priv *priv, int enable) 460 { 461 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 462 struct rsnd_mod *adg_mod = rsnd_mod_get(adg); 463 struct clk *clk; 464 int ret = 0, i; 465 466 if (enable) { 467 ret = clk_prepare_enable(adg->adg); 468 if (ret < 0) 469 return ret; 470 471 rsnd_mod_bset(adg_mod, BRGCKR, 0x80770000, adg->ckr); 472 rsnd_mod_write(adg_mod, BRRA, adg->brga); 473 rsnd_mod_write(adg_mod, BRRB, adg->brgb); 474 } 475 476 for_each_rsnd_clkin(clk, adg, i) { 477 if (enable) { 478 ret = clk_prepare_enable(clk); 479 480 /* 481 * We shouldn't use clk_get_rate() under 482 * atomic context. Let's keep it when 483 * rsnd_adg_clk_enable() was called 484 */ 485 if (ret < 0) 486 break; 487 488 adg->clkin_rate[i] = clk_get_rate(clk); 489 } else { 490 if (adg->clkin_rate[i]) 491 clk_disable_unprepare(clk); 492 493 adg->clkin_rate[i] = 0; 494 } 495 } 496 497 /* 498 * rsnd_adg_clk_enable() might return error (_disable() will not). 499 * We need to rollback in such case 500 */ 501 /* 502 * RZ/G3E per-SSI ADG and SSIF supply clocks. 503 * 504 * Follow the same style as for_each_rsnd_clkin() above: on enable, 505 * try to prepare every clock and accumulate the error. On disable, 506 * unprepare every clock. Absent optional clocks are NULL, for 507 * which clk_prepare() and clk_unprepare() are no-ops. 508 */ 509 if (enable) { 510 int sub_ret = rsnd_adg_ssi_clk_prepare(adg); 511 512 /* Preserve the first error from the clkin loop above. */ 513 if (sub_ret && !ret) 514 ret = sub_ret; 515 } else { 516 rsnd_adg_ssi_clk_unprepare(adg); 517 } 518 519 /* 520 * rsnd_adg_clk_enable() might return error (_disable() will not). 521 * We need to rollback in such case 522 */ 523 if (ret < 0) 524 rsnd_adg_clk_disable(priv); 525 526 /* disable adg */ 527 if (!enable) 528 clk_disable_unprepare(adg->adg); 529 530 return ret; 531 } 532 533 static struct clk *rsnd_adg_create_null_clk(struct rsnd_priv *priv, 534 const char * const name, 535 const char *parent) 536 { 537 struct device *dev = rsnd_priv_to_dev(priv); 538 struct clk *clk; 539 540 clk = clk_register_fixed_rate(dev, name, parent, 0, 0); 541 if (IS_ERR_OR_NULL(clk)) { 542 dev_err(dev, "create null clk error\n"); 543 return ERR_CAST(clk); 544 } 545 546 return clk; 547 } 548 549 static struct clk *rsnd_adg_null_clk_get(struct rsnd_priv *priv) 550 { 551 struct rsnd_adg *adg = priv->adg; 552 553 if (!adg->null_clk) { 554 static const char * const name = "rsnd_adg_null"; 555 556 adg->null_clk = rsnd_adg_create_null_clk(priv, name, NULL); 557 } 558 559 return adg->null_clk; 560 } 561 562 static void rsnd_adg_null_clk_clean(struct rsnd_priv *priv) 563 { 564 struct rsnd_adg *adg = priv->adg; 565 566 if (adg->null_clk) 567 clk_unregister_fixed_rate(adg->null_clk); 568 } 569 570 static int rsnd_adg_get_clkin(struct rsnd_priv *priv) 571 { 572 struct rsnd_adg *adg = priv->adg; 573 struct device *dev = rsnd_priv_to_dev(priv); 574 struct clk *clk; 575 const char * const *clkin_name; 576 int clkin_size; 577 int i; 578 579 clkin_name = clkin_name_gen2; 580 clkin_size = ARRAY_SIZE(clkin_name_gen2); 581 if (rsnd_is_gen4(priv)) { 582 clkin_name = clkin_name_gen4; 583 clkin_size = ARRAY_SIZE(clkin_name_gen4); 584 } else if (rsnd_is_rzg3e(priv)) { 585 clkin_name = clkin_name_rzg3e; 586 clkin_size = ARRAY_SIZE(clkin_name_rzg3e); 587 } 588 589 /* 590 * get adg 591 * No "adg" is not error 592 */ 593 clk = devm_clk_get(dev, "adg"); 594 if (IS_ERR_OR_NULL(clk)) 595 clk = rsnd_adg_null_clk_get(priv); 596 adg->adg = clk; 597 598 /* get clkin */ 599 for (i = 0; i < clkin_size; i++) { 600 clk = devm_clk_get(dev, clkin_name[i]); 601 602 if (IS_ERR_OR_NULL(clk)) 603 clk = rsnd_adg_null_clk_get(priv); 604 if (IS_ERR_OR_NULL(clk)) 605 goto err; 606 607 adg->clkin[i] = clk; 608 } 609 610 adg->clkin_size = clkin_size; 611 612 return 0; 613 614 err: 615 dev_err(dev, "adg clock IN get failed\n"); 616 617 rsnd_adg_null_clk_clean(priv); 618 619 return -EIO; 620 } 621 622 static void rsnd_adg_unregister_clkout(struct rsnd_priv *priv) 623 { 624 struct rsnd_adg *adg = priv->adg; 625 struct clk *clk; 626 int i; 627 628 for_each_rsnd_clkout(clk, adg, i) 629 clk_unregister_fixed_rate(clk); 630 } 631 632 static int rsnd_adg_get_clkout(struct rsnd_priv *priv) 633 { 634 struct rsnd_adg *adg = priv->adg; 635 struct clk *clk; 636 struct device *dev = rsnd_priv_to_dev(priv); 637 struct device_node *np = dev->of_node; 638 struct property *prop; 639 u32 ckr, brgx, brga, brgb; 640 u32 req_rate[ADG_HZ_SIZE] = {}; 641 uint32_t count = 0; 642 unsigned long req_Hz[ADG_HZ_SIZE]; 643 int clkout_size; 644 int i, req_size; 645 int approximate = 0; 646 const char *parent_clk_name = NULL; 647 const char * const *clkout_name; 648 int brg_table[] = { 649 [CLKA] = 0x0, 650 [CLKB] = 0x1, 651 [CLKC] = 0x4, 652 [CLKI] = 0x2, 653 }; 654 655 ckr = 0; 656 brga = 0xff; /* default */ 657 brgb = 0xff; /* default */ 658 659 /* 660 * ADG supports BRRA/BRRB output only 661 * this means all clkout0/1/2/3 will be same rate 662 */ 663 prop = of_find_property(np, "clock-frequency", NULL); 664 if (!prop) 665 goto rsnd_adg_get_clkout_end; 666 667 req_size = prop->length / sizeof(u32); 668 if (req_size > ADG_HZ_SIZE) { 669 dev_err(dev, "too many clock-frequency\n"); 670 return -EINVAL; 671 } 672 673 of_property_read_u32_array(np, "clock-frequency", req_rate, req_size); 674 req_Hz[ADG_HZ_48] = 0; 675 req_Hz[ADG_HZ_441] = 0; 676 for (i = 0; i < req_size; i++) { 677 if (0 == (req_rate[i] % 44100)) 678 req_Hz[ADG_HZ_441] = req_rate[i]; 679 if (0 == (req_rate[i] % 48000)) 680 req_Hz[ADG_HZ_48] = req_rate[i]; 681 } 682 683 /* 684 * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC 685 * have 44.1kHz or 48kHz base clocks for now. 686 * 687 * SSI itself can divide parent clock by 1/1 - 1/16 688 * see 689 * rsnd_adg_ssi_clk_try_start() 690 * rsnd_ssi_master_clk_start() 691 */ 692 693 /* 694 * [APPROXIMATE] 695 * 696 * clk_i (internal clock) can't create accurate rate, it will be approximate rate. 697 * 698 * <Note> 699 * 700 * clk_i needs x2 of required maximum rate. 701 * see 702 * - Minimum division of BRRA/BRRB 703 * - rsnd_ssi_clk_query() 704 * 705 * Sample Settings for TDM 8ch, 32bit width 706 * 707 * 8(ch) x 32(bit) x 44100(Hz) x 2<Note> = 22579200 708 * 8(ch) x 32(bit) x 48000(Hz) x 2<Note> = 24576000 709 * 710 * clock-frequency = <22579200 24576000>; 711 */ 712 for_each_rsnd_clkin(clk, adg, i) { 713 u32 rate, div; 714 715 rate = clk_get_rate(clk); 716 717 if (0 == rate) /* not used */ 718 continue; 719 720 /* BRGA */ 721 722 if (i == CLKI) 723 /* see [APPROXIMATE] */ 724 rate = (clk_get_rate(clk) / req_Hz[ADG_HZ_441]) * req_Hz[ADG_HZ_441]; 725 if (!adg->brg_rate[ADG_HZ_441] && req_Hz[ADG_HZ_441] && (0 == rate % 44100)) { 726 div = rate / req_Hz[ADG_HZ_441]; 727 brgx = rsnd_adg_calculate_brgx(div); 728 if (BRRx_MASK(brgx) == brgx) { 729 brga = brgx; 730 adg->brg_rate[ADG_HZ_441] = rate / div; 731 ckr |= brg_table[i] << 20; 732 if (req_Hz[ADG_HZ_441]) 733 parent_clk_name = __clk_get_name(clk); 734 if (i == CLKI) 735 approximate = 1; 736 } 737 } 738 739 /* BRGB */ 740 741 if (i == CLKI) 742 /* see [APPROXIMATE] */ 743 rate = (clk_get_rate(clk) / req_Hz[ADG_HZ_48]) * req_Hz[ADG_HZ_48]; 744 if (!adg->brg_rate[ADG_HZ_48] && req_Hz[ADG_HZ_48] && (0 == rate % 48000)) { 745 div = rate / req_Hz[ADG_HZ_48]; 746 brgx = rsnd_adg_calculate_brgx(div); 747 if (BRRx_MASK(brgx) == brgx) { 748 brgb = brgx; 749 adg->brg_rate[ADG_HZ_48] = rate / div; 750 ckr |= brg_table[i] << 16; 751 if (req_Hz[ADG_HZ_48]) 752 parent_clk_name = __clk_get_name(clk); 753 if (i == CLKI) 754 approximate = 1; 755 } 756 } 757 } 758 759 if (!(adg->brg_rate[ADG_HZ_48] && req_Hz[ADG_HZ_48]) && 760 !(adg->brg_rate[ADG_HZ_441] && req_Hz[ADG_HZ_441])) 761 goto rsnd_adg_get_clkout_end; 762 763 if (approximate) 764 dev_info(dev, "It uses CLK_I as approximate rate"); 765 766 clkout_name = clkout_name_gen2; 767 clkout_size = ARRAY_SIZE(clkout_name_gen2); 768 if (rsnd_is_gen4(priv)) 769 clkout_size = 1; /* reuse clkout_name_gen2[] */ 770 771 /* 772 * ADG supports BRRA/BRRB output only. 773 * this means all clkout0/1/2/3 will be * same rate 774 */ 775 776 of_property_read_u32(np, "#clock-cells", &count); 777 /* 778 * for clkout 779 */ 780 if (!count) { 781 clk = clk_register_fixed_rate(dev, clkout_name[CLKOUT], 782 parent_clk_name, 0, req_rate[0]); 783 if (IS_ERR_OR_NULL(clk)) 784 goto err; 785 786 adg->clkout[CLKOUT] = clk; 787 adg->clkout_size = 1; 788 of_clk_add_provider(np, of_clk_src_simple_get, clk); 789 } 790 /* 791 * for clkout0/1/2/3 792 */ 793 else { 794 for (i = 0; i < clkout_size; i++) { 795 clk = clk_register_fixed_rate(dev, clkout_name[i], 796 parent_clk_name, 0, 797 req_rate[0]); 798 if (IS_ERR_OR_NULL(clk)) 799 goto err; 800 801 adg->clkout[i] = clk; 802 } 803 adg->onecell.clks = adg->clkout; 804 adg->onecell.clk_num = clkout_size; 805 adg->clkout_size = clkout_size; 806 of_clk_add_provider(np, of_clk_src_onecell_get, 807 &adg->onecell); 808 } 809 810 rsnd_adg_get_clkout_end: 811 if (0 == (req_rate[0] % 8000)) 812 ckr |= BRGCKR_31; /* use BRGB output = 48kHz */ 813 814 adg->ckr = ckr; 815 adg->brga = brga; 816 adg->brgb = brgb; 817 818 return 0; 819 820 err: 821 dev_err(dev, "adg clock OUT get failed\n"); 822 823 rsnd_adg_unregister_clkout(priv); 824 825 return -EIO; 826 } 827 828 #if defined(DEBUG) || defined(CONFIG_DEBUG_FS) 829 __printf(3, 4) 830 static void dbg_msg(struct device *dev, struct seq_file *m, 831 const char *fmt, ...) 832 { 833 char msg[128]; 834 va_list args; 835 836 va_start(args, fmt); 837 vsnprintf(msg, sizeof(msg), fmt, args); 838 va_end(args); 839 840 if (m) 841 seq_puts(m, msg); 842 else 843 dev_dbg(dev, "%s", msg); 844 } 845 846 void rsnd_adg_clk_dbg_info(struct rsnd_priv *priv, struct seq_file *m) 847 { 848 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 849 struct device *dev = rsnd_priv_to_dev(priv); 850 struct clk *clk; 851 int i; 852 853 for_each_rsnd_clkin(clk, adg, i) 854 dbg_msg(dev, m, "%-18s : %pa : %ld\n", 855 __clk_get_name(clk), clk, clk_get_rate(clk)); 856 857 dbg_msg(dev, m, "BRGCKR = 0x%08x, BRRA/BRRB = 0x%x/0x%x\n", 858 adg->ckr, adg->brga, adg->brgb); 859 dbg_msg(dev, m, "BRGA (for 44100 base) = %d\n", adg->brg_rate[ADG_HZ_441]); 860 dbg_msg(dev, m, "BRGB (for 48000 base) = %d\n", adg->brg_rate[ADG_HZ_48]); 861 862 /* 863 * Actual CLKOUT will be exchanged in rsnd_adg_ssi_clk_try_start() 864 * by BRGCKR::BRGCKR_31 865 */ 866 for_each_rsnd_clkout(clk, adg, i) 867 dbg_msg(dev, m, "%-18s : %pa : %ld\n", 868 __clk_get_name(clk), clk, clk_get_rate(clk)); 869 } 870 #else 871 #define rsnd_adg_clk_dbg_info(priv, m) 872 #endif 873 874 static int rsnd_adg_get_ssi_clks(struct rsnd_priv *priv) 875 { 876 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 877 struct device *dev = rsnd_priv_to_dev(priv); 878 char name[16]; 879 int i; 880 881 /* SSIF supply clock */ 882 adg->clk_ssif_supply = devm_clk_get_optional(dev, "ssif_supply"); 883 if (IS_ERR(adg->clk_ssif_supply)) 884 return dev_err_probe(dev, PTR_ERR(adg->clk_ssif_supply), 885 "failed to get ssif_supply clock\n"); 886 887 /* Per-SSI ADG clocks (RZ/G3E-only; no legacy dotted form exists) */ 888 for (i = 0; i < ADG_SSI_MAX; i++) { 889 snprintf(name, sizeof(name), "adg-ssi-%d", i); 890 adg->clk_adg_ssi[i] = devm_clk_get_optional(dev, name); 891 if (IS_ERR(adg->clk_adg_ssi[i])) 892 return dev_err_probe(dev, PTR_ERR(adg->clk_adg_ssi[i]), 893 "failed to get %s clock\n", name); 894 } 895 896 return 0; 897 } 898 899 int rsnd_adg_probe(struct rsnd_priv *priv) 900 { 901 struct reset_control *rstc; 902 struct rsnd_adg *adg; 903 struct device *dev = rsnd_priv_to_dev(priv); 904 int ret; 905 906 adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL); 907 if (!adg) 908 return -ENOMEM; 909 910 rstc = devm_reset_control_get_optional_exclusive(dev, "adg"); 911 if (IS_ERR(rstc)) 912 return dev_err_probe(dev, PTR_ERR(rstc), "failed to get adg reset\n"); 913 914 ret = rsnd_mod_init(priv, &adg->mod, &adg_ops, NULL, rstc, 0, 0); 915 if (ret) 916 return ret; 917 918 priv->adg = adg; 919 920 ret = rsnd_adg_get_clkin(priv); 921 if (ret) 922 return ret; 923 924 ret = rsnd_adg_get_clkout(priv); 925 if (ret) 926 return ret; 927 928 /* RZ/G3E-specific: per-SSI ADG and SSIF supply clocks */ 929 ret = rsnd_adg_get_ssi_clks(priv); 930 if (ret) 931 return ret; 932 933 ret = rsnd_adg_clk_enable(priv); 934 if (ret) 935 return ret; 936 937 rsnd_adg_clk_dbg_info(priv, NULL); 938 939 return 0; 940 } 941 942 void rsnd_adg_remove(struct rsnd_priv *priv) 943 { 944 struct device *dev = rsnd_priv_to_dev(priv); 945 struct device_node *np = dev->of_node; 946 947 rsnd_adg_unregister_clkout(priv); 948 949 of_clk_del_provider(np); 950 951 rsnd_adg_clk_disable(priv); 952 953 /* It should be called after rsnd_adg_clk_disable() */ 954 rsnd_adg_null_clk_clean(priv); 955 } 956 957 static struct rsnd_mod *rsnd_adg_mod_get(struct rsnd_priv *priv) 958 { 959 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 960 961 if (!adg) 962 return NULL; 963 964 return rsnd_mod_get(adg); 965 } 966 967 void rsnd_adg_suspend(struct rsnd_priv *priv) 968 { 969 struct rsnd_mod *mod = rsnd_adg_mod_get(priv); 970 971 if (mod) 972 rsnd_suspend_clk_reset(mod->clk, mod->rstc); 973 } 974 975 void rsnd_adg_resume(struct rsnd_priv *priv) 976 { 977 struct rsnd_mod *mod = rsnd_adg_mod_get(priv); 978 979 if (mod) 980 rsnd_resume_clk_reset(mod->clk, mod->rstc); 981 } 982