1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs
4 *
5 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com
6 *
7 */
8 #include <linux/clk.h>
9 #include <linux/iopoll.h>
10 #include <linux/of.h>
11 #include <linux/module.h>
12 #include <linux/pm_runtime.h>
13 #include <linux/property.h>
14 #include <linux/regmap.h>
15 #include <linux/sys_soc.h>
16
17 #include "cqhci.h"
18 #include "sdhci-cqhci.h"
19 #include "sdhci-pltfm.h"
20
21 /* CTL_CFG Registers */
22 #define CTL_CFG_2 0x14
23 #define CTL_CFG_3 0x18
24
25 #define SLOTTYPE_MASK GENMASK(31, 30)
26 #define SLOTTYPE_EMBEDDED BIT(30)
27 #define TUNINGFORSDR50_MASK BIT(13)
28
29 /* PHY Registers */
30 #define PHY_CTRL1 0x100
31 #define PHY_CTRL2 0x104
32 #define PHY_CTRL3 0x108
33 #define PHY_CTRL4 0x10C
34 #define PHY_CTRL5 0x110
35 #define PHY_CTRL6 0x114
36 #define PHY_STAT1 0x130
37 #define PHY_STAT2 0x134
38
39 #define IOMUX_ENABLE_SHIFT 31
40 #define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT)
41 #define OTAPDLYENA_SHIFT 20
42 #define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT)
43 #define OTAPDLYSEL_SHIFT 12
44 #define OTAPDLYSEL_MASK GENMASK(15, 12)
45 #define STRBSEL_SHIFT 24
46 #define STRBSEL_4BIT_MASK GENMASK(27, 24)
47 #define STRBSEL_8BIT_MASK GENMASK(31, 24)
48 #define SEL50_SHIFT 8
49 #define SEL50_MASK BIT(SEL50_SHIFT)
50 #define SEL100_SHIFT 9
51 #define SEL100_MASK BIT(SEL100_SHIFT)
52 #define FREQSEL_SHIFT 8
53 #define FREQSEL_MASK GENMASK(10, 8)
54 #define CLKBUFSEL_SHIFT 0
55 #define CLKBUFSEL_MASK GENMASK(2, 0)
56 #define DLL_TRIM_ICP_SHIFT 4
57 #define DLL_TRIM_ICP_MASK GENMASK(7, 4)
58 #define DR_TY_SHIFT 20
59 #define DR_TY_MASK GENMASK(22, 20)
60 #define ENDLL_SHIFT 1
61 #define ENDLL_MASK BIT(ENDLL_SHIFT)
62 #define DLLRDY_SHIFT 0
63 #define DLLRDY_MASK BIT(DLLRDY_SHIFT)
64 #define PDB_SHIFT 0
65 #define PDB_MASK BIT(PDB_SHIFT)
66 #define CALDONE_SHIFT 1
67 #define CALDONE_MASK BIT(CALDONE_SHIFT)
68 #define RETRIM_SHIFT 17
69 #define RETRIM_MASK BIT(RETRIM_SHIFT)
70 #define SELDLYTXCLK_SHIFT 17
71 #define SELDLYTXCLK_MASK BIT(SELDLYTXCLK_SHIFT)
72 #define SELDLYRXCLK_SHIFT 16
73 #define SELDLYRXCLK_MASK BIT(SELDLYRXCLK_SHIFT)
74 #define ITAPDLYSEL_SHIFT 0
75 #define ITAPDLYSEL_MASK GENMASK(4, 0)
76 #define ITAPDLYENA_SHIFT 8
77 #define ITAPDLYENA_MASK BIT(ITAPDLYENA_SHIFT)
78 #define ITAPCHGWIN_SHIFT 9
79 #define ITAPCHGWIN_MASK BIT(ITAPCHGWIN_SHIFT)
80
81 #define DRIVER_STRENGTH_50_OHM 0x0
82 #define DRIVER_STRENGTH_33_OHM 0x1
83 #define DRIVER_STRENGTH_66_OHM 0x2
84 #define DRIVER_STRENGTH_100_OHM 0x3
85 #define DRIVER_STRENGTH_40_OHM 0x4
86
87 #define CLOCK_TOO_SLOW_HZ 50000000
88 #define SDHCI_AM654_AUTOSUSPEND_DELAY -1
89 #define RETRY_TUNING_MAX 10
90
91 /* Command Queue Host Controller Interface Base address */
92 #define SDHCI_AM654_CQE_BASE_ADDR 0x200
93
94 static const struct regmap_config sdhci_am654_regmap_config = {
95 .reg_bits = 32,
96 .val_bits = 32,
97 .reg_stride = 4,
98 };
99
100 struct timing_data {
101 const char *otap_binding;
102 const char *itap_binding;
103 u32 capability;
104 };
105
106 static const struct timing_data td[] = {
107 [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy",
108 "ti,itap-del-sel-legacy",
109 0},
110 [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs",
111 "ti,itap-del-sel-mmc-hs",
112 MMC_CAP_MMC_HIGHSPEED},
113 [MMC_TIMING_SD_HS] = {"ti,otap-del-sel-sd-hs",
114 "ti,itap-del-sel-sd-hs",
115 MMC_CAP_SD_HIGHSPEED},
116 [MMC_TIMING_UHS_SDR12] = {"ti,otap-del-sel-sdr12",
117 "ti,itap-del-sel-sdr12",
118 MMC_CAP_UHS_SDR12},
119 [MMC_TIMING_UHS_SDR25] = {"ti,otap-del-sel-sdr25",
120 "ti,itap-del-sel-sdr25",
121 MMC_CAP_UHS_SDR25},
122 [MMC_TIMING_UHS_SDR50] = {"ti,otap-del-sel-sdr50",
123 NULL,
124 MMC_CAP_UHS_SDR50},
125 [MMC_TIMING_UHS_SDR104] = {"ti,otap-del-sel-sdr104",
126 NULL,
127 MMC_CAP_UHS_SDR104},
128 [MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50",
129 "ti,itap-del-sel-ddr50",
130 MMC_CAP_UHS_DDR50},
131 [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52",
132 "ti,itap-del-sel-ddr52",
133 MMC_CAP_DDR},
134 [MMC_TIMING_MMC_HS200] = {"ti,otap-del-sel-hs200",
135 NULL,
136 MMC_CAP2_HS200},
137 [MMC_TIMING_MMC_HS400] = {"ti,otap-del-sel-hs400",
138 NULL,
139 MMC_CAP2_HS400},
140 };
141
142 struct sdhci_am654_data {
143 struct regmap *base;
144 u32 otap_del_sel[ARRAY_SIZE(td)];
145 u32 itap_del_sel[ARRAY_SIZE(td)];
146 u32 itap_del_ena[ARRAY_SIZE(td)];
147 u32 itap_del_sel_dt_ddr50;
148 u32 itap_del_ena_dt_ddr50;
149 int clkbuf_sel;
150 int trm_icp;
151 int drv_strength;
152 int strb_sel;
153 u32 flags;
154 u32 quirks;
155 bool dll_enable;
156
157 #define SDHCI_AM654_QUIRK_FORCE_CDTEST BIT(0)
158 #define SDHCI_AM654_QUIRK_SUPPRESS_V1P8_ENA BIT(1)
159 #define SDHCI_AM654_QUIRK_DISABLE_HS400 BIT(2)
160 };
161
162 struct window {
163 u8 start;
164 u8 end;
165 u8 length;
166 };
167
168 struct sdhci_am654_driver_data {
169 const struct sdhci_pltfm_data *pdata;
170 u32 flags;
171 u32 quirks;
172 #define IOMUX_PRESENT (1 << 0)
173 #define FREQSEL_2_BIT (1 << 1)
174 #define STRBSEL_4_BIT (1 << 2)
175 #define DLL_PRESENT (1 << 3)
176 #define DLL_CALIB (1 << 4)
177 };
178
sdhci_am654_setup_dll(struct sdhci_host * host,unsigned int clock)179 static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock)
180 {
181 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
182 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
183 int sel50, sel100, freqsel;
184 u32 mask, val;
185 int ret;
186
187 /* Disable delay chain mode */
188 regmap_update_bits(sdhci_am654->base, PHY_CTRL5,
189 SELDLYTXCLK_MASK | SELDLYRXCLK_MASK, 0);
190
191 if (sdhci_am654->flags & FREQSEL_2_BIT) {
192 switch (clock) {
193 case 200000000:
194 sel50 = 0;
195 sel100 = 0;
196 break;
197 case 100000000:
198 sel50 = 0;
199 sel100 = 1;
200 break;
201 default:
202 sel50 = 1;
203 sel100 = 0;
204 }
205
206 /* Configure PHY DLL frequency */
207 mask = SEL50_MASK | SEL100_MASK;
208 val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT);
209 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val);
210
211 } else {
212 switch (clock) {
213 case 200000000:
214 freqsel = 0x0;
215 break;
216 default:
217 freqsel = 0x4;
218 }
219
220 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, FREQSEL_MASK,
221 freqsel << FREQSEL_SHIFT);
222 }
223 /* Configure DLL TRIM */
224 mask = DLL_TRIM_ICP_MASK;
225 val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT;
226
227 /* Configure DLL driver strength */
228 mask |= DR_TY_MASK;
229 val |= sdhci_am654->drv_strength << DR_TY_SHIFT;
230 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val);
231
232 /* Enable DLL */
233 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK,
234 0x1 << ENDLL_SHIFT);
235 /*
236 * Poll for DLL ready. Use a one second timeout.
237 * Works in all experiments done so far
238 */
239 ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, val,
240 val & DLLRDY_MASK, 1000, 1000000);
241 if (ret) {
242 dev_err(mmc_dev(host->mmc), "DLL failed to relock\n");
243 return;
244 }
245 }
246
sdhci_am654_write_itapdly(struct sdhci_am654_data * sdhci_am654,u32 itapdly,u32 enable)247 static void sdhci_am654_write_itapdly(struct sdhci_am654_data *sdhci_am654,
248 u32 itapdly, u32 enable)
249 {
250 /* Set ITAPCHGWIN before writing to ITAPDLY */
251 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK,
252 1 << ITAPCHGWIN_SHIFT);
253 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK,
254 enable << ITAPDLYENA_SHIFT);
255 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK,
256 itapdly << ITAPDLYSEL_SHIFT);
257 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0);
258 }
259
sdhci_am654_setup_delay_chain(struct sdhci_am654_data * sdhci_am654,unsigned char timing)260 static void sdhci_am654_setup_delay_chain(struct sdhci_am654_data *sdhci_am654,
261 unsigned char timing)
262 {
263 u32 mask, val;
264
265 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0);
266
267 val = 1 << SELDLYTXCLK_SHIFT | 1 << SELDLYRXCLK_SHIFT;
268 mask = SELDLYTXCLK_MASK | SELDLYRXCLK_MASK;
269 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val);
270
271 sdhci_am654_write_itapdly(sdhci_am654, sdhci_am654->itap_del_sel[timing],
272 sdhci_am654->itap_del_ena[timing]);
273 }
274
sdhci_am654_set_clock(struct sdhci_host * host,unsigned int clock)275 static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock)
276 {
277 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
278 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
279 unsigned char timing = host->mmc->ios.timing;
280 u32 otap_del_sel;
281 u32 mask, val;
282
283 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0);
284
285 sdhci_set_clock(host, clock);
286
287 /* Setup Output TAP delay */
288 otap_del_sel = sdhci_am654->otap_del_sel[timing];
289
290 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
291 val = (0x1 << OTAPDLYENA_SHIFT) |
292 (otap_del_sel << OTAPDLYSEL_SHIFT);
293
294 /* Write to STRBSEL for HS400 speed mode */
295 if (timing == MMC_TIMING_MMC_HS400) {
296 if (sdhci_am654->flags & STRBSEL_4_BIT)
297 mask |= STRBSEL_4BIT_MASK;
298 else
299 mask |= STRBSEL_8BIT_MASK;
300
301 val |= sdhci_am654->strb_sel << STRBSEL_SHIFT;
302 }
303
304 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
305
306 if (timing > MMC_TIMING_UHS_SDR25 && clock >= CLOCK_TOO_SLOW_HZ) {
307 sdhci_am654_setup_dll(host, clock);
308 sdhci_am654->dll_enable = true;
309
310 if (timing == MMC_TIMING_MMC_HS400) {
311 sdhci_am654->itap_del_ena[timing] = 0x1;
312 sdhci_am654->itap_del_sel[timing] = sdhci_am654->itap_del_sel[timing - 1];
313 }
314
315 sdhci_am654_write_itapdly(sdhci_am654, sdhci_am654->itap_del_sel[timing],
316 sdhci_am654->itap_del_ena[timing]);
317 } else {
318 sdhci_am654_setup_delay_chain(sdhci_am654, timing);
319 sdhci_am654->dll_enable = false;
320 }
321
322 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK,
323 sdhci_am654->clkbuf_sel);
324 }
325
sdhci_j721e_4bit_set_clock(struct sdhci_host * host,unsigned int clock)326 static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host,
327 unsigned int clock)
328 {
329 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
330 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
331 unsigned char timing = host->mmc->ios.timing;
332 u32 otap_del_sel;
333 u32 itap_del_ena;
334 u32 itap_del_sel;
335 u32 mask, val;
336
337 /* Setup Output TAP delay */
338 otap_del_sel = sdhci_am654->otap_del_sel[timing];
339
340 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
341 val = (0x1 << OTAPDLYENA_SHIFT) |
342 (otap_del_sel << OTAPDLYSEL_SHIFT);
343
344 /* Setup Input TAP delay */
345 itap_del_ena = sdhci_am654->itap_del_ena[timing];
346 itap_del_sel = sdhci_am654->itap_del_sel[timing];
347
348 mask |= ITAPDLYENA_MASK | ITAPDLYSEL_MASK;
349 val |= (itap_del_ena << ITAPDLYENA_SHIFT) |
350 (itap_del_sel << ITAPDLYSEL_SHIFT);
351
352 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK,
353 1 << ITAPCHGWIN_SHIFT);
354 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
355 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0);
356 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK,
357 sdhci_am654->clkbuf_sel);
358
359 sdhci_set_clock(host, clock);
360 }
361
sdhci_am654_start_signal_voltage_switch(struct mmc_host * mmc,struct mmc_ios * ios)362 static int sdhci_am654_start_signal_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios)
363 {
364 struct sdhci_host *host = mmc_priv(mmc);
365 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
366 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
367 int ret;
368
369 if ((sdhci_am654->quirks & SDHCI_AM654_QUIRK_SUPPRESS_V1P8_ENA) &&
370 ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
371 if (!IS_ERR(mmc->supply.vqmmc)) {
372 ret = mmc_regulator_set_vqmmc(mmc, ios);
373 if (ret < 0) {
374 pr_err("%s: Switching to 1.8V signalling voltage failed,\n",
375 mmc_hostname(mmc));
376 return -EIO;
377 }
378 }
379 return 0;
380 }
381
382 return sdhci_start_signal_voltage_switch(mmc, ios);
383 }
384
sdhci_am654_write_power_on(struct sdhci_host * host,u8 val,int reg)385 static u8 sdhci_am654_write_power_on(struct sdhci_host *host, u8 val, int reg)
386 {
387 writeb(val, host->ioaddr + reg);
388 usleep_range(1000, 10000);
389 return readb(host->ioaddr + reg);
390 }
391
392 #define MAX_POWER_ON_TIMEOUT 1500000 /* us */
sdhci_am654_write_b(struct sdhci_host * host,u8 val,int reg)393 static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg)
394 {
395 unsigned char timing = host->mmc->ios.timing;
396 u8 pwr;
397 int ret;
398
399 if (reg == SDHCI_HOST_CONTROL) {
400 switch (timing) {
401 /*
402 * According to the data manual, HISPD bit
403 * should not be set in these speed modes.
404 */
405 case MMC_TIMING_SD_HS:
406 case MMC_TIMING_MMC_HS:
407 val &= ~SDHCI_CTRL_HISPD;
408 }
409 }
410
411 writeb(val, host->ioaddr + reg);
412 if (reg == SDHCI_POWER_CONTROL && (val & SDHCI_POWER_ON)) {
413 /*
414 * Power on will not happen until the card detect debounce
415 * timer expires. Wait at least 1.5 seconds for the power on
416 * bit to be set
417 */
418 ret = read_poll_timeout(sdhci_am654_write_power_on, pwr,
419 pwr & SDHCI_POWER_ON, 0,
420 MAX_POWER_ON_TIMEOUT, false, host, val,
421 reg);
422 if (ret)
423 dev_info(mmc_dev(host->mmc), "Power on failed\n");
424 }
425 }
426
sdhci_am654_reset(struct sdhci_host * host,u8 mask)427 static void sdhci_am654_reset(struct sdhci_host *host, u8 mask)
428 {
429 u8 ctrl;
430 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
431 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
432
433 sdhci_and_cqhci_reset(host, mask);
434
435 if (sdhci_am654->quirks & SDHCI_AM654_QUIRK_FORCE_CDTEST) {
436 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
437 ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN;
438 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
439 }
440 }
441
sdhci_am654_execute_tuning(struct mmc_host * mmc,u32 opcode)442 static int sdhci_am654_execute_tuning(struct mmc_host *mmc, u32 opcode)
443 {
444 struct sdhci_host *host = mmc_priv(mmc);
445 int err = sdhci_execute_tuning(mmc, opcode);
446
447 /*
448 * Tuning data remains in the buffer after tuning.
449 * Do a command and data reset to get rid of it
450 */
451 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
452
453 return err;
454 }
455
sdhci_am654_cqhci_irq(struct sdhci_host * host,u32 intmask)456 static u32 sdhci_am654_cqhci_irq(struct sdhci_host *host, u32 intmask)
457 {
458 int cmd_error = 0;
459 int data_error = 0;
460
461 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
462 return intmask;
463
464 cqhci_irq(host->mmc, cmd_error, data_error);
465
466 return 0;
467 }
468
469 #define ITAPDLY_LENGTH 32
470 #define ITAPDLY_LAST_INDEX (ITAPDLY_LENGTH - 1)
471
sdhci_am654_calculate_itap(struct sdhci_host * host,struct window * fail_window,u8 num_fails,bool circular_buffer)472 static int sdhci_am654_calculate_itap(struct sdhci_host *host, struct window
473 *fail_window, u8 num_fails, bool circular_buffer)
474 {
475 u8 itap = 0, start_fail = 0, end_fail = 0, pass_length = 0;
476 u8 first_fail_start = 0, last_fail_end = 0;
477 struct device *dev = mmc_dev(host->mmc);
478 struct window pass_window = {0, 0, 0};
479 int prev_fail_end = -1;
480 u8 i;
481
482 if (!num_fails) {
483 /* Retry tuning */
484 dev_dbg(dev, "No failing region found, retry tuning\n");
485 return -1;
486 }
487
488 if (fail_window->length == ITAPDLY_LENGTH) {
489 /* Retry tuning */
490 dev_dbg(dev, "No passing itapdly, retry tuning\n");
491 return -1;
492 }
493
494 first_fail_start = fail_window->start;
495 last_fail_end = fail_window[num_fails - 1].end;
496
497 for (i = 0; i < num_fails; i++) {
498 start_fail = fail_window[i].start;
499 end_fail = fail_window[i].end;
500 pass_length = start_fail - (prev_fail_end + 1);
501
502 if (pass_length > pass_window.length) {
503 pass_window.start = prev_fail_end + 1;
504 pass_window.length = pass_length;
505 }
506 prev_fail_end = end_fail;
507 }
508
509 if (!circular_buffer)
510 pass_length = ITAPDLY_LAST_INDEX - last_fail_end;
511 else
512 pass_length = ITAPDLY_LAST_INDEX - last_fail_end + first_fail_start;
513
514 if (pass_length > pass_window.length) {
515 pass_window.start = last_fail_end + 1;
516 pass_window.length = pass_length;
517 }
518
519 if (!circular_buffer)
520 itap = pass_window.start + (pass_window.length >> 1);
521 else
522 itap = (pass_window.start + (pass_window.length >> 1)) % ITAPDLY_LENGTH;
523
524 return (itap > ITAPDLY_LAST_INDEX) ? ITAPDLY_LAST_INDEX >> 1 : itap;
525 }
526
sdhci_am654_do_tuning(struct sdhci_host * host,u32 opcode)527 static int sdhci_am654_do_tuning(struct sdhci_host *host,
528 u32 opcode)
529 {
530 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
531 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
532 struct window fail_window[ITAPDLY_LENGTH];
533 struct device *dev = mmc_dev(host->mmc);
534 u8 curr_pass, itap;
535 u8 fail_index = 0;
536 u8 prev_pass = 1;
537
538 memset(fail_window, 0, sizeof(fail_window));
539
540 for (itap = 0; itap < ITAPDLY_LENGTH; itap++) {
541 sdhci_am654_write_itapdly(sdhci_am654, itap, 0x1);
542
543 curr_pass = !mmc_send_tuning(host->mmc, opcode, NULL);
544
545 if (!curr_pass && prev_pass)
546 fail_window[fail_index].start = itap;
547
548 if (!curr_pass) {
549 fail_window[fail_index].end = itap;
550 fail_window[fail_index].length++;
551 dev_dbg(dev, "Failed itapdly=%d\n", itap);
552 }
553
554 if (curr_pass && !prev_pass)
555 fail_index++;
556
557 prev_pass = curr_pass;
558 }
559
560 if (fail_window[fail_index].length != 0)
561 fail_index++;
562
563 return sdhci_am654_calculate_itap(host, fail_window, fail_index,
564 sdhci_am654->dll_enable);
565 }
566
sdhci_am654_platform_execute_tuning(struct sdhci_host * host,u32 opcode)567 static int sdhci_am654_platform_execute_tuning(struct sdhci_host *host,
568 u32 opcode)
569 {
570 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
571 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
572 unsigned char timing = host->mmc->ios.timing;
573 struct device *dev = mmc_dev(host->mmc);
574 unsigned int tuning_loop = 0;
575 int itapdly;
576
577 do {
578 itapdly = sdhci_am654_do_tuning(host, opcode);
579 if (itapdly >= 0)
580 break;
581 } while (++tuning_loop < RETRY_TUNING_MAX);
582
583 if (itapdly < 0) {
584 if (timing == MMC_TIMING_UHS_DDR50) {
585 dev_dbg(dev, "Failed DDR50 tuning, fallback to DT ITAP\n");
586 sdhci_am654->itap_del_sel[timing] = sdhci_am654->itap_del_sel_dt_ddr50;
587 sdhci_am654->itap_del_ena[timing] = sdhci_am654->itap_del_ena_dt_ddr50;
588 } else {
589 dev_err(dev, "Failed to find itapdly, fail tuning\n");
590 sdhci_am654->itap_del_ena[timing] = 0;
591 sdhci_am654->itap_del_sel[timing] = 0;
592 }
593
594 sdhci_am654_write_itapdly(sdhci_am654,
595 sdhci_am654->itap_del_sel[timing],
596 sdhci_am654->itap_del_ena[timing]);
597 return -1;
598 }
599
600 dev_dbg(dev, "Passed tuning, final itapdly=%d\n", itapdly);
601
602 /* Enable ITAPDLY */
603 sdhci_am654->itap_del_ena[timing] = 0x1;
604 sdhci_am654_write_itapdly(sdhci_am654, itapdly, sdhci_am654->itap_del_ena[timing]);
605 /* Save ITAPDLY */
606 sdhci_am654->itap_del_sel[timing] = itapdly;
607
608 return 0;
609 }
610
611 static const struct sdhci_ops sdhci_am654_ops = {
612 .platform_execute_tuning = sdhci_am654_platform_execute_tuning,
613 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
614 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
615 .set_uhs_signaling = sdhci_set_uhs_signaling,
616 .set_bus_width = sdhci_set_bus_width,
617 .set_power = sdhci_set_power_and_bus_voltage,
618 .set_clock = sdhci_am654_set_clock,
619 .write_b = sdhci_am654_write_b,
620 .irq = sdhci_am654_cqhci_irq,
621 .reset = sdhci_and_cqhci_reset,
622 };
623
624 static const struct sdhci_pltfm_data sdhci_am654_pdata = {
625 .ops = &sdhci_am654_ops,
626 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
627 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
628 SDHCI_QUIRK2_DISABLE_HW_TIMEOUT,
629 };
630
631 static const struct sdhci_am654_driver_data sdhci_am654_sr1_drvdata = {
632 .pdata = &sdhci_am654_pdata,
633 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT |
634 DLL_CALIB,
635 };
636
637 static const struct sdhci_am654_driver_data sdhci_am654_drvdata = {
638 .pdata = &sdhci_am654_pdata,
639 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT,
640 };
641
642 static const struct sdhci_ops sdhci_j721e_8bit_ops = {
643 .platform_execute_tuning = sdhci_am654_platform_execute_tuning,
644 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
645 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
646 .set_uhs_signaling = sdhci_set_uhs_signaling,
647 .set_bus_width = sdhci_set_bus_width,
648 .set_power = sdhci_set_power_and_bus_voltage,
649 .set_clock = sdhci_am654_set_clock,
650 .write_b = sdhci_am654_write_b,
651 .irq = sdhci_am654_cqhci_irq,
652 .reset = sdhci_and_cqhci_reset,
653 };
654
655 static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = {
656 .ops = &sdhci_j721e_8bit_ops,
657 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
658 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
659 SDHCI_QUIRK2_DISABLE_HW_TIMEOUT,
660 };
661
662 static const struct sdhci_am654_driver_data sdhci_j721e_8bit_drvdata = {
663 .pdata = &sdhci_j721e_8bit_pdata,
664 .flags = DLL_PRESENT | DLL_CALIB,
665 };
666
667 static const struct sdhci_ops sdhci_j721e_4bit_ops = {
668 .platform_execute_tuning = sdhci_am654_platform_execute_tuning,
669 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
670 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
671 .set_uhs_signaling = sdhci_set_uhs_signaling,
672 .set_bus_width = sdhci_set_bus_width,
673 .set_power = sdhci_set_power_and_bus_voltage,
674 .set_clock = sdhci_j721e_4bit_set_clock,
675 .write_b = sdhci_am654_write_b,
676 .irq = sdhci_am654_cqhci_irq,
677 .reset = sdhci_am654_reset,
678 };
679
680 static const struct sdhci_pltfm_data sdhci_j721e_4bit_pdata = {
681 .ops = &sdhci_j721e_4bit_ops,
682 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
683 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
684 SDHCI_QUIRK2_DISABLE_HW_TIMEOUT,
685 };
686
687 static const struct sdhci_am654_driver_data sdhci_j721e_4bit_drvdata = {
688 .pdata = &sdhci_j721e_4bit_pdata,
689 .flags = IOMUX_PRESENT,
690 };
691
692 static const struct sdhci_am654_driver_data sdhci_am62_4bit_drvdata = {
693 .pdata = &sdhci_j721e_4bit_pdata,
694 .flags = IOMUX_PRESENT,
695 .quirks = SDHCI_AM654_QUIRK_SUPPRESS_V1P8_ENA,
696 };
697
698 static const struct soc_device_attribute sdhci_am654_devices[] = {
699 { .family = "AM65X",
700 .revision = "SR1.0",
701 .data = &sdhci_am654_sr1_drvdata
702 },
703 {/* sentinel */}
704 };
705
sdhci_am654_dumpregs(struct mmc_host * mmc)706 static void sdhci_am654_dumpregs(struct mmc_host *mmc)
707 {
708 sdhci_dumpregs(mmc_priv(mmc));
709 }
710
711 static const struct cqhci_host_ops sdhci_am654_cqhci_ops = {
712 .enable = sdhci_cqe_enable,
713 .disable = sdhci_cqe_disable,
714 .dumpregs = sdhci_am654_dumpregs,
715 };
716
sdhci_am654_cqe_add_host(struct sdhci_host * host)717 static int sdhci_am654_cqe_add_host(struct sdhci_host *host)
718 {
719 struct cqhci_host *cq_host;
720
721 cq_host = devm_kzalloc(mmc_dev(host->mmc), sizeof(struct cqhci_host),
722 GFP_KERNEL);
723 if (!cq_host)
724 return -ENOMEM;
725
726 cq_host->mmio = host->ioaddr + SDHCI_AM654_CQE_BASE_ADDR;
727 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ;
728 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
729 cq_host->ops = &sdhci_am654_cqhci_ops;
730
731 host->mmc->caps2 |= MMC_CAP2_CQE;
732
733 return cqhci_init(cq_host, host->mmc, 1);
734 }
735
sdhci_am654_get_otap_delay(struct sdhci_host * host,struct sdhci_am654_data * sdhci_am654)736 static int sdhci_am654_get_otap_delay(struct sdhci_host *host,
737 struct sdhci_am654_data *sdhci_am654)
738 {
739 struct device *dev = mmc_dev(host->mmc);
740 int i;
741 int ret;
742
743 for (i = MMC_TIMING_LEGACY; i <= MMC_TIMING_MMC_HS400; i++) {
744
745 ret = device_property_read_u32(dev, td[i].otap_binding,
746 &sdhci_am654->otap_del_sel[i]);
747 if (ret) {
748 if (i == MMC_TIMING_LEGACY) {
749 dev_err(dev, "Couldn't find mandatory ti,otap-del-sel-legacy\n");
750 return ret;
751 }
752 dev_dbg(dev, "Couldn't find %s\n",
753 td[i].otap_binding);
754 /*
755 * Remove the corresponding capability
756 * if an otap-del-sel value is not found
757 */
758 if (i <= MMC_TIMING_MMC_DDR52)
759 host->mmc->caps &= ~td[i].capability;
760 else
761 host->mmc->caps2 &= ~td[i].capability;
762 }
763
764 if (td[i].itap_binding) {
765 ret = device_property_read_u32(dev, td[i].itap_binding,
766 &sdhci_am654->itap_del_sel[i]);
767 if (!ret)
768 sdhci_am654->itap_del_ena[i] = 0x1;
769 }
770 }
771
772 sdhci_am654->itap_del_sel_dt_ddr50 =
773 sdhci_am654->itap_del_sel[MMC_TIMING_UHS_DDR50];
774 sdhci_am654->itap_del_ena_dt_ddr50 =
775 sdhci_am654->itap_del_ena[MMC_TIMING_UHS_DDR50];
776
777 return 0;
778 }
779
sdhci_am654_init(struct sdhci_host * host)780 static int sdhci_am654_init(struct sdhci_host *host)
781 {
782 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
783 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
784 struct device *dev = mmc_dev(host->mmc);
785 u32 ctl_cfg_2 = 0;
786 u32 mask;
787 u32 val;
788 int ret;
789
790 /* Reset OTAP to default value */
791 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
792 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0);
793
794 if (sdhci_am654->flags & DLL_CALIB) {
795 regmap_read(sdhci_am654->base, PHY_STAT1, &val);
796 if (~val & CALDONE_MASK) {
797 /* Calibrate IO lines */
798 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
799 PDB_MASK, PDB_MASK);
800 ret = regmap_read_poll_timeout(sdhci_am654->base,
801 PHY_STAT1, val,
802 val & CALDONE_MASK,
803 1, 20);
804 if (ret)
805 return ret;
806 }
807 }
808
809 /* Enable pins by setting IO mux to 0 */
810 if (sdhci_am654->flags & IOMUX_PRESENT)
811 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
812 IOMUX_ENABLE_MASK, 0);
813
814 /* Set slot type based on SD or eMMC */
815 if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
816 ctl_cfg_2 = SLOTTYPE_EMBEDDED;
817
818 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK,
819 ctl_cfg_2);
820
821 /* Enable tuning for SDR50 */
822 regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK,
823 TUNINGFORSDR50_MASK);
824
825 ret = sdhci_setup_host(host);
826 if (ret)
827 return ret;
828
829 ret = sdhci_am654_cqe_add_host(host);
830 if (ret)
831 goto err_cleanup_host;
832
833 ret = sdhci_am654_get_otap_delay(host, sdhci_am654);
834 if (ret)
835 goto err_cleanup_host;
836
837 if (sdhci_am654->quirks & SDHCI_AM654_QUIRK_DISABLE_HS400 &&
838 host->mmc->caps2 & (MMC_CAP2_HS400 | MMC_CAP2_HS400_ES)) {
839 dev_info(dev, "HS400 mode not supported on this silicon revision, disabling it\n");
840 host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES);
841 }
842
843 ret = __sdhci_add_host(host);
844 if (ret)
845 goto err_cleanup_host;
846
847 return 0;
848
849 err_cleanup_host:
850 sdhci_cleanup_host(host);
851 return ret;
852 }
853
sdhci_am654_get_of_property(struct platform_device * pdev,struct sdhci_am654_data * sdhci_am654)854 static int sdhci_am654_get_of_property(struct platform_device *pdev,
855 struct sdhci_am654_data *sdhci_am654)
856 {
857 struct device *dev = &pdev->dev;
858 int drv_strength;
859 int ret;
860
861 if (sdhci_am654->flags & DLL_PRESENT) {
862 ret = device_property_read_u32(dev, "ti,trm-icp",
863 &sdhci_am654->trm_icp);
864 if (ret)
865 return ret;
866
867 ret = device_property_read_u32(dev, "ti,driver-strength-ohm",
868 &drv_strength);
869 if (ret)
870 return ret;
871
872 switch (drv_strength) {
873 case 50:
874 sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM;
875 break;
876 case 33:
877 sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM;
878 break;
879 case 66:
880 sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM;
881 break;
882 case 100:
883 sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM;
884 break;
885 case 40:
886 sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM;
887 break;
888 default:
889 dev_err(dev, "Invalid driver strength\n");
890 return -EINVAL;
891 }
892 }
893
894 device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel);
895 device_property_read_u32(dev, "ti,clkbuf-sel",
896 &sdhci_am654->clkbuf_sel);
897
898 if (device_property_read_bool(dev, "ti,fails-without-test-cd"))
899 sdhci_am654->quirks |= SDHCI_AM654_QUIRK_FORCE_CDTEST;
900
901 sdhci_get_of_property(pdev);
902
903 return 0;
904 }
905
906 static const struct soc_device_attribute sdhci_am654_descope_hs400[] = {
907 { .family = "AM62PX", .revision = "SR1.0" },
908 { .family = "AM62PX", .revision = "SR1.1" },
909 { /* sentinel */ }
910 };
911
912 static const struct of_device_id sdhci_am654_of_match[] = {
913 {
914 .compatible = "ti,am654-sdhci-5.1",
915 .data = &sdhci_am654_drvdata,
916 },
917 {
918 .compatible = "ti,j721e-sdhci-8bit",
919 .data = &sdhci_j721e_8bit_drvdata,
920 },
921 {
922 .compatible = "ti,j721e-sdhci-4bit",
923 .data = &sdhci_j721e_4bit_drvdata,
924 },
925 {
926 .compatible = "ti,am64-sdhci-8bit",
927 .data = &sdhci_j721e_8bit_drvdata,
928 },
929 {
930 .compatible = "ti,am64-sdhci-4bit",
931 .data = &sdhci_j721e_4bit_drvdata,
932 },
933 {
934 .compatible = "ti,am62-sdhci",
935 .data = &sdhci_am62_4bit_drvdata,
936 },
937 { /* sentinel */ }
938 };
939 MODULE_DEVICE_TABLE(of, sdhci_am654_of_match);
940
sdhci_am654_probe(struct platform_device * pdev)941 static int sdhci_am654_probe(struct platform_device *pdev)
942 {
943 const struct sdhci_am654_driver_data *drvdata;
944 const struct soc_device_attribute *soc;
945 struct sdhci_pltfm_host *pltfm_host;
946 struct sdhci_am654_data *sdhci_am654;
947 const struct of_device_id *match;
948 struct sdhci_host *host;
949 struct clk *clk_xin;
950 struct device *dev = &pdev->dev;
951 void __iomem *base;
952 int ret;
953
954 match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node);
955 drvdata = match->data;
956
957 /* Update drvdata based on SoC revision */
958 soc = soc_device_match(sdhci_am654_devices);
959 if (soc && soc->data)
960 drvdata = soc->data;
961
962 host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654));
963 if (IS_ERR(host))
964 return PTR_ERR(host);
965
966 pltfm_host = sdhci_priv(host);
967 sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
968 sdhci_am654->flags = drvdata->flags;
969 sdhci_am654->quirks = drvdata->quirks;
970
971 clk_xin = devm_clk_get(dev, "clk_xin");
972 if (IS_ERR(clk_xin)) {
973 dev_err(dev, "clk_xin clock not found.\n");
974 return PTR_ERR(clk_xin);
975 }
976
977 pltfm_host->clk = clk_xin;
978
979 base = devm_platform_ioremap_resource(pdev, 1);
980 if (IS_ERR(base)) {
981 return PTR_ERR(base);
982 }
983
984 sdhci_am654->base = devm_regmap_init_mmio(dev, base,
985 &sdhci_am654_regmap_config);
986 if (IS_ERR(sdhci_am654->base)) {
987 dev_err(dev, "Failed to initialize regmap\n");
988 return PTR_ERR(sdhci_am654->base);
989 }
990
991 ret = sdhci_am654_get_of_property(pdev, sdhci_am654);
992 if (ret)
993 return ret;
994
995 ret = mmc_of_parse(host->mmc);
996 if (ret)
997 return dev_err_probe(dev, ret, "parsing dt failed\n");
998
999 soc = soc_device_match(sdhci_am654_descope_hs400);
1000 if (soc)
1001 sdhci_am654->quirks |= SDHCI_AM654_QUIRK_DISABLE_HS400;
1002
1003 host->mmc_host_ops.start_signal_voltage_switch = sdhci_am654_start_signal_voltage_switch;
1004 host->mmc_host_ops.execute_tuning = sdhci_am654_execute_tuning;
1005
1006 pm_runtime_get_noresume(dev);
1007 ret = pm_runtime_set_active(dev);
1008 if (ret)
1009 goto pm_put;
1010 pm_runtime_enable(dev);
1011 ret = clk_prepare_enable(pltfm_host->clk);
1012 if (ret)
1013 goto pm_disable;
1014
1015 ret = sdhci_am654_init(host);
1016 if (ret)
1017 goto clk_disable;
1018
1019 /* Setting up autosuspend */
1020 pm_runtime_set_autosuspend_delay(dev, SDHCI_AM654_AUTOSUSPEND_DELAY);
1021 pm_runtime_use_autosuspend(dev);
1022 pm_runtime_put_autosuspend(dev);
1023 return 0;
1024
1025 clk_disable:
1026 clk_disable_unprepare(pltfm_host->clk);
1027 pm_disable:
1028 pm_runtime_disable(dev);
1029 pm_put:
1030 pm_runtime_put_noidle(dev);
1031 return ret;
1032 }
1033
sdhci_am654_remove(struct platform_device * pdev)1034 static void sdhci_am654_remove(struct platform_device *pdev)
1035 {
1036 struct sdhci_host *host = platform_get_drvdata(pdev);
1037 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1038 struct device *dev = &pdev->dev;
1039 int ret;
1040
1041 ret = pm_runtime_get_sync(dev);
1042 if (ret < 0)
1043 dev_err(dev, "pm_runtime_get_sync() Failed\n");
1044
1045 sdhci_remove_host(host, true);
1046 clk_disable_unprepare(pltfm_host->clk);
1047 pm_runtime_disable(dev);
1048 pm_runtime_put_noidle(dev);
1049 }
1050
sdhci_am654_restore(struct sdhci_host * host)1051 static int sdhci_am654_restore(struct sdhci_host *host)
1052 {
1053 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1054 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
1055 u32 ctl_cfg_2 = 0;
1056 u32 val;
1057 int ret;
1058
1059 if (sdhci_am654->flags & DLL_CALIB) {
1060 regmap_read(sdhci_am654->base, PHY_STAT1, &val);
1061 if (~val & CALDONE_MASK) {
1062 /* Calibrate IO lines */
1063 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
1064 PDB_MASK, PDB_MASK);
1065 ret = regmap_read_poll_timeout(sdhci_am654->base,
1066 PHY_STAT1, val,
1067 val & CALDONE_MASK,
1068 1, 20);
1069 if (ret)
1070 return ret;
1071 }
1072 }
1073
1074 /* Enable pins by setting IO mux to 0 */
1075 if (sdhci_am654->flags & IOMUX_PRESENT)
1076 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
1077 IOMUX_ENABLE_MASK, 0);
1078
1079 /* Set slot type based on SD or eMMC */
1080 if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
1081 ctl_cfg_2 = SLOTTYPE_EMBEDDED;
1082
1083 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK,
1084 ctl_cfg_2);
1085
1086 regmap_read(sdhci_am654->base, CTL_CFG_3, &val);
1087 if (~val & TUNINGFORSDR50_MASK)
1088 /* Enable tuning for SDR50 */
1089 regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK,
1090 TUNINGFORSDR50_MASK);
1091
1092 return 0;
1093 }
1094
sdhci_am654_runtime_suspend(struct device * dev)1095 static int sdhci_am654_runtime_suspend(struct device *dev)
1096 {
1097 struct sdhci_host *host = dev_get_drvdata(dev);
1098 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1099 int ret;
1100
1101 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1102 mmc_retune_needed(host->mmc);
1103
1104 ret = cqhci_suspend(host->mmc);
1105 if (ret)
1106 return ret;
1107
1108 sdhci_runtime_suspend_host(host);
1109
1110 /* disable the clock */
1111 clk_disable_unprepare(pltfm_host->clk);
1112 return 0;
1113 }
1114
sdhci_am654_runtime_resume(struct device * dev)1115 static int sdhci_am654_runtime_resume(struct device *dev)
1116 {
1117 struct sdhci_host *host = dev_get_drvdata(dev);
1118 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1119 int ret;
1120
1121 /* Enable the clock */
1122 ret = clk_prepare_enable(pltfm_host->clk);
1123 if (ret)
1124 return ret;
1125
1126 ret = sdhci_am654_restore(host);
1127 if (ret)
1128 return ret;
1129
1130 sdhci_runtime_resume_host(host, 0);
1131
1132 ret = cqhci_resume(host->mmc);
1133 if (ret)
1134 return ret;
1135
1136 return 0;
1137 }
1138
1139 static const struct dev_pm_ops sdhci_am654_dev_pm_ops = {
1140 RUNTIME_PM_OPS(sdhci_am654_runtime_suspend, sdhci_am654_runtime_resume, NULL)
1141 SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
1142 };
1143
1144 static struct platform_driver sdhci_am654_driver = {
1145 .driver = {
1146 .name = "sdhci-am654",
1147 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1148 .pm = pm_ptr(&sdhci_am654_dev_pm_ops),
1149 .of_match_table = sdhci_am654_of_match,
1150 },
1151 .probe = sdhci_am654_probe,
1152 .remove = sdhci_am654_remove,
1153 };
1154
1155 module_platform_driver(sdhci_am654_driver);
1156
1157 MODULE_DESCRIPTION("Driver for SDHCI Controller on TI's AM654 devices");
1158 MODULE_AUTHOR("Faiz Abbas <faiz_abbas@ti.com>");
1159 MODULE_LICENSE("GPL");
1160