xref: /linux/include/dt-bindings/clock/samsung,s3c64xx-clock.h (revision 3eb66e91a25497065c5322b1268cbc3953642227)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (c) 2013 Tomasz Figa <tomasz.figa at gmail.com>
4  *
5  * Device Tree binding constants for Samsung S3C64xx clock controller.
6  */
7 
8 #ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H
9 #define _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H
10 
11 /*
12  * Let each exported clock get a unique index, which is used on DT-enabled
13  * platforms to lookup the clock from a clock specifier. These indices are
14  * therefore considered an ABI and so must not be changed. This implies
15  * that new clocks should be added either in free spaces between clock groups
16  * or at the end.
17  */
18 
19 /* Core clocks. */
20 #define CLK27M			1
21 #define CLK48M			2
22 #define FOUT_APLL		3
23 #define FOUT_MPLL		4
24 #define FOUT_EPLL		5
25 #define ARMCLK			6
26 #define HCLKX2			7
27 #define HCLK			8
28 #define PCLK			9
29 
30 /* HCLK bus clocks. */
31 #define HCLK_3DSE		16
32 #define HCLK_UHOST		17
33 #define HCLK_SECUR		18
34 #define HCLK_SDMA1		19
35 #define HCLK_SDMA0		20
36 #define HCLK_IROM		21
37 #define HCLK_DDR1		22
38 #define HCLK_MEM1		23
39 #define HCLK_MEM0		24
40 #define HCLK_USB		25
41 #define HCLK_HSMMC2		26
42 #define HCLK_HSMMC1		27
43 #define HCLK_HSMMC0		28
44 #define HCLK_MDP		29
45 #define HCLK_DHOST		30
46 #define HCLK_IHOST		31
47 #define HCLK_DMA1		32
48 #define HCLK_DMA0		33
49 #define HCLK_JPEG		34
50 #define HCLK_CAMIF		35
51 #define HCLK_SCALER		36
52 #define HCLK_2D			37
53 #define HCLK_TV			38
54 #define HCLK_POST0		39
55 #define HCLK_ROT		40
56 #define HCLK_LCD		41
57 #define HCLK_TZIC		42
58 #define HCLK_INTC		43
59 #define HCLK_MFC		44
60 #define HCLK_DDR0		45
61 
62 /* PCLK bus clocks. */
63 #define PCLK_IIC1		48
64 #define PCLK_IIS2		49
65 #define PCLK_SKEY		50
66 #define PCLK_CHIPID		51
67 #define PCLK_SPI1		52
68 #define PCLK_SPI0		53
69 #define PCLK_HSIRX		54
70 #define PCLK_HSITX		55
71 #define PCLK_GPIO		56
72 #define PCLK_IIC0		57
73 #define PCLK_IIS1		58
74 #define PCLK_IIS0		59
75 #define PCLK_AC97		60
76 #define PCLK_TZPC		61
77 #define PCLK_TSADC		62
78 #define PCLK_KEYPAD		63
79 #define PCLK_IRDA		64
80 #define PCLK_PCM1		65
81 #define PCLK_PCM0		66
82 #define PCLK_PWM		67
83 #define PCLK_RTC		68
84 #define PCLK_WDT		69
85 #define PCLK_UART3		70
86 #define PCLK_UART2		71
87 #define PCLK_UART1		72
88 #define PCLK_UART0		73
89 #define PCLK_MFC		74
90 
91 /* Special clocks. */
92 #define SCLK_UHOST		80
93 #define SCLK_MMC2_48		81
94 #define SCLK_MMC1_48		82
95 #define SCLK_MMC0_48		83
96 #define SCLK_MMC2		84
97 #define SCLK_MMC1		85
98 #define SCLK_MMC0		86
99 #define SCLK_SPI1_48		87
100 #define SCLK_SPI0_48		88
101 #define SCLK_SPI1		89
102 #define SCLK_SPI0		90
103 #define SCLK_DAC27		91
104 #define SCLK_TV27		92
105 #define SCLK_SCALER27		93
106 #define SCLK_SCALER		94
107 #define SCLK_LCD27		95
108 #define SCLK_LCD		96
109 #define SCLK_FIMC		97
110 #define SCLK_POST0_27		98
111 #define SCLK_AUDIO2		99
112 #define SCLK_POST0		100
113 #define SCLK_AUDIO1		101
114 #define SCLK_AUDIO0		102
115 #define SCLK_SECUR		103
116 #define SCLK_IRDA		104
117 #define SCLK_UART		105
118 #define SCLK_MFC		106
119 #define SCLK_CAM		107
120 #define SCLK_JPEG		108
121 #define SCLK_ONENAND		109
122 
123 /* MEM0 bus clocks - S3C6410-specific. */
124 #define MEM0_CFCON		112
125 #define MEM0_ONENAND1		113
126 #define MEM0_ONENAND0		114
127 #define MEM0_NFCON		115
128 #define MEM0_SROM		116
129 
130 /* Muxes. */
131 #define MOUT_APLL		128
132 #define MOUT_MPLL		129
133 #define MOUT_EPLL		130
134 #define MOUT_MFC		131
135 #define MOUT_AUDIO0		132
136 #define MOUT_AUDIO1		133
137 #define MOUT_UART		134
138 #define MOUT_SPI0		135
139 #define MOUT_SPI1		136
140 #define MOUT_MMC0		137
141 #define MOUT_MMC1		138
142 #define MOUT_MMC2		139
143 #define MOUT_UHOST		140
144 #define MOUT_IRDA		141
145 #define MOUT_LCD		142
146 #define MOUT_SCALER		143
147 #define MOUT_DAC27		144
148 #define MOUT_TV27		145
149 #define MOUT_AUDIO2		146
150 
151 /* Dividers. */
152 #define DOUT_MPLL		160
153 #define DOUT_SECUR		161
154 #define DOUT_CAM		162
155 #define DOUT_JPEG		163
156 #define DOUT_MFC		164
157 #define DOUT_MMC0		165
158 #define DOUT_MMC1		166
159 #define DOUT_MMC2		167
160 #define DOUT_LCD		168
161 #define DOUT_SCALER		169
162 #define DOUT_UHOST		170
163 #define DOUT_SPI0		171
164 #define DOUT_SPI1		172
165 #define DOUT_AUDIO0		173
166 #define DOUT_AUDIO1		174
167 #define DOUT_UART		175
168 #define DOUT_IRDA		176
169 #define DOUT_FIMC		177
170 #define DOUT_AUDIO2		178
171 
172 /* Total number of clocks. */
173 #define NR_CLKS			(DOUT_AUDIO2 + 1)
174 
175 #endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H */
176