1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * AD7192 and similar SPI ADC driver 4 * 5 * Copyright 2011-2015 Analog Devices Inc. 6 */ 7 8 #include <linux/interrupt.h> 9 #include <linux/bitfield.h> 10 #include <linux/cleanup.h> 11 #include <linux/clk.h> 12 #include <linux/clk-provider.h> 13 #include <linux/device.h> 14 #include <linux/kernel.h> 15 #include <linux/slab.h> 16 #include <linux/sysfs.h> 17 #include <linux/spi/spi.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/err.h> 20 #include <linux/sched.h> 21 #include <linux/delay.h> 22 #include <linux/module.h> 23 #include <linux/mod_devicetable.h> 24 #include <linux/property.h> 25 #include <linux/units.h> 26 27 #include <linux/iio/iio.h> 28 #include <linux/iio/sysfs.h> 29 #include <linux/iio/buffer.h> 30 #include <linux/iio/trigger.h> 31 #include <linux/iio/trigger_consumer.h> 32 #include <linux/iio/triggered_buffer.h> 33 #include <linux/iio/adc/ad_sigma_delta.h> 34 35 /* Registers */ 36 #define AD7192_REG_COMM 0 /* Communications Register (WO, 8-bit) */ 37 #define AD7192_REG_STAT 0 /* Status Register (RO, 8-bit) */ 38 #define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */ 39 #define AD7192_REG_CONF 2 /* Configuration Register (RW, 24-bit) */ 40 #define AD7192_REG_DATA 3 /* Data Register (RO, 24/32-bit) */ 41 #define AD7192_REG_ID 4 /* ID Register (RO, 8-bit) */ 42 #define AD7192_REG_GPOCON 5 /* GPOCON Register (RW, 8-bit) */ 43 #define AD7192_REG_OFFSET 6 /* Offset Register (RW, 16-bit */ 44 /* (AD7792)/24-bit (AD7192)) */ 45 #define AD7192_REG_FULLSALE 7 /* Full-Scale Register */ 46 /* (RW, 16-bit (AD7792)/24-bit (AD7192)) */ 47 48 /* Communications Register Bit Designations (AD7192_REG_COMM) */ 49 #define AD7192_COMM_WEN BIT(7) /* Write Enable */ 50 #define AD7192_COMM_WRITE 0 /* Write Operation */ 51 #define AD7192_COMM_READ BIT(6) /* Read Operation */ 52 #define AD7192_COMM_ADDR_MASK GENMASK(5, 3) /* Register Address Mask */ 53 #define AD7192_COMM_CREAD BIT(2) /* Continuous Read of Data Register */ 54 55 /* Status Register Bit Designations (AD7192_REG_STAT) */ 56 #define AD7192_STAT_RDY BIT(7) /* Ready */ 57 #define AD7192_STAT_ERR BIT(6) /* Error (Overrange, Underrange) */ 58 #define AD7192_STAT_NOREF BIT(5) /* Error no external reference */ 59 #define AD7192_STAT_PARITY BIT(4) /* Parity */ 60 #define AD7192_STAT_CH3 BIT(2) /* Channel 3 */ 61 #define AD7192_STAT_CH2 BIT(1) /* Channel 2 */ 62 #define AD7192_STAT_CH1 BIT(0) /* Channel 1 */ 63 64 /* Mode Register Bit Designations (AD7192_REG_MODE) */ 65 #define AD7192_MODE_SEL_MASK GENMASK(23, 21) /* Operation Mode Select Mask */ 66 #define AD7192_MODE_STA_MASK BIT(20) /* Status Register transmission Mask */ 67 #define AD7192_MODE_CLKSRC_MASK GENMASK(19, 18) /* Clock Source Select Mask */ 68 #define AD7192_MODE_AVG_MASK GENMASK(17, 16) 69 /* Fast Settling Filter Average Select Mask (AD7193 only) */ 70 #define AD7192_MODE_SINC3 BIT(15) /* SINC3 Filter Select */ 71 #define AD7192_MODE_ENPAR BIT(13) /* Parity Enable */ 72 #define AD7192_MODE_CLKDIV BIT(12) /* Clock divide by 2 (AD7190/2 only)*/ 73 #define AD7192_MODE_SCYCLE BIT(11) /* Single cycle conversion */ 74 #define AD7192_MODE_REJ60 BIT(10) /* 50/60Hz notch filter */ 75 /* Filter Update Rate Select Mask */ 76 #define AD7192_MODE_RATE_MASK GENMASK(9, 0) 77 78 /* Mode Register: AD7192_MODE_SEL options */ 79 #define AD7192_MODE_CONT 0 /* Continuous Conversion Mode */ 80 #define AD7192_MODE_SINGLE 1 /* Single Conversion Mode */ 81 #define AD7192_MODE_IDLE 2 /* Idle Mode */ 82 #define AD7192_MODE_PWRDN 3 /* Power-Down Mode */ 83 #define AD7192_MODE_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */ 84 #define AD7192_MODE_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */ 85 #define AD7192_MODE_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */ 86 #define AD7192_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */ 87 88 /* Mode Register: AD7192_MODE_CLKSRC options */ 89 #define AD7192_CLK_EXT_MCLK1_2 0 /* External 4.92 MHz Clock connected*/ 90 /* from MCLK1 to MCLK2 */ 91 #define AD7192_CLK_EXT_MCLK2 1 /* External Clock applied to MCLK2 */ 92 #define AD7192_CLK_INT 2 /* Internal 4.92 MHz Clock not */ 93 /* available at the MCLK2 pin */ 94 #define AD7192_CLK_INT_CO 3 /* Internal 4.92 MHz Clock available*/ 95 /* at the MCLK2 pin */ 96 97 /* Configuration Register Bit Designations (AD7192_REG_CONF) */ 98 99 #define AD7192_CONF_CHOP BIT(23) /* CHOP enable */ 100 #define AD7192_CONF_ACX BIT(22) /* AC excitation enable(AD7195 only) */ 101 #define AD7192_CONF_REFSEL BIT(20) /* REFIN1/REFIN2 Reference Select */ 102 #define AD7192_CONF_CHAN_MASK GENMASK(18, 8) /* Channel select mask */ 103 #define AD7192_CONF_BURN BIT(7) /* Burnout current enable */ 104 #define AD7192_CONF_REFDET BIT(6) /* Reference detect enable */ 105 #define AD7192_CONF_BUF BIT(4) /* Buffered Mode Enable */ 106 #define AD7192_CONF_UNIPOLAR BIT(3) /* Unipolar/Bipolar Enable */ 107 #define AD7192_CONF_GAIN_MASK GENMASK(2, 0) /* Gain Select */ 108 109 #define AD7192_CH_AIN1P_AIN2M BIT(0) /* AIN1(+) - AIN2(-) */ 110 #define AD7192_CH_AIN3P_AIN4M BIT(1) /* AIN3(+) - AIN4(-) */ 111 #define AD7192_CH_TEMP BIT(2) /* Temp Sensor */ 112 #define AD7192_CH_AIN2P_AIN2M BIT(3) /* AIN2(+) - AIN2(-) */ 113 #define AD7192_CH_AIN1 BIT(4) /* AIN1 - AINCOM */ 114 #define AD7192_CH_AIN2 BIT(5) /* AIN2 - AINCOM */ 115 #define AD7192_CH_AIN3 BIT(6) /* AIN3 - AINCOM */ 116 #define AD7192_CH_AIN4 BIT(7) /* AIN4 - AINCOM */ 117 118 #define AD7193_CH_AIN1P_AIN2M 0x001 /* AIN1(+) - AIN2(-) */ 119 #define AD7193_CH_AIN3P_AIN4M 0x002 /* AIN3(+) - AIN4(-) */ 120 #define AD7193_CH_AIN5P_AIN6M 0x004 /* AIN5(+) - AIN6(-) */ 121 #define AD7193_CH_AIN7P_AIN8M 0x008 /* AIN7(+) - AIN8(-) */ 122 #define AD7193_CH_TEMP 0x100 /* Temp senseor */ 123 #define AD7193_CH_AIN2P_AIN2M 0x200 /* AIN2(+) - AIN2(-) */ 124 #define AD7193_CH_AIN1 0x401 /* AIN1 - AINCOM */ 125 #define AD7193_CH_AIN2 0x402 /* AIN2 - AINCOM */ 126 #define AD7193_CH_AIN3 0x404 /* AIN3 - AINCOM */ 127 #define AD7193_CH_AIN4 0x408 /* AIN4 - AINCOM */ 128 #define AD7193_CH_AIN5 0x410 /* AIN5 - AINCOM */ 129 #define AD7193_CH_AIN6 0x420 /* AIN6 - AINCOM */ 130 #define AD7193_CH_AIN7 0x440 /* AIN7 - AINCOM */ 131 #define AD7193_CH_AIN8 0x480 /* AIN7 - AINCOM */ 132 #define AD7193_CH_AINCOM 0x600 /* AINCOM - AINCOM */ 133 134 #define AD7194_CH_POS(x) (((x) - 1) << 4) 135 #define AD7194_CH_NEG(x) ((x) - 1) 136 137 /* 10th bit corresponds to CON18(Pseudo) */ 138 #define AD7194_CH(p) (BIT(10) | AD7194_CH_POS(p)) 139 140 #define AD7194_DIFF_CH(p, n) (AD7194_CH_POS(p) | AD7194_CH_NEG(n)) 141 #define AD7194_CH_TEMP 0x100 142 #define AD7194_CH_BASE_NR 2 143 #define AD7194_CH_AIN_START 1 144 #define AD7194_CH_AIN_NR 16 145 #define AD7194_CH_MAX_NR 272 146 147 /* ID Register Bit Designations (AD7192_REG_ID) */ 148 #define CHIPID_AD7190 0x4 149 #define CHIPID_AD7192 0x0 150 #define CHIPID_AD7193 0x2 151 #define CHIPID_AD7194 0x3 152 #define CHIPID_AD7195 0x6 153 #define AD7192_ID_MASK GENMASK(3, 0) 154 155 /* GPOCON Register Bit Designations (AD7192_REG_GPOCON) */ 156 #define AD7192_GPOCON_BPDSW BIT(6) /* Bridge power-down switch enable */ 157 #define AD7192_GPOCON_GP32EN BIT(5) /* Digital Output P3 and P2 enable */ 158 #define AD7192_GPOCON_GP10EN BIT(4) /* Digital Output P1 and P0 enable */ 159 #define AD7192_GPOCON_P3DAT BIT(3) /* P3 state */ 160 #define AD7192_GPOCON_P2DAT BIT(2) /* P2 state */ 161 #define AD7192_GPOCON_P1DAT BIT(1) /* P1 state */ 162 #define AD7192_GPOCON_P0DAT BIT(0) /* P0 state */ 163 164 #define AD7192_EXT_FREQ_MHZ_MIN 2457600 165 #define AD7192_EXT_FREQ_MHZ_MAX 5120000 166 #define AD7192_INT_FREQ_MHZ 4915200 167 168 #define AD7192_NO_SYNC_FILTER 1 169 #define AD7192_SYNC3_FILTER 3 170 #define AD7192_SYNC4_FILTER 4 171 172 /* NOTE: 173 * The AD7190/2/5 features a dual use data out ready DOUT/RDY output. 174 * In order to avoid contentions on the SPI bus, it's therefore necessary 175 * to use spi bus locking. 176 * 177 * The DOUT/RDY output must also be wired to an interrupt capable GPIO. 178 */ 179 180 enum { 181 AD7192_SYSCALIB_ZERO_SCALE, 182 AD7192_SYSCALIB_FULL_SCALE, 183 }; 184 185 enum { 186 ID_AD7190, 187 ID_AD7192, 188 ID_AD7193, 189 ID_AD7194, 190 ID_AD7195, 191 }; 192 193 struct ad7192_chip_info { 194 unsigned int chip_id; 195 const char *name; 196 const struct iio_chan_spec *channels; 197 u8 num_channels; 198 const struct ad_sigma_delta_info *sigma_delta_info; 199 const struct iio_info *info; 200 int (*parse_channels)(struct iio_dev *indio_dev); 201 }; 202 203 struct ad7192_state { 204 const struct ad7192_chip_info *chip_info; 205 struct clk *mclk; 206 struct clk_hw int_clk_hw; 207 u16 int_vref_mv; 208 u32 aincom_mv; 209 u32 fclk; 210 u32 mode; 211 u32 conf; 212 u32 scale_avail[8][2]; 213 u32 filter_freq_avail[4][2]; 214 u32 oversampling_ratio_avail[4]; 215 u8 gpocon; 216 u8 clock_sel; 217 struct mutex lock; /* protect sensor state */ 218 u8 syscalib_mode[8]; 219 220 struct ad_sigma_delta sd; 221 }; 222 223 static const char * const ad7192_syscalib_modes[] = { 224 [AD7192_SYSCALIB_ZERO_SCALE] = "zero_scale", 225 [AD7192_SYSCALIB_FULL_SCALE] = "full_scale", 226 }; 227 228 static int ad7192_set_syscalib_mode(struct iio_dev *indio_dev, 229 const struct iio_chan_spec *chan, 230 unsigned int mode) 231 { 232 struct ad7192_state *st = iio_priv(indio_dev); 233 234 st->syscalib_mode[chan->channel] = mode; 235 236 return 0; 237 } 238 239 static int ad7192_get_syscalib_mode(struct iio_dev *indio_dev, 240 const struct iio_chan_spec *chan) 241 { 242 struct ad7192_state *st = iio_priv(indio_dev); 243 244 return st->syscalib_mode[chan->channel]; 245 } 246 247 static ssize_t ad7192_write_syscalib(struct iio_dev *indio_dev, 248 uintptr_t private, 249 const struct iio_chan_spec *chan, 250 const char *buf, size_t len) 251 { 252 struct ad7192_state *st = iio_priv(indio_dev); 253 bool sys_calib; 254 int ret, temp; 255 256 ret = kstrtobool(buf, &sys_calib); 257 if (ret) 258 return ret; 259 260 if (!iio_device_claim_direct(indio_dev)) 261 return -EBUSY; 262 263 temp = st->syscalib_mode[chan->channel]; 264 if (sys_calib) { 265 if (temp == AD7192_SYSCALIB_ZERO_SCALE) 266 ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_ZERO, 267 chan->address); 268 else 269 ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_FULL, 270 chan->address); 271 } 272 273 iio_device_release_direct(indio_dev); 274 275 return ret ? ret : len; 276 } 277 278 static const struct iio_enum ad7192_syscalib_mode_enum = { 279 .items = ad7192_syscalib_modes, 280 .num_items = ARRAY_SIZE(ad7192_syscalib_modes), 281 .set = ad7192_set_syscalib_mode, 282 .get = ad7192_get_syscalib_mode 283 }; 284 285 static const struct iio_chan_spec_ext_info ad7192_calibsys_ext_info[] = { 286 { 287 .name = "sys_calibration", 288 .write = ad7192_write_syscalib, 289 .shared = IIO_SEPARATE, 290 }, 291 IIO_ENUM("sys_calibration_mode", IIO_SEPARATE, 292 &ad7192_syscalib_mode_enum), 293 IIO_ENUM_AVAILABLE("sys_calibration_mode", IIO_SHARED_BY_TYPE, 294 &ad7192_syscalib_mode_enum), 295 { } 296 }; 297 298 static struct ad7192_state *ad_sigma_delta_to_ad7192(struct ad_sigma_delta *sd) 299 { 300 return container_of(sd, struct ad7192_state, sd); 301 } 302 303 static int ad7192_set_channel(struct ad_sigma_delta *sd, unsigned int channel) 304 { 305 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd); 306 307 st->conf &= ~AD7192_CONF_CHAN_MASK; 308 st->conf |= FIELD_PREP(AD7192_CONF_CHAN_MASK, channel); 309 310 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); 311 } 312 313 static int ad7192_set_mode(struct ad_sigma_delta *sd, 314 enum ad_sigma_delta_mode mode) 315 { 316 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd); 317 318 st->mode &= ~AD7192_MODE_SEL_MASK; 319 st->mode |= FIELD_PREP(AD7192_MODE_SEL_MASK, mode); 320 321 return ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); 322 } 323 324 static int ad7192_append_status(struct ad_sigma_delta *sd, bool append) 325 { 326 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd); 327 unsigned int mode = st->mode; 328 int ret; 329 330 mode &= ~AD7192_MODE_STA_MASK; 331 mode |= FIELD_PREP(AD7192_MODE_STA_MASK, append); 332 333 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, mode); 334 if (ret < 0) 335 return ret; 336 337 st->mode = mode; 338 339 return 0; 340 } 341 342 static int ad7192_disable_all(struct ad_sigma_delta *sd) 343 { 344 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd); 345 u32 conf = st->conf; 346 int ret; 347 348 conf &= ~AD7192_CONF_CHAN_MASK; 349 350 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf); 351 if (ret < 0) 352 return ret; 353 354 st->conf = conf; 355 356 return 0; 357 } 358 359 static const struct ad_sigma_delta_info ad7192_sigma_delta_info = { 360 .set_channel = ad7192_set_channel, 361 .append_status = ad7192_append_status, 362 .disable_all = ad7192_disable_all, 363 .set_mode = ad7192_set_mode, 364 .has_registers = true, 365 .addr_shift = 3, 366 .read_mask = BIT(6), 367 .status_ch_mask = GENMASK(3, 0), 368 .num_slots = 4, 369 .irq_flags = IRQF_TRIGGER_FALLING, 370 .num_resetclks = 40, 371 }; 372 373 static const struct ad_sigma_delta_info ad7194_sigma_delta_info = { 374 .set_channel = ad7192_set_channel, 375 .append_status = ad7192_append_status, 376 .disable_all = ad7192_disable_all, 377 .set_mode = ad7192_set_mode, 378 .has_registers = true, 379 .addr_shift = 3, 380 .read_mask = BIT(6), 381 .status_ch_mask = GENMASK(3, 0), 382 .irq_flags = IRQF_TRIGGER_FALLING, 383 .num_resetclks = 40, 384 }; 385 386 static const struct ad_sd_calib_data ad7192_calib_arr[8] = { 387 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN1}, 388 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN1}, 389 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN2}, 390 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN2}, 391 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN3}, 392 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN3}, 393 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN4}, 394 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN4} 395 }; 396 397 static int ad7192_calibrate_all(struct ad7192_state *st) 398 { 399 return ad_sd_calibrate_all(&st->sd, ad7192_calib_arr, 400 ARRAY_SIZE(ad7192_calib_arr)); 401 } 402 403 static inline bool ad7192_valid_external_frequency(u32 freq) 404 { 405 return (freq >= AD7192_EXT_FREQ_MHZ_MIN && 406 freq <= AD7192_EXT_FREQ_MHZ_MAX); 407 } 408 409 /* 410 * Position 0 of ad7192_clock_names, xtal, corresponds to clock source 411 * configuration AD7192_CLK_EXT_MCLK1_2 and position 1, mclk, corresponds to 412 * AD7192_CLK_EXT_MCLK2 413 */ 414 static const char *const ad7192_clock_names[] = { 415 "xtal", 416 "mclk" 417 }; 418 419 static struct ad7192_state *clk_hw_to_ad7192(struct clk_hw *hw) 420 { 421 return container_of(hw, struct ad7192_state, int_clk_hw); 422 } 423 424 static unsigned long ad7192_clk_recalc_rate(struct clk_hw *hw, 425 unsigned long parent_rate) 426 { 427 return AD7192_INT_FREQ_MHZ; 428 } 429 430 static int ad7192_clk_output_is_enabled(struct clk_hw *hw) 431 { 432 struct ad7192_state *st = clk_hw_to_ad7192(hw); 433 434 return st->clock_sel == AD7192_CLK_INT_CO; 435 } 436 437 static int ad7192_clk_prepare(struct clk_hw *hw) 438 { 439 struct ad7192_state *st = clk_hw_to_ad7192(hw); 440 int ret; 441 442 st->mode &= ~AD7192_MODE_CLKSRC_MASK; 443 st->mode |= AD7192_CLK_INT_CO; 444 445 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); 446 if (ret) 447 return ret; 448 449 st->clock_sel = AD7192_CLK_INT_CO; 450 451 return 0; 452 } 453 454 static void ad7192_clk_unprepare(struct clk_hw *hw) 455 { 456 struct ad7192_state *st = clk_hw_to_ad7192(hw); 457 int ret; 458 459 st->mode &= ~AD7192_MODE_CLKSRC_MASK; 460 st->mode |= AD7192_CLK_INT; 461 462 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); 463 if (ret) 464 return; 465 466 st->clock_sel = AD7192_CLK_INT; 467 } 468 469 static const struct clk_ops ad7192_int_clk_ops = { 470 .recalc_rate = ad7192_clk_recalc_rate, 471 .is_enabled = ad7192_clk_output_is_enabled, 472 .prepare = ad7192_clk_prepare, 473 .unprepare = ad7192_clk_unprepare, 474 }; 475 476 static int ad7192_register_clk_provider(struct ad7192_state *st) 477 { 478 struct device *dev = &st->sd.spi->dev; 479 struct clk_init_data init = {}; 480 int ret; 481 482 if (!IS_ENABLED(CONFIG_COMMON_CLK)) 483 return 0; 484 485 if (!device_property_present(dev, "#clock-cells")) 486 return 0; 487 488 init.name = devm_kasprintf(dev, GFP_KERNEL, "%s-clk", 489 fwnode_get_name(dev_fwnode(dev))); 490 if (!init.name) 491 return -ENOMEM; 492 493 init.ops = &ad7192_int_clk_ops; 494 495 st->int_clk_hw.init = &init; 496 ret = devm_clk_hw_register(dev, &st->int_clk_hw); 497 if (ret) 498 return ret; 499 500 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, 501 &st->int_clk_hw); 502 } 503 504 static int ad7192_clock_setup(struct ad7192_state *st) 505 { 506 struct device *dev = &st->sd.spi->dev; 507 int ret; 508 509 /* 510 * The following two if branches are kept for backward compatibility but 511 * the use of the two devicetree properties is highly discouraged. Clock 512 * configuration should be done according to the bindings. 513 */ 514 515 if (device_property_read_bool(dev, "adi,int-clock-output-enable")) { 516 st->clock_sel = AD7192_CLK_INT_CO; 517 st->fclk = AD7192_INT_FREQ_MHZ; 518 dev_warn(dev, "Property adi,int-clock-output-enable is deprecated! Check bindings!\n"); 519 return 0; 520 } 521 522 if (device_property_read_bool(dev, "adi,clock-xtal")) { 523 st->clock_sel = AD7192_CLK_EXT_MCLK1_2; 524 st->mclk = devm_clk_get_enabled(dev, "mclk"); 525 if (IS_ERR(st->mclk)) 526 return dev_err_probe(dev, PTR_ERR(st->mclk), 527 "Failed to get mclk\n"); 528 529 st->fclk = clk_get_rate(st->mclk); 530 if (!ad7192_valid_external_frequency(st->fclk)) 531 return dev_err_probe(dev, -EINVAL, 532 "External clock frequency out of bounds\n"); 533 534 dev_warn(dev, "Property adi,clock-xtal is deprecated! Check bindings!\n"); 535 return 0; 536 } 537 538 ret = device_property_match_property_string(dev, "clock-names", 539 ad7192_clock_names, 540 ARRAY_SIZE(ad7192_clock_names)); 541 if (ret < 0) { 542 st->clock_sel = AD7192_CLK_INT; 543 st->fclk = AD7192_INT_FREQ_MHZ; 544 545 ret = ad7192_register_clk_provider(st); 546 if (ret) 547 return dev_err_probe(dev, ret, 548 "Failed to register clock provider\n"); 549 return 0; 550 } 551 552 st->clock_sel = AD7192_CLK_EXT_MCLK1_2 + ret; 553 554 st->mclk = devm_clk_get_enabled(dev, ad7192_clock_names[ret]); 555 if (IS_ERR(st->mclk)) 556 return dev_err_probe(dev, PTR_ERR(st->mclk), 557 "Failed to get clock source\n"); 558 559 st->fclk = clk_get_rate(st->mclk); 560 if (!ad7192_valid_external_frequency(st->fclk)) 561 return dev_err_probe(dev, -EINVAL, 562 "External clock frequency out of bounds\n"); 563 564 return 0; 565 } 566 567 static int ad7192_setup(struct iio_dev *indio_dev, struct device *dev) 568 { 569 struct ad7192_state *st = iio_priv(indio_dev); 570 bool rej60_en, refin2_en; 571 bool buf_en, bipolar, burnout_curr_en; 572 unsigned long long scale_uv; 573 int i, ret, id; 574 575 /* reset the serial interface */ 576 ret = ad_sd_reset(&st->sd); 577 if (ret < 0) 578 return ret; 579 580 /* 581 * Per AD7192 datasheet (Rev. A, page 34, RESET section), allow 582 * 500 us after a reset before accessing on-chip registers. 583 */ 584 fsleep(500); 585 586 /* write/read test for device presence */ 587 ret = ad_sd_read_reg(&st->sd, AD7192_REG_ID, 1, &id); 588 if (ret) 589 return ret; 590 591 id = FIELD_GET(AD7192_ID_MASK, id); 592 593 if (id != st->chip_info->chip_id) 594 dev_warn(dev, "device ID query failed (0x%X != 0x%X)\n", 595 id, st->chip_info->chip_id); 596 597 st->mode = FIELD_PREP(AD7192_MODE_SEL_MASK, AD7192_MODE_IDLE) | 598 FIELD_PREP(AD7192_MODE_CLKSRC_MASK, st->clock_sel) | 599 FIELD_PREP(AD7192_MODE_RATE_MASK, 480); 600 601 st->conf = FIELD_PREP(AD7192_CONF_GAIN_MASK, 0); 602 603 rej60_en = device_property_read_bool(dev, "adi,rejection-60-Hz-enable"); 604 if (rej60_en) 605 st->mode |= AD7192_MODE_REJ60; 606 607 refin2_en = device_property_read_bool(dev, "adi,refin2-pins-enable"); 608 if (refin2_en && st->chip_info->chip_id != CHIPID_AD7195) 609 st->conf |= AD7192_CONF_REFSEL; 610 611 st->conf &= ~AD7192_CONF_CHOP; 612 613 buf_en = device_property_read_bool(dev, "adi,buffer-enable"); 614 if (buf_en) 615 st->conf |= AD7192_CONF_BUF; 616 617 bipolar = device_property_read_bool(dev, "bipolar"); 618 if (!bipolar) 619 st->conf |= AD7192_CONF_UNIPOLAR; 620 621 burnout_curr_en = device_property_read_bool(dev, 622 "adi,burnout-currents-enable"); 623 if (burnout_curr_en && buf_en) { 624 st->conf |= AD7192_CONF_BURN; 625 } else if (burnout_curr_en) { 626 dev_warn(dev, 627 "Can't enable burnout currents: see CHOP or buffer\n"); 628 } 629 630 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); 631 if (ret) 632 return ret; 633 634 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); 635 if (ret) 636 return ret; 637 638 ret = ad7192_calibrate_all(st); 639 if (ret) 640 return ret; 641 642 /* Populate available ADC input ranges */ 643 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) { 644 scale_uv = ((u64)st->int_vref_mv * 100000000) 645 >> (indio_dev->channels[0].scan_type.realbits - 646 !FIELD_GET(AD7192_CONF_UNIPOLAR, st->conf)); 647 scale_uv >>= i; 648 649 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10; 650 st->scale_avail[i][0] = scale_uv; 651 } 652 653 st->oversampling_ratio_avail[0] = 1; 654 st->oversampling_ratio_avail[1] = 2; 655 st->oversampling_ratio_avail[2] = 8; 656 st->oversampling_ratio_avail[3] = 16; 657 658 st->filter_freq_avail[0][0] = 600; 659 st->filter_freq_avail[1][0] = 800; 660 st->filter_freq_avail[2][0] = 2300; 661 st->filter_freq_avail[3][0] = 2720; 662 663 st->filter_freq_avail[0][1] = 1000; 664 st->filter_freq_avail[1][1] = 1000; 665 st->filter_freq_avail[2][1] = 1000; 666 st->filter_freq_avail[3][1] = 1000; 667 668 return 0; 669 } 670 671 static ssize_t ad7192_show_ac_excitation(struct device *dev, 672 struct device_attribute *attr, 673 char *buf) 674 { 675 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 676 struct ad7192_state *st = iio_priv(indio_dev); 677 678 return sysfs_emit(buf, "%ld\n", FIELD_GET(AD7192_CONF_ACX, st->conf)); 679 } 680 681 static ssize_t ad7192_show_bridge_switch(struct device *dev, 682 struct device_attribute *attr, 683 char *buf) 684 { 685 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 686 struct ad7192_state *st = iio_priv(indio_dev); 687 688 return sysfs_emit(buf, "%ld\n", 689 FIELD_GET(AD7192_GPOCON_BPDSW, st->gpocon)); 690 } 691 692 static ssize_t ad7192_set(struct device *dev, 693 struct device_attribute *attr, 694 const char *buf, 695 size_t len) 696 { 697 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 698 struct ad7192_state *st = iio_priv(indio_dev); 699 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); 700 int ret; 701 bool val; 702 703 ret = kstrtobool(buf, &val); 704 if (ret < 0) 705 return ret; 706 707 if (!iio_device_claim_direct(indio_dev)) 708 return -EBUSY; 709 710 switch ((u32)this_attr->address) { 711 case AD7192_REG_GPOCON: 712 if (val) 713 st->gpocon |= AD7192_GPOCON_BPDSW; 714 else 715 st->gpocon &= ~AD7192_GPOCON_BPDSW; 716 717 ad_sd_write_reg(&st->sd, AD7192_REG_GPOCON, 1, st->gpocon); 718 break; 719 case AD7192_REG_CONF: 720 if (val) 721 st->conf |= AD7192_CONF_ACX; 722 else 723 st->conf &= ~AD7192_CONF_ACX; 724 725 ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); 726 break; 727 default: 728 ret = -EINVAL; 729 } 730 731 iio_device_release_direct(indio_dev); 732 733 return ret ? ret : len; 734 } 735 736 static int ad7192_compute_f_order(struct ad7192_state *st, bool sinc3_en, bool chop_en) 737 { 738 u8 avg_factor_selected, oversampling_ratio; 739 740 avg_factor_selected = FIELD_GET(AD7192_MODE_AVG_MASK, st->mode); 741 742 if (!avg_factor_selected && !chop_en) 743 return 1; 744 745 oversampling_ratio = st->oversampling_ratio_avail[avg_factor_selected]; 746 747 if (sinc3_en) 748 return AD7192_SYNC3_FILTER + oversampling_ratio - 1; 749 750 return AD7192_SYNC4_FILTER + oversampling_ratio - 1; 751 } 752 753 static int ad7192_get_f_order(struct ad7192_state *st) 754 { 755 bool sinc3_en, chop_en; 756 757 sinc3_en = FIELD_GET(AD7192_MODE_SINC3, st->mode); 758 chop_en = FIELD_GET(AD7192_CONF_CHOP, st->conf); 759 760 return ad7192_compute_f_order(st, sinc3_en, chop_en); 761 } 762 763 static int ad7192_compute_f_adc(struct ad7192_state *st, bool sinc3_en, 764 bool chop_en) 765 { 766 unsigned int f_order = ad7192_compute_f_order(st, sinc3_en, chop_en); 767 768 return DIV_ROUND_CLOSEST(st->fclk, 769 f_order * FIELD_GET(AD7192_MODE_RATE_MASK, st->mode)); 770 } 771 772 static int ad7192_get_f_adc(struct ad7192_state *st) 773 { 774 unsigned int f_order = ad7192_get_f_order(st); 775 776 return DIV_ROUND_CLOSEST(st->fclk, 777 f_order * FIELD_GET(AD7192_MODE_RATE_MASK, st->mode)); 778 } 779 780 static void ad7192_update_filter_freq_avail(struct ad7192_state *st) 781 { 782 unsigned int fadc; 783 784 /* Formulas for filter at page 25 of the datasheet */ 785 fadc = ad7192_compute_f_adc(st, false, true); 786 st->filter_freq_avail[0][0] = DIV_ROUND_CLOSEST(fadc * 240, 1024); 787 788 fadc = ad7192_compute_f_adc(st, true, true); 789 st->filter_freq_avail[1][0] = DIV_ROUND_CLOSEST(fadc * 240, 1024); 790 791 fadc = ad7192_compute_f_adc(st, false, false); 792 st->filter_freq_avail[2][0] = DIV_ROUND_CLOSEST(fadc * 230, 1024); 793 794 fadc = ad7192_compute_f_adc(st, true, false); 795 st->filter_freq_avail[3][0] = DIV_ROUND_CLOSEST(fadc * 272, 1024); 796 } 797 798 static IIO_DEVICE_ATTR(bridge_switch_en, 0644, 799 ad7192_show_bridge_switch, ad7192_set, 800 AD7192_REG_GPOCON); 801 802 static IIO_DEVICE_ATTR(ac_excitation_en, 0644, 803 ad7192_show_ac_excitation, ad7192_set, 804 AD7192_REG_CONF); 805 806 static struct attribute *ad7192_attributes[] = { 807 &iio_dev_attr_bridge_switch_en.dev_attr.attr, 808 NULL 809 }; 810 811 static const struct attribute_group ad7192_attribute_group = { 812 .attrs = ad7192_attributes, 813 }; 814 815 static struct attribute *ad7195_attributes[] = { 816 &iio_dev_attr_bridge_switch_en.dev_attr.attr, 817 &iio_dev_attr_ac_excitation_en.dev_attr.attr, 818 NULL 819 }; 820 821 static const struct attribute_group ad7195_attribute_group = { 822 .attrs = ad7195_attributes, 823 }; 824 825 static unsigned int ad7192_get_temp_scale(bool unipolar) 826 { 827 return unipolar ? 2815 * 2 : 2815; 828 } 829 830 static int ad7192_set_3db_filter_freq(struct ad7192_state *st, 831 int val, int val2) 832 { 833 int i, ret, freq; 834 unsigned int diff_new, diff_old; 835 int idx = 0; 836 837 diff_old = U32_MAX; 838 freq = val * 1000 + val2; 839 840 for (i = 0; i < ARRAY_SIZE(st->filter_freq_avail); i++) { 841 diff_new = abs(freq - st->filter_freq_avail[i][0]); 842 if (diff_new < diff_old) { 843 diff_old = diff_new; 844 idx = i; 845 } 846 } 847 848 switch (idx) { 849 case 0: 850 st->mode &= ~AD7192_MODE_SINC3; 851 852 st->conf |= AD7192_CONF_CHOP; 853 break; 854 case 1: 855 st->mode |= AD7192_MODE_SINC3; 856 857 st->conf |= AD7192_CONF_CHOP; 858 break; 859 case 2: 860 st->mode &= ~AD7192_MODE_SINC3; 861 862 st->conf &= ~AD7192_CONF_CHOP; 863 break; 864 case 3: 865 st->mode |= AD7192_MODE_SINC3; 866 867 st->conf &= ~AD7192_CONF_CHOP; 868 break; 869 } 870 871 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); 872 if (ret < 0) 873 return ret; 874 875 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); 876 } 877 878 static int ad7192_get_3db_filter_freq(struct ad7192_state *st) 879 { 880 unsigned int fadc; 881 882 fadc = ad7192_get_f_adc(st); 883 884 if (FIELD_GET(AD7192_CONF_CHOP, st->conf)) 885 return DIV_ROUND_CLOSEST(fadc * 240, 1024); 886 if (FIELD_GET(AD7192_MODE_SINC3, st->mode)) 887 return DIV_ROUND_CLOSEST(fadc * 272, 1024); 888 else 889 return DIV_ROUND_CLOSEST(fadc * 230, 1024); 890 } 891 892 static int ad7192_read_raw(struct iio_dev *indio_dev, 893 struct iio_chan_spec const *chan, 894 int *val, 895 int *val2, 896 long m) 897 { 898 struct ad7192_state *st = iio_priv(indio_dev); 899 bool unipolar = FIELD_GET(AD7192_CONF_UNIPOLAR, st->conf); 900 u8 gain = FIELD_GET(AD7192_CONF_GAIN_MASK, st->conf); 901 902 switch (m) { 903 case IIO_CHAN_INFO_RAW: 904 return ad_sigma_delta_single_conversion(indio_dev, chan, val); 905 case IIO_CHAN_INFO_SCALE: 906 switch (chan->type) { 907 case IIO_VOLTAGE: 908 mutex_lock(&st->lock); 909 *val = st->scale_avail[gain][0]; 910 *val2 = st->scale_avail[gain][1]; 911 mutex_unlock(&st->lock); 912 return IIO_VAL_INT_PLUS_NANO; 913 case IIO_TEMP: 914 *val = 0; 915 *val2 = 1000000000 / ad7192_get_temp_scale(unipolar); 916 return IIO_VAL_INT_PLUS_NANO; 917 default: 918 return -EINVAL; 919 } 920 case IIO_CHAN_INFO_OFFSET: 921 if (!unipolar) 922 *val = -(1 << (chan->scan_type.realbits - 1)); 923 else 924 *val = 0; 925 926 switch (chan->type) { 927 case IIO_VOLTAGE: 928 /* 929 * Only applies to pseudo-differential inputs. 930 * AINCOM voltage has to be converted to "raw" units. 931 */ 932 if (st->aincom_mv && !chan->differential) 933 *val += DIV_ROUND_CLOSEST_ULL((u64)st->aincom_mv * NANO, 934 st->scale_avail[gain][1]); 935 return IIO_VAL_INT; 936 /* Kelvin to Celsius */ 937 case IIO_TEMP: 938 *val -= 273 * ad7192_get_temp_scale(unipolar); 939 return IIO_VAL_INT; 940 default: 941 return -EINVAL; 942 } 943 case IIO_CHAN_INFO_SAMP_FREQ: 944 *val = DIV_ROUND_CLOSEST(ad7192_get_f_adc(st), 1024); 945 return IIO_VAL_INT; 946 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 947 *val = ad7192_get_3db_filter_freq(st); 948 *val2 = 1000; 949 return IIO_VAL_FRACTIONAL; 950 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 951 *val = st->oversampling_ratio_avail[FIELD_GET(AD7192_MODE_AVG_MASK, st->mode)]; 952 return IIO_VAL_INT; 953 } 954 955 return -EINVAL; 956 } 957 958 static int __ad7192_write_raw(struct iio_dev *indio_dev, 959 struct iio_chan_spec const *chan, 960 int val, 961 int val2, 962 long mask) 963 { 964 struct ad7192_state *st = iio_priv(indio_dev); 965 int i, div; 966 unsigned int tmp; 967 968 guard(mutex)(&st->lock); 969 970 switch (mask) { 971 case IIO_CHAN_INFO_SCALE: 972 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) { 973 if (val2 != st->scale_avail[i][1]) 974 continue; 975 976 tmp = st->conf; 977 st->conf &= ~AD7192_CONF_GAIN_MASK; 978 st->conf |= FIELD_PREP(AD7192_CONF_GAIN_MASK, i); 979 if (tmp == st->conf) 980 return 0; 981 ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); 982 ad7192_calibrate_all(st); 983 return 0; 984 } 985 return -EINVAL; 986 case IIO_CHAN_INFO_SAMP_FREQ: 987 if (!val) 988 return -EINVAL; 989 990 div = st->fclk / (val * ad7192_get_f_order(st) * 1024); 991 if (div < 1 || div > 1023) 992 return -EINVAL; 993 994 st->mode &= ~AD7192_MODE_RATE_MASK; 995 st->mode |= FIELD_PREP(AD7192_MODE_RATE_MASK, div); 996 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); 997 ad7192_update_filter_freq_avail(st); 998 return 0; 999 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 1000 return ad7192_set_3db_filter_freq(st, val, val2 / 1000); 1001 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1002 for (i = 0; i < ARRAY_SIZE(st->oversampling_ratio_avail); i++) { 1003 if (val != st->oversampling_ratio_avail[i]) 1004 continue; 1005 1006 tmp = st->mode; 1007 st->mode &= ~AD7192_MODE_AVG_MASK; 1008 st->mode |= FIELD_PREP(AD7192_MODE_AVG_MASK, i); 1009 if (tmp == st->mode) 1010 return 0; 1011 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); 1012 ad7192_update_filter_freq_avail(st); 1013 return 0; 1014 } 1015 return -EINVAL; 1016 default: 1017 return -EINVAL; 1018 } 1019 } 1020 1021 static int ad7192_write_raw(struct iio_dev *indio_dev, 1022 struct iio_chan_spec const *chan, 1023 int val, 1024 int val2, 1025 long mask) 1026 { 1027 int ret; 1028 1029 if (!iio_device_claim_direct(indio_dev)) 1030 return -EBUSY; 1031 1032 ret = __ad7192_write_raw(indio_dev, chan, val, val2, mask); 1033 1034 iio_device_release_direct(indio_dev); 1035 1036 return ret; 1037 } 1038 1039 static int ad7192_write_raw_get_fmt(struct iio_dev *indio_dev, 1040 struct iio_chan_spec const *chan, 1041 long mask) 1042 { 1043 switch (mask) { 1044 case IIO_CHAN_INFO_SCALE: 1045 return IIO_VAL_INT_PLUS_NANO; 1046 case IIO_CHAN_INFO_SAMP_FREQ: 1047 return IIO_VAL_INT; 1048 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 1049 return IIO_VAL_INT_PLUS_MICRO; 1050 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1051 return IIO_VAL_INT; 1052 default: 1053 return -EINVAL; 1054 } 1055 } 1056 1057 static int ad7192_read_avail(struct iio_dev *indio_dev, 1058 struct iio_chan_spec const *chan, 1059 const int **vals, int *type, int *length, 1060 long mask) 1061 { 1062 struct ad7192_state *st = iio_priv(indio_dev); 1063 1064 switch (mask) { 1065 case IIO_CHAN_INFO_SCALE: 1066 *vals = (int *)st->scale_avail; 1067 *type = IIO_VAL_INT_PLUS_NANO; 1068 /* Values are stored in a 2D matrix */ 1069 *length = ARRAY_SIZE(st->scale_avail) * 2; 1070 1071 return IIO_AVAIL_LIST; 1072 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 1073 *vals = (int *)st->filter_freq_avail; 1074 *type = IIO_VAL_FRACTIONAL; 1075 *length = ARRAY_SIZE(st->filter_freq_avail) * 2; 1076 1077 return IIO_AVAIL_LIST; 1078 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1079 *vals = (int *)st->oversampling_ratio_avail; 1080 *type = IIO_VAL_INT; 1081 *length = ARRAY_SIZE(st->oversampling_ratio_avail); 1082 1083 return IIO_AVAIL_LIST; 1084 } 1085 1086 return -EINVAL; 1087 } 1088 1089 static int ad7192_update_scan_mode(struct iio_dev *indio_dev, const unsigned long *scan_mask) 1090 { 1091 struct ad7192_state *st = iio_priv(indio_dev); 1092 u32 conf = st->conf; 1093 int ret; 1094 int i; 1095 1096 conf &= ~AD7192_CONF_CHAN_MASK; 1097 for_each_set_bit(i, scan_mask, 8) 1098 conf |= FIELD_PREP(AD7192_CONF_CHAN_MASK, BIT(i)); 1099 1100 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf); 1101 if (ret < 0) 1102 return ret; 1103 1104 st->conf = conf; 1105 1106 return 0; 1107 } 1108 1109 static const struct iio_info ad7192_info = { 1110 .read_raw = ad7192_read_raw, 1111 .write_raw = ad7192_write_raw, 1112 .write_raw_get_fmt = ad7192_write_raw_get_fmt, 1113 .read_avail = ad7192_read_avail, 1114 .attrs = &ad7192_attribute_group, 1115 .validate_trigger = ad_sd_validate_trigger, 1116 .update_scan_mode = ad7192_update_scan_mode, 1117 }; 1118 1119 static const struct iio_info ad7194_info = { 1120 .read_raw = ad7192_read_raw, 1121 .write_raw = ad7192_write_raw, 1122 .write_raw_get_fmt = ad7192_write_raw_get_fmt, 1123 .read_avail = ad7192_read_avail, 1124 .validate_trigger = ad_sd_validate_trigger, 1125 }; 1126 1127 static const struct iio_info ad7195_info = { 1128 .read_raw = ad7192_read_raw, 1129 .write_raw = ad7192_write_raw, 1130 .write_raw_get_fmt = ad7192_write_raw_get_fmt, 1131 .read_avail = ad7192_read_avail, 1132 .attrs = &ad7195_attribute_group, 1133 .validate_trigger = ad_sd_validate_trigger, 1134 .update_scan_mode = ad7192_update_scan_mode, 1135 }; 1136 1137 #define __AD719x_CHANNEL(_si, _channel1, _channel2, _address, _type, \ 1138 _mask_all, _mask_type_av, _mask_all_av, _ext_info) \ 1139 { \ 1140 .type = (_type), \ 1141 .differential = ((_channel2) == -1 ? 0 : 1), \ 1142 .indexed = 1, \ 1143 .channel = (_channel1), \ 1144 .channel2 = (_channel2), \ 1145 .address = (_address), \ 1146 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 1147 BIT(IIO_CHAN_INFO_OFFSET), \ 1148 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 1149 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 1150 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \ 1151 (_mask_all), \ 1152 .info_mask_shared_by_type_available = (_mask_type_av), \ 1153 .info_mask_shared_by_all_available = \ 1154 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \ 1155 (_mask_all_av), \ 1156 .ext_info = (_ext_info), \ 1157 .scan_index = (_si), \ 1158 .scan_type = { \ 1159 .sign = 'u', \ 1160 .realbits = 24, \ 1161 .storagebits = 32, \ 1162 .endianness = IIO_BE, \ 1163 }, \ 1164 } 1165 1166 #define AD719x_DIFF_CHANNEL(_si, _channel1, _channel2, _address) \ 1167 __AD719x_CHANNEL(_si, _channel1, _channel2, _address, IIO_VOLTAGE, 0, \ 1168 BIT(IIO_CHAN_INFO_SCALE), 0, ad7192_calibsys_ext_info) 1169 1170 #define AD719x_CHANNEL(_si, _channel1, _address) \ 1171 __AD719x_CHANNEL(_si, _channel1, -1, _address, IIO_VOLTAGE, 0, \ 1172 BIT(IIO_CHAN_INFO_SCALE), 0, ad7192_calibsys_ext_info) 1173 1174 #define AD719x_TEMP_CHANNEL(_si, _address) \ 1175 __AD719x_CHANNEL(_si, 0, -1, _address, IIO_TEMP, 0, 0, 0, NULL) 1176 1177 #define AD7193_DIFF_CHANNEL(_si, _channel1, _channel2, _address) \ 1178 __AD719x_CHANNEL(_si, _channel1, _channel2, _address, \ 1179 IIO_VOLTAGE, \ 1180 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 1181 BIT(IIO_CHAN_INFO_SCALE), \ 1182 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 1183 ad7192_calibsys_ext_info) 1184 1185 #define AD7193_CHANNEL(_si, _channel1, _address) \ 1186 AD7193_DIFF_CHANNEL(_si, _channel1, -1, _address) 1187 1188 static const struct iio_chan_spec ad7192_channels[] = { 1189 AD719x_DIFF_CHANNEL(0, 1, 2, AD7192_CH_AIN1P_AIN2M), 1190 AD719x_DIFF_CHANNEL(1, 3, 4, AD7192_CH_AIN3P_AIN4M), 1191 AD719x_TEMP_CHANNEL(2, AD7192_CH_TEMP), 1192 AD719x_DIFF_CHANNEL(3, 2, 2, AD7192_CH_AIN2P_AIN2M), 1193 AD719x_CHANNEL(4, 1, AD7192_CH_AIN1), 1194 AD719x_CHANNEL(5, 2, AD7192_CH_AIN2), 1195 AD719x_CHANNEL(6, 3, AD7192_CH_AIN3), 1196 AD719x_CHANNEL(7, 4, AD7192_CH_AIN4), 1197 IIO_CHAN_SOFT_TIMESTAMP(8), 1198 }; 1199 1200 static const struct iio_chan_spec ad7193_channels[] = { 1201 AD7193_DIFF_CHANNEL(0, 1, 2, AD7193_CH_AIN1P_AIN2M), 1202 AD7193_DIFF_CHANNEL(1, 3, 4, AD7193_CH_AIN3P_AIN4M), 1203 AD7193_DIFF_CHANNEL(2, 5, 6, AD7193_CH_AIN5P_AIN6M), 1204 AD7193_DIFF_CHANNEL(3, 7, 8, AD7193_CH_AIN7P_AIN8M), 1205 AD719x_TEMP_CHANNEL(4, AD7193_CH_TEMP), 1206 AD7193_DIFF_CHANNEL(5, 2, 2, AD7193_CH_AIN2P_AIN2M), 1207 AD7193_CHANNEL(6, 1, AD7193_CH_AIN1), 1208 AD7193_CHANNEL(7, 2, AD7193_CH_AIN2), 1209 AD7193_CHANNEL(8, 3, AD7193_CH_AIN3), 1210 AD7193_CHANNEL(9, 4, AD7193_CH_AIN4), 1211 AD7193_CHANNEL(10, 5, AD7193_CH_AIN5), 1212 AD7193_CHANNEL(11, 6, AD7193_CH_AIN6), 1213 AD7193_CHANNEL(12, 7, AD7193_CH_AIN7), 1214 AD7193_CHANNEL(13, 8, AD7193_CH_AIN8), 1215 IIO_CHAN_SOFT_TIMESTAMP(14), 1216 }; 1217 1218 static bool ad7194_validate_ain_channel(struct device *dev, u32 ain) 1219 { 1220 return in_range(ain, AD7194_CH_AIN_START, AD7194_CH_AIN_NR); 1221 } 1222 1223 static int ad7194_parse_channels(struct iio_dev *indio_dev) 1224 { 1225 struct device *dev = indio_dev->dev.parent; 1226 struct iio_chan_spec *ad7194_channels; 1227 const struct iio_chan_spec ad7194_chan = AD7193_CHANNEL(0, 0, 0); 1228 const struct iio_chan_spec ad7194_chan_diff = AD7193_DIFF_CHANNEL(0, 0, 0, 0); 1229 const struct iio_chan_spec ad7194_chan_temp = AD719x_TEMP_CHANNEL(0, 0); 1230 const struct iio_chan_spec ad7194_chan_timestamp = IIO_CHAN_SOFT_TIMESTAMP(0); 1231 unsigned int num_channels, index = 0; 1232 u32 ain[2]; 1233 int ret; 1234 1235 num_channels = device_get_child_node_count(dev); 1236 if (num_channels > AD7194_CH_MAX_NR) 1237 return dev_err_probe(dev, -EINVAL, "Too many channels: %u\n", 1238 num_channels); 1239 1240 num_channels += AD7194_CH_BASE_NR; 1241 1242 ad7194_channels = devm_kcalloc(dev, num_channels, 1243 sizeof(*ad7194_channels), GFP_KERNEL); 1244 if (!ad7194_channels) 1245 return -ENOMEM; 1246 1247 indio_dev->channels = ad7194_channels; 1248 indio_dev->num_channels = num_channels; 1249 1250 device_for_each_child_node_scoped(dev, child) { 1251 ret = fwnode_property_read_u32_array(child, "diff-channels", 1252 ain, ARRAY_SIZE(ain)); 1253 if (ret == 0) { 1254 if (!ad7194_validate_ain_channel(dev, ain[0])) 1255 return dev_err_probe(dev, -EINVAL, 1256 "Invalid AIN channel: %u\n", 1257 ain[0]); 1258 1259 if (!ad7194_validate_ain_channel(dev, ain[1])) 1260 return dev_err_probe(dev, -EINVAL, 1261 "Invalid AIN channel: %u\n", 1262 ain[1]); 1263 1264 *ad7194_channels = ad7194_chan_diff; 1265 ad7194_channels->scan_index = index++; 1266 ad7194_channels->channel = ain[0]; 1267 ad7194_channels->channel2 = ain[1]; 1268 ad7194_channels->address = AD7194_DIFF_CH(ain[0], ain[1]); 1269 } else { 1270 ret = fwnode_property_read_u32(child, "single-channel", 1271 &ain[0]); 1272 if (ret) 1273 return dev_err_probe(dev, ret, 1274 "Missing channel property\n"); 1275 1276 if (!ad7194_validate_ain_channel(dev, ain[0])) 1277 return dev_err_probe(dev, -EINVAL, 1278 "Invalid AIN channel: %u\n", 1279 ain[0]); 1280 1281 *ad7194_channels = ad7194_chan; 1282 ad7194_channels->scan_index = index++; 1283 ad7194_channels->channel = ain[0]; 1284 ad7194_channels->address = AD7194_CH(ain[0]); 1285 } 1286 ad7194_channels++; 1287 } 1288 1289 *ad7194_channels = ad7194_chan_temp; 1290 ad7194_channels->scan_index = index++; 1291 ad7194_channels->address = AD7194_CH_TEMP; 1292 ad7194_channels++; 1293 1294 *ad7194_channels = ad7194_chan_timestamp; 1295 ad7194_channels->scan_index = index; 1296 1297 return 0; 1298 } 1299 1300 static const struct ad7192_chip_info ad7192_chip_info_tbl[] = { 1301 [ID_AD7190] = { 1302 .chip_id = CHIPID_AD7190, 1303 .name = "ad7190", 1304 .channels = ad7192_channels, 1305 .num_channels = ARRAY_SIZE(ad7192_channels), 1306 .sigma_delta_info = &ad7192_sigma_delta_info, 1307 .info = &ad7192_info, 1308 }, 1309 [ID_AD7192] = { 1310 .chip_id = CHIPID_AD7192, 1311 .name = "ad7192", 1312 .channels = ad7192_channels, 1313 .num_channels = ARRAY_SIZE(ad7192_channels), 1314 .sigma_delta_info = &ad7192_sigma_delta_info, 1315 .info = &ad7192_info, 1316 }, 1317 [ID_AD7193] = { 1318 .chip_id = CHIPID_AD7193, 1319 .name = "ad7193", 1320 .channels = ad7193_channels, 1321 .num_channels = ARRAY_SIZE(ad7193_channels), 1322 .sigma_delta_info = &ad7192_sigma_delta_info, 1323 .info = &ad7192_info, 1324 }, 1325 [ID_AD7194] = { 1326 .chip_id = CHIPID_AD7194, 1327 .name = "ad7194", 1328 .info = &ad7194_info, 1329 .sigma_delta_info = &ad7194_sigma_delta_info, 1330 .parse_channels = ad7194_parse_channels, 1331 }, 1332 [ID_AD7195] = { 1333 .chip_id = CHIPID_AD7195, 1334 .name = "ad7195", 1335 .channels = ad7192_channels, 1336 .num_channels = ARRAY_SIZE(ad7192_channels), 1337 .sigma_delta_info = &ad7192_sigma_delta_info, 1338 .info = &ad7195_info, 1339 }, 1340 }; 1341 1342 static int ad7192_probe(struct spi_device *spi) 1343 { 1344 struct device *dev = &spi->dev; 1345 struct ad7192_state *st; 1346 struct iio_dev *indio_dev; 1347 int ret, avdd_mv; 1348 1349 if (!spi->irq) 1350 return dev_err_probe(dev, -ENODEV, "Failed to get IRQ\n"); 1351 1352 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 1353 if (!indio_dev) 1354 return -ENOMEM; 1355 1356 st = iio_priv(indio_dev); 1357 1358 mutex_init(&st->lock); 1359 1360 /* 1361 * Regulator aincom is optional to maintain compatibility with older DT. 1362 * Newer firmware should provide a zero volt fixed supply if wired to 1363 * ground. 1364 */ 1365 ret = devm_regulator_get_enable_read_voltage(dev, "aincom"); 1366 if (ret < 0 && ret != -ENODEV) 1367 return dev_err_probe(dev, ret, "Failed to get AINCOM voltage\n"); 1368 1369 st->aincom_mv = ret == -ENODEV ? 0 : ret / MILLI; 1370 1371 /* AVDD can optionally be used as reference voltage */ 1372 ret = devm_regulator_get_enable_read_voltage(dev, "avdd"); 1373 if (ret == -ENODEV || ret == -EINVAL) { 1374 int ret2; 1375 1376 /* 1377 * We get -EINVAL if avdd is a supply with unknown voltage. We 1378 * still need to enable it since it is also a power supply. 1379 */ 1380 ret2 = devm_regulator_get_enable(dev, "avdd"); 1381 if (ret2) 1382 return dev_err_probe(dev, ret2, 1383 "Failed to enable AVDD supply\n"); 1384 } else if (ret < 0) { 1385 return dev_err_probe(dev, ret, "Failed to get AVDD voltage\n"); 1386 } 1387 1388 avdd_mv = ret == -ENODEV || ret == -EINVAL ? 0 : ret / MILLI; 1389 1390 ret = devm_regulator_get_enable(dev, "dvdd"); 1391 if (ret) 1392 return dev_err_probe(dev, ret, "Failed to enable specified DVdd supply\n"); 1393 1394 /* 1395 * This is either REFIN1 or REFIN2 depending on adi,refin2-pins-enable. 1396 * If this supply is not present, fall back to AVDD as reference. 1397 */ 1398 ret = devm_regulator_get_enable_read_voltage(dev, "vref"); 1399 if (ret == -ENODEV) { 1400 if (avdd_mv == 0) 1401 return dev_err_probe(dev, -ENODEV, 1402 "No reference voltage available\n"); 1403 } else if (ret < 0) { 1404 return ret; 1405 } 1406 1407 st->int_vref_mv = ret == -ENODEV ? avdd_mv : ret / MILLI; 1408 1409 st->chip_info = spi_get_device_match_data(spi); 1410 indio_dev->name = st->chip_info->name; 1411 indio_dev->modes = INDIO_DIRECT_MODE; 1412 indio_dev->info = st->chip_info->info; 1413 if (st->chip_info->parse_channels) { 1414 ret = st->chip_info->parse_channels(indio_dev); 1415 if (ret) 1416 return ret; 1417 } else { 1418 indio_dev->channels = st->chip_info->channels; 1419 indio_dev->num_channels = st->chip_info->num_channels; 1420 } 1421 1422 ret = ad_sd_init(&st->sd, indio_dev, spi, st->chip_info->sigma_delta_info); 1423 if (ret) 1424 return ret; 1425 1426 ret = devm_ad_sd_setup_buffer_and_trigger(dev, indio_dev); 1427 if (ret) 1428 return ret; 1429 1430 ret = ad7192_clock_setup(st); 1431 if (ret) 1432 return ret; 1433 1434 ret = ad7192_setup(indio_dev, dev); 1435 if (ret) 1436 return ret; 1437 1438 return devm_iio_device_register(dev, indio_dev); 1439 } 1440 1441 static const struct of_device_id ad7192_of_match[] = { 1442 { .compatible = "adi,ad7190", .data = &ad7192_chip_info_tbl[ID_AD7190] }, 1443 { .compatible = "adi,ad7192", .data = &ad7192_chip_info_tbl[ID_AD7192] }, 1444 { .compatible = "adi,ad7193", .data = &ad7192_chip_info_tbl[ID_AD7193] }, 1445 { .compatible = "adi,ad7194", .data = &ad7192_chip_info_tbl[ID_AD7194] }, 1446 { .compatible = "adi,ad7195", .data = &ad7192_chip_info_tbl[ID_AD7195] }, 1447 { } 1448 }; 1449 MODULE_DEVICE_TABLE(of, ad7192_of_match); 1450 1451 static const struct spi_device_id ad7192_ids[] = { 1452 { "ad7190", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7190] }, 1453 { "ad7192", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7192] }, 1454 { "ad7193", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7193] }, 1455 { "ad7194", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7194] }, 1456 { "ad7195", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7195] }, 1457 { } 1458 }; 1459 MODULE_DEVICE_TABLE(spi, ad7192_ids); 1460 1461 static struct spi_driver ad7192_driver = { 1462 .driver = { 1463 .name = "ad7192", 1464 .of_match_table = ad7192_of_match, 1465 }, 1466 .probe = ad7192_probe, 1467 .id_table = ad7192_ids, 1468 }; 1469 module_spi_driver(ad7192_driver); 1470 1471 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); 1472 MODULE_DESCRIPTION("Analog Devices AD7192 and similar ADC"); 1473 MODULE_LICENSE("GPL v2"); 1474 MODULE_IMPORT_NS("IIO_AD_SIGMA_DELTA"); 1475