1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_HDMI_TYPES_H 27 #define DC_HDMI_TYPES_H 28 29 #include "os_types.h" 30 31 /* Address range from 0x00 to 0x1F.*/ 32 #define DP_ADAPTOR_TYPE2_SIZE 0x20 33 #define DP_ADAPTOR_TYPE2_REG_ID 0x10 34 #define DP_ADAPTOR_TYPE2_REG_MAX_TMDS_CLK 0x1D 35 /* Identifies adaptor as Dual-mode adaptor */ 36 #define DP_ADAPTOR_TYPE2_ID 0xA0 37 /* MHz*/ 38 #define DP_ADAPTOR_TYPE2_MAX_TMDS_CLK 600 39 /* MHz*/ 40 #define DP_ADAPTOR_TYPE2_MIN_TMDS_CLK 25 41 /* kHZ*/ 42 #define DP_ADAPTOR_DVI_MAX_TMDS_CLK 165000 43 /* kHZ*/ 44 #define DP_ADAPTOR_HDMI_SAFE_MAX_TMDS_CLK 340000 45 46 struct dp_hdmi_dongle_signature_data { 47 int8_t id[15];/* "DP-HDMI ADAPTOR"*/ 48 uint8_t eot;/* end of transmition '\x4' */ 49 }; 50 51 /* DP-HDMI dongle slave address for retrieving dongle signature*/ 52 #define DP_HDMI_DONGLE_ADDRESS 0x40 53 #define DP_HDMI_DONGLE_SIGNATURE_EOT 0x04 54 55 56 /* SCDC Address defines (HDMI 2.0)*/ 57 #define HDMI_SCDC_WRITE_UPDATE_0_ARRAY 3 58 #define HDMI_SCDC_ADDRESS 0x54 59 #define HDMI_SCDC_SINK_VERSION 0x01 60 #define HDMI_SCDC_SOURCE_VERSION 0x02 61 #define HDMI_SCDC_UPDATE_0 0x10 62 #define HDMI_SCDC_TMDS_CONFIG 0x20 63 #define HDMI_SCDC_SCRAMBLER_STATUS 0x21 64 #define HDMI_SCDC_CONFIG_0 0x30 65 #define HDMI_SCDC_CONFIG_1 0x31 66 #define HDMI_SCDC_SOURCE_TEST_REQ 0x35 67 #define HDMI_SCDC_STATUS_FLAGS 0x40 68 #define HDMI_SCDC_LTP_REQ 0x41 69 #define HDMI_SCDC_ERR_DETECT 0x50 70 #define HDMI_SCDC_TEST_CONFIG 0xC0 71 72 #define HDMI_SCDC_MANUFACTURER_OUI 0xD0 73 #define HDMI_SCDC_DEVICE_ID 0xDB 74 75 /* IDCC defines (HDMI 2.0) */ 76 #define HDMI_IDCC_ADDRESS 0x50 77 #define HDMI_IDCC_MARKER0 0xAE 78 #define HDMI_IDCC_MARKER1 0x6E 79 #define HDMI_IDCC_MARKER2 0x60 80 81 enum hdmi_idcc_scope { 82 HDMI_IDCC_SCOPE_WRITE = 0x00, 83 HDMI_IDCC_SCOPE_RW_CA = 0x01, 84 HDMI_IDCC_SCOPE_RW_SINK = 0x02, 85 }; 86 87 union hdmi_idcc_source_id { 88 struct { 89 uint8_t SI_PCA_n:1; 90 uint8_t AC_n:1; 91 uint8_t RESERVED:6; 92 } bits; 93 uint8_t raw; 94 }; 95 96 union hdmi_idcc_cable_id { 97 struct { 98 uint8_t Cat1_n:1; 99 uint8_t Cat2_n:1; 100 uint8_t Cat3_n:1; 101 uint8_t Cat4_n:1; 102 uint8_t RESERVED:4; 103 uint8_t HEAC_n:1; 104 uint8_t PCA_DEP_n:1; 105 uint8_t MonoDir_n:1; 106 uint8_t MonoDirErr_n:1; 107 uint8_t PCA_ON_n:1; 108 uint8_t no_DeEmphasis_n:1; 109 uint8_t no_PreShoot_n:1; 110 uint8_t RESERVED2:1; 111 uint8_t RND_bits_7_0:8; 112 uint8_t RND_bits_15_8:8; 113 } bits; 114 uint8_t raw[4]; 115 }; 116 union hdmi_scdc_update_read_data { 117 uint8_t byte[2]; 118 struct { 119 uint8_t STATUS_UPDATE:1; 120 uint8_t CED_UPDATE:1; 121 uint8_t RR_TEST:1; 122 uint8_t SOURCE_TEST_UPDATE:1; 123 uint8_t FRL_START:1; 124 uint8_t FLT_UPDATE:1; 125 uint8_t RSED_UPDATE:1; 126 uint8_t RESERVED:1; 127 uint8_t RESERVED2:8; 128 } fields; 129 }; 130 131 union hdmi_scdc_status_flags_data { 132 uint8_t byte; 133 struct { 134 uint8_t CLOCK_DETECTED:1; 135 uint8_t CH0_LOCKED:1; 136 uint8_t CH1_LOCKED:1; 137 uint8_t CH2_LOCKED:1; 138 uint8_t LANE3_LOCKED:1; 139 uint8_t RESERVED:1; 140 uint8_t FLT_READY:1; 141 uint8_t DSC_DECODEFAIL:1; 142 } fields; 143 }; 144 145 union hdmi_scdc_LTP_req_data { 146 uint8_t byte[2]; 147 struct { 148 uint8_t LN0_LTP_REQ:4; 149 uint8_t LN1_LTP_REQ:4; 150 uint8_t LN2_LTP_REQ:4; 151 uint8_t LN3_LTP_REQ:4; 152 } fields; 153 }; 154 155 union hdmi_scdc_ced_data { 156 uint8_t byte[11]; 157 struct { 158 uint8_t CH0_8LOW:8; 159 uint8_t CH0_7HIGH:7; 160 uint8_t CH0_VALID:1; 161 uint8_t CH1_8LOW:8; 162 uint8_t CH1_7HIGH:7; 163 uint8_t CH1_VALID:1; 164 uint8_t CH2_8LOW:8; 165 uint8_t CH2_7HIGH:7; 166 uint8_t CH2_VALID:1; 167 uint8_t CHECKSUM:8; 168 uint8_t LN3_8LOW:8; 169 uint8_t LN3_7HIGH:7; 170 uint8_t LN3_VALID:1; 171 uint8_t RSC_8LOW:8; 172 uint8_t RSC_7HIGH:7; 173 uint8_t RSC_VALID:1; 174 } fields; 175 }; 176 177 union hdmi_scdc_manufacturer_OUI_data { 178 uint8_t byte[3]; 179 struct { 180 uint8_t Manufacturer_OUI_1:8; 181 uint8_t Manufacturer_OUI_2:8; 182 uint8_t Manufacturer_OUI_3:8; 183 } fields; 184 }; 185 186 union hdmi_scdc_device_id_data { 187 uint8_t byte; 188 struct { 189 uint8_t Hardware_Minor_Rev:4; 190 uint8_t Hardware_Major_Rev:4; 191 } fields; 192 }; 193 194 union hdmi_scdc_configuration { 195 uint8_t byte[2]; 196 struct { 197 uint8_t RR_ENABLE:1; 198 uint8_t FLT_NO_RETRAIN:1; 199 uint8_t RESERVED:6; 200 uint8_t FRL_RATE:4; 201 uint8_t FFE_LEVELS:4; 202 } fields; 203 }; 204 205 union hdmi_scdc_source_test_req { 206 uint8_t byte; 207 struct { 208 uint8_t RESERVED:1; 209 uint8_t TXFFE_PRESHOOT:1; 210 uint8_t TXFFE_DEEMPHASIS:1; 211 uint8_t TXFFE_NOFFE:1; 212 uint8_t RESERVED2:1; 213 uint8_t FLT_NO_TIMEOUT:1; 214 uint8_t DSC_FRL_MAX:1; 215 uint8_t FRL_MAX:1; 216 } fields; 217 }; 218 219 union hdmi_scdc_test_config_Data { 220 uint8_t byte; 221 struct { 222 uint8_t TEST_READ_REQUEST_DELAY:7; 223 uint8_t TEST_READ_REQUEST: 1; 224 } fields; 225 }; 226 227 enum hdmi_frl_borrow_mode { 228 HDMI_FRL_BORROW_MODE_NONE, 229 HDMI_FRL_BORROW_MODE_FROM_ACTIVE, 230 HDMI_FRL_BORROW_MODE_FROM_BLANK 231 }; 232 233 enum link_result { 234 LINK_RESULT_UNKNOWN = 0, 235 LINK_RESULT_SUCCESS, 236 LINK_RESULT_LOWER_LINKRATE, 237 LINK_RESULT_TIMEOUT, 238 LINK_RESULT_FALLBACK 239 }; 240 241 enum hdmi_frl_link_rate { 242 HDMI_FRL_LINK_RATE_DISABLE = 0, 243 HDMI_FRL_LINK_RATE_3GBPS, 244 HDMI_FRL_LINK_RATE_6GBPS, 245 HDMI_FRL_LINK_RATE_6GBPS_4LANE, 246 HDMI_FRL_LINK_RATE_8GBPS, 247 HDMI_FRL_LINK_RATE_10GBPS, 248 HDMI_FRL_LINK_RATE_12GBPS, 249 HDMI_FRL_LINK_RATE_16GBPS, 250 HDMI_FRL_LINK_RATE_20GBPS, 251 HDMI_FRL_LINK_RATE_24GBPS 252 }; 253 254 struct frl_borrow_params { 255 int audio_packets_line; 256 int hc_active_target; 257 int hc_blank_target; 258 enum hdmi_frl_borrow_mode borrow_mode; 259 }; 260 261 struct dc_hdmi_frl_link_settings { 262 enum hdmi_frl_link_rate frl_link_rate; 263 uint8_t frl_num_lanes; 264 struct frl_borrow_params borrow_params; 265 int average_tribyte_rate; 266 }; 267 268 struct dc_hdmi_frl_flags { 269 unsigned int force_frl_rate; 270 bool ignore_ffe; 271 int select_ffe; 272 int limit_ffe; 273 bool force_frl_always; 274 bool force_frl_dsc; 275 bool force_frl_max; 276 bool apply_vsdb_rcc_wa; 277 }; 278 279 struct dc_hdmi_frl_link_training_overrides { 280 bool force_frl_always; 281 bool force_frl_max; 282 uint8_t max_retries; 283 bool valid; 284 }; 285 #endif /* DC_HDMI_TYPES_H */ 286