xref: /linux/drivers/scsi/qlogicpti.h (revision 597473720f4dc69749542bfcfed4a927a43d935e)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* qlogicpti.h: Performance Technologies QlogicISP sbus card defines.
3  *
4  * Copyright (C) 1996 David S. Miller (davem@caipfs.rutgers.edu)
5  */
6 
7 #ifndef _QLOGICPTI_H
8 #define _QLOGICPTI_H
9 
10 /* Qlogic/SBUS controller registers. */
11 #define SBUS_CFG1	0x006UL
12 #define SBUS_CTRL	0x008UL
13 #define SBUS_STAT	0x00aUL
14 #define SBUS_SEMAPHORE	0x00cUL
15 #define CMD_DMA_CTRL	0x022UL
16 #define DATA_DMA_CTRL	0x042UL
17 #define MBOX0		0x080UL
18 #define MBOX1		0x082UL
19 #define MBOX2		0x084UL
20 #define MBOX3		0x086UL
21 #define MBOX4		0x088UL
22 #define MBOX5		0x08aUL
23 #define CPU_CMD		0x214UL
24 #define CPU_ORIDE	0x224UL
25 #define CPU_PCTRL	0x272UL
26 #define CPU_PDIFF	0x276UL
27 #define RISC_PSR	0x420UL
28 #define RISC_MTREG	0x42EUL
29 #define HCCTRL		0x440UL
30 
31 /* SCSI parameters for this driver. */
32 #define MAX_TARGETS	16
33 #define MAX_LUNS	8
34 
35 /* With the qlogic interface, every queue slot can hold a SCSI
36  * command with up to 4 scatter/gather entries.  If we need more
37  * than 4 entries, continuation entries can be used that hold
38  * another 7 entries each.  Unlike for other drivers, this means
39  * that the maximum number of scatter/gather entries we can
40  * support at any given time is a function of the number of queue
41  * slots available.  That is, host->can_queue and host->sg_tablesize
42  * are dynamic and _not_ independent.  This all works fine because
43  * requests are queued serially and the scatter/gather limit is
44  * determined for each queue request anew.
45  */
46 #define QLOGICPTI_REQ_QUEUE_LEN	255	/* must be power of two - 1 */
47 #define QLOGICPTI_MAX_SG(ql)	(4 + (((ql) > 0) ? 7*((ql) - 1) : 0))
48 
49 /* mailbox command complete status codes */
50 #define MBOX_COMMAND_COMPLETE		0x4000
51 #define INVALID_COMMAND			0x4001
52 #define HOST_INTERFACE_ERROR		0x4002
53 #define TEST_FAILED			0x4003
54 #define COMMAND_ERROR			0x4005
55 #define COMMAND_PARAM_ERROR		0x4006
56 
57 /* async event status codes */
58 #define ASYNC_SCSI_BUS_RESET		0x8001
59 #define SYSTEM_ERROR			0x8002
60 #define REQUEST_TRANSFER_ERROR		0x8003
61 #define RESPONSE_TRANSFER_ERROR		0x8004
62 #define REQUEST_QUEUE_WAKEUP		0x8005
63 #define EXECUTION_TIMEOUT_RESET		0x8006
64 
65 /* Am I fucking pedantic or what? */
66 struct Entry_header {
67 #ifdef __BIG_ENDIAN
68 	u8	entry_cnt;
69 	u8	entry_type;
70 	u8	flags;
71 	u8	sys_def_1;
72 #else /* __LITTLE_ENDIAN */
73 	u8	entry_type;
74 	u8	entry_cnt;
75 	u8	sys_def_1;
76 	u8	flags;
77 #endif
78 };
79 
80 /* entry header type commands */
81 #define ENTRY_COMMAND		1
82 #define ENTRY_CONTINUATION	2
83 #define ENTRY_STATUS		3
84 #define ENTRY_MARKER		4
85 #define ENTRY_EXTENDED_COMMAND	5
86 
87 /* entry header flag definitions */
88 #define EFLAG_CONTINUATION	1
89 #define EFLAG_BUSY		2
90 #define EFLAG_BAD_HEADER	4
91 #define EFLAG_BAD_PAYLOAD	8
92 
93 struct dataseg {
94 	u32	d_base;
95 	u32	d_count;
96 };
97 
98 struct Command_Entry {
99 	struct Entry_header	hdr;
100 	u32			handle;
101 #ifdef __BIG_ENDIAN
102 	u8			target_id;
103 	u8			target_lun;
104 #else /* __LITTLE_ENDIAN */
105 	u8			target_lun;
106 	u8			target_id;
107 #endif
108 	u16			cdb_length;
109 	u16			control_flags;
110 	u16			rsvd;
111 	u16			time_out;
112 	u16			segment_cnt;
113 	u8			cdb[12];
114 	struct dataseg		dataseg[4];
115 };
116 
117 /* command entry control flag definitions */
118 #define CFLAG_NODISC		0x01
119 #define CFLAG_HEAD_TAG		0x02
120 #define CFLAG_ORDERED_TAG	0x04
121 #define CFLAG_SIMPLE_TAG	0x08
122 #define CFLAG_TAR_RTN		0x10
123 #define CFLAG_READ		0x20
124 #define CFLAG_WRITE		0x40
125 
126 struct Ext_Command_Entry {
127 	struct Entry_header	hdr;
128 	u32			handle;
129 #ifdef __BIG_ENDIAN
130 	u8			target_id;
131 	u8			target_lun;
132 #else /* __LITTLE_ENDIAN */
133 	u8			target_lun;
134 	u8			target_id;
135 #endif
136 	u16			cdb_length;
137 	u16			control_flags;
138 	u16			rsvd;
139 	u16			time_out;
140 	u16			segment_cnt;
141 	u8			cdb[44];
142 };
143 
144 struct Continuation_Entry {
145 	struct Entry_header	hdr;
146 	u32			reserved;
147 	struct dataseg		dataseg[7];
148 };
149 
150 struct Marker_Entry {
151 	struct Entry_header	hdr;
152 	u32			reserved;
153 #ifdef __BIG_ENDIAN
154 	u8			target_id;
155 	u8			target_lun;
156 #else /* __LITTLE_ENDIAN */
157 	u8			target_lun;
158 	u8			target_id;
159 #endif
160 #ifdef __BIG_ENDIAN
161 	u8			rsvd;
162 	u8			modifier;
163 #else /* __LITTLE_ENDIAN */
164 	u8			modifier;
165 	u8			rsvd;
166 #endif
167 	u8			rsvds[52];
168 };
169 
170 /* marker entry modifier definitions */
171 #define SYNC_DEVICE	0
172 #define SYNC_TARGET	1
173 #define SYNC_ALL	2
174 
175 struct Status_Entry {
176 	struct Entry_header	hdr;
177 	u32			handle;
178 	u16			scsi_status;
179 	u16			completion_status;
180 	u16			state_flags;
181 	u16			status_flags;
182 	u16			time;
183 	u16			req_sense_len;
184 	u32			residual;
185 	u8			rsvd[8];
186 	u8			req_sense_data[32];
187 };
188 
189 /* status entry completion status definitions */
190 #define CS_COMPLETE			0x0000
191 #define CS_INCOMPLETE			0x0001
192 #define CS_DMA_ERROR			0x0002
193 #define CS_TRANSPORT_ERROR		0x0003
194 #define CS_RESET_OCCURRED		0x0004
195 #define CS_ABORTED			0x0005
196 #define CS_TIMEOUT			0x0006
197 #define CS_DATA_OVERRUN			0x0007
198 #define CS_COMMAND_OVERRUN		0x0008
199 #define CS_STATUS_OVERRUN		0x0009
200 #define CS_BAD_MESSAGE			0x000a
201 #define CS_NO_MESSAGE_OUT		0x000b
202 #define CS_EXT_ID_FAILED		0x000c
203 #define CS_IDE_MSG_FAILED		0x000d
204 #define CS_ABORT_MSG_FAILED		0x000e
205 #define CS_REJECT_MSG_FAILED		0x000f
206 #define CS_NOP_MSG_FAILED		0x0010
207 #define CS_PARITY_ERROR_MSG_FAILED	0x0011
208 #define CS_DEVICE_RESET_MSG_FAILED	0x0012
209 #define CS_ID_MSG_FAILED		0x0013
210 #define CS_UNEXP_BUS_FREE		0x0014
211 #define CS_DATA_UNDERRUN		0x0015
212 #define CS_BUS_RESET			0x001c
213 
214 /* status entry state flag definitions */
215 #define SF_GOT_BUS			0x0100
216 #define SF_GOT_TARGET			0x0200
217 #define SF_SENT_CDB			0x0400
218 #define SF_TRANSFERRED_DATA		0x0800
219 #define SF_GOT_STATUS			0x1000
220 #define SF_GOT_SENSE			0x2000
221 
222 /* status entry status flag definitions */
223 #define STF_DISCONNECT			0x0001
224 #define STF_SYNCHRONOUS			0x0002
225 #define STF_PARITY_ERROR		0x0004
226 #define STF_BUS_RESET			0x0008
227 #define STF_DEVICE_RESET		0x0010
228 #define STF_ABORTED			0x0020
229 #define STF_TIMEOUT			0x0040
230 #define STF_NEGOTIATION			0x0080
231 
232 /* mailbox commands */
233 #define MBOX_NO_OP			0x0000
234 #define MBOX_LOAD_RAM			0x0001
235 #define MBOX_EXEC_FIRMWARE		0x0002
236 #define MBOX_DUMP_RAM			0x0003
237 #define MBOX_WRITE_RAM_WORD		0x0004
238 #define MBOX_READ_RAM_WORD		0x0005
239 #define MBOX_MAILBOX_REG_TEST		0x0006
240 #define MBOX_VERIFY_CHECKSUM		0x0007
241 #define MBOX_ABOUT_FIRMWARE		0x0008
242 #define MBOX_CHECK_FIRMWARE		0x000e
243 #define MBOX_INIT_REQ_QUEUE		0x0010
244 #define MBOX_INIT_RES_QUEUE		0x0011
245 #define MBOX_EXECUTE_IOCB		0x0012
246 #define MBOX_WAKE_UP			0x0013
247 #define MBOX_STOP_FIRMWARE		0x0014
248 #define MBOX_ABORT			0x0015
249 #define MBOX_ABORT_DEVICE		0x0016
250 #define MBOX_ABORT_TARGET		0x0017
251 #define MBOX_BUS_RESET			0x0018
252 #define MBOX_STOP_QUEUE			0x0019
253 #define MBOX_START_QUEUE		0x001a
254 #define MBOX_SINGLE_STEP_QUEUE		0x001b
255 #define MBOX_ABORT_QUEUE		0x001c
256 #define MBOX_GET_DEV_QUEUE_STATUS	0x001d
257 #define MBOX_GET_FIRMWARE_STATUS	0x001f
258 #define MBOX_GET_INIT_SCSI_ID		0x0020
259 #define MBOX_GET_SELECT_TIMEOUT		0x0021
260 #define MBOX_GET_RETRY_COUNT		0x0022
261 #define MBOX_GET_TAG_AGE_LIMIT		0x0023
262 #define MBOX_GET_CLOCK_RATE		0x0024
263 #define MBOX_GET_ACT_NEG_STATE		0x0025
264 #define MBOX_GET_ASYNC_DATA_SETUP_TIME	0x0026
265 #define MBOX_GET_SBUS_PARAMS		0x0027
266 #define MBOX_GET_TARGET_PARAMS		0x0028
267 #define MBOX_GET_DEV_QUEUE_PARAMS	0x0029
268 #define MBOX_SET_INIT_SCSI_ID		0x0030
269 #define MBOX_SET_SELECT_TIMEOUT		0x0031
270 #define MBOX_SET_RETRY_COUNT		0x0032
271 #define MBOX_SET_TAG_AGE_LIMIT		0x0033
272 #define MBOX_SET_CLOCK_RATE		0x0034
273 #define MBOX_SET_ACTIVE_NEG_STATE	0x0035
274 #define MBOX_SET_ASYNC_DATA_SETUP_TIME	0x0036
275 #define MBOX_SET_SBUS_CONTROL_PARAMS	0x0037
276 #define MBOX_SET_TARGET_PARAMS		0x0038
277 #define MBOX_SET_DEV_QUEUE_PARAMS	0x0039
278 
279 struct host_param {
280 	u_short		initiator_scsi_id;
281 	u_short		bus_reset_delay;
282 	u_short		retry_count;
283 	u_short		retry_delay;
284 	u_short		async_data_setup_time;
285 	u_short		req_ack_active_negation;
286 	u_short		data_line_active_negation;
287 	u_short		data_dma_burst_enable;
288 	u_short		command_dma_burst_enable;
289 	u_short		tag_aging;
290 	u_short		selection_timeout;
291 	u_short		max_queue_depth;
292 };
293 
294 /*
295  * Device Flags:
296  *
297  * Bit  Name
298  * ---------
299  *  7   Disconnect Privilege
300  *  6   Parity Checking
301  *  5   Wide Data Transfers
302  *  4   Synchronous Data Transfers
303  *  3   Tagged Queuing
304  *  2   Automatic Request Sense
305  *  1   Stop Queue on Check Condition
306  *  0   Renegotiate on Error
307  */
308 
309 struct dev_param {
310 	u_short		device_flags;
311 	u_short		execution_throttle;
312 	u_short		synchronous_period;
313 	u_short		synchronous_offset;
314 	u_short		device_enable;
315 	u_short		reserved; /* pad */
316 };
317 
318 /*
319  * The result queue can be quite a bit smaller since continuation entries
320  * do not show up there:
321  */
322 #define RES_QUEUE_LEN		255	/* Must be power of two - 1 */
323 #define QUEUE_ENTRY_LEN		64
324 
325 #define NEXT_REQ_PTR(wheee)   (((wheee) + 1) & QLOGICPTI_REQ_QUEUE_LEN)
326 #define NEXT_RES_PTR(wheee)   (((wheee) + 1) & RES_QUEUE_LEN)
327 #define PREV_REQ_PTR(wheee)   (((wheee) - 1) & QLOGICPTI_REQ_QUEUE_LEN)
328 #define PREV_RES_PTR(wheee)   (((wheee) - 1) & RES_QUEUE_LEN)
329 
330 struct pti_queue_entry {
331 	char __opaque[QUEUE_ENTRY_LEN];
332 };
333 
334 struct scsi_cmnd;
335 
336 /* Software state for the driver. */
337 struct qlogicpti {
338 	/* These are the hot elements in the cache, so they come first. */
339 	void __iomem             *qregs;                /* Adapter registers          */
340 	struct pti_queue_entry   *res_cpu;              /* Ptr to RESPONSE bufs (CPU) */
341 	struct pti_queue_entry   *req_cpu;              /* Ptr to REQUEST bufs (CPU)  */
342 
343 	u_int	                  req_in_ptr;		/* index of next request slot */
344 	u_int	                  res_out_ptr;		/* index of next result slot  */
345 	long	                  send_marker;		/* must we send a marker?     */
346 	struct platform_device	 *op;
347 	unsigned long		  __pad;
348 
349 	int                       cmd_count[MAX_TARGETS];
350 	unsigned long             tag_ages[MAX_TARGETS];
351 
352 	/* The cmd->handler is only 32-bits, so that things work even on monster
353 	 * Ex000 sparc64 machines with >4GB of ram we just keep track of the
354 	 * scsi command pointers here.  This is essentially what Matt Jacob does. -DaveM
355 	 */
356 	struct scsi_cmnd         *cmd_slots[QLOGICPTI_REQ_QUEUE_LEN + 1];
357 
358 	/* The rest of the elements are unimportant for performance. */
359 	struct qlogicpti         *next;
360 	dma_addr_t                res_dvma;             /* Ptr to RESPONSE bufs (DVMA)*/
361 	dma_addr_t                req_dvma;             /* Ptr to REQUEST bufs (DVMA) */
362 	u_char	                  fware_majrev, fware_minrev, fware_micrev;
363 	struct Scsi_Host         *qhost;
364 	int                       qpti_id;
365 	int                       scsi_id;
366 	int                       prom_node;
367 	int                       irq;
368 	char                      differential, ultra, clock;
369 	unsigned char             bursts;
370 	struct	host_param        host_param;
371 	struct	dev_param         dev_param[MAX_TARGETS];
372 
373 	void __iomem              *sreg;
374 #define SREG_TPOWER               0x80   /* State of termpwr           */
375 #define SREG_FUSE                 0x40   /* State of on board fuse     */
376 #define SREG_PDISAB               0x20   /* Disable state for power on */
377 #define SREG_DSENSE               0x10   /* Sense for differential     */
378 #define SREG_IMASK                0x0c   /* Interrupt level            */
379 #define SREG_SPMASK               0x03   /* Mask for switch pack       */
380 	unsigned char             swsreg;
381 	unsigned int
382 		gotirq	:	1,	/* this instance got an irq */
383 		is_pti	: 	1;	/* Non-zero if this is a PTI board. */
384 };
385 
386 /* How to twiddle them bits... */
387 
388 /* SBUS config register one. */
389 #define SBUS_CFG1_EPAR          0x0100      /* Enable parity checking           */
390 #define SBUS_CFG1_FMASK         0x00f0      /* Forth code cycle mask            */
391 #define SBUS_CFG1_BENAB         0x0004      /* Burst dvma enable                */
392 #define SBUS_CFG1_B64           0x0003      /* Enable 64byte bursts             */
393 #define SBUS_CFG1_B32           0x0002      /* Enable 32byte bursts             */
394 #define SBUS_CFG1_B16           0x0001      /* Enable 16byte bursts             */
395 #define SBUS_CFG1_B8            0x0008      /* Enable 8byte bursts              */
396 
397 /* SBUS control register */
398 #define SBUS_CTRL_EDIRQ         0x0020      /* Enable Data DVMA Interrupts      */
399 #define SBUS_CTRL_ECIRQ         0x0010      /* Enable Command DVMA Interrupts   */
400 #define SBUS_CTRL_ESIRQ         0x0008      /* Enable SCSI Processor Interrupts */
401 #define SBUS_CTRL_ERIRQ         0x0004      /* Enable RISC Processor Interrupts */
402 #define SBUS_CTRL_GENAB         0x0002      /* Global Interrupt Enable          */
403 #define SBUS_CTRL_RESET         0x0001      /* Soft Reset                       */
404 
405 /* SBUS status register */
406 #define SBUS_STAT_DINT          0x0020      /* Data DVMA IRQ pending            */
407 #define SBUS_STAT_CINT          0x0010      /* Command DVMA IRQ pending         */
408 #define SBUS_STAT_SINT          0x0008      /* SCSI Processor IRQ pending       */
409 #define SBUS_STAT_RINT          0x0004      /* RISC Processor IRQ pending       */
410 #define SBUS_STAT_GINT          0x0002      /* Global IRQ pending               */
411 
412 /* SBUS semaphore register */
413 #define SBUS_SEMAPHORE_STAT     0x0002      /* Semaphore status bit             */
414 #define SBUS_SEMAPHORE_LCK      0x0001      /* Semaphore lock bit               */
415 
416 /* DVMA control register */
417 #define DMA_CTRL_CSUSPEND       0x0010      /* DMA channel suspend              */
418 #define DMA_CTRL_CCLEAR         0x0008      /* DMA channel clear and reset      */
419 #define DMA_CTRL_FCLEAR         0x0004      /* DMA fifo clear                   */
420 #define DMA_CTRL_CIRQ           0x0002      /* DMA irq clear                    */
421 #define DMA_CTRL_DMASTART       0x0001      /* DMA transfer start               */
422 
423 /* SCSI processor override register */
424 #define CPU_ORIDE_ETRIG         0x8000      /* External trigger enable          */
425 #define CPU_ORIDE_STEP          0x4000      /* Single step mode enable          */
426 #define CPU_ORIDE_BKPT          0x2000      /* Breakpoint reg enable            */
427 #define CPU_ORIDE_PWRITE        0x1000      /* SCSI pin write enable            */
428 #define CPU_ORIDE_OFORCE        0x0800      /* Force outputs on                 */
429 #define CPU_ORIDE_LBACK         0x0400      /* SCSI loopback enable             */
430 #define CPU_ORIDE_PTEST         0x0200      /* Parity test enable               */
431 #define CPU_ORIDE_TENAB         0x0100      /* SCSI pins tristate enable        */
432 #define CPU_ORIDE_TPINS         0x0080      /* SCSI pins enable                 */
433 #define CPU_ORIDE_FRESET        0x0008      /* FIFO reset                       */
434 #define CPU_ORIDE_CTERM         0x0004      /* Command terminate                */
435 #define CPU_ORIDE_RREG          0x0002      /* Reset SCSI processor regs        */
436 #define CPU_ORIDE_RMOD          0x0001      /* Reset SCSI processor module      */
437 
438 /* SCSI processor commands */
439 #define CPU_CMD_BRESET          0x300b      /* Reset SCSI bus                   */
440 
441 /* SCSI processor pin control register */
442 #define CPU_PCTRL_PVALID        0x8000      /* Phase bits are valid             */
443 #define CPU_PCTRL_PHI           0x0400      /* Parity bit high                  */
444 #define CPU_PCTRL_PLO           0x0200      /* Parity bit low                   */
445 #define CPU_PCTRL_REQ           0x0100      /* REQ bus signal                   */
446 #define CPU_PCTRL_ACK           0x0080      /* ACK bus signal                   */
447 #define CPU_PCTRL_RST           0x0040      /* RST bus signal                   */
448 #define CPU_PCTRL_BSY           0x0020      /* BSY bus signal                   */
449 #define CPU_PCTRL_SEL           0x0010      /* SEL bus signal                   */
450 #define CPU_PCTRL_ATN           0x0008      /* ATN bus signal                   */
451 #define CPU_PCTRL_MSG           0x0004      /* MSG bus signal                   */
452 #define CPU_PCTRL_CD            0x0002      /* CD bus signal                    */
453 #define CPU_PCTRL_IO            0x0001      /* IO bus signal                    */
454 
455 /* SCSI processor differential pins register */
456 #define CPU_PDIFF_SENSE         0x0200      /* Differential sense               */
457 #define CPU_PDIFF_MODE          0x0100      /* Differential mode                */
458 #define CPU_PDIFF_OENAB         0x0080      /* Outputs enable                   */
459 #define CPU_PDIFF_PMASK         0x007c      /* Differential control pins        */
460 #define CPU_PDIFF_TGT           0x0002      /* Target mode enable               */
461 #define CPU_PDIFF_INIT          0x0001      /* Initiator mode enable            */
462 
463 /* RISC processor status register */
464 #define RISC_PSR_FTRUE          0x8000      /* Force true                       */
465 #define RISC_PSR_LCD            0x4000      /* Loop counter shows done status   */
466 #define RISC_PSR_RIRQ           0x2000      /* RISC irq status                  */
467 #define RISC_PSR_TOFLOW         0x1000      /* Timer overflow (rollover)        */
468 #define RISC_PSR_AOFLOW         0x0800      /* Arithmetic overflow              */
469 #define RISC_PSR_AMSB           0x0400      /* Arithmetic big endian            */
470 #define RISC_PSR_ACARRY         0x0200      /* Arithmetic carry                 */
471 #define RISC_PSR_AZERO          0x0100      /* Arithmetic zero                  */
472 #define RISC_PSR_ULTRA          0x0020      /* Ultra mode                       */
473 #define RISC_PSR_DIRQ           0x0010      /* DVMA interrupt                   */
474 #define RISC_PSR_SIRQ           0x0008      /* SCSI processor interrupt         */
475 #define RISC_PSR_HIRQ           0x0004      /* Host interrupt                   */
476 #define RISC_PSR_IPEND          0x0002      /* Interrupt pending                */
477 #define RISC_PSR_FFALSE         0x0001      /* Force false                      */
478 
479 /* RISC processor memory timing register */
480 #define RISC_MTREG_P1DFLT       0x1200      /* Default read/write timing, pg1   */
481 #define RISC_MTREG_P0DFLT       0x0012      /* Default read/write timing, pg0   */
482 #define RISC_MTREG_P1ULTRA      0x2300      /* Ultra-mode rw timing, pg1        */
483 #define RISC_MTREG_P0ULTRA      0x0023      /* Ultra-mode rw timing, pg0        */
484 
485 /* Host command/ctrl register */
486 #define HCCTRL_NOP              0x0000      /* CMD: No operation                */
487 #define HCCTRL_RESET            0x1000      /* CMD: Reset RISC cpu              */
488 #define HCCTRL_PAUSE            0x2000      /* CMD: Pause RISC cpu              */
489 #define HCCTRL_REL              0x3000      /* CMD: Release paused RISC cpu     */
490 #define HCCTRL_STEP             0x4000      /* CMD: Single step RISC cpu        */
491 #define HCCTRL_SHIRQ            0x5000      /* CMD: Set host irq                */
492 #define HCCTRL_CHIRQ            0x6000      /* CMD: Clear host irq              */
493 #define HCCTRL_CRIRQ            0x7000      /* CMD: Clear RISC cpu irq          */
494 #define HCCTRL_BKPT             0x8000      /* CMD: Breakpoint enables change   */
495 #define HCCTRL_TMODE            0xf000      /* CMD: Enable test mode            */
496 #define HCCTRL_HIRQ             0x0080      /* Host IRQ pending                 */
497 #define HCCTRL_RRIP             0x0040      /* RISC cpu reset in happening now  */
498 #define HCCTRL_RPAUSED          0x0020      /* RISC cpu is paused now           */
499 #define HCCTRL_EBENAB           0x0010      /* External breakpoint enable       */
500 #define HCCTRL_B1ENAB           0x0008      /* Breakpoint 1 enable              */
501 #define HCCTRL_B0ENAB           0x0004      /* Breakpoint 0 enable              */
502 
503 /* For our interrupt engine. */
504 #define for_each_qlogicpti(qp) \
505         for((qp) = qptichain; (qp); (qp) = (qp)->next)
506 
507 #endif /* !(_QLOGICPTI_H) */
508