1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Cadence UART driver (found in Xilinx Zynq)
4 *
5 * Copyright (c) 2011 - 2014 Xilinx, Inc.
6 *
7 * This driver has originally been pushed by Xilinx using a Zynq-branding. This
8 * still shows in the naming of this file, the kconfig symbols and some symbols
9 * in the code.
10 */
11
12 #include <linux/platform_device.h>
13 #include <linux/serial.h>
14 #include <linux/console.h>
15 #include <linux/serial_core.h>
16 #include <linux/slab.h>
17 #include <linux/tty.h>
18 #include <linux/tty_flip.h>
19 #include <linux/clk.h>
20 #include <linux/irq.h>
21 #include <linux/io.h>
22 #include <linux/of.h>
23 #include <linux/module.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/gpio.h>
26 #include <linux/gpio/consumer.h>
27 #include <linux/delay.h>
28 #include <linux/reset.h>
29
30 #define CDNS_UART_TTY_NAME "ttyPS"
31 #define CDNS_UART_NAME "xuartps"
32 #define CDNS_UART_MAJOR 0 /* use dynamic node allocation */
33 #define CDNS_UART_MINOR 0 /* works best with devtmpfs */
34 #define CDNS_UART_NR_PORTS 16
35 #define CDNS_UART_FIFO_SIZE 64 /* FIFO size */
36 #define TX_TIMEOUT 500000
37
38 /* Rx Trigger level */
39 static int rx_trigger_level = 56;
40 module_param(rx_trigger_level, uint, 0444);
41 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
42
43 /* Rx Timeout */
44 static int rx_timeout = 10;
45 module_param(rx_timeout, uint, 0444);
46 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
47
48 /* Register offsets for the UART. */
49 #define CDNS_UART_CR 0x00 /* Control Register */
50 #define CDNS_UART_MR 0x04 /* Mode Register */
51 #define CDNS_UART_IER 0x08 /* Interrupt Enable */
52 #define CDNS_UART_IDR 0x0C /* Interrupt Disable */
53 #define CDNS_UART_IMR 0x10 /* Interrupt Mask */
54 #define CDNS_UART_ISR 0x14 /* Interrupt Status */
55 #define CDNS_UART_BAUDGEN 0x18 /* Baud Rate Generator */
56 #define CDNS_UART_RXTOUT 0x1C /* RX Timeout */
57 #define CDNS_UART_RXWM 0x20 /* RX FIFO Trigger Level */
58 #define CDNS_UART_MODEMCR 0x24 /* Modem Control */
59 #define CDNS_UART_MODEMSR 0x28 /* Modem Status */
60 #define CDNS_UART_SR 0x2C /* Channel Status */
61 #define CDNS_UART_FIFO 0x30 /* FIFO */
62 #define CDNS_UART_BAUDDIV 0x34 /* Baud Rate Divider */
63 #define CDNS_UART_FLOWDEL 0x38 /* Flow Delay */
64 #define CDNS_UART_IRRX_PWIDTH 0x3C /* IR Min Received Pulse Width */
65 #define CDNS_UART_IRTX_PWIDTH 0x40 /* IR Transmitted pulse Width */
66 #define CDNS_UART_TXWM 0x44 /* TX FIFO Trigger Level */
67 #define CDNS_UART_RXBS 0x48 /* RX FIFO byte status register */
68
69 /* Control Register Bit Definitions */
70 #define CDNS_UART_CR_STOPBRK 0x00000100 /* Stop TX break */
71 #define CDNS_UART_CR_STARTBRK 0x00000080 /* Set TX break */
72 #define CDNS_UART_CR_TX_DIS 0x00000020 /* TX disabled. */
73 #define CDNS_UART_CR_TX_EN 0x00000010 /* TX enabled */
74 #define CDNS_UART_CR_RX_DIS 0x00000008 /* RX disabled. */
75 #define CDNS_UART_CR_RX_EN 0x00000004 /* RX enabled */
76 #define CDNS_UART_CR_TXRST 0x00000002 /* TX logic reset */
77 #define CDNS_UART_CR_RXRST 0x00000001 /* RX logic reset */
78 #define CDNS_UART_CR_RST_TO 0x00000040 /* Restart Timeout Counter */
79 #define CDNS_UART_RXBS_PARITY 0x00000001 /* Parity error status */
80 #define CDNS_UART_RXBS_FRAMING 0x00000002 /* Framing error status */
81 #define CDNS_UART_RXBS_BRK 0x00000004 /* Overrun error status */
82
83 /*
84 * Mode Register:
85 * The mode register (MR) defines the mode of transfer as well as the data
86 * format. If this register is modified during transmission or reception,
87 * data validity cannot be guaranteed.
88 */
89 #define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
90 #define CDNS_UART_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */
91 #define CDNS_UART_MR_CHMODE_NORM 0x00000000 /* Normal mode */
92 #define CDNS_UART_MR_CHMODE_MASK 0x00000300 /* Mask for mode bits */
93
94 #define CDNS_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */
95 #define CDNS_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
96
97 #define CDNS_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
98 #define CDNS_UART_MR_PARITY_MARK 0x00000018 /* Mark parity mode */
99 #define CDNS_UART_MR_PARITY_SPACE 0x00000010 /* Space parity mode */
100 #define CDNS_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */
101 #define CDNS_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */
102
103 #define CDNS_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */
104 #define CDNS_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */
105 #define CDNS_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */
106
107 /*
108 * Interrupt Registers:
109 * Interrupt control logic uses the interrupt enable register (IER) and the
110 * interrupt disable register (IDR) to set the value of the bits in the
111 * interrupt mask register (IMR). The IMR determines whether to pass an
112 * interrupt to the interrupt status register (ISR).
113 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
114 * interrupt. IMR and ISR are read only, and IER and IDR are write only.
115 * Reading either IER or IDR returns 0x00.
116 * All four registers have the same bit definitions.
117 */
118 #define CDNS_UART_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */
119 #define CDNS_UART_IXR_PARITY 0x00000080 /* Parity error interrupt */
120 #define CDNS_UART_IXR_FRAMING 0x00000040 /* Framing error interrupt */
121 #define CDNS_UART_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */
122 #define CDNS_UART_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */
123 #define CDNS_UART_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */
124 #define CDNS_UART_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */
125 #define CDNS_UART_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */
126 #define CDNS_UART_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */
127 #define CDNS_UART_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */
128 #define CDNS_UART_IXR_RXMASK 0x000021e7 /* Valid RX bit mask */
129
130 /*
131 * Do not enable parity error interrupt for the following
132 * reason: When parity error interrupt is enabled, each Rx
133 * parity error always results in 2 events. The first one
134 * being parity error interrupt and the second one with a
135 * proper Rx interrupt with the incoming data. Disabling
136 * parity error interrupt ensures better handling of parity
137 * error events. With this change, for a parity error case, we
138 * get a Rx interrupt with parity error set in ISR register
139 * and we still handle parity errors in the desired way.
140 */
141
142 #define CDNS_UART_RX_IRQS (CDNS_UART_IXR_FRAMING | \
143 CDNS_UART_IXR_OVERRUN | \
144 CDNS_UART_IXR_RXTRIG | \
145 CDNS_UART_IXR_TOUT)
146
147 /* Goes in read_status_mask for break detection as the HW doesn't do it*/
148 #define CDNS_UART_IXR_BRK 0x00002000
149
150 #define CDNS_UART_RXBS_SUPPORT BIT(1)
151 /*
152 * Modem Control register:
153 * The read/write Modem Control register controls the interface with the modem
154 * or data set, or a peripheral device emulating a modem.
155 */
156 #define CDNS_UART_MODEMCR_FCM 0x00000020 /* Automatic flow control mode */
157 #define CDNS_UART_MODEMCR_RTS 0x00000002 /* Request to send output control */
158 #define CDNS_UART_MODEMCR_DTR 0x00000001 /* Data Terminal Ready */
159
160 /*
161 * Modem Status register:
162 * The read/write Modem Status register reports the interface with the modem
163 * or data set, or a peripheral device emulating a modem.
164 */
165 #define CDNS_UART_MODEMSR_DCD BIT(7) /* Data Carrier Detect */
166 #define CDNS_UART_MODEMSR_RI BIT(6) /* Ting Indicator */
167 #define CDNS_UART_MODEMSR_DSR BIT(5) /* Data Set Ready */
168 #define CDNS_UART_MODEMSR_CTS BIT(4) /* Clear To Send */
169
170 /*
171 * Channel Status Register:
172 * The channel status register (CSR) is provided to enable the control logic
173 * to monitor the status of bits in the channel interrupt status register,
174 * even if these are masked out by the interrupt mask register.
175 */
176 #define CDNS_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
177 #define CDNS_UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
178 #define CDNS_UART_SR_TXFULL 0x00000010 /* TX FIFO full */
179 #define CDNS_UART_SR_RXTRIG 0x00000001 /* Rx Trigger */
180 #define CDNS_UART_SR_TACTIVE 0x00000800 /* TX state machine active */
181
182 /* baud dividers min/max values */
183 #define CDNS_UART_BDIV_MIN 4
184 #define CDNS_UART_BDIV_MAX 255
185 #define CDNS_UART_CD_MAX 65535
186 #define UART_AUTOSUSPEND_TIMEOUT 3000
187
188 /**
189 * struct cdns_uart - device data
190 * @port: Pointer to the UART port
191 * @uartclk: Reference clock
192 * @pclk: APB clock
193 * @cdns_uart_driver: Pointer to UART driver
194 * @baud: Current baud rate
195 * @clk_rate_change_nb: Notifier block for clock changes
196 * @quirks: Flags for RXBS support.
197 * @cts_override: Modem control state override
198 * @gpiod_rts: Pointer to the gpio descriptor
199 * @rs485_tx_started: RS485 tx state
200 * @tx_timer: Timer for tx
201 * @rstc: Pointer to the reset control
202 */
203 struct cdns_uart {
204 struct uart_port *port;
205 struct clk *uartclk;
206 struct clk *pclk;
207 struct uart_driver *cdns_uart_driver;
208 unsigned int baud;
209 struct notifier_block clk_rate_change_nb;
210 u32 quirks;
211 bool cts_override;
212 struct gpio_desc *gpiod_rts;
213 bool rs485_tx_started;
214 struct hrtimer tx_timer;
215 struct reset_control *rstc;
216 };
217 struct cdns_platform_data {
218 u32 quirks;
219 };
220
221 static struct serial_rs485 cdns_rs485_supported = {
222 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND |
223 SER_RS485_RTS_AFTER_SEND,
224 .delay_rts_before_send = 1,
225 .delay_rts_after_send = 1,
226 };
227
228 #define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \
229 clk_rate_change_nb)
230
231 /**
232 * cdns_uart_handle_rx - Handle the received bytes along with Rx errors.
233 * @dev_id: Id of the UART port
234 * @isrstatus: The interrupt status register value as read
235 * Return: None
236 */
cdns_uart_handle_rx(void * dev_id,unsigned int isrstatus)237 static void cdns_uart_handle_rx(void *dev_id, unsigned int isrstatus)
238 {
239 struct uart_port *port = (struct uart_port *)dev_id;
240 struct cdns_uart *cdns_uart = port->private_data;
241 unsigned int data;
242 unsigned int rxbs_status = 0;
243 unsigned int status_mask;
244 unsigned int framerrprocessed = 0;
245 char status = TTY_NORMAL;
246 bool is_rxbs_support;
247
248 is_rxbs_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
249
250 while ((readl(port->membase + CDNS_UART_SR) &
251 CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) {
252 if (is_rxbs_support)
253 rxbs_status = readl(port->membase + CDNS_UART_RXBS);
254 data = readl(port->membase + CDNS_UART_FIFO);
255 port->icount.rx++;
256 /*
257 * There is no hardware break detection in Zynq, so we interpret
258 * framing error with all-zeros data as a break sequence.
259 * Most of the time, there's another non-zero byte at the
260 * end of the sequence.
261 */
262 if (!is_rxbs_support && (isrstatus & CDNS_UART_IXR_FRAMING)) {
263 if (!data) {
264 port->read_status_mask |= CDNS_UART_IXR_BRK;
265 framerrprocessed = 1;
266 continue;
267 }
268 }
269 if (is_rxbs_support && (rxbs_status & CDNS_UART_RXBS_BRK)) {
270 port->icount.brk++;
271 status = TTY_BREAK;
272 if (uart_handle_break(port))
273 continue;
274 }
275
276 isrstatus &= port->read_status_mask;
277 isrstatus &= ~port->ignore_status_mask;
278 status_mask = port->read_status_mask;
279 status_mask &= ~port->ignore_status_mask;
280
281 if (data &&
282 (port->read_status_mask & CDNS_UART_IXR_BRK)) {
283 port->read_status_mask &= ~CDNS_UART_IXR_BRK;
284 port->icount.brk++;
285 if (uart_handle_break(port))
286 continue;
287 }
288
289 if (uart_prepare_sysrq_char(port, data))
290 continue;
291
292 if (is_rxbs_support) {
293 if ((rxbs_status & CDNS_UART_RXBS_PARITY)
294 && (status_mask & CDNS_UART_IXR_PARITY)) {
295 port->icount.parity++;
296 status = TTY_PARITY;
297 }
298 if ((rxbs_status & CDNS_UART_RXBS_FRAMING)
299 && (status_mask & CDNS_UART_IXR_PARITY)) {
300 port->icount.frame++;
301 status = TTY_FRAME;
302 }
303 } else {
304 if (isrstatus & CDNS_UART_IXR_PARITY) {
305 port->icount.parity++;
306 status = TTY_PARITY;
307 }
308 if ((isrstatus & CDNS_UART_IXR_FRAMING) &&
309 !framerrprocessed) {
310 port->icount.frame++;
311 status = TTY_FRAME;
312 }
313 }
314 if (isrstatus & CDNS_UART_IXR_OVERRUN) {
315 port->icount.overrun++;
316 tty_insert_flip_char(&port->state->port, 0,
317 TTY_OVERRUN);
318 }
319 tty_insert_flip_char(&port->state->port, data, status);
320 isrstatus = 0;
321 }
322
323 tty_flip_buffer_push(&port->state->port);
324 }
325
326 /**
327 * cdns_rts_gpio_enable - Configure RTS/GPIO to high/low
328 * @cdns_uart: Handle to the cdns_uart
329 * @enable: Value to be set to RTS/GPIO
330 */
cdns_rts_gpio_enable(struct cdns_uart * cdns_uart,bool enable)331 static void cdns_rts_gpio_enable(struct cdns_uart *cdns_uart, bool enable)
332 {
333 u32 val;
334
335 if (cdns_uart->gpiod_rts) {
336 gpiod_set_value(cdns_uart->gpiod_rts, enable);
337 } else {
338 val = readl(cdns_uart->port->membase + CDNS_UART_MODEMCR);
339 if (enable)
340 val |= CDNS_UART_MODEMCR_RTS;
341 else
342 val &= ~CDNS_UART_MODEMCR_RTS;
343 writel(val, cdns_uart->port->membase + CDNS_UART_MODEMCR);
344 }
345 }
346
347 /**
348 * cdns_rs485_tx_setup - Tx setup specific to rs485
349 * @cdns_uart: Handle to the cdns_uart
350 */
cdns_rs485_tx_setup(struct cdns_uart * cdns_uart)351 static void cdns_rs485_tx_setup(struct cdns_uart *cdns_uart)
352 {
353 bool enable;
354
355 enable = cdns_uart->port->rs485.flags & SER_RS485_RTS_ON_SEND;
356 cdns_rts_gpio_enable(cdns_uart, enable);
357
358 cdns_uart->rs485_tx_started = true;
359 }
360
361 /**
362 * cdns_rs485_rx_setup - Rx setup specific to rs485
363 * @cdns_uart: Handle to the cdns_uart
364 */
cdns_rs485_rx_setup(struct cdns_uart * cdns_uart)365 static void cdns_rs485_rx_setup(struct cdns_uart *cdns_uart)
366 {
367 bool enable;
368
369 enable = cdns_uart->port->rs485.flags & SER_RS485_RTS_AFTER_SEND;
370 cdns_rts_gpio_enable(cdns_uart, enable);
371
372 cdns_uart->rs485_tx_started = false;
373 }
374
375 /**
376 * cdns_uart_tx_empty - Check whether TX is empty
377 * @port: Handle to the uart port structure
378 *
379 * Return: TIOCSER_TEMT on success, 0 otherwise
380 */
cdns_uart_tx_empty(struct uart_port * port)381 static unsigned int cdns_uart_tx_empty(struct uart_port *port)
382 {
383 unsigned int status;
384
385 status = readl(port->membase + CDNS_UART_SR);
386 status &= (CDNS_UART_SR_TXEMPTY | CDNS_UART_SR_TACTIVE);
387 return (status == CDNS_UART_SR_TXEMPTY) ? TIOCSER_TEMT : 0;
388 }
389
390 /**
391 * cdns_rs485_rx_callback - Timer rx callback handler for rs485.
392 * @t: Handle to the hrtimer structure
393 */
cdns_rs485_rx_callback(struct hrtimer * t)394 static enum hrtimer_restart cdns_rs485_rx_callback(struct hrtimer *t)
395 {
396 struct cdns_uart *cdns_uart = container_of(t, struct cdns_uart, tx_timer);
397
398 /*
399 * Default Rx should be setup, because Rx signaling path
400 * need to enable to receive data.
401 */
402 cdns_rs485_rx_setup(cdns_uart);
403
404 return HRTIMER_NORESTART;
405 }
406
407 /**
408 * cdns_calc_after_tx_delay - calculate delay required for after tx.
409 * @cdns_uart: Handle to the cdns_uart
410 */
cdns_calc_after_tx_delay(struct cdns_uart * cdns_uart)411 static u64 cdns_calc_after_tx_delay(struct cdns_uart *cdns_uart)
412 {
413 /*
414 * Frame time + stop bit time + rs485.delay_rts_after_send
415 */
416 return cdns_uart->port->frame_time
417 + DIV_ROUND_UP(cdns_uart->port->frame_time, 7)
418 + (u64)cdns_uart->port->rs485.delay_rts_after_send * NSEC_PER_MSEC;
419 }
420
421 /**
422 * cdns_uart_handle_tx - Handle the bytes to be transmitted.
423 * @dev_id: Id of the UART port
424 * Return: None
425 */
cdns_uart_handle_tx(void * dev_id)426 static void cdns_uart_handle_tx(void *dev_id)
427 {
428 struct uart_port *port = (struct uart_port *)dev_id;
429 struct cdns_uart *cdns_uart = port->private_data;
430 struct tty_port *tport = &port->state->port;
431 unsigned int numbytes;
432 unsigned char ch;
433
434 if (kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(port)) {
435 /* Disable the TX Empty interrupt */
436 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR);
437 return;
438 }
439
440 numbytes = port->fifosize;
441 while (numbytes &&
442 !(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL) &&
443 uart_fifo_get(port, &ch)) {
444 writel(ch, port->membase + CDNS_UART_FIFO);
445 numbytes--;
446 }
447
448 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
449 uart_write_wakeup(port);
450
451 /* Enable the TX Empty interrupt */
452 writel(CDNS_UART_IXR_TXEMPTY, cdns_uart->port->membase + CDNS_UART_IER);
453
454 if (cdns_uart->port->rs485.flags & SER_RS485_ENABLED &&
455 (kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(port))) {
456 hrtimer_update_function(&cdns_uart->tx_timer, cdns_rs485_rx_callback);
457 hrtimer_start(&cdns_uart->tx_timer,
458 ns_to_ktime(cdns_calc_after_tx_delay(cdns_uart)), HRTIMER_MODE_REL);
459 }
460 }
461
462 /**
463 * cdns_uart_isr - Interrupt handler
464 * @irq: Irq number
465 * @dev_id: Id of the port
466 *
467 * Return: IRQHANDLED
468 */
cdns_uart_isr(int irq,void * dev_id)469 static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
470 {
471 struct uart_port *port = (struct uart_port *)dev_id;
472 unsigned int isrstatus;
473
474 uart_port_lock(port);
475
476 /* Read the interrupt status register to determine which
477 * interrupt(s) is/are active and clear them.
478 */
479 isrstatus = readl(port->membase + CDNS_UART_ISR);
480 writel(isrstatus, port->membase + CDNS_UART_ISR);
481
482 if (isrstatus & CDNS_UART_IXR_TXEMPTY) {
483 cdns_uart_handle_tx(dev_id);
484 isrstatus &= ~CDNS_UART_IXR_TXEMPTY;
485 }
486
487 isrstatus &= port->read_status_mask;
488 isrstatus &= ~port->ignore_status_mask;
489 /*
490 * Skip RX processing if RX is disabled as RXEMPTY will never be set
491 * as read bytes will not be removed from the FIFO.
492 */
493 if (isrstatus & CDNS_UART_IXR_RXMASK &&
494 !(readl(port->membase + CDNS_UART_CR) & CDNS_UART_CR_RX_DIS))
495 cdns_uart_handle_rx(dev_id, isrstatus);
496
497 uart_unlock_and_check_sysrq(port);
498 return IRQ_HANDLED;
499 }
500
501 /**
502 * cdns_uart_calc_baud_divs - Calculate baud rate divisors
503 * @clk: UART module input clock
504 * @baud: Desired baud rate
505 * @rbdiv: BDIV value (return value)
506 * @rcd: CD value (return value)
507 * @div8: Value for clk_sel bit in mod (return value)
508 * Return: baud rate, requested baud when possible, or actual baud when there
509 * was too much error, zero if no valid divisors are found.
510 *
511 * Formula to obtain baud rate is
512 * baud_tx/rx rate = clk/CD * (BDIV + 1)
513 * input_clk = (Uart User Defined Clock or Apb Clock)
514 * depends on UCLKEN in MR Reg
515 * clk = input_clk or input_clk/8;
516 * depends on CLKS in MR reg
517 * CD and BDIV depends on values in
518 * baud rate generate register
519 * baud rate clock divisor register
520 */
cdns_uart_calc_baud_divs(unsigned int clk,unsigned int baud,u32 * rbdiv,u32 * rcd,int * div8)521 static unsigned int cdns_uart_calc_baud_divs(unsigned int clk,
522 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8)
523 {
524 u32 cd, bdiv;
525 unsigned int calc_baud;
526 unsigned int bestbaud = 0;
527 unsigned int bauderror;
528 unsigned int besterror = ~0;
529
530 if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) {
531 *div8 = 1;
532 clk /= 8;
533 } else {
534 *div8 = 0;
535 }
536
537 for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) {
538 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1));
539 if (cd < 1 || cd > CDNS_UART_CD_MAX)
540 continue;
541
542 calc_baud = clk / (cd * (bdiv + 1));
543
544 if (baud > calc_baud)
545 bauderror = baud - calc_baud;
546 else
547 bauderror = calc_baud - baud;
548
549 if (besterror > bauderror) {
550 *rbdiv = bdiv;
551 *rcd = cd;
552 bestbaud = calc_baud;
553 besterror = bauderror;
554 }
555 }
556 /* use the values when percent error is acceptable */
557 if (((besterror * 100) / baud) < 3)
558 bestbaud = baud;
559
560 return bestbaud;
561 }
562
563 /**
564 * cdns_uart_set_baud_rate - Calculate and set the baud rate
565 * @port: Handle to the uart port structure
566 * @baud: Baud rate to set
567 * Return: baud rate, requested baud when possible, or actual baud when there
568 * was too much error, zero if no valid divisors are found.
569 */
cdns_uart_set_baud_rate(struct uart_port * port,unsigned int baud)570 static unsigned int cdns_uart_set_baud_rate(struct uart_port *port,
571 unsigned int baud)
572 {
573 unsigned int calc_baud;
574 u32 cd = 0, bdiv = 0;
575 u32 mreg;
576 int div8;
577 struct cdns_uart *cdns_uart = port->private_data;
578
579 calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd,
580 &div8);
581
582 /* Write new divisors to hardware */
583 mreg = readl(port->membase + CDNS_UART_MR);
584 if (div8)
585 mreg |= CDNS_UART_MR_CLKSEL;
586 else
587 mreg &= ~CDNS_UART_MR_CLKSEL;
588 writel(mreg, port->membase + CDNS_UART_MR);
589 writel(cd, port->membase + CDNS_UART_BAUDGEN);
590 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
591 cdns_uart->baud = baud;
592
593 return calc_baud;
594 }
595
596 #ifdef CONFIG_COMMON_CLK
597 /**
598 * cdns_uart_clk_notifier_cb - Clock notifier callback
599 * @nb: Notifier block
600 * @event: Notify event
601 * @data: Notifier data
602 * Return: NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error.
603 */
cdns_uart_clk_notifier_cb(struct notifier_block * nb,unsigned long event,void * data)604 static int cdns_uart_clk_notifier_cb(struct notifier_block *nb,
605 unsigned long event, void *data)
606 {
607 u32 ctrl_reg;
608 struct uart_port *port;
609 int locked = 0;
610 struct clk_notifier_data *ndata = data;
611 struct cdns_uart *cdns_uart = to_cdns_uart(nb);
612 unsigned long flags;
613
614 port = cdns_uart->port;
615 if (port->suspended)
616 return NOTIFY_OK;
617
618 switch (event) {
619 case PRE_RATE_CHANGE:
620 {
621 u32 bdiv, cd;
622 int div8;
623
624 /*
625 * Find out if current baud-rate can be achieved with new clock
626 * frequency.
627 */
628 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud,
629 &bdiv, &cd, &div8)) {
630 dev_warn(port->dev, "clock rate change rejected\n");
631 return NOTIFY_BAD;
632 }
633
634 uart_port_lock_irqsave(cdns_uart->port, &flags);
635
636 /* Disable the TX and RX to set baud rate */
637 ctrl_reg = readl(port->membase + CDNS_UART_CR);
638 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
639 writel(ctrl_reg, port->membase + CDNS_UART_CR);
640
641 uart_port_unlock_irqrestore(cdns_uart->port, flags);
642
643 return NOTIFY_OK;
644 }
645 case POST_RATE_CHANGE:
646 /*
647 * Set clk dividers to generate correct baud with new clock
648 * frequency.
649 */
650
651 uart_port_lock_irqsave(cdns_uart->port, &flags);
652
653 locked = 1;
654 port->uartclk = ndata->new_rate;
655
656 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port,
657 cdns_uart->baud);
658 fallthrough;
659 case ABORT_RATE_CHANGE:
660 if (!locked)
661 uart_port_lock_irqsave(cdns_uart->port, &flags);
662
663 /* Set TX/RX Reset */
664 ctrl_reg = readl(port->membase + CDNS_UART_CR);
665 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
666 writel(ctrl_reg, port->membase + CDNS_UART_CR);
667
668 while (readl(port->membase + CDNS_UART_CR) &
669 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
670 cpu_relax();
671
672 /*
673 * Clear the RX disable and TX disable bits and then set the TX
674 * enable bit and RX enable bit to enable the transmitter and
675 * receiver.
676 */
677 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
678 ctrl_reg = readl(port->membase + CDNS_UART_CR);
679 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
680 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
681 writel(ctrl_reg, port->membase + CDNS_UART_CR);
682
683 uart_port_unlock_irqrestore(cdns_uart->port, flags);
684
685 return NOTIFY_OK;
686 default:
687 return NOTIFY_DONE;
688 }
689 }
690 #endif
691
692 /**
693 * cdns_rs485_tx_callback - Timer tx callback handler for rs485.
694 * @t: Handle to the hrtimer structure
695 */
cdns_rs485_tx_callback(struct hrtimer * t)696 static enum hrtimer_restart cdns_rs485_tx_callback(struct hrtimer *t)
697 {
698 struct cdns_uart *cdns_uart = container_of(t, struct cdns_uart, tx_timer);
699
700 uart_port_lock(cdns_uart->port);
701 cdns_uart_handle_tx(cdns_uart->port);
702 uart_port_unlock(cdns_uart->port);
703
704 return HRTIMER_NORESTART;
705 }
706
707 /**
708 * cdns_uart_start_tx - Start transmitting bytes
709 * @port: Handle to the uart port structure
710 */
cdns_uart_start_tx(struct uart_port * port)711 static void cdns_uart_start_tx(struct uart_port *port)
712 {
713 unsigned int status;
714 struct cdns_uart *cdns_uart = port->private_data;
715
716 if (uart_tx_stopped(port))
717 return;
718
719 /*
720 * Set the TX enable bit and clear the TX disable bit to enable the
721 * transmitter.
722 */
723 status = readl(port->membase + CDNS_UART_CR);
724 status &= ~CDNS_UART_CR_TX_DIS;
725 status |= CDNS_UART_CR_TX_EN;
726 writel(status, port->membase + CDNS_UART_CR);
727
728 if (kfifo_is_empty(&port->state->port.xmit_fifo))
729 return;
730
731 /* Clear the TX Empty interrupt */
732 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR);
733
734 if (cdns_uart->port->rs485.flags & SER_RS485_ENABLED) {
735 if (!cdns_uart->rs485_tx_started) {
736 hrtimer_update_function(&cdns_uart->tx_timer, cdns_rs485_tx_callback);
737 cdns_rs485_tx_setup(cdns_uart);
738 return hrtimer_start(&cdns_uart->tx_timer,
739 ms_to_ktime(port->rs485.delay_rts_before_send),
740 HRTIMER_MODE_REL);
741 }
742 }
743 cdns_uart_handle_tx(port);
744 }
745
746 /**
747 * cdns_uart_stop_tx - Stop TX
748 * @port: Handle to the uart port structure
749 */
cdns_uart_stop_tx(struct uart_port * port)750 static void cdns_uart_stop_tx(struct uart_port *port)
751 {
752 unsigned int regval;
753 struct cdns_uart *cdns_uart = port->private_data;
754
755 if (cdns_uart->port->rs485.flags & SER_RS485_ENABLED)
756 cdns_rs485_rx_setup(cdns_uart);
757
758 regval = readl(port->membase + CDNS_UART_CR);
759 regval |= CDNS_UART_CR_TX_DIS;
760 /* Disable the transmitter */
761 writel(regval, port->membase + CDNS_UART_CR);
762 }
763
764 /**
765 * cdns_uart_stop_rx - Stop RX
766 * @port: Handle to the uart port structure
767 */
cdns_uart_stop_rx(struct uart_port * port)768 static void cdns_uart_stop_rx(struct uart_port *port)
769 {
770 unsigned int regval;
771
772 /* Disable RX IRQs */
773 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR);
774
775 /* Disable the receiver */
776 regval = readl(port->membase + CDNS_UART_CR);
777 regval |= CDNS_UART_CR_RX_DIS;
778 writel(regval, port->membase + CDNS_UART_CR);
779 }
780
781 /**
782 * cdns_uart_break_ctl - Based on the input ctl we have to start or stop
783 * transmitting char breaks
784 * @port: Handle to the uart port structure
785 * @ctl: Value based on which start or stop decision is taken
786 */
cdns_uart_break_ctl(struct uart_port * port,int ctl)787 static void cdns_uart_break_ctl(struct uart_port *port, int ctl)
788 {
789 unsigned int status;
790 unsigned long flags;
791
792 uart_port_lock_irqsave(port, &flags);
793
794 status = readl(port->membase + CDNS_UART_CR);
795
796 if (ctl == -1)
797 writel(CDNS_UART_CR_STARTBRK | (~CDNS_UART_CR_STOPBRK & status),
798 port->membase + CDNS_UART_CR);
799 else {
800 if ((status & CDNS_UART_CR_STOPBRK) == 0)
801 writel(CDNS_UART_CR_STOPBRK | status,
802 port->membase + CDNS_UART_CR);
803 }
804 uart_port_unlock_irqrestore(port, flags);
805 }
806
807 /**
808 * cdns_uart_set_termios - termios operations, handling data length, parity,
809 * stop bits, flow control, baud rate
810 * @port: Handle to the uart port structure
811 * @termios: Handle to the input termios structure
812 * @old: Values of the previously saved termios structure
813 */
cdns_uart_set_termios(struct uart_port * port,struct ktermios * termios,const struct ktermios * old)814 static void cdns_uart_set_termios(struct uart_port *port,
815 struct ktermios *termios,
816 const struct ktermios *old)
817 {
818 u32 cval = 0;
819 unsigned int baud, minbaud, maxbaud;
820 unsigned long flags;
821 unsigned int ctrl_reg, mode_reg;
822
823 uart_port_lock_irqsave(port, &flags);
824
825 /* Disable the TX and RX to set baud rate */
826 ctrl_reg = readl(port->membase + CDNS_UART_CR);
827 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
828 writel(ctrl_reg, port->membase + CDNS_UART_CR);
829
830 /*
831 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
832 * min and max baud should be calculated here based on port->uartclk.
833 * this way we get a valid baud and can safely call set_baud()
834 */
835 minbaud = port->uartclk /
836 ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8);
837 maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1);
838 baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud);
839 baud = cdns_uart_set_baud_rate(port, baud);
840 if (tty_termios_baud_rate(termios))
841 tty_termios_encode_baud_rate(termios, baud, baud);
842
843 /* Update the per-port timeout. */
844 uart_update_timeout(port, termios->c_cflag, baud);
845
846 /* Set TX/RX Reset */
847 ctrl_reg = readl(port->membase + CDNS_UART_CR);
848 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
849 writel(ctrl_reg, port->membase + CDNS_UART_CR);
850
851 while (readl(port->membase + CDNS_UART_CR) &
852 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
853 cpu_relax();
854
855 /*
856 * Clear the RX disable and TX disable bits and then set the TX enable
857 * bit and RX enable bit to enable the transmitter and receiver.
858 */
859 ctrl_reg = readl(port->membase + CDNS_UART_CR);
860 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
861 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
862 writel(ctrl_reg, port->membase + CDNS_UART_CR);
863
864 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
865
866 port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |
867 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;
868 port->ignore_status_mask = 0;
869
870 if (termios->c_iflag & INPCK)
871 port->read_status_mask |= CDNS_UART_IXR_PARITY |
872 CDNS_UART_IXR_FRAMING;
873
874 if (termios->c_iflag & IGNPAR)
875 port->ignore_status_mask |= CDNS_UART_IXR_PARITY |
876 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
877
878 /* ignore all characters if CREAD is not set */
879 if ((termios->c_cflag & CREAD) == 0)
880 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG |
881 CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY |
882 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
883
884 mode_reg = readl(port->membase + CDNS_UART_MR);
885
886 /* Handling Data Size */
887 switch (termios->c_cflag & CSIZE) {
888 case CS6:
889 cval |= CDNS_UART_MR_CHARLEN_6_BIT;
890 break;
891 case CS7:
892 cval |= CDNS_UART_MR_CHARLEN_7_BIT;
893 break;
894 default:
895 case CS8:
896 cval |= CDNS_UART_MR_CHARLEN_8_BIT;
897 termios->c_cflag &= ~CSIZE;
898 termios->c_cflag |= CS8;
899 break;
900 }
901
902 /* Handling Parity and Stop Bits length */
903 if (termios->c_cflag & CSTOPB)
904 cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */
905 else
906 cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */
907
908 if (termios->c_cflag & PARENB) {
909 /* Mark or Space parity */
910 if (termios->c_cflag & CMSPAR) {
911 if (termios->c_cflag & PARODD)
912 cval |= CDNS_UART_MR_PARITY_MARK;
913 else
914 cval |= CDNS_UART_MR_PARITY_SPACE;
915 } else {
916 if (termios->c_cflag & PARODD)
917 cval |= CDNS_UART_MR_PARITY_ODD;
918 else
919 cval |= CDNS_UART_MR_PARITY_EVEN;
920 }
921 } else {
922 cval |= CDNS_UART_MR_PARITY_NONE;
923 }
924 cval |= mode_reg & 1;
925 writel(cval, port->membase + CDNS_UART_MR);
926
927 cval = readl(port->membase + CDNS_UART_MODEMCR);
928 if (termios->c_cflag & CRTSCTS)
929 cval |= CDNS_UART_MODEMCR_FCM;
930 else
931 cval &= ~CDNS_UART_MODEMCR_FCM;
932 writel(cval, port->membase + CDNS_UART_MODEMCR);
933
934 uart_port_unlock_irqrestore(port, flags);
935 }
936
937 /**
938 * cdns_uart_startup - Called when an application opens a cdns_uart port
939 * @port: Handle to the uart port structure
940 *
941 * Return: 0 on success, negative errno otherwise
942 */
cdns_uart_startup(struct uart_port * port)943 static int cdns_uart_startup(struct uart_port *port)
944 {
945 struct cdns_uart *cdns_uart = port->private_data;
946 bool is_brk_support;
947 int ret;
948 unsigned long flags;
949 unsigned int status = 0;
950
951 is_brk_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
952
953 ret = reset_control_deassert(cdns_uart->rstc);
954 if (ret)
955 return ret;
956
957 uart_port_lock_irqsave(port, &flags);
958
959 /* Disable the TX and RX */
960 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
961 port->membase + CDNS_UART_CR);
962
963 /* Set the Control Register with TX/RX Enable, TX/RX Reset,
964 * no break chars.
965 */
966 writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST,
967 port->membase + CDNS_UART_CR);
968
969 while (readl(port->membase + CDNS_UART_CR) &
970 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
971 cpu_relax();
972
973 if (cdns_uart->port->rs485.flags & SER_RS485_ENABLED)
974 cdns_rs485_rx_setup(cdns_uart);
975
976 /*
977 * Clear the RX disable bit and then set the RX enable bit to enable
978 * the receiver.
979 */
980 status = readl(port->membase + CDNS_UART_CR);
981 status &= ~CDNS_UART_CR_RX_DIS;
982 status |= CDNS_UART_CR_RX_EN;
983 writel(status, port->membase + CDNS_UART_CR);
984
985 /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
986 * no parity.
987 */
988 writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT
989 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT,
990 port->membase + CDNS_UART_MR);
991
992 /*
993 * Set the RX FIFO Trigger level to use most of the FIFO, but it
994 * can be tuned with a module parameter
995 */
996 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
997
998 /*
999 * Receive Timeout register is enabled but it
1000 * can be tuned with a module parameter
1001 */
1002 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
1003
1004 /* Clear out any pending interrupts before enabling them */
1005 writel(readl(port->membase + CDNS_UART_ISR),
1006 port->membase + CDNS_UART_ISR);
1007
1008 uart_port_unlock_irqrestore(port, flags);
1009
1010 ret = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, port);
1011 if (ret) {
1012 dev_err(port->dev, "request_irq '%d' failed with %d\n",
1013 port->irq, ret);
1014 return ret;
1015 }
1016
1017 /* Set the Interrupt Registers with desired interrupts */
1018 if (is_brk_support)
1019 writel(CDNS_UART_RX_IRQS | CDNS_UART_IXR_BRK,
1020 port->membase + CDNS_UART_IER);
1021 else
1022 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER);
1023
1024 return 0;
1025 }
1026
1027 /**
1028 * cdns_uart_shutdown - Called when an application closes a cdns_uart port
1029 * @port: Handle to the uart port structure
1030 */
cdns_uart_shutdown(struct uart_port * port)1031 static void cdns_uart_shutdown(struct uart_port *port)
1032 {
1033 int status;
1034 unsigned long flags;
1035 struct cdns_uart *cdns_uart = port->private_data;
1036
1037 if (cdns_uart->port->rs485.flags & SER_RS485_ENABLED)
1038 hrtimer_cancel(&cdns_uart->tx_timer);
1039
1040 uart_port_lock_irqsave(port, &flags);
1041
1042 /* Disable interrupts */
1043 status = readl(port->membase + CDNS_UART_IMR);
1044 writel(status, port->membase + CDNS_UART_IDR);
1045 writel(0xffffffff, port->membase + CDNS_UART_ISR);
1046
1047 /* Disable the TX and RX */
1048 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
1049 port->membase + CDNS_UART_CR);
1050
1051 uart_port_unlock_irqrestore(port, flags);
1052
1053 free_irq(port->irq, port);
1054 }
1055
1056 /**
1057 * cdns_uart_type - Set UART type to cdns_uart port
1058 * @port: Handle to the uart port structure
1059 *
1060 * Return: string on success, NULL otherwise
1061 */
cdns_uart_type(struct uart_port * port)1062 static const char *cdns_uart_type(struct uart_port *port)
1063 {
1064 return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL;
1065 }
1066
1067 /**
1068 * cdns_uart_verify_port - Verify the port params
1069 * @port: Handle to the uart port structure
1070 * @ser: Handle to the structure whose members are compared
1071 *
1072 * Return: 0 on success, negative errno otherwise.
1073 */
cdns_uart_verify_port(struct uart_port * port,struct serial_struct * ser)1074 static int cdns_uart_verify_port(struct uart_port *port,
1075 struct serial_struct *ser)
1076 {
1077 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
1078 return -EINVAL;
1079 if (port->irq != ser->irq)
1080 return -EINVAL;
1081 if (ser->io_type != UPIO_MEM)
1082 return -EINVAL;
1083 if (port->iobase != ser->port)
1084 return -EINVAL;
1085 if (ser->hub6 != 0)
1086 return -EINVAL;
1087 return 0;
1088 }
1089
1090 /**
1091 * cdns_uart_request_port - Claim the memory region attached to cdns_uart port,
1092 * called when the driver adds a cdns_uart port via
1093 * uart_add_one_port()
1094 * @port: Handle to the uart port structure
1095 *
1096 * Return: 0 on success, negative errno otherwise.
1097 */
cdns_uart_request_port(struct uart_port * port)1098 static int cdns_uart_request_port(struct uart_port *port)
1099 {
1100 if (!request_mem_region(port->mapbase, port->mapsize,
1101 CDNS_UART_NAME)) {
1102 return -ENOMEM;
1103 }
1104
1105 port->membase = ioremap(port->mapbase, port->mapsize);
1106 if (!port->membase) {
1107 dev_err(port->dev, "Unable to map registers\n");
1108 release_mem_region(port->mapbase, port->mapsize);
1109 return -ENOMEM;
1110 }
1111 return 0;
1112 }
1113
1114 /**
1115 * cdns_uart_release_port - Release UART port
1116 * @port: Handle to the uart port structure
1117 *
1118 * Release the memory region attached to a cdns_uart port. Called when the
1119 * driver removes a cdns_uart port via uart_remove_one_port().
1120 */
cdns_uart_release_port(struct uart_port * port)1121 static void cdns_uart_release_port(struct uart_port *port)
1122 {
1123 release_mem_region(port->mapbase, port->mapsize);
1124 iounmap(port->membase);
1125 port->membase = NULL;
1126 }
1127
1128 /**
1129 * cdns_uart_config_port - Configure UART port
1130 * @port: Handle to the uart port structure
1131 * @flags: If any
1132 */
cdns_uart_config_port(struct uart_port * port,int flags)1133 static void cdns_uart_config_port(struct uart_port *port, int flags)
1134 {
1135 if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0)
1136 port->type = PORT_XUARTPS;
1137 }
1138
1139 /**
1140 * cdns_uart_get_mctrl - Get the modem control state
1141 * @port: Handle to the uart port structure
1142 *
1143 * Return: the modem control state
1144 */
cdns_uart_get_mctrl(struct uart_port * port)1145 static unsigned int cdns_uart_get_mctrl(struct uart_port *port)
1146 {
1147 u32 val;
1148 unsigned int mctrl = 0;
1149 struct cdns_uart *cdns_uart_data = port->private_data;
1150
1151 if (cdns_uart_data->cts_override)
1152 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
1153
1154 val = readl(port->membase + CDNS_UART_MODEMSR);
1155 if (val & CDNS_UART_MODEMSR_CTS)
1156 mctrl |= TIOCM_CTS;
1157 if (val & CDNS_UART_MODEMSR_DSR)
1158 mctrl |= TIOCM_DSR;
1159 if (val & CDNS_UART_MODEMSR_RI)
1160 mctrl |= TIOCM_RNG;
1161 if (val & CDNS_UART_MODEMSR_DCD)
1162 mctrl |= TIOCM_CAR;
1163
1164 return mctrl;
1165 }
1166
cdns_uart_set_mctrl(struct uart_port * port,unsigned int mctrl)1167 static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1168 {
1169 u32 val;
1170 u32 mode_reg;
1171 struct cdns_uart *cdns_uart_data = port->private_data;
1172
1173 if (cdns_uart_data->cts_override)
1174 return;
1175
1176 val = readl(port->membase + CDNS_UART_MODEMCR);
1177 mode_reg = readl(port->membase + CDNS_UART_MR);
1178
1179 val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR);
1180 mode_reg &= ~CDNS_UART_MR_CHMODE_MASK;
1181
1182 if (mctrl & TIOCM_RTS)
1183 val |= CDNS_UART_MODEMCR_RTS;
1184 if (cdns_uart_data->gpiod_rts)
1185 gpiod_set_value(cdns_uart_data->gpiod_rts, !(mctrl & TIOCM_RTS));
1186 if (mctrl & TIOCM_DTR)
1187 val |= CDNS_UART_MODEMCR_DTR;
1188 if (mctrl & TIOCM_LOOP)
1189 mode_reg |= CDNS_UART_MR_CHMODE_L_LOOP;
1190 else
1191 mode_reg |= CDNS_UART_MR_CHMODE_NORM;
1192
1193 writel(val, port->membase + CDNS_UART_MODEMCR);
1194 writel(mode_reg, port->membase + CDNS_UART_MR);
1195 }
1196
1197 #ifdef CONFIG_CONSOLE_POLL
cdns_uart_poll_get_char(struct uart_port * port)1198 static int cdns_uart_poll_get_char(struct uart_port *port)
1199 {
1200 int c;
1201 unsigned long flags;
1202
1203 uart_port_lock_irqsave(port, &flags);
1204
1205 /* Check if FIFO is empty */
1206 if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY)
1207 c = NO_POLL_CHAR;
1208 else /* Read a character */
1209 c = (unsigned char) readl(port->membase + CDNS_UART_FIFO);
1210
1211 uart_port_unlock_irqrestore(port, flags);
1212
1213 return c;
1214 }
1215
cdns_uart_poll_put_char(struct uart_port * port,unsigned char c)1216 static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c)
1217 {
1218 unsigned long flags;
1219
1220 uart_port_lock_irqsave(port, &flags);
1221
1222 /* Wait until FIFO is empty */
1223 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1224 cpu_relax();
1225
1226 /* Write a character */
1227 writel(c, port->membase + CDNS_UART_FIFO);
1228
1229 /* Wait until FIFO is empty */
1230 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1231 cpu_relax();
1232
1233 uart_port_unlock_irqrestore(port, flags);
1234 }
1235 #endif
1236
cdns_uart_pm(struct uart_port * port,unsigned int state,unsigned int oldstate)1237 static void cdns_uart_pm(struct uart_port *port, unsigned int state,
1238 unsigned int oldstate)
1239 {
1240 switch (state) {
1241 case UART_PM_STATE_OFF:
1242 pm_runtime_mark_last_busy(port->dev);
1243 pm_runtime_put_autosuspend(port->dev);
1244 break;
1245 default:
1246 pm_runtime_get_sync(port->dev);
1247 break;
1248 }
1249 }
1250
1251 static const struct uart_ops cdns_uart_ops = {
1252 .set_mctrl = cdns_uart_set_mctrl,
1253 .get_mctrl = cdns_uart_get_mctrl,
1254 .start_tx = cdns_uart_start_tx,
1255 .stop_tx = cdns_uart_stop_tx,
1256 .stop_rx = cdns_uart_stop_rx,
1257 .tx_empty = cdns_uart_tx_empty,
1258 .break_ctl = cdns_uart_break_ctl,
1259 .set_termios = cdns_uart_set_termios,
1260 .startup = cdns_uart_startup,
1261 .shutdown = cdns_uart_shutdown,
1262 .pm = cdns_uart_pm,
1263 .type = cdns_uart_type,
1264 .verify_port = cdns_uart_verify_port,
1265 .request_port = cdns_uart_request_port,
1266 .release_port = cdns_uart_release_port,
1267 .config_port = cdns_uart_config_port,
1268 #ifdef CONFIG_CONSOLE_POLL
1269 .poll_get_char = cdns_uart_poll_get_char,
1270 .poll_put_char = cdns_uart_poll_put_char,
1271 #endif
1272 };
1273
1274 static struct uart_driver cdns_uart_uart_driver;
1275
1276 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1277 /**
1278 * cdns_uart_console_putchar - write the character to the FIFO buffer
1279 * @port: Handle to the uart port structure
1280 * @ch: Character to be written
1281 */
cdns_uart_console_putchar(struct uart_port * port,unsigned char ch)1282 static void cdns_uart_console_putchar(struct uart_port *port, unsigned char ch)
1283 {
1284 unsigned int ctrl_reg;
1285 unsigned long timeout;
1286
1287 timeout = jiffies + msecs_to_jiffies(1000);
1288 while (1) {
1289 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1290 if (!(ctrl_reg & CDNS_UART_CR_TX_DIS))
1291 break;
1292 if (time_after(jiffies, timeout)) {
1293 dev_warn(port->dev,
1294 "timeout waiting for Enable\n");
1295 return;
1296 }
1297 cpu_relax();
1298 }
1299
1300 timeout = jiffies + msecs_to_jiffies(1000);
1301 while (1) {
1302 ctrl_reg = readl(port->membase + CDNS_UART_SR);
1303
1304 if (!(ctrl_reg & CDNS_UART_SR_TXFULL))
1305 break;
1306 if (time_after(jiffies, timeout)) {
1307 dev_warn(port->dev,
1308 "timeout waiting for TX fifo\n");
1309 return;
1310 }
1311 cpu_relax();
1312 }
1313 writel(ch, port->membase + CDNS_UART_FIFO);
1314 }
1315
cdns_early_write(struct console * con,const char * s,unsigned int n)1316 static void cdns_early_write(struct console *con, const char *s,
1317 unsigned int n)
1318 {
1319 struct earlycon_device *dev = con->data;
1320
1321 uart_console_write(&dev->port, s, n, cdns_uart_console_putchar);
1322 }
1323
cdns_early_console_setup(struct earlycon_device * device,const char * opt)1324 static int __init cdns_early_console_setup(struct earlycon_device *device,
1325 const char *opt)
1326 {
1327 struct uart_port *port = &device->port;
1328
1329 if (!port->membase)
1330 return -ENODEV;
1331
1332 /* initialise control register */
1333 writel(CDNS_UART_CR_TX_EN|CDNS_UART_CR_TXRST|CDNS_UART_CR_RXRST,
1334 port->membase + CDNS_UART_CR);
1335
1336 /* only set baud if specified on command line - otherwise
1337 * assume it has been initialized by a boot loader.
1338 */
1339 if (port->uartclk && device->baud) {
1340 u32 cd = 0, bdiv = 0;
1341 u32 mr;
1342 int div8;
1343
1344 cdns_uart_calc_baud_divs(port->uartclk, device->baud,
1345 &bdiv, &cd, &div8);
1346 mr = CDNS_UART_MR_PARITY_NONE;
1347 if (div8)
1348 mr |= CDNS_UART_MR_CLKSEL;
1349
1350 writel(mr, port->membase + CDNS_UART_MR);
1351 writel(cd, port->membase + CDNS_UART_BAUDGEN);
1352 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
1353 }
1354
1355 device->con->write = cdns_early_write;
1356
1357 return 0;
1358 }
1359 OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup);
1360 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup);
1361 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup);
1362 OF_EARLYCON_DECLARE(cdns, "xlnx,zynqmp-uart", cdns_early_console_setup);
1363
1364
1365 /* Static pointer to console port */
1366 static struct uart_port *console_port;
1367
1368 /**
1369 * cdns_uart_console_write - perform write operation
1370 * @co: Console handle
1371 * @s: Pointer to character array
1372 * @count: No of characters
1373 */
cdns_uart_console_write(struct console * co,const char * s,unsigned int count)1374 static void cdns_uart_console_write(struct console *co, const char *s,
1375 unsigned int count)
1376 {
1377 struct uart_port *port = console_port;
1378 unsigned long flags;
1379 unsigned int imr, ctrl;
1380 int locked = 1;
1381
1382 if (oops_in_progress)
1383 locked = uart_port_trylock_irqsave(port, &flags);
1384 else
1385 uart_port_lock_irqsave(port, &flags);
1386
1387 /* save and disable interrupt */
1388 imr = readl(port->membase + CDNS_UART_IMR);
1389 writel(imr, port->membase + CDNS_UART_IDR);
1390
1391 /*
1392 * Make sure that the tx part is enabled. Set the TX enable bit and
1393 * clear the TX disable bit to enable the transmitter.
1394 */
1395 ctrl = readl(port->membase + CDNS_UART_CR);
1396 ctrl &= ~CDNS_UART_CR_TX_DIS;
1397 ctrl |= CDNS_UART_CR_TX_EN;
1398 writel(ctrl, port->membase + CDNS_UART_CR);
1399
1400 uart_console_write(port, s, count, cdns_uart_console_putchar);
1401 while (cdns_uart_tx_empty(port) != TIOCSER_TEMT)
1402 cpu_relax();
1403
1404 /* restore interrupt state */
1405 writel(imr, port->membase + CDNS_UART_IER);
1406
1407 if (locked)
1408 uart_port_unlock_irqrestore(port, flags);
1409 }
1410
1411 /**
1412 * cdns_uart_console_setup - Initialize the uart to default config
1413 * @co: Console handle
1414 * @options: Initial settings of uart
1415 *
1416 * Return: 0 on success, negative errno otherwise.
1417 */
cdns_uart_console_setup(struct console * co,char * options)1418 static int cdns_uart_console_setup(struct console *co, char *options)
1419 {
1420 struct uart_port *port = console_port;
1421
1422 int baud = 9600;
1423 int bits = 8;
1424 int parity = 'n';
1425 int flow = 'n';
1426 unsigned long time_out;
1427
1428 if (!port->membase) {
1429 pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n",
1430 co->index);
1431 return -ENODEV;
1432 }
1433
1434 if (options)
1435 uart_parse_options(options, &baud, &parity, &bits, &flow);
1436
1437 /* Wait for tx_empty before setting up the console */
1438 time_out = jiffies + usecs_to_jiffies(TX_TIMEOUT);
1439
1440 while (time_before(jiffies, time_out) &&
1441 cdns_uart_tx_empty(port) != TIOCSER_TEMT)
1442 cpu_relax();
1443
1444 return uart_set_options(port, co, baud, parity, bits, flow);
1445 }
1446
1447 static struct console cdns_uart_console = {
1448 .name = CDNS_UART_TTY_NAME,
1449 .write = cdns_uart_console_write,
1450 .device = uart_console_device,
1451 .setup = cdns_uart_console_setup,
1452 .flags = CON_PRINTBUFFER,
1453 .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */
1454 .data = &cdns_uart_uart_driver,
1455 };
1456 #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
1457
1458 #ifdef CONFIG_PM_SLEEP
1459 /**
1460 * cdns_uart_suspend - suspend event
1461 * @device: Pointer to the device structure
1462 *
1463 * Return: 0
1464 */
cdns_uart_suspend(struct device * device)1465 static int cdns_uart_suspend(struct device *device)
1466 {
1467 struct uart_port *port = dev_get_drvdata(device);
1468 struct cdns_uart *cdns_uart = port->private_data;
1469 int may_wake;
1470
1471 may_wake = device_may_wakeup(device);
1472
1473 if (console_suspend_enabled && uart_console(port) && may_wake) {
1474 unsigned long flags;
1475
1476 uart_port_lock_irqsave(port, &flags);
1477 /* Empty the receive FIFO 1st before making changes */
1478 while (!(readl(port->membase + CDNS_UART_SR) &
1479 CDNS_UART_SR_RXEMPTY))
1480 readl(port->membase + CDNS_UART_FIFO);
1481 /* set RX trigger level to 1 */
1482 writel(1, port->membase + CDNS_UART_RXWM);
1483 /* disable RX timeout interrups */
1484 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR);
1485 uart_port_unlock_irqrestore(port, flags);
1486 }
1487
1488 /*
1489 * Call the API provided in serial_core.c file which handles
1490 * the suspend.
1491 */
1492 return uart_suspend_port(cdns_uart->cdns_uart_driver, port);
1493 }
1494
1495 /**
1496 * cdns_uart_resume - Resume after a previous suspend
1497 * @device: Pointer to the device structure
1498 *
1499 * Return: 0
1500 */
cdns_uart_resume(struct device * device)1501 static int cdns_uart_resume(struct device *device)
1502 {
1503 struct uart_port *port = dev_get_drvdata(device);
1504 struct cdns_uart *cdns_uart = port->private_data;
1505 unsigned long flags;
1506 u32 ctrl_reg;
1507 int may_wake;
1508 int ret;
1509
1510 may_wake = device_may_wakeup(device);
1511
1512 if (console_suspend_enabled && uart_console(port) && !may_wake) {
1513 ret = clk_enable(cdns_uart->pclk);
1514 if (ret)
1515 return ret;
1516
1517 ret = clk_enable(cdns_uart->uartclk);
1518 if (ret) {
1519 clk_disable(cdns_uart->pclk);
1520 return ret;
1521 }
1522
1523 uart_port_lock_irqsave(port, &flags);
1524
1525 /* Set TX/RX Reset */
1526 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1527 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
1528 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1529 while (readl(port->membase + CDNS_UART_CR) &
1530 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
1531 cpu_relax();
1532
1533 /* restore rx timeout value */
1534 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
1535 /* Enable Tx/Rx */
1536 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1537 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
1538 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
1539 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1540
1541 clk_disable(cdns_uart->uartclk);
1542 clk_disable(cdns_uart->pclk);
1543 uart_port_unlock_irqrestore(port, flags);
1544 } else {
1545 uart_port_lock_irqsave(port, &flags);
1546 /* restore original rx trigger level */
1547 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
1548 /* enable RX timeout interrupt */
1549 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER);
1550 uart_port_unlock_irqrestore(port, flags);
1551 }
1552
1553 return uart_resume_port(cdns_uart->cdns_uart_driver, port);
1554 }
1555 #endif /* ! CONFIG_PM_SLEEP */
cdns_runtime_suspend(struct device * dev)1556 static int __maybe_unused cdns_runtime_suspend(struct device *dev)
1557 {
1558 struct uart_port *port = dev_get_drvdata(dev);
1559 struct cdns_uart *cdns_uart = port->private_data;
1560
1561 clk_disable(cdns_uart->uartclk);
1562 clk_disable(cdns_uart->pclk);
1563 return 0;
1564 };
1565
cdns_runtime_resume(struct device * dev)1566 static int __maybe_unused cdns_runtime_resume(struct device *dev)
1567 {
1568 struct uart_port *port = dev_get_drvdata(dev);
1569 struct cdns_uart *cdns_uart = port->private_data;
1570 int ret;
1571
1572 ret = clk_enable(cdns_uart->pclk);
1573 if (ret)
1574 return ret;
1575
1576 ret = clk_enable(cdns_uart->uartclk);
1577 if (ret) {
1578 clk_disable(cdns_uart->pclk);
1579 return ret;
1580 }
1581 return 0;
1582 };
1583
1584 static const struct dev_pm_ops cdns_uart_dev_pm_ops = {
1585 SET_SYSTEM_SLEEP_PM_OPS(cdns_uart_suspend, cdns_uart_resume)
1586 SET_RUNTIME_PM_OPS(cdns_runtime_suspend,
1587 cdns_runtime_resume, NULL)
1588 };
1589
1590 static const struct cdns_platform_data zynqmp_uart_def = {
1591 .quirks = CDNS_UART_RXBS_SUPPORT, };
1592
1593 /* Match table for of_platform binding */
1594 static const struct of_device_id cdns_uart_of_match[] = {
1595 { .compatible = "xlnx,xuartps", },
1596 { .compatible = "cdns,uart-r1p8", },
1597 { .compatible = "cdns,uart-r1p12", .data = &zynqmp_uart_def },
1598 { .compatible = "xlnx,zynqmp-uart", .data = &zynqmp_uart_def },
1599 {}
1600 };
1601 MODULE_DEVICE_TABLE(of, cdns_uart_of_match);
1602
1603 /* Temporary variable for storing number of instances */
1604 static int instances;
1605
1606 /**
1607 * cdns_rs485_config - Called when an application calls TIOCSRS485 ioctl.
1608 * @port: Pointer to the uart_port structure
1609 * @termios: Pointer to the ktermios structure
1610 * @rs485: Pointer to the serial_rs485 structure
1611 *
1612 * Return: 0
1613 */
cdns_rs485_config(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485)1614 static int cdns_rs485_config(struct uart_port *port, struct ktermios *termios,
1615 struct serial_rs485 *rs485)
1616 {
1617 u32 val;
1618 struct cdns_uart *cdns_uart = port->private_data;
1619
1620 if (rs485->flags & SER_RS485_ENABLED) {
1621 dev_dbg(port->dev, "Setting UART to RS485\n");
1622 /* Make sure auto RTS is disabled */
1623 val = readl(port->membase + CDNS_UART_MODEMCR);
1624 val &= ~CDNS_UART_MODEMCR_FCM;
1625 writel(val, port->membase + CDNS_UART_MODEMCR);
1626
1627 /* Timer setup */
1628 hrtimer_setup(&cdns_uart->tx_timer, &cdns_rs485_tx_callback, CLOCK_MONOTONIC,
1629 HRTIMER_MODE_REL);
1630
1631 /* Disable transmitter and make Rx setup*/
1632 cdns_uart_stop_tx(port);
1633 } else {
1634 hrtimer_cancel(&cdns_uart->tx_timer);
1635 }
1636 return 0;
1637 }
1638
1639 /**
1640 * cdns_uart_probe - Platform driver probe
1641 * @pdev: Pointer to the platform device structure
1642 *
1643 * Return: 0 on success, negative errno otherwise
1644 */
cdns_uart_probe(struct platform_device * pdev)1645 static int cdns_uart_probe(struct platform_device *pdev)
1646 {
1647 int rc, id, irq;
1648 struct uart_port *port;
1649 struct resource *res;
1650 struct cdns_uart *cdns_uart_data;
1651 const struct of_device_id *match;
1652
1653 cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data),
1654 GFP_KERNEL);
1655 if (!cdns_uart_data)
1656 return -ENOMEM;
1657 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
1658 if (!port)
1659 return -ENOMEM;
1660
1661 /* Look for a serialN alias */
1662 id = of_alias_get_id(pdev->dev.of_node, "serial");
1663 if (id < 0)
1664 id = 0;
1665
1666 if (id >= CDNS_UART_NR_PORTS) {
1667 dev_err(&pdev->dev, "Cannot get uart_port structure\n");
1668 return -ENODEV;
1669 }
1670
1671 if (!cdns_uart_uart_driver.state) {
1672 cdns_uart_uart_driver.owner = THIS_MODULE;
1673 cdns_uart_uart_driver.driver_name = CDNS_UART_NAME;
1674 cdns_uart_uart_driver.dev_name = CDNS_UART_TTY_NAME;
1675 cdns_uart_uart_driver.major = CDNS_UART_MAJOR;
1676 cdns_uart_uart_driver.minor = CDNS_UART_MINOR;
1677 cdns_uart_uart_driver.nr = CDNS_UART_NR_PORTS;
1678 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1679 cdns_uart_uart_driver.cons = &cdns_uart_console;
1680 #endif
1681
1682 rc = uart_register_driver(&cdns_uart_uart_driver);
1683 if (rc < 0) {
1684 dev_err(&pdev->dev, "Failed to register driver\n");
1685 return rc;
1686 }
1687 }
1688
1689 cdns_uart_data->cdns_uart_driver = &cdns_uart_uart_driver;
1690
1691 match = of_match_node(cdns_uart_of_match, pdev->dev.of_node);
1692 if (match && match->data) {
1693 const struct cdns_platform_data *data = match->data;
1694
1695 cdns_uart_data->quirks = data->quirks;
1696 }
1697
1698 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk");
1699 if (PTR_ERR(cdns_uart_data->pclk) == -EPROBE_DEFER) {
1700 rc = PTR_ERR(cdns_uart_data->pclk);
1701 goto err_out_unregister_driver;
1702 }
1703
1704 if (IS_ERR(cdns_uart_data->pclk)) {
1705 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk");
1706 if (IS_ERR(cdns_uart_data->pclk)) {
1707 rc = PTR_ERR(cdns_uart_data->pclk);
1708 goto err_out_unregister_driver;
1709 }
1710 dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n");
1711 }
1712
1713 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk");
1714 if (PTR_ERR(cdns_uart_data->uartclk) == -EPROBE_DEFER) {
1715 rc = PTR_ERR(cdns_uart_data->uartclk);
1716 goto err_out_unregister_driver;
1717 }
1718
1719 if (IS_ERR(cdns_uart_data->uartclk)) {
1720 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk");
1721 if (IS_ERR(cdns_uart_data->uartclk)) {
1722 rc = PTR_ERR(cdns_uart_data->uartclk);
1723 goto err_out_unregister_driver;
1724 }
1725 dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n");
1726 }
1727
1728 cdns_uart_data->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
1729 if (IS_ERR(cdns_uart_data->rstc)) {
1730 rc = PTR_ERR(cdns_uart_data->rstc);
1731 dev_err_probe(&pdev->dev, rc, "Cannot get UART reset\n");
1732 goto err_out_unregister_driver;
1733 }
1734
1735 rc = clk_prepare_enable(cdns_uart_data->pclk);
1736 if (rc) {
1737 dev_err(&pdev->dev, "Unable to enable pclk clock.\n");
1738 goto err_out_unregister_driver;
1739 }
1740 rc = clk_prepare_enable(cdns_uart_data->uartclk);
1741 if (rc) {
1742 dev_err(&pdev->dev, "Unable to enable device clock.\n");
1743 goto err_out_clk_dis_pclk;
1744 }
1745
1746 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1747 if (!res) {
1748 rc = -ENODEV;
1749 goto err_out_clk_disable;
1750 }
1751
1752 irq = platform_get_irq(pdev, 0);
1753 if (irq < 0) {
1754 rc = irq;
1755 goto err_out_clk_disable;
1756 }
1757
1758 #ifdef CONFIG_COMMON_CLK
1759 cdns_uart_data->clk_rate_change_nb.notifier_call =
1760 cdns_uart_clk_notifier_cb;
1761 if (clk_notifier_register(cdns_uart_data->uartclk,
1762 &cdns_uart_data->clk_rate_change_nb))
1763 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1764 #endif
1765
1766 /* At this point, we've got an empty uart_port struct, initialize it */
1767 spin_lock_init(&port->lock);
1768 port->type = PORT_UNKNOWN;
1769 port->iotype = UPIO_MEM32;
1770 port->flags = UPF_BOOT_AUTOCONF;
1771 port->ops = &cdns_uart_ops;
1772 port->fifosize = CDNS_UART_FIFO_SIZE;
1773 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE);
1774 port->line = id;
1775
1776 /*
1777 * Register the port.
1778 * This function also registers this device with the tty layer
1779 * and triggers invocation of the config_port() entry point.
1780 */
1781 port->mapbase = res->start;
1782 port->mapsize = resource_size(res);
1783 port->irq = irq;
1784 port->dev = &pdev->dev;
1785 port->uartclk = clk_get_rate(cdns_uart_data->uartclk);
1786 port->private_data = cdns_uart_data;
1787 port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |
1788 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;
1789 port->rs485_config = cdns_rs485_config;
1790 port->rs485_supported = cdns_rs485_supported;
1791 cdns_uart_data->port = port;
1792 platform_set_drvdata(pdev, port);
1793
1794 rc = uart_get_rs485_mode(port);
1795 if (rc)
1796 goto err_out_clk_notifier;
1797
1798 cdns_uart_data->gpiod_rts = devm_gpiod_get_optional(&pdev->dev, "rts",
1799 GPIOD_OUT_LOW);
1800 if (IS_ERR(cdns_uart_data->gpiod_rts)) {
1801 rc = PTR_ERR(cdns_uart_data->gpiod_rts);
1802 dev_err(port->dev, "xuartps: devm_gpiod_get_optional failed\n");
1803 goto err_out_clk_notifier;
1804 }
1805
1806 pm_runtime_use_autosuspend(&pdev->dev);
1807 pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT);
1808 pm_runtime_set_active(&pdev->dev);
1809 pm_runtime_enable(&pdev->dev);
1810 device_init_wakeup(port->dev, true);
1811
1812 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1813 /*
1814 * If console hasn't been found yet try to assign this port
1815 * because it is required to be assigned for console setup function.
1816 * If register_console() don't assign value, then console_port pointer
1817 * is cleanup.
1818 */
1819 if (!console_port) {
1820 cdns_uart_console.index = id;
1821 console_port = port;
1822 }
1823 #endif
1824 if (cdns_uart_data->port->rs485.flags & SER_RS485_ENABLED)
1825 cdns_rs485_rx_setup(cdns_uart_data);
1826
1827 rc = uart_add_one_port(&cdns_uart_uart_driver, port);
1828 if (rc) {
1829 dev_err(&pdev->dev,
1830 "uart_add_one_port() failed; err=%i\n", rc);
1831 goto err_out_pm_disable;
1832 }
1833
1834 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1835 /* This is not port which is used for console that's why clean it up */
1836 if (console_port == port &&
1837 !console_is_registered(cdns_uart_uart_driver.cons)) {
1838 console_port = NULL;
1839 cdns_uart_console.index = -1;
1840 }
1841 #endif
1842
1843 cdns_uart_data->cts_override = of_property_read_bool(pdev->dev.of_node,
1844 "cts-override");
1845
1846 instances++;
1847
1848 return 0;
1849
1850 err_out_pm_disable:
1851 pm_runtime_disable(&pdev->dev);
1852 pm_runtime_set_suspended(&pdev->dev);
1853 pm_runtime_dont_use_autosuspend(&pdev->dev);
1854 err_out_clk_notifier:
1855 #ifdef CONFIG_COMMON_CLK
1856 clk_notifier_unregister(cdns_uart_data->uartclk,
1857 &cdns_uart_data->clk_rate_change_nb);
1858 #endif
1859 err_out_clk_disable:
1860 clk_disable_unprepare(cdns_uart_data->uartclk);
1861 err_out_clk_dis_pclk:
1862 clk_disable_unprepare(cdns_uart_data->pclk);
1863 err_out_unregister_driver:
1864 if (!instances)
1865 uart_unregister_driver(cdns_uart_data->cdns_uart_driver);
1866 return rc;
1867 }
1868
1869 /**
1870 * cdns_uart_remove - called when the platform driver is unregistered
1871 * @pdev: Pointer to the platform device structure
1872 */
cdns_uart_remove(struct platform_device * pdev)1873 static void cdns_uart_remove(struct platform_device *pdev)
1874 {
1875 struct uart_port *port = platform_get_drvdata(pdev);
1876 struct cdns_uart *cdns_uart_data = port->private_data;
1877
1878 /* Remove the cdns_uart port from the serial core */
1879 #ifdef CONFIG_COMMON_CLK
1880 clk_notifier_unregister(cdns_uart_data->uartclk,
1881 &cdns_uart_data->clk_rate_change_nb);
1882 #endif
1883 uart_remove_one_port(cdns_uart_data->cdns_uart_driver, port);
1884 port->mapbase = 0;
1885 clk_disable_unprepare(cdns_uart_data->uartclk);
1886 clk_disable_unprepare(cdns_uart_data->pclk);
1887 pm_runtime_disable(&pdev->dev);
1888 pm_runtime_set_suspended(&pdev->dev);
1889 pm_runtime_dont_use_autosuspend(&pdev->dev);
1890 device_init_wakeup(&pdev->dev, false);
1891
1892 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1893 if (console_port == port)
1894 console_port = NULL;
1895 #endif
1896 reset_control_assert(cdns_uart_data->rstc);
1897
1898 if (!--instances)
1899 uart_unregister_driver(cdns_uart_data->cdns_uart_driver);
1900 }
1901
1902 static struct platform_driver cdns_uart_platform_driver = {
1903 .probe = cdns_uart_probe,
1904 .remove = cdns_uart_remove,
1905 .driver = {
1906 .name = CDNS_UART_NAME,
1907 .of_match_table = cdns_uart_of_match,
1908 .pm = &cdns_uart_dev_pm_ops,
1909 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_XILINX_PS_UART),
1910 },
1911 };
1912
cdns_uart_init(void)1913 static int __init cdns_uart_init(void)
1914 {
1915 /* Register the platform driver */
1916 return platform_driver_register(&cdns_uart_platform_driver);
1917 }
1918
cdns_uart_exit(void)1919 static void __exit cdns_uart_exit(void)
1920 {
1921 /* Unregister the platform driver */
1922 platform_driver_unregister(&cdns_uart_platform_driver);
1923 }
1924
1925 arch_initcall(cdns_uart_init);
1926 module_exit(cdns_uart_exit);
1927
1928 MODULE_DESCRIPTION("Driver for Cadence UART");
1929 MODULE_AUTHOR("Xilinx Inc.");
1930 MODULE_LICENSE("GPL");
1931