1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2 // Copyright(c) 2015-17 Intel Corporation.
3
4 /*
5 * Cadence SoundWire Master module
6 * Used by Master driver
7 */
8
9 #include <linux/cleanup.h>
10 #include <linux/crc8.h>
11 #include <linux/delay.h>
12 #include <linux/device.h>
13 #include <linux/debugfs.h>
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/module.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/soundwire/sdw_registers.h>
19 #include <linux/soundwire/sdw.h>
20 #include <sound/pcm_params.h>
21 #include <sound/soc.h>
22 #include <linux/workqueue.h>
23 #include "bus.h"
24 #include "cadence_master.h"
25
26 static int interrupt_mask;
27 module_param_named(cnds_mcp_int_mask, interrupt_mask, int, 0444);
28 MODULE_PARM_DESC(cdns_mcp_int_mask, "Cadence MCP IntMask");
29
30 #define CDNS_MCP_CONFIG 0x0
31 #define CDNS_MCP_CONFIG_BUS_REL BIT(6)
32
33 #define CDNS_IP_MCP_CONFIG 0x0 /* IP offset added at run-time */
34
35 #define CDNS_IP_MCP_CONFIG_MCMD_RETRY GENMASK(27, 24)
36 #define CDNS_IP_MCP_CONFIG_MPREQ_DELAY GENMASK(20, 16)
37 #define CDNS_IP_MCP_CONFIG_MMASTER BIT(7)
38 #define CDNS_IP_MCP_CONFIG_SNIFFER BIT(5)
39 #define CDNS_IP_MCP_CONFIG_CMD BIT(3)
40 #define CDNS_IP_MCP_CONFIG_OP GENMASK(2, 0)
41 #define CDNS_IP_MCP_CONFIG_OP_NORMAL 0
42
43 #define CDNS_MCP_CONTROL 0x4
44
45 #define CDNS_MCP_CONTROL_CMD_RST BIT(7)
46 #define CDNS_MCP_CONTROL_SOFT_RST BIT(6)
47 #define CDNS_MCP_CONTROL_HW_RST BIT(4)
48 #define CDNS_MCP_CONTROL_CLK_STOP_CLR BIT(2)
49
50 #define CDNS_IP_MCP_CONTROL 0x4 /* IP offset added at run-time */
51
52 #define CDNS_IP_MCP_CONTROL_RST_DELAY GENMASK(10, 8)
53 #define CDNS_IP_MCP_CONTROL_SW_RST BIT(5)
54 #define CDNS_IP_MCP_CONTROL_CLK_PAUSE BIT(3)
55 #define CDNS_IP_MCP_CONTROL_CMD_ACCEPT BIT(1)
56 #define CDNS_IP_MCP_CONTROL_BLOCK_WAKEUP BIT(0)
57
58 #define CDNS_IP_MCP_CMDCTRL 0x8 /* IP offset added at run-time */
59
60 #define CDNS_IP_MCP_CMDCTRL_INSERT_PARITY_ERR BIT(2)
61
62 #define CDNS_MCP_SSPSTAT 0xC
63 #define CDNS_MCP_FRAME_SHAPE 0x10
64 #define CDNS_MCP_FRAME_SHAPE_INIT 0x14
65 #define CDNS_MCP_FRAME_SHAPE_COL_MASK GENMASK(2, 0)
66 #define CDNS_MCP_FRAME_SHAPE_ROW_MASK GENMASK(7, 3)
67
68 #define CDNS_MCP_CONFIG_UPDATE 0x18
69 #define CDNS_MCP_CONFIG_UPDATE_BIT BIT(0)
70
71 #define CDNS_MCP_PHYCTRL 0x1C
72 #define CDNS_MCP_SSP_CTRL0 0x20
73 #define CDNS_MCP_SSP_CTRL1 0x28
74 #define CDNS_MCP_CLK_CTRL0 0x30
75 #define CDNS_MCP_CLK_CTRL1 0x38
76 #define CDNS_MCP_CLK_MCLKD_MASK GENMASK(7, 0)
77
78 #define CDNS_MCP_STAT 0x40
79
80 #define CDNS_MCP_STAT_ACTIVE_BANK BIT(20)
81 #define CDNS_MCP_STAT_CLK_STOP BIT(16)
82
83 #define CDNS_MCP_INTSTAT 0x44
84 #define CDNS_MCP_INTMASK 0x48
85
86 #define CDNS_MCP_INT_IRQ BIT(31)
87 #define CDNS_MCP_INT_RESERVED1 GENMASK(30, 17)
88 #define CDNS_MCP_INT_WAKEUP BIT(16)
89 #define CDNS_MCP_INT_SLAVE_RSVD BIT(15)
90 #define CDNS_MCP_INT_SLAVE_ALERT BIT(14)
91 #define CDNS_MCP_INT_SLAVE_ATTACH BIT(13)
92 #define CDNS_MCP_INT_SLAVE_NATTACH BIT(12)
93 #define CDNS_MCP_INT_SLAVE_MASK GENMASK(15, 12)
94 #define CDNS_MCP_INT_DPINT BIT(11)
95 #define CDNS_MCP_INT_CTRL_CLASH BIT(10)
96 #define CDNS_MCP_INT_DATA_CLASH BIT(9)
97 #define CDNS_MCP_INT_PARITY BIT(8)
98 #define CDNS_MCP_INT_CMD_ERR BIT(7)
99 #define CDNS_MCP_INT_RESERVED2 GENMASK(6, 4)
100 #define CDNS_MCP_INT_RX_NE BIT(3)
101 #define CDNS_MCP_INT_RX_WL BIT(2)
102 #define CDNS_MCP_INT_TXE BIT(1)
103 #define CDNS_MCP_INT_TXF BIT(0)
104 #define CDNS_MCP_INT_RESERVED (CDNS_MCP_INT_RESERVED1 | CDNS_MCP_INT_RESERVED2)
105
106 #define CDNS_MCP_INTSET 0x4C
107
108 #define CDNS_MCP_SLAVE_STAT 0x50
109 #define CDNS_MCP_SLAVE_STAT_MASK GENMASK(1, 0)
110
111 #define CDNS_MCP_SLAVE_INTSTAT0 0x54
112 #define CDNS_MCP_SLAVE_INTSTAT1 0x58
113 #define CDNS_MCP_SLAVE_INTSTAT_NPRESENT BIT(0)
114 #define CDNS_MCP_SLAVE_INTSTAT_ATTACHED BIT(1)
115 #define CDNS_MCP_SLAVE_INTSTAT_ALERT BIT(2)
116 #define CDNS_MCP_SLAVE_INTSTAT_RESERVED BIT(3)
117 #define CDNS_MCP_SLAVE_STATUS_BITS GENMASK(3, 0)
118 #define CDNS_MCP_SLAVE_STATUS_NUM 4
119
120 #define CDNS_MCP_SLAVE_INTMASK0 0x5C
121 #define CDNS_MCP_SLAVE_INTMASK1 0x60
122
123 #define CDNS_MCP_SLAVE_INTMASK0_MASK GENMASK(31, 0)
124 #define CDNS_MCP_SLAVE_INTMASK1_MASK GENMASK(15, 0)
125
126 #define CDNS_MCP_PORT_INTSTAT 0x64
127 #define CDNS_MCP_PDI_STAT 0x6C
128
129 #define CDNS_MCP_FIFOLEVEL 0x78
130 #define CDNS_MCP_FIFOSTAT 0x7C
131 #define CDNS_MCP_RX_FIFO_AVAIL GENMASK(5, 0)
132
133 #define CDNS_IP_MCP_CMD_BASE 0x80 /* IP offset added at run-time */
134 #define CDNS_IP_MCP_RESP_BASE 0x80 /* IP offset added at run-time */
135 /* FIFO can hold 8 commands */
136 #define CDNS_MCP_CMD_LEN 8
137 #define CDNS_MCP_CMD_WORD_LEN 0x4
138
139 #define CDNS_MCP_CMD_SSP_TAG BIT(31)
140 #define CDNS_MCP_CMD_COMMAND GENMASK(30, 28)
141 #define CDNS_MCP_CMD_DEV_ADDR GENMASK(27, 24)
142 #define CDNS_MCP_CMD_REG_ADDR GENMASK(23, 8)
143 #define CDNS_MCP_CMD_REG_DATA GENMASK(7, 0)
144
145 #define CDNS_MCP_CMD_READ 2
146 #define CDNS_MCP_CMD_WRITE 3
147
148 #define CDNS_MCP_RESP_RDATA GENMASK(15, 8)
149 #define CDNS_MCP_RESP_ACK BIT(0)
150 #define CDNS_MCP_RESP_NACK BIT(1)
151
152 #define CDNS_DP_SIZE 128
153
154 #define CDNS_DPN_B0_CONFIG(n) (0x100 + CDNS_DP_SIZE * (n))
155 #define CDNS_DPN_B0_CH_EN(n) (0x104 + CDNS_DP_SIZE * (n))
156 #define CDNS_DPN_B0_SAMPLE_CTRL(n) (0x108 + CDNS_DP_SIZE * (n))
157 #define CDNS_DPN_B0_OFFSET_CTRL(n) (0x10C + CDNS_DP_SIZE * (n))
158 #define CDNS_DPN_B0_HCTRL(n) (0x110 + CDNS_DP_SIZE * (n))
159 #define CDNS_DPN_B0_ASYNC_CTRL(n) (0x114 + CDNS_DP_SIZE * (n))
160
161 #define CDNS_DPN_B1_CONFIG(n) (0x118 + CDNS_DP_SIZE * (n))
162 #define CDNS_DPN_B1_CH_EN(n) (0x11C + CDNS_DP_SIZE * (n))
163 #define CDNS_DPN_B1_SAMPLE_CTRL(n) (0x120 + CDNS_DP_SIZE * (n))
164 #define CDNS_DPN_B1_OFFSET_CTRL(n) (0x124 + CDNS_DP_SIZE * (n))
165 #define CDNS_DPN_B1_HCTRL(n) (0x128 + CDNS_DP_SIZE * (n))
166 #define CDNS_DPN_B1_ASYNC_CTRL(n) (0x12C + CDNS_DP_SIZE * (n))
167
168 #define CDNS_DPN_CONFIG_BPM BIT(18)
169 #define CDNS_DPN_CONFIG_BGC GENMASK(17, 16)
170 #define CDNS_DPN_CONFIG_WL GENMASK(12, 8)
171 #define CDNS_DPN_CONFIG_PORT_DAT GENMASK(3, 2)
172 #define CDNS_DPN_CONFIG_PORT_FLOW GENMASK(1, 0)
173
174 #define CDNS_DPN_SAMPLE_CTRL_SI GENMASK(15, 0)
175
176 #define CDNS_DPN_OFFSET_CTRL_1 GENMASK(7, 0)
177 #define CDNS_DPN_OFFSET_CTRL_2 GENMASK(15, 8)
178
179 #define CDNS_DPN_HCTRL_HSTOP GENMASK(3, 0)
180 #define CDNS_DPN_HCTRL_HSTART GENMASK(7, 4)
181 #define CDNS_DPN_HCTRL_LCTRL GENMASK(10, 8)
182
183 #define CDNS_PORTCTRL 0x130
184 #define CDNS_PORTCTRL_TEST_FAILED BIT(1)
185 #define CDNS_PORTCTRL_DIRN BIT(7)
186 #define CDNS_PORTCTRL_BANK_INVERT BIT(8)
187 #define CDNS_PORTCTRL_BULK_ENABLE BIT(16)
188
189 #define CDNS_PORT_OFFSET 0x80
190
191 #define CDNS_PDI_CONFIG(n) (0x1100 + (n) * 16)
192
193 #define CDNS_PDI_CONFIG_SOFT_RESET BIT(24)
194 #define CDNS_PDI_CONFIG_CHANNEL GENMASK(15, 8)
195 #define CDNS_PDI_CONFIG_PORT GENMASK(4, 0)
196
197 /* Driver defaults */
198 #define CDNS_TX_TIMEOUT 500
199
200 #define CDNS_SCP_RX_FIFOLEVEL 0x2
201
202 /*
203 * register accessor helpers
204 */
cdns_readl(struct sdw_cdns * cdns,int offset)205 static inline u32 cdns_readl(struct sdw_cdns *cdns, int offset)
206 {
207 return readl(cdns->registers + offset);
208 }
209
cdns_writel(struct sdw_cdns * cdns,int offset,u32 value)210 static inline void cdns_writel(struct sdw_cdns *cdns, int offset, u32 value)
211 {
212 writel(value, cdns->registers + offset);
213 }
214
cdns_ip_readl(struct sdw_cdns * cdns,int offset)215 static inline u32 cdns_ip_readl(struct sdw_cdns *cdns, int offset)
216 {
217 return cdns_readl(cdns, cdns->ip_offset + offset);
218 }
219
cdns_ip_writel(struct sdw_cdns * cdns,int offset,u32 value)220 static inline void cdns_ip_writel(struct sdw_cdns *cdns, int offset, u32 value)
221 {
222 return cdns_writel(cdns, cdns->ip_offset + offset, value);
223 }
224
cdns_updatel(struct sdw_cdns * cdns,int offset,u32 mask,u32 val)225 static inline void cdns_updatel(struct sdw_cdns *cdns,
226 int offset, u32 mask, u32 val)
227 {
228 u32 tmp;
229
230 tmp = cdns_readl(cdns, offset);
231 tmp = (tmp & ~mask) | val;
232 cdns_writel(cdns, offset, tmp);
233 }
234
cdns_ip_updatel(struct sdw_cdns * cdns,int offset,u32 mask,u32 val)235 static inline void cdns_ip_updatel(struct sdw_cdns *cdns,
236 int offset, u32 mask, u32 val)
237 {
238 cdns_updatel(cdns, cdns->ip_offset + offset, mask, val);
239 }
240
cdns_set_wait(struct sdw_cdns * cdns,int offset,u32 mask,u32 value)241 static int cdns_set_wait(struct sdw_cdns *cdns, int offset, u32 mask, u32 value)
242 {
243 int timeout = 10;
244 u32 reg_read;
245
246 /* Wait for bit to be set */
247 do {
248 reg_read = readl(cdns->registers + offset);
249 if ((reg_read & mask) == value)
250 return 0;
251
252 timeout--;
253 usleep_range(50, 100);
254 } while (timeout != 0);
255
256 return -ETIMEDOUT;
257 }
258
cdns_clear_bit(struct sdw_cdns * cdns,int offset,u32 value)259 static int cdns_clear_bit(struct sdw_cdns *cdns, int offset, u32 value)
260 {
261 writel(value, cdns->registers + offset);
262
263 /* Wait for bit to be self cleared */
264 return cdns_set_wait(cdns, offset, value, 0);
265 }
266
267 /*
268 * all changes to the MCP_CONFIG, MCP_CONTROL, MCP_CMDCTRL and MCP_PHYCTRL
269 * need to be confirmed with a write to MCP_CONFIG_UPDATE
270 */
cdns_config_update(struct sdw_cdns * cdns)271 static int cdns_config_update(struct sdw_cdns *cdns)
272 {
273 int ret;
274
275 if (sdw_cdns_is_clock_stop(cdns)) {
276 dev_err(cdns->dev, "Cannot program MCP_CONFIG_UPDATE in ClockStopMode\n");
277 return -EINVAL;
278 }
279
280 ret = cdns_clear_bit(cdns, CDNS_MCP_CONFIG_UPDATE,
281 CDNS_MCP_CONFIG_UPDATE_BIT);
282 if (ret < 0)
283 dev_err(cdns->dev, "Config update timedout\n");
284
285 return ret;
286 }
287
288 /**
289 * sdw_cdns_config_update() - Update configurations
290 * @cdns: Cadence instance
291 */
sdw_cdns_config_update(struct sdw_cdns * cdns)292 void sdw_cdns_config_update(struct sdw_cdns *cdns)
293 {
294 /* commit changes */
295 cdns_writel(cdns, CDNS_MCP_CONFIG_UPDATE, CDNS_MCP_CONFIG_UPDATE_BIT);
296 }
297 EXPORT_SYMBOL(sdw_cdns_config_update);
298
299 /**
300 * sdw_cdns_config_update_set_wait() - wait until configuration update bit is self-cleared
301 * @cdns: Cadence instance
302 */
sdw_cdns_config_update_set_wait(struct sdw_cdns * cdns)303 int sdw_cdns_config_update_set_wait(struct sdw_cdns *cdns)
304 {
305 /* the hardware recommendation is to wait at least 300us */
306 return cdns_set_wait(cdns, CDNS_MCP_CONFIG_UPDATE,
307 CDNS_MCP_CONFIG_UPDATE_BIT, 0);
308 }
309 EXPORT_SYMBOL(sdw_cdns_config_update_set_wait);
310
311 /*
312 * debugfs
313 */
314 #ifdef CONFIG_DEBUG_FS
315
316 #define RD_BUF (2 * PAGE_SIZE)
317
cdns_sprintf(struct sdw_cdns * cdns,char * buf,size_t pos,unsigned int reg)318 static ssize_t cdns_sprintf(struct sdw_cdns *cdns,
319 char *buf, size_t pos, unsigned int reg)
320 {
321 return scnprintf(buf + pos, RD_BUF - pos,
322 "%4x\t%8x\n", reg, cdns_readl(cdns, reg));
323 }
324
cdns_reg_show(struct seq_file * s,void * data)325 static int cdns_reg_show(struct seq_file *s, void *data)
326 {
327 struct sdw_cdns *cdns = s->private;
328 ssize_t ret;
329 int num_ports;
330 int i, j;
331
332 char *buf __free(kfree) = kzalloc(RD_BUF, GFP_KERNEL);
333 if (!buf)
334 return -ENOMEM;
335
336 ret = scnprintf(buf, RD_BUF, "Register Value\n");
337 ret += scnprintf(buf + ret, RD_BUF - ret, "\nMCP Registers\n");
338 /* 8 MCP registers */
339 for (i = CDNS_MCP_CONFIG; i <= CDNS_MCP_PHYCTRL; i += sizeof(u32))
340 ret += cdns_sprintf(cdns, buf, ret, i);
341
342 ret += scnprintf(buf + ret, RD_BUF - ret,
343 "\nStatus & Intr Registers\n");
344 /* 13 Status & Intr registers (offsets 0x70 and 0x74 not defined) */
345 for (i = CDNS_MCP_STAT; i <= CDNS_MCP_FIFOSTAT; i += sizeof(u32))
346 ret += cdns_sprintf(cdns, buf, ret, i);
347
348 ret += scnprintf(buf + ret, RD_BUF - ret,
349 "\nSSP & Clk ctrl Registers\n");
350 ret += cdns_sprintf(cdns, buf, ret, CDNS_MCP_SSP_CTRL0);
351 ret += cdns_sprintf(cdns, buf, ret, CDNS_MCP_SSP_CTRL1);
352 ret += cdns_sprintf(cdns, buf, ret, CDNS_MCP_CLK_CTRL0);
353 ret += cdns_sprintf(cdns, buf, ret, CDNS_MCP_CLK_CTRL1);
354
355 ret += scnprintf(buf + ret, RD_BUF - ret,
356 "\nDPn B0 Registers\n");
357
358 num_ports = cdns->num_ports;
359
360 for (i = 0; i < num_ports; i++) {
361 ret += scnprintf(buf + ret, RD_BUF - ret,
362 "\nDP-%d\n", i);
363 for (j = CDNS_DPN_B0_CONFIG(i);
364 j < CDNS_DPN_B0_ASYNC_CTRL(i); j += sizeof(u32))
365 ret += cdns_sprintf(cdns, buf, ret, j);
366 }
367
368 ret += scnprintf(buf + ret, RD_BUF - ret,
369 "\nDPn B1 Registers\n");
370 for (i = 0; i < num_ports; i++) {
371 ret += scnprintf(buf + ret, RD_BUF - ret,
372 "\nDP-%d\n", i);
373
374 for (j = CDNS_DPN_B1_CONFIG(i);
375 j < CDNS_DPN_B1_ASYNC_CTRL(i); j += sizeof(u32))
376 ret += cdns_sprintf(cdns, buf, ret, j);
377 }
378
379 ret += scnprintf(buf + ret, RD_BUF - ret,
380 "\nDPn Control Registers\n");
381 for (i = 0; i < num_ports; i++)
382 ret += cdns_sprintf(cdns, buf, ret,
383 CDNS_PORTCTRL + i * CDNS_PORT_OFFSET);
384
385 ret += scnprintf(buf + ret, RD_BUF - ret,
386 "\nPDIn Config Registers\n");
387
388 /* number of PDI and ports is interchangeable */
389 for (i = 0; i < num_ports; i++)
390 ret += cdns_sprintf(cdns, buf, ret, CDNS_PDI_CONFIG(i));
391
392 seq_printf(s, "%s", buf);
393
394 return 0;
395 }
396 DEFINE_SHOW_ATTRIBUTE(cdns_reg);
397
cdns_hw_reset(void * data,u64 value)398 static int cdns_hw_reset(void *data, u64 value)
399 {
400 struct sdw_cdns *cdns = data;
401 int ret;
402
403 if (value != 1)
404 return -EINVAL;
405
406 /* Userspace changed the hardware state behind the kernel's back */
407 add_taint(TAINT_USER, LOCKDEP_STILL_OK);
408
409 ret = sdw_cdns_exit_reset(cdns);
410
411 dev_dbg(cdns->dev, "link hw_reset done: %d\n", ret);
412
413 return ret;
414 }
415
416 DEFINE_DEBUGFS_ATTRIBUTE(cdns_hw_reset_fops, NULL, cdns_hw_reset, "%llu\n");
417
cdns_parity_error_injection(void * data,u64 value)418 static int cdns_parity_error_injection(void *data, u64 value)
419 {
420 struct sdw_cdns *cdns = data;
421 struct sdw_bus *bus;
422 int ret;
423
424 if (value != 1)
425 return -EINVAL;
426
427 bus = &cdns->bus;
428
429 /*
430 * Resume Master device. If this results in a bus reset, the
431 * Slave devices will re-attach and be re-enumerated.
432 */
433 ret = pm_runtime_resume_and_get(bus->dev);
434 if (ret < 0 && ret != -EACCES) {
435 dev_err_ratelimited(cdns->dev,
436 "pm_runtime_resume_and_get failed in %s, ret %d\n",
437 __func__, ret);
438 return ret;
439 }
440
441 /*
442 * wait long enough for Slave(s) to be in steady state. This
443 * does not need to be super precise.
444 */
445 msleep(200);
446
447 /*
448 * Take the bus lock here to make sure that any bus transactions
449 * will be queued while we inject a parity error on a dummy read
450 */
451 mutex_lock(&bus->bus_lock);
452
453 /* program hardware to inject parity error */
454 cdns_ip_updatel(cdns, CDNS_IP_MCP_CMDCTRL,
455 CDNS_IP_MCP_CMDCTRL_INSERT_PARITY_ERR,
456 CDNS_IP_MCP_CMDCTRL_INSERT_PARITY_ERR);
457
458 /* commit changes */
459 ret = cdns_clear_bit(cdns, CDNS_MCP_CONFIG_UPDATE, CDNS_MCP_CONFIG_UPDATE_BIT);
460 if (ret < 0)
461 goto unlock;
462
463 /* do a broadcast dummy read to avoid bus clashes */
464 ret = sdw_bread_no_pm_unlocked(&cdns->bus, 0xf, SDW_SCP_DEVID_0);
465 dev_info(cdns->dev, "parity error injection, read: %d\n", ret);
466
467 /* program hardware to disable parity error */
468 cdns_ip_updatel(cdns, CDNS_IP_MCP_CMDCTRL,
469 CDNS_IP_MCP_CMDCTRL_INSERT_PARITY_ERR,
470 0);
471
472 /* commit changes */
473 ret = cdns_clear_bit(cdns, CDNS_MCP_CONFIG_UPDATE, CDNS_MCP_CONFIG_UPDATE_BIT);
474 if (ret < 0)
475 goto unlock;
476
477 /* Userspace changed the hardware state behind the kernel's back */
478 add_taint(TAINT_USER, LOCKDEP_STILL_OK);
479
480 unlock:
481 /* Continue bus operation with parity error injection disabled */
482 mutex_unlock(&bus->bus_lock);
483
484 /*
485 * allow Master device to enter pm_runtime suspend. This may
486 * also result in Slave devices suspending.
487 */
488 pm_runtime_mark_last_busy(bus->dev);
489 pm_runtime_put_autosuspend(bus->dev);
490
491 return 0;
492 }
493
494 DEFINE_DEBUGFS_ATTRIBUTE(cdns_parity_error_fops, NULL,
495 cdns_parity_error_injection, "%llu\n");
496
cdns_set_pdi_loopback_source(void * data,u64 value)497 static int cdns_set_pdi_loopback_source(void *data, u64 value)
498 {
499 struct sdw_cdns *cdns = data;
500 unsigned int pdi_out_num = cdns->pcm.num_bd + cdns->pcm.num_out;
501
502 if (value > pdi_out_num)
503 return -EINVAL;
504
505 /* Userspace changed the hardware state behind the kernel's back */
506 add_taint(TAINT_USER, LOCKDEP_STILL_OK);
507
508 cdns->pdi_loopback_source = value;
509
510 return 0;
511 }
512 DEFINE_DEBUGFS_ATTRIBUTE(cdns_pdi_loopback_source_fops, NULL, cdns_set_pdi_loopback_source, "%llu\n");
513
cdns_set_pdi_loopback_target(void * data,u64 value)514 static int cdns_set_pdi_loopback_target(void *data, u64 value)
515 {
516 struct sdw_cdns *cdns = data;
517 unsigned int pdi_in_num = cdns->pcm.num_bd + cdns->pcm.num_in;
518
519 if (value > pdi_in_num)
520 return -EINVAL;
521
522 /* Userspace changed the hardware state behind the kernel's back */
523 add_taint(TAINT_USER, LOCKDEP_STILL_OK);
524
525 cdns->pdi_loopback_target = value;
526
527 return 0;
528 }
529 DEFINE_DEBUGFS_ATTRIBUTE(cdns_pdi_loopback_target_fops, NULL, cdns_set_pdi_loopback_target, "%llu\n");
530
531 /**
532 * sdw_cdns_debugfs_init() - Cadence debugfs init
533 * @cdns: Cadence instance
534 * @root: debugfs root
535 */
sdw_cdns_debugfs_init(struct sdw_cdns * cdns,struct dentry * root)536 void sdw_cdns_debugfs_init(struct sdw_cdns *cdns, struct dentry *root)
537 {
538 debugfs_create_file("cdns-registers", 0400, root, cdns, &cdns_reg_fops);
539
540 debugfs_create_file("cdns-hw-reset", 0200, root, cdns,
541 &cdns_hw_reset_fops);
542
543 debugfs_create_file("cdns-parity-error-injection", 0200, root, cdns,
544 &cdns_parity_error_fops);
545
546 cdns->pdi_loopback_source = -1;
547 cdns->pdi_loopback_target = -1;
548
549 debugfs_create_file("cdns-pdi-loopback-source", 0200, root, cdns,
550 &cdns_pdi_loopback_source_fops);
551
552 debugfs_create_file("cdns-pdi-loopback-target", 0200, root, cdns,
553 &cdns_pdi_loopback_target_fops);
554
555 }
556 EXPORT_SYMBOL_GPL(sdw_cdns_debugfs_init);
557
558 #endif /* CONFIG_DEBUG_FS */
559
560 /*
561 * IO Calls
562 */
563 static enum sdw_command_response
cdns_fill_msg_resp(struct sdw_cdns * cdns,struct sdw_msg * msg,int count,int offset)564 cdns_fill_msg_resp(struct sdw_cdns *cdns,
565 struct sdw_msg *msg, int count, int offset)
566 {
567 int nack = 0, no_ack = 0;
568 int i;
569
570 /* check message response */
571 for (i = 0; i < count; i++) {
572 if (!(cdns->response_buf[i] & CDNS_MCP_RESP_ACK)) {
573 no_ack = 1;
574 dev_vdbg(cdns->dev, "Msg Ack not received, cmd %d\n", i);
575 }
576 if (cdns->response_buf[i] & CDNS_MCP_RESP_NACK) {
577 nack = 1;
578 dev_err_ratelimited(cdns->dev, "Msg NACK received, cmd %d\n", i);
579 }
580 }
581
582 if (nack) {
583 dev_err_ratelimited(cdns->dev, "Msg NACKed for Slave %d\n", msg->dev_num);
584 return SDW_CMD_FAIL;
585 }
586
587 if (no_ack) {
588 dev_dbg_ratelimited(cdns->dev, "Msg ignored for Slave %d\n", msg->dev_num);
589 return SDW_CMD_IGNORED;
590 }
591
592 if (msg->flags == SDW_MSG_FLAG_READ) {
593 /* fill response */
594 for (i = 0; i < count; i++)
595 msg->buf[i + offset] = FIELD_GET(CDNS_MCP_RESP_RDATA,
596 cdns->response_buf[i]);
597 }
598
599 return SDW_CMD_OK;
600 }
601
cdns_read_response(struct sdw_cdns * cdns)602 static void cdns_read_response(struct sdw_cdns *cdns)
603 {
604 u32 num_resp, cmd_base;
605 int i;
606
607 /* RX_FIFO_AVAIL can be 2 entries more than the FIFO size */
608 BUILD_BUG_ON(ARRAY_SIZE(cdns->response_buf) < CDNS_MCP_CMD_LEN + 2);
609
610 num_resp = cdns_readl(cdns, CDNS_MCP_FIFOSTAT);
611 num_resp &= CDNS_MCP_RX_FIFO_AVAIL;
612 if (num_resp > ARRAY_SIZE(cdns->response_buf)) {
613 dev_warn(cdns->dev, "RX AVAIL %d too long\n", num_resp);
614 num_resp = ARRAY_SIZE(cdns->response_buf);
615 }
616
617 cmd_base = CDNS_IP_MCP_CMD_BASE;
618
619 for (i = 0; i < num_resp; i++) {
620 cdns->response_buf[i] = cdns_ip_readl(cdns, cmd_base);
621 cmd_base += CDNS_MCP_CMD_WORD_LEN;
622 }
623 }
624
625 static enum sdw_command_response
_cdns_xfer_msg(struct sdw_cdns * cdns,struct sdw_msg * msg,int cmd,int offset,int count,bool defer)626 _cdns_xfer_msg(struct sdw_cdns *cdns, struct sdw_msg *msg, int cmd,
627 int offset, int count, bool defer)
628 {
629 unsigned long time;
630 u32 base, i, data;
631 u16 addr;
632
633 /* Program the watermark level for RX FIFO */
634 if (cdns->msg_count != count) {
635 cdns_writel(cdns, CDNS_MCP_FIFOLEVEL, count);
636 cdns->msg_count = count;
637 }
638
639 base = CDNS_IP_MCP_CMD_BASE;
640 addr = msg->addr + offset;
641
642 for (i = 0; i < count; i++) {
643 data = FIELD_PREP(CDNS_MCP_CMD_DEV_ADDR, msg->dev_num);
644 data |= FIELD_PREP(CDNS_MCP_CMD_COMMAND, cmd);
645 data |= FIELD_PREP(CDNS_MCP_CMD_REG_ADDR, addr);
646 addr++;
647
648 if (msg->flags == SDW_MSG_FLAG_WRITE)
649 data |= msg->buf[i + offset];
650
651 data |= FIELD_PREP(CDNS_MCP_CMD_SSP_TAG, msg->ssp_sync);
652 cdns_ip_writel(cdns, base, data);
653 base += CDNS_MCP_CMD_WORD_LEN;
654 }
655
656 if (defer)
657 return SDW_CMD_OK;
658
659 /* wait for timeout or response */
660 time = wait_for_completion_timeout(&cdns->tx_complete,
661 msecs_to_jiffies(CDNS_TX_TIMEOUT));
662 if (!time) {
663 dev_err(cdns->dev, "IO transfer timed out, cmd %d device %d addr %x len %d\n",
664 cmd, msg->dev_num, msg->addr, msg->len);
665 msg->len = 0;
666
667 /* Drain anything in the RX_FIFO */
668 cdns_read_response(cdns);
669
670 return SDW_CMD_TIMEOUT;
671 }
672
673 return cdns_fill_msg_resp(cdns, msg, count, offset);
674 }
675
676 static enum sdw_command_response
cdns_program_scp_addr(struct sdw_cdns * cdns,struct sdw_msg * msg)677 cdns_program_scp_addr(struct sdw_cdns *cdns, struct sdw_msg *msg)
678 {
679 int nack = 0, no_ack = 0;
680 unsigned long time;
681 u32 data[2], base;
682 int i;
683
684 /* Program the watermark level for RX FIFO */
685 if (cdns->msg_count != CDNS_SCP_RX_FIFOLEVEL) {
686 cdns_writel(cdns, CDNS_MCP_FIFOLEVEL, CDNS_SCP_RX_FIFOLEVEL);
687 cdns->msg_count = CDNS_SCP_RX_FIFOLEVEL;
688 }
689
690 data[0] = FIELD_PREP(CDNS_MCP_CMD_DEV_ADDR, msg->dev_num);
691 data[0] |= FIELD_PREP(CDNS_MCP_CMD_COMMAND, 0x3);
692 data[1] = data[0];
693
694 data[0] |= FIELD_PREP(CDNS_MCP_CMD_REG_ADDR, SDW_SCP_ADDRPAGE1);
695 data[1] |= FIELD_PREP(CDNS_MCP_CMD_REG_ADDR, SDW_SCP_ADDRPAGE2);
696
697 data[0] |= msg->addr_page1;
698 data[1] |= msg->addr_page2;
699
700 base = CDNS_IP_MCP_CMD_BASE;
701 cdns_ip_writel(cdns, base, data[0]);
702 base += CDNS_MCP_CMD_WORD_LEN;
703 cdns_ip_writel(cdns, base, data[1]);
704
705 time = wait_for_completion_timeout(&cdns->tx_complete,
706 msecs_to_jiffies(CDNS_TX_TIMEOUT));
707 if (!time) {
708 dev_err(cdns->dev, "SCP Msg trf timed out\n");
709 msg->len = 0;
710 return SDW_CMD_TIMEOUT;
711 }
712
713 /* check response the writes */
714 for (i = 0; i < 2; i++) {
715 if (!(cdns->response_buf[i] & CDNS_MCP_RESP_ACK)) {
716 no_ack = 1;
717 dev_err(cdns->dev, "Program SCP Ack not received\n");
718 if (cdns->response_buf[i] & CDNS_MCP_RESP_NACK) {
719 nack = 1;
720 dev_err(cdns->dev, "Program SCP NACK received\n");
721 }
722 }
723 }
724
725 /* For NACK, NO ack, don't return err if we are in Broadcast mode */
726 if (nack) {
727 dev_err_ratelimited(cdns->dev,
728 "SCP_addrpage NACKed for Slave %d\n", msg->dev_num);
729 return SDW_CMD_FAIL;
730 }
731
732 if (no_ack) {
733 dev_dbg_ratelimited(cdns->dev,
734 "SCP_addrpage ignored for Slave %d\n", msg->dev_num);
735 return SDW_CMD_IGNORED;
736 }
737
738 return SDW_CMD_OK;
739 }
740
cdns_prep_msg(struct sdw_cdns * cdns,struct sdw_msg * msg,int * cmd)741 static int cdns_prep_msg(struct sdw_cdns *cdns, struct sdw_msg *msg, int *cmd)
742 {
743 int ret;
744
745 if (msg->page) {
746 ret = cdns_program_scp_addr(cdns, msg);
747 if (ret) {
748 msg->len = 0;
749 return ret;
750 }
751 }
752
753 switch (msg->flags) {
754 case SDW_MSG_FLAG_READ:
755 *cmd = CDNS_MCP_CMD_READ;
756 break;
757
758 case SDW_MSG_FLAG_WRITE:
759 *cmd = CDNS_MCP_CMD_WRITE;
760 break;
761
762 default:
763 dev_err(cdns->dev, "Invalid msg cmd: %d\n", msg->flags);
764 return -EINVAL;
765 }
766
767 return 0;
768 }
769
770 enum sdw_command_response
cdns_xfer_msg(struct sdw_bus * bus,struct sdw_msg * msg)771 cdns_xfer_msg(struct sdw_bus *bus, struct sdw_msg *msg)
772 {
773 struct sdw_cdns *cdns = bus_to_cdns(bus);
774 int cmd = 0, ret, i;
775
776 ret = cdns_prep_msg(cdns, msg, &cmd);
777 if (ret)
778 return SDW_CMD_FAIL_OTHER;
779
780 for (i = 0; i < msg->len / CDNS_MCP_CMD_LEN; i++) {
781 ret = _cdns_xfer_msg(cdns, msg, cmd, i * CDNS_MCP_CMD_LEN,
782 CDNS_MCP_CMD_LEN, false);
783 if (ret != SDW_CMD_OK)
784 return ret;
785 }
786
787 if (!(msg->len % CDNS_MCP_CMD_LEN))
788 return SDW_CMD_OK;
789
790 return _cdns_xfer_msg(cdns, msg, cmd, i * CDNS_MCP_CMD_LEN,
791 msg->len % CDNS_MCP_CMD_LEN, false);
792 }
793 EXPORT_SYMBOL(cdns_xfer_msg);
794
795 enum sdw_command_response
cdns_xfer_msg_defer(struct sdw_bus * bus)796 cdns_xfer_msg_defer(struct sdw_bus *bus)
797 {
798 struct sdw_cdns *cdns = bus_to_cdns(bus);
799 struct sdw_defer *defer = &bus->defer_msg;
800 struct sdw_msg *msg = defer->msg;
801 int cmd = 0, ret;
802
803 /* for defer only 1 message is supported */
804 if (msg->len > 1)
805 return -ENOTSUPP;
806
807 ret = cdns_prep_msg(cdns, msg, &cmd);
808 if (ret)
809 return SDW_CMD_FAIL_OTHER;
810
811 return _cdns_xfer_msg(cdns, msg, cmd, 0, msg->len, true);
812 }
813 EXPORT_SYMBOL(cdns_xfer_msg_defer);
814
cdns_read_ping_status(struct sdw_bus * bus)815 u32 cdns_read_ping_status(struct sdw_bus *bus)
816 {
817 struct sdw_cdns *cdns = bus_to_cdns(bus);
818
819 return cdns_readl(cdns, CDNS_MCP_SLAVE_STAT);
820 }
821 EXPORT_SYMBOL(cdns_read_ping_status);
822
823 /*
824 * IRQ handling
825 */
826
cdns_update_slave_status(struct sdw_cdns * cdns,u64 slave_intstat)827 static int cdns_update_slave_status(struct sdw_cdns *cdns,
828 u64 slave_intstat)
829 {
830 enum sdw_slave_status status[SDW_MAX_DEVICES + 1];
831 bool is_slave = false;
832 u32 mask;
833 u32 val;
834 int i, set_status;
835
836 memset(status, 0, sizeof(status));
837
838 for (i = 0; i <= SDW_MAX_DEVICES; i++) {
839 mask = (slave_intstat >> (i * CDNS_MCP_SLAVE_STATUS_NUM)) &
840 CDNS_MCP_SLAVE_STATUS_BITS;
841
842 set_status = 0;
843
844 if (mask) {
845 is_slave = true;
846
847 if (mask & CDNS_MCP_SLAVE_INTSTAT_RESERVED) {
848 status[i] = SDW_SLAVE_RESERVED;
849 set_status++;
850 }
851
852 if (mask & CDNS_MCP_SLAVE_INTSTAT_ATTACHED) {
853 status[i] = SDW_SLAVE_ATTACHED;
854 set_status++;
855 }
856
857 if (mask & CDNS_MCP_SLAVE_INTSTAT_ALERT) {
858 status[i] = SDW_SLAVE_ALERT;
859 set_status++;
860 }
861
862 if (mask & CDNS_MCP_SLAVE_INTSTAT_NPRESENT) {
863 status[i] = SDW_SLAVE_UNATTACHED;
864 set_status++;
865 }
866 }
867
868 /*
869 * check that there was a single reported Slave status and when
870 * there is not use the latest status extracted from PING commands
871 */
872 if (set_status != 1) {
873 val = cdns_readl(cdns, CDNS_MCP_SLAVE_STAT);
874 val >>= (i * 2);
875
876 switch (val & 0x3) {
877 case 0:
878 status[i] = SDW_SLAVE_UNATTACHED;
879 break;
880 case 1:
881 status[i] = SDW_SLAVE_ATTACHED;
882 break;
883 case 2:
884 status[i] = SDW_SLAVE_ALERT;
885 break;
886 case 3:
887 default:
888 status[i] = SDW_SLAVE_RESERVED;
889 break;
890 }
891 }
892 }
893
894 if (is_slave) {
895 int ret;
896
897 mutex_lock(&cdns->status_update_lock);
898 ret = sdw_handle_slave_status(&cdns->bus, status);
899 mutex_unlock(&cdns->status_update_lock);
900 return ret;
901 }
902
903 return 0;
904 }
905
906 /**
907 * sdw_cdns_irq() - Cadence interrupt handler
908 * @irq: irq number
909 * @dev_id: irq context
910 */
sdw_cdns_irq(int irq,void * dev_id)911 irqreturn_t sdw_cdns_irq(int irq, void *dev_id)
912 {
913 struct sdw_cdns *cdns = dev_id;
914 u32 int_status;
915
916 /* Check if the link is up */
917 if (!cdns->link_up)
918 return IRQ_NONE;
919
920 int_status = cdns_readl(cdns, CDNS_MCP_INTSTAT);
921
922 /* check for reserved values read as zero */
923 if (int_status & CDNS_MCP_INT_RESERVED)
924 return IRQ_NONE;
925
926 if (!(int_status & CDNS_MCP_INT_IRQ))
927 return IRQ_NONE;
928
929 if (int_status & CDNS_MCP_INT_RX_WL) {
930 struct sdw_bus *bus = &cdns->bus;
931 struct sdw_defer *defer = &bus->defer_msg;
932
933 cdns_read_response(cdns);
934
935 /*
936 * Clear interrupt before signalling the completion to avoid
937 * a race between this thread and the main thread starting
938 * another TX.
939 */
940 cdns_writel(cdns, CDNS_MCP_INTSTAT, CDNS_MCP_INT_RX_WL);
941 int_status &= ~CDNS_MCP_INT_RX_WL;
942
943 if (defer && defer->msg) {
944 cdns_fill_msg_resp(cdns, defer->msg,
945 defer->length, 0);
946 complete(&defer->complete);
947 } else {
948 complete(&cdns->tx_complete);
949 }
950 }
951
952 if (int_status & CDNS_MCP_INT_PARITY) {
953 /* Parity error detected by Master */
954 dev_err_ratelimited(cdns->dev, "Parity error\n");
955 }
956
957 if (int_status & CDNS_MCP_INT_CTRL_CLASH) {
958 /* Slave is driving bit slot during control word */
959 dev_err_ratelimited(cdns->dev, "Bus clash for control word\n");
960 }
961
962 if (int_status & CDNS_MCP_INT_DATA_CLASH) {
963 /*
964 * Multiple slaves trying to drive bit slot, or issue with
965 * ownership of data bits or Slave gone bonkers
966 */
967 dev_err_ratelimited(cdns->dev, "Bus clash for data word\n");
968 }
969
970 if (cdns->bus.params.m_data_mode != SDW_PORT_DATA_MODE_NORMAL &&
971 int_status & CDNS_MCP_INT_DPINT) {
972 u32 port_intstat;
973
974 /* just log which ports report an error */
975 port_intstat = cdns_readl(cdns, CDNS_MCP_PORT_INTSTAT);
976 dev_err_ratelimited(cdns->dev, "DP interrupt: PortIntStat %8x\n",
977 port_intstat);
978
979 /* clear status w/ write1 */
980 cdns_writel(cdns, CDNS_MCP_PORT_INTSTAT, port_intstat);
981 }
982
983 if (int_status & CDNS_MCP_INT_SLAVE_MASK) {
984 /* Mask the Slave interrupt and wake thread */
985 cdns_updatel(cdns, CDNS_MCP_INTMASK,
986 CDNS_MCP_INT_SLAVE_MASK, 0);
987
988 int_status &= ~CDNS_MCP_INT_SLAVE_MASK;
989
990 /*
991 * Deal with possible race condition between interrupt
992 * handling and disabling interrupts on suspend.
993 *
994 * If the master is in the process of disabling
995 * interrupts, don't schedule a workqueue
996 */
997 if (cdns->interrupt_enabled)
998 schedule_work(&cdns->work);
999 }
1000
1001 cdns_writel(cdns, CDNS_MCP_INTSTAT, int_status);
1002 return IRQ_HANDLED;
1003 }
1004 EXPORT_SYMBOL(sdw_cdns_irq);
1005
cdns_check_attached_status_dwork(struct work_struct * work)1006 static void cdns_check_attached_status_dwork(struct work_struct *work)
1007 {
1008 struct sdw_cdns *cdns =
1009 container_of(work, struct sdw_cdns, attach_dwork.work);
1010 enum sdw_slave_status status[SDW_MAX_DEVICES + 1];
1011 u32 val;
1012 int ret;
1013 int i;
1014
1015 val = cdns_readl(cdns, CDNS_MCP_SLAVE_STAT);
1016
1017 for (i = 0; i <= SDW_MAX_DEVICES; i++) {
1018 status[i] = val & 0x3;
1019 if (status[i])
1020 dev_dbg(cdns->dev, "Peripheral %d status: %d\n", i, status[i]);
1021 val >>= 2;
1022 }
1023
1024 mutex_lock(&cdns->status_update_lock);
1025 ret = sdw_handle_slave_status(&cdns->bus, status);
1026 mutex_unlock(&cdns->status_update_lock);
1027 if (ret < 0)
1028 dev_err(cdns->dev, "%s: sdw_handle_slave_status failed: %d\n", __func__, ret);
1029 }
1030
1031 /**
1032 * cdns_update_slave_status_work - update slave status in a work since we will need to handle
1033 * other interrupts eg. CDNS_MCP_INT_RX_WL during the update slave
1034 * process.
1035 * @work: cdns worker thread
1036 */
cdns_update_slave_status_work(struct work_struct * work)1037 static void cdns_update_slave_status_work(struct work_struct *work)
1038 {
1039 struct sdw_cdns *cdns =
1040 container_of(work, struct sdw_cdns, work);
1041 u32 slave0, slave1;
1042 u64 slave_intstat;
1043 u32 device0_status;
1044 int retry_count = 0;
1045
1046 /*
1047 * Clear main interrupt first so we don't lose any assertions
1048 * that happen during this function.
1049 */
1050 cdns_writel(cdns, CDNS_MCP_INTSTAT, CDNS_MCP_INT_SLAVE_MASK);
1051
1052 slave0 = cdns_readl(cdns, CDNS_MCP_SLAVE_INTSTAT0);
1053 slave1 = cdns_readl(cdns, CDNS_MCP_SLAVE_INTSTAT1);
1054
1055 /*
1056 * Clear the bits before handling so we don't lose any
1057 * bits that re-assert.
1058 */
1059 cdns_writel(cdns, CDNS_MCP_SLAVE_INTSTAT0, slave0);
1060 cdns_writel(cdns, CDNS_MCP_SLAVE_INTSTAT1, slave1);
1061
1062 /* combine the two status */
1063 slave_intstat = ((u64)slave1 << 32) | slave0;
1064
1065 dev_dbg_ratelimited(cdns->dev, "Slave status change: 0x%llx\n", slave_intstat);
1066
1067 update_status:
1068 cdns_update_slave_status(cdns, slave_intstat);
1069
1070 /*
1071 * When there is more than one peripheral per link, it's
1072 * possible that a deviceB becomes attached after we deal with
1073 * the attachment of deviceA. Since the hardware does a
1074 * logical AND, the attachment of the second device does not
1075 * change the status seen by the driver.
1076 *
1077 * In that case, clearing the registers above would result in
1078 * the deviceB never being detected - until a change of status
1079 * is observed on the bus.
1080 *
1081 * To avoid this race condition, re-check if any device0 needs
1082 * attention with PING commands. There is no need to check for
1083 * ALERTS since they are not allowed until a non-zero
1084 * device_number is assigned.
1085 *
1086 * Do not clear the INTSTAT0/1. While looping to enumerate devices on
1087 * #0 there could be status changes on other devices - these must
1088 * be kept in the INTSTAT so they can be handled when all #0 devices
1089 * have been handled.
1090 */
1091
1092 device0_status = cdns_readl(cdns, CDNS_MCP_SLAVE_STAT);
1093 device0_status &= 3;
1094
1095 if (device0_status == SDW_SLAVE_ATTACHED) {
1096 if (retry_count++ < SDW_MAX_DEVICES) {
1097 dev_dbg_ratelimited(cdns->dev,
1098 "Device0 detected after clearing status, iteration %d\n",
1099 retry_count);
1100 slave_intstat = CDNS_MCP_SLAVE_INTSTAT_ATTACHED;
1101 goto update_status;
1102 } else {
1103 dev_err_ratelimited(cdns->dev,
1104 "Device0 detected after %d iterations\n",
1105 retry_count);
1106 }
1107 }
1108
1109 /* unmask Slave interrupt now */
1110 cdns_updatel(cdns, CDNS_MCP_INTMASK,
1111 CDNS_MCP_INT_SLAVE_MASK, CDNS_MCP_INT_SLAVE_MASK);
1112
1113 }
1114
1115 /* paranoia check to make sure self-cleared bits are indeed cleared */
sdw_cdns_check_self_clearing_bits(struct sdw_cdns * cdns,const char * string,bool initial_delay,int reset_iterations)1116 void sdw_cdns_check_self_clearing_bits(struct sdw_cdns *cdns, const char *string,
1117 bool initial_delay, int reset_iterations)
1118 {
1119 u32 ip_mcp_control;
1120 u32 mcp_control;
1121 u32 mcp_config_update;
1122 int i;
1123
1124 if (initial_delay)
1125 usleep_range(1000, 1500);
1126
1127 ip_mcp_control = cdns_ip_readl(cdns, CDNS_IP_MCP_CONTROL);
1128
1129 /* the following bits should be cleared immediately */
1130 if (ip_mcp_control & CDNS_IP_MCP_CONTROL_SW_RST)
1131 dev_err(cdns->dev, "%s failed: IP_MCP_CONTROL_SW_RST is not cleared\n", string);
1132
1133 mcp_control = cdns_readl(cdns, CDNS_MCP_CONTROL);
1134
1135 /* the following bits should be cleared immediately */
1136 if (mcp_control & CDNS_MCP_CONTROL_CMD_RST)
1137 dev_err(cdns->dev, "%s failed: MCP_CONTROL_CMD_RST is not cleared\n", string);
1138 if (mcp_control & CDNS_MCP_CONTROL_SOFT_RST)
1139 dev_err(cdns->dev, "%s failed: MCP_CONTROL_SOFT_RST is not cleared\n", string);
1140 if (mcp_control & CDNS_MCP_CONTROL_CLK_STOP_CLR)
1141 dev_err(cdns->dev, "%s failed: MCP_CONTROL_CLK_STOP_CLR is not cleared\n", string);
1142
1143 mcp_config_update = cdns_readl(cdns, CDNS_MCP_CONFIG_UPDATE);
1144 if (mcp_config_update & CDNS_MCP_CONFIG_UPDATE_BIT)
1145 dev_err(cdns->dev, "%s failed: MCP_CONFIG_UPDATE_BIT is not cleared\n", string);
1146
1147 i = 0;
1148 while (mcp_control & CDNS_MCP_CONTROL_HW_RST) {
1149 if (i == reset_iterations) {
1150 dev_err(cdns->dev, "%s failed: MCP_CONTROL_HW_RST is not cleared\n", string);
1151 break;
1152 }
1153
1154 dev_dbg(cdns->dev, "%s: MCP_CONTROL_HW_RST is not cleared at iteration %d\n", string, i);
1155 i++;
1156
1157 usleep_range(1000, 1500);
1158 mcp_control = cdns_readl(cdns, CDNS_MCP_CONTROL);
1159 }
1160
1161 }
1162 EXPORT_SYMBOL(sdw_cdns_check_self_clearing_bits);
1163
1164 /*
1165 * init routines
1166 */
1167
1168 /**
1169 * sdw_cdns_exit_reset() - Program reset parameters and start bus operations
1170 * @cdns: Cadence instance
1171 */
sdw_cdns_exit_reset(struct sdw_cdns * cdns)1172 int sdw_cdns_exit_reset(struct sdw_cdns *cdns)
1173 {
1174 /* keep reset delay unchanged to 4096 cycles */
1175
1176 /* use hardware generated reset */
1177 cdns_updatel(cdns, CDNS_MCP_CONTROL,
1178 CDNS_MCP_CONTROL_HW_RST,
1179 CDNS_MCP_CONTROL_HW_RST);
1180
1181 /* commit changes */
1182 return cdns_config_update(cdns);
1183 }
1184 EXPORT_SYMBOL(sdw_cdns_exit_reset);
1185
1186 /**
1187 * cdns_enable_slave_interrupts() - Enable SDW slave interrupts
1188 * @cdns: Cadence instance
1189 * @state: boolean for true/false
1190 */
cdns_enable_slave_interrupts(struct sdw_cdns * cdns,bool state)1191 static void cdns_enable_slave_interrupts(struct sdw_cdns *cdns, bool state)
1192 {
1193 u32 mask;
1194
1195 mask = cdns_readl(cdns, CDNS_MCP_INTMASK);
1196 if (state)
1197 mask |= CDNS_MCP_INT_SLAVE_MASK;
1198 else
1199 mask &= ~CDNS_MCP_INT_SLAVE_MASK;
1200
1201 cdns_writel(cdns, CDNS_MCP_INTMASK, mask);
1202 }
1203
1204 /**
1205 * sdw_cdns_enable_interrupt() - Enable SDW interrupts
1206 * @cdns: Cadence instance
1207 * @state: True if we are trying to enable interrupt.
1208 */
sdw_cdns_enable_interrupt(struct sdw_cdns * cdns,bool state)1209 int sdw_cdns_enable_interrupt(struct sdw_cdns *cdns, bool state)
1210 {
1211 u32 slave_intmask0 = 0;
1212 u32 slave_intmask1 = 0;
1213 u32 mask = 0;
1214
1215 if (!state)
1216 goto update_masks;
1217
1218 slave_intmask0 = CDNS_MCP_SLAVE_INTMASK0_MASK;
1219 slave_intmask1 = CDNS_MCP_SLAVE_INTMASK1_MASK;
1220
1221 /* enable detection of all slave state changes */
1222 mask = CDNS_MCP_INT_SLAVE_MASK;
1223
1224 /* enable detection of bus issues */
1225 mask |= CDNS_MCP_INT_CTRL_CLASH | CDNS_MCP_INT_DATA_CLASH |
1226 CDNS_MCP_INT_PARITY;
1227
1228 /* port interrupt limited to test modes for now */
1229 if (cdns->bus.params.m_data_mode != SDW_PORT_DATA_MODE_NORMAL)
1230 mask |= CDNS_MCP_INT_DPINT;
1231
1232 /* enable detection of RX fifo level */
1233 mask |= CDNS_MCP_INT_RX_WL;
1234
1235 /*
1236 * CDNS_MCP_INT_IRQ needs to be set otherwise all previous
1237 * settings are irrelevant
1238 */
1239 mask |= CDNS_MCP_INT_IRQ;
1240
1241 if (interrupt_mask) /* parameter override */
1242 mask = interrupt_mask;
1243
1244 update_masks:
1245 /* clear slave interrupt status before enabling interrupt */
1246 if (state) {
1247 u32 slave_state;
1248
1249 slave_state = cdns_readl(cdns, CDNS_MCP_SLAVE_INTSTAT0);
1250 cdns_writel(cdns, CDNS_MCP_SLAVE_INTSTAT0, slave_state);
1251 slave_state = cdns_readl(cdns, CDNS_MCP_SLAVE_INTSTAT1);
1252 cdns_writel(cdns, CDNS_MCP_SLAVE_INTSTAT1, slave_state);
1253 }
1254 cdns->interrupt_enabled = state;
1255
1256 /*
1257 * Complete any on-going status updates before updating masks,
1258 * and cancel queued status updates.
1259 *
1260 * There could be a race with a new interrupt thrown before
1261 * the 3 mask updates below are complete, so in the interrupt
1262 * we use the 'interrupt_enabled' status to prevent new work
1263 * from being queued.
1264 */
1265 if (!state)
1266 cancel_work_sync(&cdns->work);
1267
1268 cdns_writel(cdns, CDNS_MCP_SLAVE_INTMASK0, slave_intmask0);
1269 cdns_writel(cdns, CDNS_MCP_SLAVE_INTMASK1, slave_intmask1);
1270 cdns_writel(cdns, CDNS_MCP_INTMASK, mask);
1271
1272 return 0;
1273 }
1274 EXPORT_SYMBOL(sdw_cdns_enable_interrupt);
1275
cdns_allocate_pdi(struct sdw_cdns * cdns,struct sdw_cdns_pdi ** stream,u32 num)1276 static int cdns_allocate_pdi(struct sdw_cdns *cdns,
1277 struct sdw_cdns_pdi **stream,
1278 u32 num)
1279 {
1280 struct sdw_cdns_pdi *pdi;
1281 int i;
1282
1283 if (!num)
1284 return 0;
1285
1286 pdi = devm_kcalloc(cdns->dev, num, sizeof(*pdi), GFP_KERNEL);
1287 if (!pdi)
1288 return -ENOMEM;
1289
1290 for (i = 0; i < num; i++) {
1291 pdi[i].num = i;
1292 }
1293
1294 *stream = pdi;
1295 return 0;
1296 }
1297
1298 /**
1299 * sdw_cdns_pdi_init() - PDI initialization routine
1300 *
1301 * @cdns: Cadence instance
1302 * @config: Stream configurations
1303 */
sdw_cdns_pdi_init(struct sdw_cdns * cdns,struct sdw_cdns_stream_config config)1304 int sdw_cdns_pdi_init(struct sdw_cdns *cdns,
1305 struct sdw_cdns_stream_config config)
1306 {
1307 struct sdw_cdns_streams *stream;
1308 int ret;
1309
1310 cdns->pcm.num_bd = config.pcm_bd;
1311 cdns->pcm.num_in = config.pcm_in;
1312 cdns->pcm.num_out = config.pcm_out;
1313
1314 /* Allocate PDIs for PCMs */
1315 stream = &cdns->pcm;
1316
1317 /* we allocate PDI0 and PDI1 which are used for Bulk */
1318 ret = cdns_allocate_pdi(cdns, &stream->bd, stream->num_bd);
1319 if (ret)
1320 return ret;
1321
1322 ret = cdns_allocate_pdi(cdns, &stream->in, stream->num_in);
1323 if (ret)
1324 return ret;
1325
1326 ret = cdns_allocate_pdi(cdns, &stream->out, stream->num_out);
1327 if (ret)
1328 return ret;
1329
1330 /* Update total number of PCM PDIs */
1331 stream->num_pdi = stream->num_bd + stream->num_in + stream->num_out;
1332 cdns->num_ports = stream->num_pdi;
1333
1334 return 0;
1335 }
1336 EXPORT_SYMBOL(sdw_cdns_pdi_init);
1337
cdns_set_initial_frame_shape(int n_rows,int n_cols)1338 static u32 cdns_set_initial_frame_shape(int n_rows, int n_cols)
1339 {
1340 u32 val;
1341 int c;
1342 int r;
1343
1344 r = sdw_find_row_index(n_rows);
1345 c = sdw_find_col_index(n_cols);
1346
1347 val = FIELD_PREP(CDNS_MCP_FRAME_SHAPE_ROW_MASK, r);
1348 val |= FIELD_PREP(CDNS_MCP_FRAME_SHAPE_COL_MASK, c);
1349
1350 return val;
1351 }
1352
cdns_init_clock_ctrl(struct sdw_cdns * cdns)1353 static int cdns_init_clock_ctrl(struct sdw_cdns *cdns)
1354 {
1355 struct sdw_bus *bus = &cdns->bus;
1356 struct sdw_master_prop *prop = &bus->prop;
1357 u32 val;
1358 u32 ssp_interval;
1359 int divider;
1360
1361 dev_dbg(cdns->dev, "mclk %d max %d row %d col %d\n",
1362 prop->mclk_freq,
1363 prop->max_clk_freq,
1364 prop->default_row,
1365 prop->default_col);
1366
1367 if (!prop->default_frame_rate || !prop->default_row) {
1368 dev_err(cdns->dev, "Default frame_rate %d or row %d is invalid\n",
1369 prop->default_frame_rate, prop->default_row);
1370 return -EINVAL;
1371 }
1372
1373 /* Set clock divider */
1374 divider = (prop->mclk_freq * SDW_DOUBLE_RATE_FACTOR /
1375 bus->params.curr_dr_freq) - 1;
1376
1377 cdns_updatel(cdns, CDNS_MCP_CLK_CTRL0,
1378 CDNS_MCP_CLK_MCLKD_MASK, divider);
1379 cdns_updatel(cdns, CDNS_MCP_CLK_CTRL1,
1380 CDNS_MCP_CLK_MCLKD_MASK, divider);
1381
1382 /* Set frame shape base on the actual bus frequency. */
1383 prop->default_col = bus->params.curr_dr_freq /
1384 prop->default_frame_rate / prop->default_row;
1385
1386 /*
1387 * Frame shape changes after initialization have to be done
1388 * with the bank switch mechanism
1389 */
1390 val = cdns_set_initial_frame_shape(prop->default_row,
1391 prop->default_col);
1392 cdns_writel(cdns, CDNS_MCP_FRAME_SHAPE_INIT, val);
1393
1394 /* Set SSP interval to default value */
1395 ssp_interval = prop->default_frame_rate / SDW_CADENCE_GSYNC_HZ;
1396 cdns_writel(cdns, CDNS_MCP_SSP_CTRL0, ssp_interval);
1397 cdns_writel(cdns, CDNS_MCP_SSP_CTRL1, ssp_interval);
1398
1399 return 0;
1400 }
1401
1402 /**
1403 * sdw_cdns_soft_reset() - Cadence soft-reset
1404 * @cdns: Cadence instance
1405 */
sdw_cdns_soft_reset(struct sdw_cdns * cdns)1406 int sdw_cdns_soft_reset(struct sdw_cdns *cdns)
1407 {
1408 int ret;
1409
1410 cdns_updatel(cdns, CDNS_MCP_CONTROL, CDNS_MCP_CONTROL_SOFT_RST,
1411 CDNS_MCP_CONTROL_SOFT_RST);
1412
1413 ret = cdns_config_update(cdns);
1414 if (ret < 0) {
1415 dev_err(cdns->dev, "%s: config update failed\n", __func__);
1416 return ret;
1417 }
1418
1419 ret = cdns_set_wait(cdns, CDNS_MCP_CONTROL, CDNS_MCP_CONTROL_SOFT_RST, 0);
1420 if (ret < 0)
1421 dev_err(cdns->dev, "%s: Soft Reset timed out\n", __func__);
1422
1423 return ret;
1424 }
1425 EXPORT_SYMBOL(sdw_cdns_soft_reset);
1426
1427 /**
1428 * sdw_cdns_init() - Cadence initialization
1429 * @cdns: Cadence instance
1430 */
sdw_cdns_init(struct sdw_cdns * cdns)1431 int sdw_cdns_init(struct sdw_cdns *cdns)
1432 {
1433 int ret;
1434 u32 val;
1435
1436 ret = cdns_init_clock_ctrl(cdns);
1437 if (ret)
1438 return ret;
1439
1440 sdw_cdns_check_self_clearing_bits(cdns, __func__, false, 0);
1441
1442 /* reset msg_count to default value of FIFOLEVEL */
1443 cdns->msg_count = cdns_readl(cdns, CDNS_MCP_FIFOLEVEL);
1444
1445 /* flush command FIFOs */
1446 cdns_updatel(cdns, CDNS_MCP_CONTROL, CDNS_MCP_CONTROL_CMD_RST,
1447 CDNS_MCP_CONTROL_CMD_RST);
1448
1449 /* Set cmd accept mode */
1450 cdns_ip_updatel(cdns, CDNS_IP_MCP_CONTROL, CDNS_IP_MCP_CONTROL_CMD_ACCEPT,
1451 CDNS_IP_MCP_CONTROL_CMD_ACCEPT);
1452
1453 /* disable wakeup */
1454 cdns_ip_updatel(cdns, CDNS_IP_MCP_CONTROL,
1455 CDNS_IP_MCP_CONTROL_BLOCK_WAKEUP,
1456 0);
1457
1458 /* Configure mcp config */
1459 val = cdns_readl(cdns, CDNS_MCP_CONFIG);
1460
1461 /* Disable auto bus release */
1462 val &= ~CDNS_MCP_CONFIG_BUS_REL;
1463
1464 cdns_writel(cdns, CDNS_MCP_CONFIG, val);
1465
1466 /* Configure IP mcp config */
1467 val = cdns_ip_readl(cdns, CDNS_IP_MCP_CONFIG);
1468
1469 /* enable bus operations with clock and data */
1470 val &= ~CDNS_IP_MCP_CONFIG_OP;
1471 val |= CDNS_IP_MCP_CONFIG_OP_NORMAL;
1472
1473 /* Set cmd mode for Tx and Rx cmds */
1474 val &= ~CDNS_IP_MCP_CONFIG_CMD;
1475
1476 /* Disable sniffer mode */
1477 val &= ~CDNS_IP_MCP_CONFIG_SNIFFER;
1478
1479 if (cdns->bus.multi_link)
1480 /* Set Multi-master mode to take gsync into account */
1481 val |= CDNS_IP_MCP_CONFIG_MMASTER;
1482
1483 /* leave frame delay to hardware default of 0x1F */
1484
1485 /* leave command retry to hardware default of 0 */
1486
1487 cdns_ip_writel(cdns, CDNS_IP_MCP_CONFIG, val);
1488
1489 /* changes will be committed later */
1490 return 0;
1491 }
1492 EXPORT_SYMBOL(sdw_cdns_init);
1493
cdns_bus_conf(struct sdw_bus * bus,struct sdw_bus_params * params)1494 int cdns_bus_conf(struct sdw_bus *bus, struct sdw_bus_params *params)
1495 {
1496 struct sdw_master_prop *prop = &bus->prop;
1497 struct sdw_cdns *cdns = bus_to_cdns(bus);
1498 int mcp_clkctrl_off;
1499 int divider;
1500
1501 if (!params->curr_dr_freq) {
1502 dev_err(cdns->dev, "NULL curr_dr_freq\n");
1503 return -EINVAL;
1504 }
1505
1506 divider = prop->mclk_freq * SDW_DOUBLE_RATE_FACTOR /
1507 params->curr_dr_freq;
1508 divider--; /* divider is 1/(N+1) */
1509
1510 if (params->next_bank)
1511 mcp_clkctrl_off = CDNS_MCP_CLK_CTRL1;
1512 else
1513 mcp_clkctrl_off = CDNS_MCP_CLK_CTRL0;
1514
1515 cdns_updatel(cdns, mcp_clkctrl_off, CDNS_MCP_CLK_MCLKD_MASK, divider);
1516
1517 return 0;
1518 }
1519 EXPORT_SYMBOL(cdns_bus_conf);
1520
cdns_port_params(struct sdw_bus * bus,struct sdw_port_params * p_params,unsigned int bank)1521 static int cdns_port_params(struct sdw_bus *bus,
1522 struct sdw_port_params *p_params, unsigned int bank)
1523 {
1524 struct sdw_cdns *cdns = bus_to_cdns(bus);
1525 int dpn_config_off_source;
1526 int dpn_config_off_target;
1527 int target_num = p_params->num;
1528 int source_num = p_params->num;
1529 bool override = false;
1530 int dpn_config;
1531
1532 if (target_num == cdns->pdi_loopback_target &&
1533 cdns->pdi_loopback_source != -1) {
1534 source_num = cdns->pdi_loopback_source;
1535 override = true;
1536 }
1537
1538 if (bank) {
1539 dpn_config_off_source = CDNS_DPN_B1_CONFIG(source_num);
1540 dpn_config_off_target = CDNS_DPN_B1_CONFIG(target_num);
1541 } else {
1542 dpn_config_off_source = CDNS_DPN_B0_CONFIG(source_num);
1543 dpn_config_off_target = CDNS_DPN_B0_CONFIG(target_num);
1544 }
1545
1546 dpn_config = cdns_readl(cdns, dpn_config_off_source);
1547
1548 /* use port params if there is no loopback, otherwise use source as is */
1549 if (!override) {
1550 u32p_replace_bits(&dpn_config, p_params->bps - 1, CDNS_DPN_CONFIG_WL);
1551 u32p_replace_bits(&dpn_config, p_params->flow_mode, CDNS_DPN_CONFIG_PORT_FLOW);
1552 u32p_replace_bits(&dpn_config, p_params->data_mode, CDNS_DPN_CONFIG_PORT_DAT);
1553 }
1554
1555 cdns_writel(cdns, dpn_config_off_target, dpn_config);
1556
1557 return 0;
1558 }
1559
cdns_transport_params(struct sdw_bus * bus,struct sdw_transport_params * t_params,enum sdw_reg_bank bank)1560 static int cdns_transport_params(struct sdw_bus *bus,
1561 struct sdw_transport_params *t_params,
1562 enum sdw_reg_bank bank)
1563 {
1564 struct sdw_cdns *cdns = bus_to_cdns(bus);
1565 int dpn_config;
1566 int dpn_config_off_source;
1567 int dpn_config_off_target;
1568 int dpn_hctrl;
1569 int dpn_hctrl_off_source;
1570 int dpn_hctrl_off_target;
1571 int dpn_offsetctrl;
1572 int dpn_offsetctrl_off_source;
1573 int dpn_offsetctrl_off_target;
1574 int dpn_samplectrl;
1575 int dpn_samplectrl_off_source;
1576 int dpn_samplectrl_off_target;
1577 int source_num = t_params->port_num;
1578 int target_num = t_params->port_num;
1579 bool override = false;
1580
1581 if (target_num == cdns->pdi_loopback_target &&
1582 cdns->pdi_loopback_source != -1) {
1583 source_num = cdns->pdi_loopback_source;
1584 override = true;
1585 }
1586
1587 /*
1588 * Note: Only full data port is supported on the Master side for
1589 * both PCM and PDM ports.
1590 */
1591
1592 if (bank) {
1593 dpn_config_off_source = CDNS_DPN_B1_CONFIG(source_num);
1594 dpn_hctrl_off_source = CDNS_DPN_B1_HCTRL(source_num);
1595 dpn_offsetctrl_off_source = CDNS_DPN_B1_OFFSET_CTRL(source_num);
1596 dpn_samplectrl_off_source = CDNS_DPN_B1_SAMPLE_CTRL(source_num);
1597
1598 dpn_config_off_target = CDNS_DPN_B1_CONFIG(target_num);
1599 dpn_hctrl_off_target = CDNS_DPN_B1_HCTRL(target_num);
1600 dpn_offsetctrl_off_target = CDNS_DPN_B1_OFFSET_CTRL(target_num);
1601 dpn_samplectrl_off_target = CDNS_DPN_B1_SAMPLE_CTRL(target_num);
1602
1603 } else {
1604 dpn_config_off_source = CDNS_DPN_B0_CONFIG(source_num);
1605 dpn_hctrl_off_source = CDNS_DPN_B0_HCTRL(source_num);
1606 dpn_offsetctrl_off_source = CDNS_DPN_B0_OFFSET_CTRL(source_num);
1607 dpn_samplectrl_off_source = CDNS_DPN_B0_SAMPLE_CTRL(source_num);
1608
1609 dpn_config_off_target = CDNS_DPN_B0_CONFIG(target_num);
1610 dpn_hctrl_off_target = CDNS_DPN_B0_HCTRL(target_num);
1611 dpn_offsetctrl_off_target = CDNS_DPN_B0_OFFSET_CTRL(target_num);
1612 dpn_samplectrl_off_target = CDNS_DPN_B0_SAMPLE_CTRL(target_num);
1613 }
1614
1615 dpn_config = cdns_readl(cdns, dpn_config_off_source);
1616 if (!override) {
1617 u32p_replace_bits(&dpn_config, t_params->blk_grp_ctrl, CDNS_DPN_CONFIG_BGC);
1618 u32p_replace_bits(&dpn_config, t_params->blk_pkg_mode, CDNS_DPN_CONFIG_BPM);
1619 }
1620 cdns_writel(cdns, dpn_config_off_target, dpn_config);
1621
1622 if (!override) {
1623 dpn_offsetctrl = 0;
1624 u32p_replace_bits(&dpn_offsetctrl, t_params->offset1, CDNS_DPN_OFFSET_CTRL_1);
1625 u32p_replace_bits(&dpn_offsetctrl, t_params->offset2, CDNS_DPN_OFFSET_CTRL_2);
1626 } else {
1627 dpn_offsetctrl = cdns_readl(cdns, dpn_offsetctrl_off_source);
1628 }
1629 cdns_writel(cdns, dpn_offsetctrl_off_target, dpn_offsetctrl);
1630
1631 if (!override) {
1632 dpn_hctrl = 0;
1633 u32p_replace_bits(&dpn_hctrl, t_params->hstart, CDNS_DPN_HCTRL_HSTART);
1634 u32p_replace_bits(&dpn_hctrl, t_params->hstop, CDNS_DPN_HCTRL_HSTOP);
1635 u32p_replace_bits(&dpn_hctrl, t_params->lane_ctrl, CDNS_DPN_HCTRL_LCTRL);
1636 } else {
1637 dpn_hctrl = cdns_readl(cdns, dpn_hctrl_off_source);
1638 }
1639 cdns_writel(cdns, dpn_hctrl_off_target, dpn_hctrl);
1640
1641 if (!override)
1642 dpn_samplectrl = t_params->sample_interval - 1;
1643 else
1644 dpn_samplectrl = cdns_readl(cdns, dpn_samplectrl_off_source);
1645 cdns_writel(cdns, dpn_samplectrl_off_target, dpn_samplectrl);
1646
1647 return 0;
1648 }
1649
cdns_port_enable(struct sdw_bus * bus,struct sdw_enable_ch * enable_ch,unsigned int bank)1650 static int cdns_port_enable(struct sdw_bus *bus,
1651 struct sdw_enable_ch *enable_ch, unsigned int bank)
1652 {
1653 struct sdw_cdns *cdns = bus_to_cdns(bus);
1654 int dpn_chnen_off, ch_mask;
1655
1656 if (bank)
1657 dpn_chnen_off = CDNS_DPN_B1_CH_EN(enable_ch->port_num);
1658 else
1659 dpn_chnen_off = CDNS_DPN_B0_CH_EN(enable_ch->port_num);
1660
1661 ch_mask = enable_ch->ch_mask * enable_ch->enable;
1662 cdns_writel(cdns, dpn_chnen_off, ch_mask);
1663
1664 return 0;
1665 }
1666
1667 static const struct sdw_master_port_ops cdns_port_ops = {
1668 .dpn_set_port_params = cdns_port_params,
1669 .dpn_set_port_transport_params = cdns_transport_params,
1670 .dpn_port_enable_ch = cdns_port_enable,
1671 };
1672
1673 /**
1674 * sdw_cdns_is_clock_stop: Check clock status
1675 *
1676 * @cdns: Cadence instance
1677 */
sdw_cdns_is_clock_stop(struct sdw_cdns * cdns)1678 bool sdw_cdns_is_clock_stop(struct sdw_cdns *cdns)
1679 {
1680 return !!(cdns_readl(cdns, CDNS_MCP_STAT) & CDNS_MCP_STAT_CLK_STOP);
1681 }
1682 EXPORT_SYMBOL(sdw_cdns_is_clock_stop);
1683
1684 /**
1685 * sdw_cdns_clock_stop: Cadence clock stop configuration routine
1686 *
1687 * @cdns: Cadence instance
1688 * @block_wake: prevent wakes if required by the platform
1689 */
sdw_cdns_clock_stop(struct sdw_cdns * cdns,bool block_wake)1690 int sdw_cdns_clock_stop(struct sdw_cdns *cdns, bool block_wake)
1691 {
1692 bool slave_present = false;
1693 struct sdw_slave *slave;
1694 int ret;
1695
1696 sdw_cdns_check_self_clearing_bits(cdns, __func__, false, 0);
1697
1698 /* Check suspend status */
1699 if (sdw_cdns_is_clock_stop(cdns)) {
1700 dev_dbg(cdns->dev, "Clock is already stopped\n");
1701 return 0;
1702 }
1703
1704 /*
1705 * wait for any in-flight peripheral event handling to complete before stopping the clock.
1706 * No need to disable peripheral interrupts before canceling the work, as the peripheral
1707 * interrupts are already masked before the work is scheduled.
1708 */
1709 cancel_work_sync(&cdns->work);
1710
1711 /*
1712 * Before entering clock stop we mask the Slave
1713 * interrupts. This helps avoid having to deal with e.g. a
1714 * Slave becoming UNATTACHED while the clock is being stopped
1715 */
1716 cdns_enable_slave_interrupts(cdns, false);
1717
1718 /*
1719 * For specific platforms, it is required to be able to put
1720 * master into a state in which it ignores wake-up trials
1721 * in clock stop state
1722 */
1723 if (block_wake)
1724 cdns_ip_updatel(cdns, CDNS_IP_MCP_CONTROL,
1725 CDNS_IP_MCP_CONTROL_BLOCK_WAKEUP,
1726 CDNS_IP_MCP_CONTROL_BLOCK_WAKEUP);
1727
1728 list_for_each_entry(slave, &cdns->bus.slaves, node) {
1729 if (slave->status == SDW_SLAVE_ATTACHED ||
1730 slave->status == SDW_SLAVE_ALERT) {
1731 slave_present = true;
1732 break;
1733 }
1734 }
1735
1736 /* commit changes */
1737 ret = cdns_config_update(cdns);
1738 if (ret < 0) {
1739 dev_err(cdns->dev, "%s: config_update failed\n", __func__);
1740 return ret;
1741 }
1742
1743 /* Prepare slaves for clock stop */
1744 if (slave_present) {
1745 ret = sdw_bus_prep_clk_stop(&cdns->bus);
1746 if (ret < 0 && ret != -ENODATA) {
1747 dev_err(cdns->dev, "prepare clock stop failed %d\n", ret);
1748 return ret;
1749 }
1750 }
1751
1752 /*
1753 * Enter clock stop mode and only report errors if there are
1754 * Slave devices present (ALERT or ATTACHED)
1755 */
1756 ret = sdw_bus_clk_stop(&cdns->bus);
1757 if (ret < 0 && slave_present && ret != -ENODATA) {
1758 dev_err(cdns->dev, "bus clock stop failed %d\n", ret);
1759 return ret;
1760 }
1761
1762 ret = cdns_set_wait(cdns, CDNS_MCP_STAT,
1763 CDNS_MCP_STAT_CLK_STOP,
1764 CDNS_MCP_STAT_CLK_STOP);
1765 if (ret < 0)
1766 dev_err(cdns->dev, "Clock stop failed %d\n", ret);
1767
1768 return ret;
1769 }
1770 EXPORT_SYMBOL(sdw_cdns_clock_stop);
1771
1772 /**
1773 * sdw_cdns_clock_restart: Cadence PM clock restart configuration routine
1774 *
1775 * @cdns: Cadence instance
1776 * @bus_reset: context may be lost while in low power modes and the bus
1777 * may require a Severe Reset and re-enumeration after a wake.
1778 */
sdw_cdns_clock_restart(struct sdw_cdns * cdns,bool bus_reset)1779 int sdw_cdns_clock_restart(struct sdw_cdns *cdns, bool bus_reset)
1780 {
1781 int ret;
1782
1783 /* unmask Slave interrupts that were masked when stopping the clock */
1784 cdns_enable_slave_interrupts(cdns, true);
1785
1786 ret = cdns_clear_bit(cdns, CDNS_MCP_CONTROL,
1787 CDNS_MCP_CONTROL_CLK_STOP_CLR);
1788 if (ret < 0) {
1789 dev_err(cdns->dev, "Couldn't exit from clock stop\n");
1790 return ret;
1791 }
1792
1793 ret = cdns_set_wait(cdns, CDNS_MCP_STAT, CDNS_MCP_STAT_CLK_STOP, 0);
1794 if (ret < 0) {
1795 dev_err(cdns->dev, "clock stop exit failed %d\n", ret);
1796 return ret;
1797 }
1798
1799 cdns_ip_updatel(cdns, CDNS_IP_MCP_CONTROL,
1800 CDNS_IP_MCP_CONTROL_BLOCK_WAKEUP, 0);
1801
1802 cdns_ip_updatel(cdns, CDNS_IP_MCP_CONTROL, CDNS_IP_MCP_CONTROL_CMD_ACCEPT,
1803 CDNS_IP_MCP_CONTROL_CMD_ACCEPT);
1804
1805 if (!bus_reset) {
1806
1807 /* enable bus operations with clock and data */
1808 cdns_ip_updatel(cdns, CDNS_IP_MCP_CONFIG,
1809 CDNS_IP_MCP_CONFIG_OP,
1810 CDNS_IP_MCP_CONFIG_OP_NORMAL);
1811
1812 ret = cdns_config_update(cdns);
1813 if (ret < 0) {
1814 dev_err(cdns->dev, "%s: config_update failed\n", __func__);
1815 return ret;
1816 }
1817
1818 ret = sdw_bus_exit_clk_stop(&cdns->bus);
1819 if (ret < 0)
1820 dev_err(cdns->dev, "bus failed to exit clock stop %d\n", ret);
1821 }
1822
1823 return ret;
1824 }
1825 EXPORT_SYMBOL(sdw_cdns_clock_restart);
1826
1827 /**
1828 * sdw_cdns_probe() - Cadence probe routine
1829 * @cdns: Cadence instance
1830 */
sdw_cdns_probe(struct sdw_cdns * cdns)1831 int sdw_cdns_probe(struct sdw_cdns *cdns)
1832 {
1833 init_completion(&cdns->tx_complete);
1834 cdns->bus.port_ops = &cdns_port_ops;
1835
1836 mutex_init(&cdns->status_update_lock);
1837
1838 INIT_WORK(&cdns->work, cdns_update_slave_status_work);
1839 INIT_DELAYED_WORK(&cdns->attach_dwork, cdns_check_attached_status_dwork);
1840
1841 return 0;
1842 }
1843 EXPORT_SYMBOL(sdw_cdns_probe);
1844
cdns_set_sdw_stream(struct snd_soc_dai * dai,void * stream,int direction)1845 int cdns_set_sdw_stream(struct snd_soc_dai *dai,
1846 void *stream, int direction)
1847 {
1848 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
1849 struct sdw_cdns_dai_runtime *dai_runtime;
1850
1851 dai_runtime = cdns->dai_runtime_array[dai->id];
1852
1853 if (stream) {
1854 /* first paranoia check */
1855 if (dai_runtime) {
1856 dev_err(dai->dev,
1857 "dai_runtime already allocated for dai %s\n",
1858 dai->name);
1859 return -EINVAL;
1860 }
1861
1862 /* allocate and set dai_runtime info */
1863 dai_runtime = kzalloc_obj(*dai_runtime);
1864 if (!dai_runtime)
1865 return -ENOMEM;
1866
1867 dai_runtime->stream_type = SDW_STREAM_PCM;
1868
1869 dai_runtime->bus = &cdns->bus;
1870 dai_runtime->link_id = cdns->instance;
1871
1872 dai_runtime->stream = stream;
1873 dai_runtime->direction = direction;
1874
1875 cdns->dai_runtime_array[dai->id] = dai_runtime;
1876 } else {
1877 /* second paranoia check */
1878 if (!dai_runtime) {
1879 dev_err(dai->dev,
1880 "dai_runtime not allocated for dai %s\n",
1881 dai->name);
1882 return -EINVAL;
1883 }
1884
1885 /* for NULL stream we release allocated dai_runtime */
1886 kfree(dai_runtime);
1887 cdns->dai_runtime_array[dai->id] = NULL;
1888 }
1889 return 0;
1890 }
1891 EXPORT_SYMBOL(cdns_set_sdw_stream);
1892
1893 /**
1894 * cdns_find_pdi() - Find a free PDI
1895 *
1896 * @cdns: Cadence instance
1897 * @num: Number of PDIs
1898 * @pdi: PDI instances
1899 * @dai_id: DAI id
1900 *
1901 * Find a PDI for a given PDI array. The PDI num and dai_id are
1902 * expected to match, return NULL otherwise.
1903 */
cdns_find_pdi(struct sdw_cdns * cdns,unsigned int num,struct sdw_cdns_pdi * pdi,int dai_id)1904 static struct sdw_cdns_pdi *cdns_find_pdi(struct sdw_cdns *cdns,
1905 unsigned int num,
1906 struct sdw_cdns_pdi *pdi,
1907 int dai_id)
1908 {
1909 int i;
1910
1911 for (i = 0; i < num; i++)
1912 if (pdi[i].num == dai_id)
1913 return &pdi[i];
1914
1915 return NULL;
1916 }
1917
1918 /**
1919 * sdw_cdns_config_stream: Configure a stream
1920 *
1921 * @cdns: Cadence instance
1922 * @ch: Channel count
1923 * @dir: Data direction
1924 * @pdi: PDI to be used
1925 */
sdw_cdns_config_stream(struct sdw_cdns * cdns,u32 ch,u32 dir,struct sdw_cdns_pdi * pdi)1926 void sdw_cdns_config_stream(struct sdw_cdns *cdns,
1927 u32 ch, u32 dir, struct sdw_cdns_pdi *pdi)
1928 {
1929 u32 offset, val = 0;
1930
1931 if (dir == SDW_DATA_DIR_RX) {
1932 val = CDNS_PORTCTRL_DIRN;
1933
1934 if (cdns->bus.params.m_data_mode != SDW_PORT_DATA_MODE_NORMAL)
1935 val |= CDNS_PORTCTRL_TEST_FAILED;
1936 } else if (pdi->num == 0 || pdi->num == 1) {
1937 val |= CDNS_PORTCTRL_BULK_ENABLE;
1938 }
1939 offset = CDNS_PORTCTRL + pdi->num * CDNS_PORT_OFFSET;
1940 cdns_updatel(cdns, offset,
1941 CDNS_PORTCTRL_DIRN | CDNS_PORTCTRL_TEST_FAILED |
1942 CDNS_PORTCTRL_BULK_ENABLE,
1943 val);
1944
1945 /* The DataPort0 needs to be mapped to both PDI0 and PDI1 ! */
1946 if (pdi->num == 1)
1947 val = 0;
1948 else
1949 val = pdi->num;
1950 val |= CDNS_PDI_CONFIG_SOFT_RESET;
1951 val |= FIELD_PREP(CDNS_PDI_CONFIG_CHANNEL, (1 << ch) - 1);
1952 cdns_writel(cdns, CDNS_PDI_CONFIG(pdi->num), val);
1953 }
1954 EXPORT_SYMBOL(sdw_cdns_config_stream);
1955
1956 /**
1957 * sdw_cdns_alloc_pdi() - Allocate a PDI
1958 *
1959 * @cdns: Cadence instance
1960 * @stream: Stream to be allocated
1961 * @ch: Channel count
1962 * @dir: Data direction
1963 * @dai_id: DAI id
1964 */
sdw_cdns_alloc_pdi(struct sdw_cdns * cdns,struct sdw_cdns_streams * stream,u32 ch,u32 dir,int dai_id)1965 struct sdw_cdns_pdi *sdw_cdns_alloc_pdi(struct sdw_cdns *cdns,
1966 struct sdw_cdns_streams *stream,
1967 u32 ch, u32 dir, int dai_id)
1968 {
1969 struct sdw_cdns_pdi *pdi = NULL;
1970
1971 if (dir == SDW_DATA_DIR_RX)
1972 pdi = cdns_find_pdi(cdns, stream->num_in, stream->in,
1973 dai_id);
1974 else
1975 pdi = cdns_find_pdi(cdns, stream->num_out, stream->out,
1976 dai_id);
1977
1978 /* check if we found a PDI, else find in bi-directional */
1979 if (!pdi)
1980 pdi = cdns_find_pdi(cdns, stream->num_bd, stream->bd,
1981 dai_id);
1982
1983 if (pdi) {
1984 pdi->l_ch_num = 0;
1985 pdi->h_ch_num = ch - 1;
1986 pdi->dir = dir;
1987 pdi->ch_count = ch;
1988 }
1989
1990 return pdi;
1991 }
1992 EXPORT_SYMBOL(sdw_cdns_alloc_pdi);
1993
1994 /*
1995 * the MIPI SoundWire CRC8 polynomial is X^8 + X^6 + X^3 + X^2 + 1, MSB first
1996 * The value is (1)01001101 = 0x4D
1997 *
1998 * the table below was generated with
1999 *
2000 * u8 crc8_lookup_table[CRC8_TABLE_SIZE];
2001 * crc8_populate_msb(crc8_lookup_table, SDW_CRC8_POLY);
2002 *
2003 */
2004 #define SDW_CRC8_SEED 0xFF
2005 #define SDW_CRC8_POLY 0x4D
2006
2007 static const u8 sdw_crc8_lookup_msb[CRC8_TABLE_SIZE] = {
2008 0x00, 0x4d, 0x9a, 0xd7, 0x79, 0x34, 0xe3, 0xae, /* 0 - 7 */
2009 0xf2, 0xbf, 0x68, 0x25, 0x8b, 0xc6, 0x11, 0x5c, /* 8 -15 */
2010 0xa9, 0xe4, 0x33, 0x7e, 0xd0, 0x9d, 0x4a, 0x07, /* 16 - 23 */
2011 0x5b, 0x16, 0xc1, 0x8c, 0x22, 0x6f, 0xb8, 0xf5, /* 24 - 31 */
2012 0x1f, 0x52, 0x85, 0xc8, 0x66, 0x2b, 0xfc, 0xb1, /* 32 - 39 */
2013 0xed, 0xa0, 0x77, 0x3a, 0x94, 0xd9, 0x0e, 0x43, /* 40 - 47 */
2014 0xb6, 0xfb, 0x2c, 0x61, 0xcf, 0x82, 0x55, 0x18, /* 48 - 55 */
2015 0x44, 0x09, 0xde, 0x93, 0x3d, 0x70, 0xa7, 0xea, /* 56 - 63 */
2016 0x3e, 0x73, 0xa4, 0xe9, 0x47, 0x0a, 0xdd, 0x90, /* 64 - 71 */
2017 0xcc, 0x81, 0x56, 0x1b, 0xb5, 0xf8, 0x2f, 0x62, /* 72 - 79 */
2018 0x97, 0xda, 0x0d, 0x40, 0xee, 0xa3, 0x74, 0x39, /* 80 - 87 */
2019 0x65, 0x28, 0xff, 0xb2, 0x1c, 0x51, 0x86, 0xcb, /* 88 - 95 */
2020 0x21, 0x6c, 0xbb, 0xf6, 0x58, 0x15, 0xc2, 0x8f, /* 96 - 103 */
2021 0xd3, 0x9e, 0x49, 0x04, 0xaa, 0xe7, 0x30, 0x7d, /* 104 - 111 */
2022 0x88, 0xc5, 0x12, 0x5f, 0xf1, 0xbc, 0x6b, 0x26, /* 112 - 119 */
2023 0x7a, 0x37, 0xe0, 0xad, 0x03, 0x4e, 0x99, 0xd4, /* 120 - 127 */
2024 0x7c, 0x31, 0xe6, 0xab, 0x05, 0x48, 0x9f, 0xd2, /* 128 - 135 */
2025 0x8e, 0xc3, 0x14, 0x59, 0xf7, 0xba, 0x6d, 0x20, /* 136 - 143 */
2026 0xd5, 0x98, 0x4f, 0x02, 0xac, 0xe1, 0x36, 0x7b, /* 144 - 151 */
2027 0x27, 0x6a, 0xbd, 0xf0, 0x5e, 0x13, 0xc4, 0x89, /* 152 - 159 */
2028 0x63, 0x2e, 0xf9, 0xb4, 0x1a, 0x57, 0x80, 0xcd, /* 160 - 167 */
2029 0x91, 0xdc, 0x0b, 0x46, 0xe8, 0xa5, 0x72, 0x3f, /* 168 - 175 */
2030 0xca, 0x87, 0x50, 0x1d, 0xb3, 0xfe, 0x29, 0x64, /* 176 - 183 */
2031 0x38, 0x75, 0xa2, 0xef, 0x41, 0x0c, 0xdb, 0x96, /* 184 - 191 */
2032 0x42, 0x0f, 0xd8, 0x95, 0x3b, 0x76, 0xa1, 0xec, /* 192 - 199 */
2033 0xb0, 0xfd, 0x2a, 0x67, 0xc9, 0x84, 0x53, 0x1e, /* 200 - 207 */
2034 0xeb, 0xa6, 0x71, 0x3c, 0x92, 0xdf, 0x08, 0x45, /* 208 - 215 */
2035 0x19, 0x54, 0x83, 0xce, 0x60, 0x2d, 0xfa, 0xb7, /* 216 - 223 */
2036 0x5d, 0x10, 0xc7, 0x8a, 0x24, 0x69, 0xbe, 0xf3, /* 224 - 231 */
2037 0xaf, 0xe2, 0x35, 0x78, 0xd6, 0x9b, 0x4c, 0x01, /* 232 - 239 */
2038 0xf4, 0xb9, 0x6e, 0x23, 0x8d, 0xc0, 0x17, 0x5a, /* 240 - 247 */
2039 0x06, 0x4b, 0x9c, 0xd1, 0x7f, 0x32, 0xe5, 0xa8 /* 248 - 255 */
2040 };
2041
2042 /* BPT/BRA helpers */
2043
2044 #define SDW_CDNS_BRA_HDR 6 /* defined by MIPI */
2045 #define SDW_CDNS_BRA_HDR_CRC 1 /* defined by MIPI */
2046 #define SDW_CDNS_BRA_HDR_CRC_PAD 1 /* Cadence only */
2047 #define SDW_CDNS_BRA_HDR_RESP 1 /* defined by MIPI */
2048 #define SDW_CDNS_BRA_HDR_RESP_PAD 1 /* Cadence only */
2049
2050 #define SDW_CDNS_BRA_DATA_PAD 1 /* Cadence only */
2051 #define SDW_CDNS_BRA_DATA_CRC 1 /* defined by MIPI */
2052 #define SDW_CDNS_BRA_DATA_CRC_PAD 1 /* Cadence only */
2053
2054 #define SDW_CDNS_BRA_FOOTER_RESP 1 /* defined by MIPI */
2055 #define SDW_CDNS_BRA_FOOTER_RESP_PAD 1 /* Cadence only */
2056
2057 #define SDW_CDNS_WRITE_PDI1_BUFFER_SIZE \
2058 ((SDW_CDNS_BRA_HDR_RESP + SDW_CDNS_BRA_HDR_RESP_PAD + \
2059 SDW_CDNS_BRA_FOOTER_RESP + SDW_CDNS_BRA_FOOTER_RESP_PAD) * 2)
2060
2061 #define SDW_CDNS_READ_PDI0_BUFFER_SIZE \
2062 ((SDW_CDNS_BRA_HDR + SDW_CDNS_BRA_HDR_CRC + SDW_CDNS_BRA_HDR_CRC_PAD) * 2)
2063
sdw_cdns_bra_actual_data_size(unsigned int allocated_bytes_per_frame)2064 static unsigned int sdw_cdns_bra_actual_data_size(unsigned int allocated_bytes_per_frame)
2065 {
2066 unsigned int total;
2067
2068 if (allocated_bytes_per_frame < (SDW_CDNS_BRA_HDR + SDW_CDNS_BRA_HDR_CRC +
2069 SDW_CDNS_BRA_HDR_RESP + SDW_CDNS_BRA_DATA_CRC +
2070 SDW_CDNS_BRA_FOOTER_RESP))
2071 return 0;
2072
2073 total = allocated_bytes_per_frame - SDW_CDNS_BRA_HDR - SDW_CDNS_BRA_HDR_CRC -
2074 SDW_CDNS_BRA_HDR_RESP - SDW_CDNS_BRA_DATA_CRC - SDW_CDNS_BRA_FOOTER_RESP;
2075
2076 return total;
2077 }
2078
sdw_cdns_write_pdi0_buffer_size(unsigned int actual_data_size)2079 static unsigned int sdw_cdns_write_pdi0_buffer_size(unsigned int actual_data_size)
2080 {
2081 unsigned int total;
2082
2083 total = SDW_CDNS_BRA_HDR + SDW_CDNS_BRA_HDR_CRC + SDW_CDNS_BRA_HDR_CRC_PAD;
2084
2085 total += actual_data_size;
2086 if (actual_data_size & 1)
2087 total += SDW_CDNS_BRA_DATA_PAD;
2088
2089 total += SDW_CDNS_BRA_DATA_CRC + SDW_CDNS_BRA_DATA_CRC_PAD;
2090
2091 return total * 2;
2092 }
2093
sdw_cdns_read_pdi1_buffer_size(unsigned int actual_data_size)2094 static unsigned int sdw_cdns_read_pdi1_buffer_size(unsigned int actual_data_size)
2095 {
2096 unsigned int total;
2097
2098 total = SDW_CDNS_BRA_HDR_RESP + SDW_CDNS_BRA_HDR_RESP_PAD;
2099
2100 total += actual_data_size;
2101 if (actual_data_size & 1)
2102 total += SDW_CDNS_BRA_DATA_PAD;
2103
2104 total += SDW_CDNS_BRA_HDR_CRC + SDW_CDNS_BRA_HDR_CRC_PAD;
2105
2106 total += SDW_CDNS_BRA_FOOTER_RESP + SDW_CDNS_BRA_FOOTER_RESP_PAD;
2107
2108 return total * 2;
2109 }
2110
sdw_cdns_bpt_find_bandwidth(int command,int row,int col,int frame_rate,unsigned int * tx_dma_bandwidth,unsigned int * rx_dma_bandwidth)2111 int sdw_cdns_bpt_find_bandwidth(int command, /* 0: write, 1: read */
2112 int row, int col, int frame_rate,
2113 unsigned int *tx_dma_bandwidth,
2114 unsigned int *rx_dma_bandwidth)
2115 {
2116 unsigned int bpt_bits = row * (col - 1);
2117 unsigned int bpt_bytes = bpt_bits >> 3;
2118 unsigned int pdi0_buffer_size;
2119 unsigned int pdi1_buffer_size;
2120 unsigned int data_per_frame;
2121
2122 data_per_frame = sdw_cdns_bra_actual_data_size(bpt_bytes);
2123 if (!data_per_frame)
2124 return -EINVAL;
2125
2126 if (command == 0) {
2127 pdi0_buffer_size = sdw_cdns_write_pdi0_buffer_size(data_per_frame);
2128 pdi1_buffer_size = SDW_CDNS_WRITE_PDI1_BUFFER_SIZE;
2129 } else {
2130 pdi0_buffer_size = SDW_CDNS_READ_PDI0_BUFFER_SIZE;
2131 pdi1_buffer_size = sdw_cdns_read_pdi1_buffer_size(data_per_frame);
2132 }
2133
2134 *tx_dma_bandwidth = pdi0_buffer_size * 8 * frame_rate;
2135 *rx_dma_bandwidth = pdi1_buffer_size * 8 * frame_rate;
2136
2137 return 0;
2138 }
2139 EXPORT_SYMBOL(sdw_cdns_bpt_find_bandwidth);
2140
sdw_cdns_bpt_find_buffer_sizes(int command,int row,int col,unsigned int data_bytes,unsigned int requested_bytes_per_frame,unsigned int bra_block_alignment,unsigned int * data_per_frame,unsigned int * pdi0_buffer_size,unsigned int * pdi1_buffer_size,unsigned int * num_frames)2141 int sdw_cdns_bpt_find_buffer_sizes(int command, /* 0: write, 1: read */
2142 int row, int col, unsigned int data_bytes,
2143 unsigned int requested_bytes_per_frame,
2144 unsigned int bra_block_alignment,
2145 unsigned int *data_per_frame, unsigned int *pdi0_buffer_size,
2146 unsigned int *pdi1_buffer_size, unsigned int *num_frames)
2147 {
2148 unsigned int bpt_bits = row * (col - 1);
2149 unsigned int bpt_bytes = bpt_bits >> 3;
2150 unsigned int actual_bpt_bytes;
2151 unsigned int pdi0_tx_size;
2152 unsigned int pdi1_rx_size;
2153 unsigned int remainder;
2154
2155 if (!data_bytes)
2156 return -EINVAL;
2157
2158 actual_bpt_bytes = sdw_cdns_bra_actual_data_size(bpt_bytes);
2159 if (!actual_bpt_bytes)
2160 return -EINVAL;
2161
2162 /*
2163 * the caller may want to set the number of bytes per frame,
2164 * allow when possible
2165 */
2166 if (requested_bytes_per_frame < actual_bpt_bytes)
2167 actual_bpt_bytes = requested_bytes_per_frame;
2168
2169 if (bra_block_alignment) {
2170 /* align to a multiple of bra_block_alignment */
2171 if (actual_bpt_bytes < bra_block_alignment) {
2172 pr_err("effective bytes per frame %u is smaller than block alignment %u\n",
2173 actual_bpt_bytes, bra_block_alignment);
2174 return -EINVAL;
2175 }
2176 actual_bpt_bytes -= (actual_bpt_bytes % bra_block_alignment);
2177 }
2178
2179 *data_per_frame = actual_bpt_bytes;
2180
2181 if (data_bytes < actual_bpt_bytes)
2182 actual_bpt_bytes = data_bytes;
2183
2184 if (command == 0) {
2185 /*
2186 * for writes we need to send all the data_bytes per frame,
2187 * even for the last frame which may only transport fewer bytes
2188 */
2189
2190 *num_frames = DIV_ROUND_UP(data_bytes, actual_bpt_bytes);
2191
2192 pdi0_tx_size = sdw_cdns_write_pdi0_buffer_size(actual_bpt_bytes);
2193 pdi1_rx_size = SDW_CDNS_WRITE_PDI1_BUFFER_SIZE;
2194
2195 *pdi0_buffer_size = pdi0_tx_size * *num_frames;
2196 *pdi1_buffer_size = pdi1_rx_size * *num_frames;
2197 } else {
2198 /*
2199 * for reads we need to retrieve only what is requested in the BPT
2200 * header, so the last frame needs to be special-cased
2201 */
2202 *num_frames = data_bytes / actual_bpt_bytes;
2203
2204 pdi0_tx_size = SDW_CDNS_READ_PDI0_BUFFER_SIZE;
2205 pdi1_rx_size = sdw_cdns_read_pdi1_buffer_size(actual_bpt_bytes);
2206
2207 *pdi0_buffer_size = pdi0_tx_size * *num_frames;
2208 *pdi1_buffer_size = pdi1_rx_size * *num_frames;
2209
2210 remainder = data_bytes % actual_bpt_bytes;
2211 if (remainder) {
2212 pdi0_tx_size = SDW_CDNS_READ_PDI0_BUFFER_SIZE;
2213 pdi1_rx_size = sdw_cdns_read_pdi1_buffer_size(remainder);
2214
2215 *num_frames = *num_frames + 1;
2216 *pdi0_buffer_size += pdi0_tx_size;
2217 *pdi1_buffer_size += pdi1_rx_size;
2218 }
2219 }
2220
2221 return 0;
2222 }
2223 EXPORT_SYMBOL(sdw_cdns_bpt_find_buffer_sizes);
2224
sdw_cdns_copy_write_data(u8 * data,int data_size,u8 * dma_buffer,int dma_buffer_size)2225 static int sdw_cdns_copy_write_data(u8 *data, int data_size, u8 *dma_buffer, int dma_buffer_size)
2226 {
2227 /*
2228 * the implementation copies the data one byte at a time. Experiments with
2229 * two bytes at a time did not seem to improve the performance
2230 */
2231 int i, j;
2232
2233 /* size check to prevent out of bounds access */
2234 i = data_size - 1;
2235 j = (2 * i) - (i & 1);
2236 if (data_size & 1)
2237 j++;
2238 j += 2;
2239 if (j >= dma_buffer_size)
2240 return -EINVAL;
2241
2242 /* copy data */
2243 for (i = 0; i < data_size; i++) {
2244 j = (2 * i) - (i & 1);
2245 dma_buffer[j] = data[i];
2246 }
2247 /* add required pad */
2248 if (data_size & 1)
2249 dma_buffer[++j] = 0;
2250 /* skip last two bytes */
2251 j += 2;
2252
2253 /* offset and data are off-by-one */
2254 return j + 1;
2255 }
2256
sdw_cdns_prepare_write_pd0_buffer(u8 * header,unsigned int header_size,u8 * data,unsigned int data_size,u8 * dma_buffer,unsigned int dma_buffer_size,unsigned int * dma_data_written,unsigned int frame_counter)2257 static int sdw_cdns_prepare_write_pd0_buffer(u8 *header, unsigned int header_size,
2258 u8 *data, unsigned int data_size,
2259 u8 *dma_buffer, unsigned int dma_buffer_size,
2260 unsigned int *dma_data_written,
2261 unsigned int frame_counter)
2262 {
2263 int data_written;
2264 u8 *last_byte;
2265 u8 crc;
2266
2267 *dma_data_written = 0;
2268
2269 data_written = sdw_cdns_copy_write_data(header, header_size, dma_buffer, dma_buffer_size);
2270 if (data_written < 0)
2271 return data_written;
2272 dma_buffer[3] = BIT(7);
2273 dma_buffer[3] |= frame_counter & GENMASK(3, 0);
2274
2275 dma_buffer += data_written;
2276 dma_buffer_size -= data_written;
2277 *dma_data_written += data_written;
2278
2279 crc = SDW_CRC8_SEED;
2280 crc = crc8(sdw_crc8_lookup_msb, header, header_size, crc);
2281
2282 data_written = sdw_cdns_copy_write_data(&crc, 1, dma_buffer, dma_buffer_size);
2283 if (data_written < 0)
2284 return data_written;
2285 dma_buffer += data_written;
2286 dma_buffer_size -= data_written;
2287 *dma_data_written += data_written;
2288
2289 data_written = sdw_cdns_copy_write_data(data, data_size, dma_buffer, dma_buffer_size);
2290 if (data_written < 0)
2291 return data_written;
2292 dma_buffer += data_written;
2293 dma_buffer_size -= data_written;
2294 *dma_data_written += data_written;
2295
2296 crc = SDW_CRC8_SEED;
2297 crc = crc8(sdw_crc8_lookup_msb, data, data_size, crc);
2298 data_written = sdw_cdns_copy_write_data(&crc, 1, dma_buffer, dma_buffer_size);
2299 if (data_written < 0)
2300 return data_written;
2301 dma_buffer += data_written;
2302 dma_buffer_size -= data_written;
2303 *dma_data_written += data_written;
2304
2305 /* tag last byte */
2306 last_byte = dma_buffer - 1;
2307 last_byte[0] = BIT(6);
2308
2309 return 0;
2310 }
2311
sdw_cdns_prepare_read_pd0_buffer(u8 * header,unsigned int header_size,u8 * dma_buffer,unsigned int dma_buffer_size,unsigned int * dma_data_written,unsigned int frame_counter)2312 static int sdw_cdns_prepare_read_pd0_buffer(u8 *header, unsigned int header_size,
2313 u8 *dma_buffer, unsigned int dma_buffer_size,
2314 unsigned int *dma_data_written,
2315 unsigned int frame_counter)
2316 {
2317 int data_written;
2318 u8 *last_byte;
2319 u8 crc;
2320
2321 *dma_data_written = 0;
2322
2323 data_written = sdw_cdns_copy_write_data(header, header_size, dma_buffer, dma_buffer_size);
2324 if (data_written < 0)
2325 return data_written;
2326 dma_buffer[3] = BIT(7);
2327 dma_buffer[3] |= frame_counter & GENMASK(3, 0);
2328
2329 dma_buffer += data_written;
2330 dma_buffer_size -= data_written;
2331 *dma_data_written += data_written;
2332
2333 crc = SDW_CRC8_SEED;
2334 crc = crc8(sdw_crc8_lookup_msb, header, header_size, crc);
2335
2336 data_written = sdw_cdns_copy_write_data(&crc, 1, dma_buffer, dma_buffer_size);
2337 if (data_written < 0)
2338 return data_written;
2339 dma_buffer += data_written;
2340 dma_buffer_size -= data_written;
2341 *dma_data_written += data_written;
2342
2343 /* tag last byte */
2344 last_byte = dma_buffer - 1;
2345 last_byte[0] = BIT(6);
2346
2347 return 0;
2348 }
2349
2350 #define CDNS_BPT_ROLLING_COUNTER_START 1
2351
sdw_cdns_prepare_write_dma_buffer(u8 dev_num,struct sdw_bpt_section * sec,int num_sec,int data_per_frame,u8 * dma_buffer,int dma_buffer_size,int * dma_buffer_total_bytes)2352 int sdw_cdns_prepare_write_dma_buffer(u8 dev_num, struct sdw_bpt_section *sec, int num_sec,
2353 int data_per_frame, u8 *dma_buffer,
2354 int dma_buffer_size, int *dma_buffer_total_bytes)
2355 {
2356 int total_dma_data_written = 0;
2357 u8 *p_dma_buffer = dma_buffer;
2358 u8 header[SDW_CDNS_BRA_HDR];
2359 unsigned int start_register;
2360 unsigned int section_size;
2361 int dma_data_written;
2362 u8 *p_data;
2363 u8 counter;
2364 int ret;
2365 int i;
2366
2367 counter = CDNS_BPT_ROLLING_COUNTER_START;
2368
2369 header[0] = BIT(1); /* write command: BIT(1) set */
2370 header[0] |= GENMASK(7, 6); /* header is active */
2371 header[0] |= (dev_num << 2);
2372
2373 for (i = 0; i < num_sec; i++) {
2374 start_register = sec[i].addr;
2375 section_size = sec[i].len;
2376 p_data = sec[i].buf;
2377
2378 while (section_size >= data_per_frame) {
2379 header[0] &= ~BIT(0);
2380 header[0] |= (data_per_frame >> 8) & BIT(0);
2381 header[1] = data_per_frame & 0xFF;
2382 header[2] = start_register >> 24 & 0xFF;
2383 header[3] = start_register >> 16 & 0xFF;
2384 header[4] = start_register >> 8 & 0xFF;
2385 header[5] = start_register >> 0 & 0xFF;
2386
2387 ret = sdw_cdns_prepare_write_pd0_buffer(header, SDW_CDNS_BRA_HDR,
2388 p_data, data_per_frame,
2389 p_dma_buffer, dma_buffer_size,
2390 &dma_data_written, counter);
2391 if (ret < 0)
2392 return ret;
2393
2394 counter++;
2395
2396 p_data += data_per_frame;
2397 section_size -= data_per_frame;
2398
2399 p_dma_buffer += dma_data_written;
2400 dma_buffer_size -= dma_data_written;
2401 total_dma_data_written += dma_data_written;
2402
2403 start_register += data_per_frame;
2404 }
2405
2406 if (section_size) {
2407 header[0] &= ~BIT(0);
2408 header[0] |= (section_size >> 8) & BIT(0);
2409 header[1] = section_size & 0xFF;
2410 header[2] = start_register >> 24 & 0xFF;
2411 header[3] = start_register >> 16 & 0xFF;
2412 header[4] = start_register >> 8 & 0xFF;
2413 header[5] = start_register >> 0 & 0xFF;
2414
2415 ret = sdw_cdns_prepare_write_pd0_buffer(header, SDW_CDNS_BRA_HDR,
2416 p_data, section_size,
2417 p_dma_buffer, dma_buffer_size,
2418 &dma_data_written, counter);
2419 if (ret < 0)
2420 return ret;
2421
2422 counter++;
2423
2424 p_dma_buffer += dma_data_written;
2425 dma_buffer_size -= dma_data_written;
2426 total_dma_data_written += dma_data_written;
2427 }
2428 }
2429
2430 *dma_buffer_total_bytes = total_dma_data_written;
2431
2432 return 0;
2433 }
2434 EXPORT_SYMBOL(sdw_cdns_prepare_write_dma_buffer);
2435
sdw_cdns_prepare_read_dma_buffer(u8 dev_num,struct sdw_bpt_section * sec,int num_sec,int data_per_frame,u8 * dma_buffer,int dma_buffer_size,int * dma_buffer_total_bytes,unsigned int fake_size)2436 int sdw_cdns_prepare_read_dma_buffer(u8 dev_num, struct sdw_bpt_section *sec, int num_sec,
2437 int data_per_frame, u8 *dma_buffer, int dma_buffer_size,
2438 int *dma_buffer_total_bytes, unsigned int fake_size)
2439 {
2440 int total_dma_data_written = 0;
2441 u8 *p_dma_buffer = dma_buffer;
2442 u8 header[SDW_CDNS_BRA_HDR];
2443 unsigned int start_register;
2444 unsigned int data_size;
2445 int dma_data_written;
2446 u8 counter;
2447 int ret;
2448 int i;
2449
2450 counter = CDNS_BPT_ROLLING_COUNTER_START;
2451
2452 header[0] = 0; /* read command: BIT(1) cleared */
2453 header[0] |= GENMASK(7, 6); /* header is active */
2454 header[0] |= (dev_num << 2);
2455
2456 for (i = 0; i < num_sec; i++) {
2457 start_register = sec[i].addr;
2458 data_size = sec[i].len;
2459 while (data_size >= data_per_frame) {
2460 header[0] &= ~BIT(0);
2461 header[0] |= (data_per_frame >> 8) & BIT(0);
2462 header[1] = data_per_frame & 0xFF;
2463 header[2] = start_register >> 24 & 0xFF;
2464 header[3] = start_register >> 16 & 0xFF;
2465 header[4] = start_register >> 8 & 0xFF;
2466 header[5] = start_register >> 0 & 0xFF;
2467
2468 ret = sdw_cdns_prepare_read_pd0_buffer(header, SDW_CDNS_BRA_HDR,
2469 p_dma_buffer, dma_buffer_size,
2470 &dma_data_written, counter);
2471 if (ret < 0)
2472 return ret;
2473
2474 counter++;
2475
2476 data_size -= data_per_frame;
2477
2478 p_dma_buffer += dma_data_written;
2479 dma_buffer_size -= dma_data_written;
2480 total_dma_data_written += dma_data_written;
2481
2482 start_register += data_per_frame;
2483 }
2484
2485 if (data_size) {
2486 header[0] &= ~BIT(0);
2487 header[0] |= (data_size >> 8) & BIT(0);
2488 header[1] = data_size & 0xFF;
2489 header[2] = start_register >> 24 & 0xFF;
2490 header[3] = start_register >> 16 & 0xFF;
2491 header[4] = start_register >> 8 & 0xFF;
2492 header[5] = start_register >> 0 & 0xFF;
2493
2494 ret = sdw_cdns_prepare_read_pd0_buffer(header, SDW_CDNS_BRA_HDR,
2495 p_dma_buffer, dma_buffer_size,
2496 &dma_data_written, counter);
2497 if (ret < 0)
2498 return ret;
2499
2500 counter++;
2501
2502 p_dma_buffer += dma_data_written;
2503 dma_buffer_size -= dma_data_written;
2504 total_dma_data_written += dma_data_written;
2505 }
2506 }
2507
2508 /* Add fake frame */
2509 header[0] &= ~GENMASK(7, 6); /* Set inactive flag in BPT/BRA frame heade */
2510 while (fake_size >= data_per_frame) {
2511 header[0] &= ~BIT(0);
2512 header[0] |= (data_per_frame >> 8) & BIT(0);
2513 header[1] = data_per_frame & 0xFF;
2514 ret = sdw_cdns_prepare_read_pd0_buffer(header, SDW_CDNS_BRA_HDR, p_dma_buffer,
2515 dma_buffer_size, &dma_data_written,
2516 counter);
2517 if (ret < 0)
2518 return ret;
2519
2520 counter++;
2521
2522 fake_size -= data_per_frame;
2523 p_dma_buffer += dma_data_written;
2524 dma_buffer_size -= dma_data_written;
2525 total_dma_data_written += dma_data_written;
2526 }
2527
2528 if (fake_size) {
2529 header[0] &= ~BIT(0);
2530 header[0] |= (fake_size >> 8) & BIT(0);
2531 header[1] = fake_size & 0xFF;
2532 ret = sdw_cdns_prepare_read_pd0_buffer(header, SDW_CDNS_BRA_HDR, p_dma_buffer,
2533 dma_buffer_size, &dma_data_written,
2534 counter);
2535 if (ret < 0)
2536 return ret;
2537
2538 counter++;
2539
2540 p_dma_buffer += dma_data_written;
2541 dma_buffer_size -= dma_data_written;
2542 total_dma_data_written += dma_data_written;
2543 }
2544
2545 *dma_buffer_total_bytes = total_dma_data_written;
2546
2547 return 0;
2548 }
2549 EXPORT_SYMBOL(sdw_cdns_prepare_read_dma_buffer);
2550
check_counter(u32 val,u8 counter)2551 static int check_counter(u32 val, u8 counter)
2552 {
2553 u8 frame;
2554
2555 frame = (val >> 24) & GENMASK(3, 0);
2556 if (counter != frame)
2557 return -EIO;
2558 return 0;
2559 }
2560
check_response(u32 val)2561 static int check_response(u32 val)
2562 {
2563 u8 response;
2564
2565 response = (val >> 3) & GENMASK(1, 0);
2566 if (response == 0) /* Ignored */
2567 return -ENODATA;
2568 if (response != 1) /* ACK */
2569 return -EIO;
2570
2571 return 0;
2572 }
2573
check_frame_start(u32 header,u8 counter)2574 static int check_frame_start(u32 header, u8 counter)
2575 {
2576 int ret;
2577
2578 /* check frame_start marker */
2579 if (!(header & BIT(31)))
2580 return -EIO;
2581
2582 ret = check_counter(header, counter);
2583 if (ret < 0)
2584 return ret;
2585
2586 return check_response(header);
2587 }
2588
check_frame_end(u32 footer)2589 static int check_frame_end(u32 footer)
2590 {
2591 /* check frame_end marker */
2592 if (!(footer & BIT(30)))
2593 return -EIO;
2594
2595 return check_response(footer);
2596 }
2597
sdw_cdns_check_write_response(struct device * dev,u8 * dma_buffer,int dma_buffer_size,int num_frames)2598 int sdw_cdns_check_write_response(struct device *dev, u8 *dma_buffer,
2599 int dma_buffer_size, int num_frames)
2600 {
2601 u32 *p_data;
2602 int counter;
2603 u32 header;
2604 u32 footer;
2605 int ret;
2606 int i;
2607
2608 /* paranoia check on buffer size */
2609 if (dma_buffer_size != num_frames * 8)
2610 return -EINVAL;
2611
2612 counter = CDNS_BPT_ROLLING_COUNTER_START;
2613 p_data = (u32 *)dma_buffer;
2614
2615 for (i = 0; i < num_frames; i++) {
2616 header = *p_data++;
2617 footer = *p_data++;
2618
2619 ret = check_frame_start(header, counter);
2620 if (ret < 0) {
2621 dev_err(dev, "%s: bad frame %d/%d start header %x\n",
2622 __func__, i + 1, num_frames, header);
2623 return ret;
2624 }
2625
2626 ret = check_frame_end(footer);
2627 if (ret < 0) {
2628 dev_err(dev, "%s: bad frame %d/%d end footer %x\n",
2629 __func__, i + 1, num_frames, footer);
2630 return ret;
2631 }
2632
2633 counter++;
2634 counter &= GENMASK(3, 0);
2635 }
2636 return 0;
2637 }
2638 EXPORT_SYMBOL(sdw_cdns_check_write_response);
2639
extract_read_data(u32 * data,int num_bytes,u8 * buffer)2640 static u8 extract_read_data(u32 *data, int num_bytes, u8 *buffer)
2641 {
2642 u32 val;
2643 int i;
2644 u8 crc;
2645 u8 b0;
2646 u8 b1;
2647
2648 crc = SDW_CRC8_SEED;
2649
2650 /* process two bytes at a time */
2651 for (i = 0; i < num_bytes / 2; i++) {
2652 val = *data++;
2653
2654 b0 = val & 0xff;
2655 b1 = (val >> 8) & 0xff;
2656
2657 *buffer++ = b0;
2658 crc = crc8(sdw_crc8_lookup_msb, &b0, 1, crc);
2659
2660 *buffer++ = b1;
2661 crc = crc8(sdw_crc8_lookup_msb, &b1, 1, crc);
2662 }
2663 /* handle remaining byte if it exists */
2664 if (num_bytes & 1) {
2665 val = *data;
2666
2667 b0 = val & 0xff;
2668
2669 *buffer++ = b0;
2670 crc = crc8(sdw_crc8_lookup_msb, &b0, 1, crc);
2671 }
2672 return crc;
2673 }
2674
sdw_cdns_check_read_response(struct device * dev,u8 * dma_buffer,int dma_buffer_size,struct sdw_bpt_section * sec,int num_sec,int num_frames,int data_per_frame)2675 int sdw_cdns_check_read_response(struct device *dev, u8 *dma_buffer, int dma_buffer_size,
2676 struct sdw_bpt_section *sec, int num_sec, int num_frames,
2677 int data_per_frame)
2678 {
2679 int total_num_bytes = 0;
2680 int buffer_size = 0;
2681 int sec_index;
2682 u32 *p_data;
2683 u8 *p_buf;
2684 int counter;
2685 u32 header;
2686 u32 footer;
2687 u8 expected_crc;
2688 u8 crc;
2689 int len;
2690 int ret;
2691 int i;
2692
2693 counter = CDNS_BPT_ROLLING_COUNTER_START;
2694 p_data = (u32 *)dma_buffer;
2695
2696 sec_index = 0;
2697 p_buf = sec[sec_index].buf;
2698 buffer_size = sec[sec_index].len;
2699
2700 for (i = 0; i < num_frames; i++) {
2701 header = *p_data++;
2702
2703 ret = check_frame_start(header, counter);
2704 if (ret < 0) {
2705 dev_err(dev, "%s: bad frame %d/%d start header %x\n",
2706 __func__, i + 1, num_frames, header);
2707 return ret;
2708 }
2709
2710 len = data_per_frame;
2711 if (total_num_bytes + data_per_frame > buffer_size)
2712 len = buffer_size - total_num_bytes;
2713
2714 crc = extract_read_data(p_data, len, p_buf);
2715
2716 p_data += (len + 1) / 2;
2717 expected_crc = *p_data++ & 0xff;
2718
2719 if (crc != expected_crc) {
2720 dev_err(dev, "%s: bad frame %d/%d crc %#x expected %#x\n",
2721 __func__, i + 1, num_frames, crc, expected_crc);
2722 return -EIO;
2723 }
2724
2725 p_buf += len;
2726 total_num_bytes += len;
2727
2728 footer = *p_data++;
2729 ret = check_frame_end(footer);
2730 if (ret < 0) {
2731 dev_err(dev, "%s: bad frame %d/%d end footer %x\n",
2732 __func__, i + 1, num_frames, footer);
2733 return ret;
2734 }
2735
2736 counter++;
2737 counter &= GENMASK(3, 0);
2738
2739 if (buffer_size == total_num_bytes && (i + 1) < num_frames) {
2740 sec_index++;
2741 if (sec_index >= num_sec) {
2742 dev_err(dev, "%s: incorrect section index %d i %d\n",
2743 __func__, sec_index, i);
2744 return -EINVAL;
2745 }
2746 p_buf = sec[sec_index].buf;
2747 buffer_size = sec[sec_index].len;
2748 total_num_bytes = 0;
2749 }
2750 }
2751 return 0;
2752 }
2753 EXPORT_SYMBOL(sdw_cdns_check_read_response);
2754
2755 MODULE_LICENSE("Dual BSD/GPL");
2756 MODULE_DESCRIPTION("Cadence Soundwire Library");
2757