1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #ifndef __RTW89_FW_H__
6 #define __RTW89_FW_H__
7
8 #include "core.h"
9
10 enum rtw89_fw_dl_status {
11 RTW89_FWDL_INITIAL_STATE = 0,
12 RTW89_FWDL_FWDL_ONGOING = 1,
13 RTW89_FWDL_CHECKSUM_FAIL = 2,
14 RTW89_FWDL_SECURITY_FAIL = 3,
15 RTW89_FWDL_CV_NOT_MATCH = 4,
16 RTW89_FWDL_RSVD0 = 5,
17 RTW89_FWDL_WCPU_FWDL_RDY = 6,
18 RTW89_FWDL_WCPU_FW_INIT_RDY = 7
19 };
20
21 struct rtw89_c2hreg_hdr {
22 u32 w0;
23 };
24
25 #define RTW89_C2HREG_HDR_FUNC_MASK GENMASK(6, 0)
26 #define RTW89_C2HREG_HDR_ACK BIT(7)
27 #define RTW89_C2HREG_HDR_LEN_MASK GENMASK(11, 8)
28 #define RTW89_C2HREG_HDR_SEQ_MASK GENMASK(15, 12)
29
30 struct rtw89_c2hreg_phycap {
31 u32 w0;
32 u32 w1;
33 u32 w2;
34 u32 w3;
35 } __packed;
36
37 #define RTW89_C2HREG_PHYCAP_W0_FUNC GENMASK(6, 0)
38 #define RTW89_C2HREG_PHYCAP_W0_ACK BIT(7)
39 #define RTW89_C2HREG_PHYCAP_W0_LEN GENMASK(11, 8)
40 #define RTW89_C2HREG_PHYCAP_W0_SEQ GENMASK(15, 12)
41 #define RTW89_C2HREG_PHYCAP_W0_RX_NSS GENMASK(23, 16)
42 #define RTW89_C2HREG_PHYCAP_W0_BW GENMASK(31, 24)
43 #define RTW89_C2HREG_PHYCAP_W1_TX_NSS GENMASK(7, 0)
44 #define RTW89_C2HREG_PHYCAP_W1_PROT GENMASK(15, 8)
45 #define RTW89_C2HREG_PHYCAP_W1_NIC GENMASK(23, 16)
46 #define RTW89_C2HREG_PHYCAP_W1_WL_FUNC GENMASK(31, 24)
47 #define RTW89_C2HREG_PHYCAP_W2_HW_TYPE GENMASK(7, 0)
48 #define RTW89_C2HREG_PHYCAP_W3_ANT_TX_NUM GENMASK(15, 8)
49 #define RTW89_C2HREG_PHYCAP_W3_ANT_RX_NUM GENMASK(23, 16)
50 #define RTW89_C2HREG_PHYCAP_W3_BAND_SEL GENMASK(31, 24)
51
52 #define RTW89_C2HREG_PHYCAP_P1_W0_B1_RX_NSS GENMASK(23, 16)
53 #define RTW89_C2HREG_PHYCAP_P1_W0_B1_BW GENMASK(31, 24)
54 #define RTW89_C2HREG_PHYCAP_P1_W1_B1_TX_NSS GENMASK(7, 0)
55 #define RTW89_C2HREG_PHYCAP_P1_W1_B1_ANT_TX_NUM GENMASK(15, 8)
56 #define RTW89_C2HREG_PHYCAP_P1_W1_B1_ANT_RX_NUM GENMASK(23, 16)
57 #define RTW89_C2HREG_PHYCAP_P1_W1_B1_BAND_SEL GENMASK(31, 24)
58 #define RTW89_C2HREG_PHYCAP_P1_W2_QAM GENMASK(7, 0)
59 #define RTW89_C2HREG_PHYCAP_P1_W2_QAM_256 0x1
60 #define RTW89_C2HREG_PHYCAP_P1_W2_QAM_1024 0x2
61 #define RTW89_C2HREG_PHYCAP_P1_W2_QAM_4096 0x3
62 #define RTW89_C2HREG_PHYCAP_P1_W2_B1_QAM GENMASK(15, 8)
63
64 #define RTW89_C2HREG_AOAC_RPT_1_W0_KEY_IDX GENMASK(23, 16)
65 #define RTW89_C2HREG_AOAC_RPT_1_W1_IV_0 GENMASK(7, 0)
66 #define RTW89_C2HREG_AOAC_RPT_1_W1_IV_1 GENMASK(15, 8)
67 #define RTW89_C2HREG_AOAC_RPT_1_W1_IV_2 GENMASK(23, 16)
68 #define RTW89_C2HREG_AOAC_RPT_1_W1_IV_3 GENMASK(31, 24)
69 #define RTW89_C2HREG_AOAC_RPT_1_W2_IV_4 GENMASK(7, 0)
70 #define RTW89_C2HREG_AOAC_RPT_1_W2_IV_5 GENMASK(15, 8)
71 #define RTW89_C2HREG_AOAC_RPT_1_W2_IV_6 GENMASK(23, 16)
72 #define RTW89_C2HREG_AOAC_RPT_1_W2_IV_7 GENMASK(31, 24)
73 #define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_0 GENMASK(7, 0)
74 #define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_1 GENMASK(15, 8)
75 #define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_2 GENMASK(23, 16)
76 #define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_3 GENMASK(31, 24)
77 #define RTW89_C2HREG_AOAC_RPT_2_W0_PTK_IV_4 GENMASK(23, 16)
78 #define RTW89_C2HREG_AOAC_RPT_2_W0_PTK_IV_5 GENMASK(31, 24)
79 #define RTW89_C2HREG_AOAC_RPT_2_W1_PTK_IV_6 GENMASK(7, 0)
80 #define RTW89_C2HREG_AOAC_RPT_2_W1_PTK_IV_7 GENMASK(15, 8)
81 #define RTW89_C2HREG_AOAC_RPT_2_W1_IGTK_IPN_IV_0 GENMASK(23, 16)
82 #define RTW89_C2HREG_AOAC_RPT_2_W1_IGTK_IPN_IV_1 GENMASK(31, 24)
83 #define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_2 GENMASK(7, 0)
84 #define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_3 GENMASK(15, 8)
85 #define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_4 GENMASK(23, 16)
86 #define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_5 GENMASK(31, 24)
87 #define RTW89_C2HREG_AOAC_RPT_2_W3_IGTK_IPN_IV_6 GENMASK(7, 0)
88 #define RTW89_C2HREG_AOAC_RPT_2_W3_IGTK_IPN_IV_7 GENMASK(15, 8)
89
90 struct rtw89_h2creg_hdr {
91 u32 w0;
92 };
93
94 #define RTW89_H2CREG_HDR_FUNC_MASK GENMASK(6, 0)
95 #define RTW89_H2CREG_HDR_LEN_MASK GENMASK(11, 8)
96
97 struct rtw89_h2creg_sch_tx_en {
98 u32 w0;
99 u32 w1;
100 } __packed;
101
102 #define RTW89_H2CREG_SCH_TX_EN_W0_EN GENMASK(31, 16)
103 #define RTW89_H2CREG_SCH_TX_EN_W1_MASK GENMASK(15, 0)
104 #define RTW89_H2CREG_SCH_TX_EN_W1_BAND BIT(16)
105
106 #define RTW89_H2CREG_WOW_CPUIO_RX_CTRL_EN GENMASK(23, 16)
107
108 #define RTW89_H2CREG_GET_FEATURE_PART_NUM GENMASK(23, 16)
109
110 #define RTW89_H2CREG_MAX 4
111 #define RTW89_C2HREG_MAX 4
112 #define RTW89_C2HREG_HDR_LEN 2
113 #define RTW89_H2CREG_HDR_LEN 2
114 #define RTW89_C2H_TIMEOUT 1000000
115 struct rtw89_mac_c2h_info {
116 u8 id;
117 u8 content_len;
118 union {
119 u32 c2hreg[RTW89_C2HREG_MAX];
120 struct rtw89_c2hreg_hdr hdr;
121 struct rtw89_c2hreg_phycap phycap;
122 } u;
123 };
124
125 struct rtw89_mac_h2c_info {
126 u8 id;
127 u8 content_len;
128 union {
129 u32 h2creg[RTW89_H2CREG_MAX];
130 struct rtw89_h2creg_hdr hdr;
131 struct rtw89_h2creg_sch_tx_en sch_tx_en;
132 } u;
133 };
134
135 enum rtw89_mac_h2c_type {
136 RTW89_FWCMD_H2CREG_FUNC_H2CREG_LB = 0,
137 RTW89_FWCMD_H2CREG_FUNC_CNSL_CMD,
138 RTW89_FWCMD_H2CREG_FUNC_FWERR,
139 RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE,
140 RTW89_FWCMD_H2CREG_FUNC_GETPKT_INFORM,
141 RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN,
142 RTW89_FWCMD_H2CREG_FUNC_WOW_TRX_STOP,
143 RTW89_FWCMD_H2CREG_FUNC_AOAC_RPT_1,
144 RTW89_FWCMD_H2CREG_FUNC_AOAC_RPT_2,
145 RTW89_FWCMD_H2CREG_FUNC_AOAC_RPT_3_REQ,
146 RTW89_FWCMD_H2CREG_FUNC_WOW_CPUIO_RX_CTRL,
147 };
148
149 enum rtw89_mac_c2h_type {
150 RTW89_FWCMD_C2HREG_FUNC_C2HREG_LB = 0,
151 RTW89_FWCMD_C2HREG_FUNC_ERR_RPT,
152 RTW89_FWCMD_C2HREG_FUNC_ERR_MSG,
153 RTW89_FWCMD_C2HREG_FUNC_PHY_CAP,
154 RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT,
155 RTW89_FWCMD_C2HREG_FUNC_WOW_CPUIO_RX_ACK = 0xA,
156 RTW89_FWCMD_C2HREG_FUNC_PHY_CAP_PART1 = 0xC,
157 RTW89_FWCMD_C2HREG_FUNC_NULL = 0xFF,
158 };
159
160 enum rtw89_fw_c2h_category {
161 RTW89_C2H_CAT_TEST,
162 RTW89_C2H_CAT_MAC,
163 RTW89_C2H_CAT_OUTSRC,
164 };
165
166 enum rtw89_fw_log_level {
167 RTW89_FW_LOG_LEVEL_OFF,
168 RTW89_FW_LOG_LEVEL_CRT,
169 RTW89_FW_LOG_LEVEL_SER,
170 RTW89_FW_LOG_LEVEL_WARN,
171 RTW89_FW_LOG_LEVEL_LOUD,
172 RTW89_FW_LOG_LEVEL_TR,
173 };
174
175 enum rtw89_fw_log_path {
176 RTW89_FW_LOG_LEVEL_UART,
177 RTW89_FW_LOG_LEVEL_C2H,
178 RTW89_FW_LOG_LEVEL_SNI,
179 };
180
181 enum rtw89_fw_log_comp {
182 RTW89_FW_LOG_COMP_VER,
183 RTW89_FW_LOG_COMP_INIT,
184 RTW89_FW_LOG_COMP_TASK,
185 RTW89_FW_LOG_COMP_CNS,
186 RTW89_FW_LOG_COMP_H2C,
187 RTW89_FW_LOG_COMP_C2H,
188 RTW89_FW_LOG_COMP_TX,
189 RTW89_FW_LOG_COMP_RX,
190 RTW89_FW_LOG_COMP_IPSEC,
191 RTW89_FW_LOG_COMP_TIMER,
192 RTW89_FW_LOG_COMP_DBGPKT,
193 RTW89_FW_LOG_COMP_PS,
194 RTW89_FW_LOG_COMP_ERROR,
195 RTW89_FW_LOG_COMP_WOWLAN,
196 RTW89_FW_LOG_COMP_SECURE_BOOT,
197 RTW89_FW_LOG_COMP_BTC,
198 RTW89_FW_LOG_COMP_BB,
199 RTW89_FW_LOG_COMP_TWT,
200 RTW89_FW_LOG_COMP_RF,
201 RTW89_FW_LOG_COMP_MCC = 20,
202 RTW89_FW_LOG_COMP_SCAN = 28,
203 };
204
205 enum rtw89_pkt_offload_op {
206 RTW89_PKT_OFLD_OP_ADD,
207 RTW89_PKT_OFLD_OP_DEL,
208 RTW89_PKT_OFLD_OP_READ,
209
210 NUM_OF_RTW89_PKT_OFFLOAD_OP,
211 };
212
213 #define RTW89_PKT_OFLD_WAIT_TAG(pkt_id, pkt_op) \
214 ((pkt_id) * NUM_OF_RTW89_PKT_OFFLOAD_OP + (pkt_op))
215
216 enum rtw89_scanofld_notify_reason {
217 RTW89_SCAN_DWELL_NOTIFY,
218 RTW89_SCAN_PRE_TX_NOTIFY,
219 RTW89_SCAN_POST_TX_NOTIFY,
220 RTW89_SCAN_ENTER_CH_NOTIFY,
221 RTW89_SCAN_LEAVE_CH_NOTIFY,
222 RTW89_SCAN_END_SCAN_NOTIFY,
223 RTW89_SCAN_REPORT_NOTIFY,
224 RTW89_SCAN_CHKPT_NOTIFY,
225 RTW89_SCAN_ENTER_OP_NOTIFY,
226 RTW89_SCAN_LEAVE_OP_NOTIFY,
227 };
228
229 enum rtw89_scanofld_status {
230 RTW89_SCAN_STATUS_NOTIFY,
231 RTW89_SCAN_STATUS_SUCCESS,
232 RTW89_SCAN_STATUS_FAIL,
233 };
234
235 enum rtw89_chan_type {
236 RTW89_CHAN_OPERATE = 0,
237 RTW89_CHAN_ACTIVE,
238 RTW89_CHAN_DFS,
239 };
240
241 enum rtw89_p2pps_action {
242 RTW89_P2P_ACT_INIT = 0,
243 RTW89_P2P_ACT_UPDATE = 1,
244 RTW89_P2P_ACT_REMOVE = 2,
245 RTW89_P2P_ACT_TERMINATE = 3,
246 };
247
248 #define RTW89_DEFAULT_CQM_HYST 4
249 #define RTW89_DEFAULT_CQM_THOLD -70
250
251 enum rtw89_bcn_fltr_offload_mode {
252 RTW89_BCN_FLTR_OFFLOAD_MODE_0 = 0,
253 RTW89_BCN_FLTR_OFFLOAD_MODE_1,
254 RTW89_BCN_FLTR_OFFLOAD_MODE_2,
255 RTW89_BCN_FLTR_OFFLOAD_MODE_3,
256
257 RTW89_BCN_FLTR_OFFLOAD_MODE_DEFAULT = RTW89_BCN_FLTR_OFFLOAD_MODE_0,
258 };
259
260 enum rtw89_bcn_fltr_type {
261 RTW89_BCN_FLTR_BEACON_LOSS,
262 RTW89_BCN_FLTR_RSSI,
263 RTW89_BCN_FLTR_NOTIFY,
264 };
265
266 enum rtw89_bcn_fltr_rssi_event {
267 RTW89_BCN_FLTR_RSSI_NOT_CHANGED,
268 RTW89_BCN_FLTR_RSSI_HIGH,
269 RTW89_BCN_FLTR_RSSI_LOW,
270 };
271
272 #define FWDL_SECTION_MAX_NUM 10
273 #define FWDL_SECTION_CHKSUM_LEN 8
274 #define FWDL_SECTION_PER_PKT_LEN 2020
275
276 struct rtw89_fw_hdr_section_info {
277 u8 redl;
278 const u8 *addr;
279 u32 len;
280 u32 len_override;
281 u32 dladdr;
282 u32 mssc;
283 u8 type;
284 bool ignore;
285 const u8 *key_addr;
286 u32 key_len;
287 u32 key_idx;
288 };
289
290 struct rtw89_fw_bin_info {
291 u8 section_num;
292 u32 hdr_len;
293 bool dynamic_hdr_en;
294 u32 dynamic_hdr_len;
295 u8 idmem_share_mode;
296 bool dsp_checksum;
297 bool secure_section_exist;
298 struct rtw89_fw_hdr_section_info section_info[FWDL_SECTION_MAX_NUM];
299 };
300
301 struct rtw89_fw_macid_pause_grp {
302 __le32 pause_grp[4];
303 __le32 mask_grp[4];
304 } __packed;
305
306 struct rtw89_fw_macid_pause_sleep_grp {
307 struct {
308 __le32 pause_grp[4];
309 __le32 pause_mask_grp[4];
310 __le32 sleep_grp[4];
311 __le32 sleep_mask_grp[4];
312 } __packed n[4];
313 } __packed;
314
315 #define RTW89_H2C_MAX_SIZE 2048
316 #define RTW89_CHANNEL_TIME 45
317 #define RTW89_CHANNEL_TIME_6G 20
318 #define RTW89_DFS_CHAN_TIME 105
319 #define RTW89_OFF_CHAN_TIME 100
320 #define RTW89_DWELL_TIME 20
321 #define RTW89_DWELL_TIME_6G 10
322 #define RTW89_SCAN_WIDTH 0
323 #define RTW89_SCANOFLD_MAX_SSID 8
324 #define RTW89_SCANOFLD_MAX_IE_LEN 512
325 #define RTW89_SCANOFLD_PKT_NONE 0xFF
326 #define RTW89_SCANOFLD_DEBUG_MASK 0x1F
327 #define RTW89_CHAN_INVALID 0xFF
328 #define RTW89_MAC_CHINFO_SIZE 28
329 #define RTW89_MAC_CHINFO_SIZE_BE 32
330 #define RTW89_SCAN_LIST_GUARD 4
331 #define RTW89_SCAN_LIST_LIMIT(size) \
332 ((RTW89_H2C_MAX_SIZE / (size)) - RTW89_SCAN_LIST_GUARD)
333 #define RTW89_SCAN_LIST_LIMIT_AX RTW89_SCAN_LIST_LIMIT(RTW89_MAC_CHINFO_SIZE)
334 #define RTW89_SCAN_LIST_LIMIT_BE RTW89_SCAN_LIST_LIMIT(RTW89_MAC_CHINFO_SIZE_BE)
335
336 #define RTW89_BCN_LOSS_CNT 10
337
338 struct rtw89_mac_chinfo {
339 u8 period;
340 u8 dwell_time;
341 u8 central_ch;
342 u8 pri_ch;
343 u8 bw:3;
344 u8 notify_action:5;
345 u8 num_pkt:4;
346 u8 tx_pkt:1;
347 u8 pause_data:1;
348 u8 ch_band:2;
349 u8 probe_id;
350 u8 dfs_ch:1;
351 u8 tx_null:1;
352 u8 rand_seq_num:1;
353 u8 cfg_tx_pwr:1;
354 u8 rsvd0: 4;
355 u8 pkt_id[RTW89_SCANOFLD_MAX_SSID];
356 u16 tx_pwr_idx;
357 u8 rsvd1;
358 struct list_head list;
359 bool is_psc;
360 };
361
362 struct rtw89_mac_chinfo_be {
363 u8 period;
364 u8 dwell_time;
365 u8 central_ch;
366 u8 pri_ch;
367 u8 bw:3;
368 u8 ch_band:2;
369 u8 dfs_ch:1;
370 u8 pause_data:1;
371 u8 tx_null:1;
372 u8 rand_seq_num:1;
373 u8 notify_action:5;
374 u8 probe_id;
375 u8 leave_crit;
376 u8 chkpt_timer;
377 u8 leave_time;
378 u8 leave_th;
379 u16 tx_pkt_ctrl;
380 u8 pkt_id[RTW89_SCANOFLD_MAX_SSID];
381 u8 sw_def;
382 u16 fw_probe0_ssids;
383 u16 fw_probe0_shortssids;
384 u16 fw_probe0_bssids;
385
386 struct list_head list;
387 bool is_psc;
388 };
389
390 struct rtw89_pktofld_info {
391 struct list_head list;
392 u8 id;
393 bool wildcard_6ghz;
394
395 /* Below fields are for WiFi 6 chips 6 GHz RNR use only */
396 u8 ssid[IEEE80211_MAX_SSID_LEN];
397 u8 ssid_len;
398 u8 bssid[ETH_ALEN];
399 u16 channel_6ghz;
400 bool cancel;
401 };
402
403 struct rtw89_h2c_ra {
404 __le32 w0;
405 __le32 w1;
406 __le32 w2;
407 __le32 w3;
408 } __packed;
409
410 #define RTW89_H2C_RA_W0_IS_DIS BIT(0)
411 #define RTW89_H2C_RA_W0_MODE GENMASK(5, 1)
412 #define RTW89_H2C_RA_W0_BW_CAP GENMASK(7, 6)
413 #define RTW89_H2C_RA_W0_MACID GENMASK(15, 8)
414 #define RTW89_H2C_RA_W0_DCM BIT(16)
415 #define RTW89_H2C_RA_W0_ER BIT(17)
416 #define RTW89_H2C_RA_W0_INIT_RATE_LV GENMASK(19, 18)
417 #define RTW89_H2C_RA_W0_UPD_ALL BIT(20)
418 #define RTW89_H2C_RA_W0_SGI BIT(21)
419 #define RTW89_H2C_RA_W0_LDPC BIT(22)
420 #define RTW89_H2C_RA_W0_STBC BIT(23)
421 #define RTW89_H2C_RA_W0_SS_NUM GENMASK(26, 24)
422 #define RTW89_H2C_RA_W0_GILTF GENMASK(29, 27)
423 #define RTW89_H2C_RA_W0_UPD_BW_NSS_MASK BIT(30)
424 #define RTW89_H2C_RA_W0_UPD_MASK BIT(31)
425 #define RTW89_H2C_RA_W1_RAMASK_LO32 GENMASK(31, 0)
426 #define RTW89_H2C_RA_W2_RAMASK_HI32 GENMASK(30, 0)
427 #define RTW89_H2C_RA_W2_BFEE_CSI_CTL BIT(31)
428 #define RTW89_H2C_RA_W3_BAND_NUM GENMASK(7, 0)
429 #define RTW89_H2C_RA_W3_RA_CSI_RATE_EN BIT(8)
430 #define RTW89_H2C_RA_W3_FIXED_CSI_RATE_EN BIT(9)
431 #define RTW89_H2C_RA_W3_CR_TBL_SEL BIT(10)
432 #define RTW89_H2C_RA_W3_FIX_GILTF_EN BIT(11)
433 #define RTW89_H2C_RA_W3_FIX_GILTF GENMASK(14, 12)
434 #define RTW89_H2C_RA_W3_FIXED_CSI_MCS_SS_IDX GENMASK(23, 16)
435 #define RTW89_H2C_RA_W3_FIXED_CSI_MODE GENMASK(25, 24)
436 #define RTW89_H2C_RA_W3_FIXED_CSI_GI_LTF GENMASK(28, 26)
437 #define RTW89_H2C_RA_W3_FIXED_CSI_BW GENMASK(31, 29)
438
439 struct rtw89_h2c_ra_v1 {
440 struct rtw89_h2c_ra v0;
441 __le32 w4;
442 __le32 w5;
443 } __packed;
444
445 #define RTW89_H2C_RA_V1_W4_MODE_EHT GENMASK(6, 0)
446 #define RTW89_H2C_RA_V1_W4_BW_EHT GENMASK(10, 8)
447 #define RTW89_H2C_RA_V1_W4_RAMASK_UHL16 GENMASK(31, 16)
448 #define RTW89_H2C_RA_V1_W5_RAMASK_UHH16 GENMASK(15, 0)
449
RTW89_SET_FWCMD_SEC_IDX(void * cmd,u32 val)450 static inline void RTW89_SET_FWCMD_SEC_IDX(void *cmd, u32 val)
451 {
452 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 0));
453 }
454
RTW89_SET_FWCMD_SEC_OFFSET(void * cmd,u32 val)455 static inline void RTW89_SET_FWCMD_SEC_OFFSET(void *cmd, u32 val)
456 {
457 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8));
458 }
459
RTW89_SET_FWCMD_SEC_LEN(void * cmd,u32 val)460 static inline void RTW89_SET_FWCMD_SEC_LEN(void *cmd, u32 val)
461 {
462 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(23, 16));
463 }
464
RTW89_SET_FWCMD_SEC_TYPE(void * cmd,u32 val)465 static inline void RTW89_SET_FWCMD_SEC_TYPE(void *cmd, u32 val)
466 {
467 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(3, 0));
468 }
469
RTW89_SET_FWCMD_SEC_EXT_KEY(void * cmd,u32 val)470 static inline void RTW89_SET_FWCMD_SEC_EXT_KEY(void *cmd, u32 val)
471 {
472 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(4));
473 }
474
RTW89_SET_FWCMD_SEC_SPP_MODE(void * cmd,u32 val)475 static inline void RTW89_SET_FWCMD_SEC_SPP_MODE(void *cmd, u32 val)
476 {
477 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(5));
478 }
479
RTW89_SET_FWCMD_SEC_KEY0(void * cmd,u32 val)480 static inline void RTW89_SET_FWCMD_SEC_KEY0(void *cmd, u32 val)
481 {
482 le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(31, 0));
483 }
484
RTW89_SET_FWCMD_SEC_KEY1(void * cmd,u32 val)485 static inline void RTW89_SET_FWCMD_SEC_KEY1(void *cmd, u32 val)
486 {
487 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 0));
488 }
489
RTW89_SET_FWCMD_SEC_KEY2(void * cmd,u32 val)490 static inline void RTW89_SET_FWCMD_SEC_KEY2(void *cmd, u32 val)
491 {
492 le32p_replace_bits((__le32 *)(cmd) + 0x04, val, GENMASK(31, 0));
493 }
494
RTW89_SET_FWCMD_SEC_KEY3(void * cmd,u32 val)495 static inline void RTW89_SET_FWCMD_SEC_KEY3(void *cmd, u32 val)
496 {
497 le32p_replace_bits((__le32 *)(cmd) + 0x05, val, GENMASK(31, 0));
498 }
499
RTW89_SET_EDCA_SEL(void * cmd,u32 val)500 static inline void RTW89_SET_EDCA_SEL(void *cmd, u32 val)
501 {
502 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(1, 0));
503 }
504
RTW89_SET_EDCA_BAND(void * cmd,u32 val)505 static inline void RTW89_SET_EDCA_BAND(void *cmd, u32 val)
506 {
507 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(3));
508 }
509
RTW89_SET_EDCA_WMM(void * cmd,u32 val)510 static inline void RTW89_SET_EDCA_WMM(void *cmd, u32 val)
511 {
512 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(4));
513 }
514
RTW89_SET_EDCA_AC(void * cmd,u32 val)515 static inline void RTW89_SET_EDCA_AC(void *cmd, u32 val)
516 {
517 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(6, 5));
518 }
519
RTW89_SET_EDCA_PARAM(void * cmd,u32 val)520 static inline void RTW89_SET_EDCA_PARAM(void *cmd, u32 val)
521 {
522 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 0));
523 }
524 #define FW_EDCA_PARAM_TXOPLMT_MSK GENMASK(26, 16)
525 #define FW_EDCA_PARAM_CWMAX_MSK GENMASK(15, 12)
526 #define FW_EDCA_PARAM_CWMIN_MSK GENMASK(11, 8)
527 #define FW_EDCA_PARAM_AIFS_MSK GENMASK(7, 0)
528
529 #define FWDL_SECURITY_SECTION_TYPE 9
530 #define FWDL_SECURITY_SIGLEN 512
531 #define FWDL_SECURITY_CHKSUM_LEN 8
532
533 struct rtw89_fw_dynhdr_sec {
534 __le32 w0;
535 u8 content[];
536 } __packed;
537
538 struct rtw89_fw_dynhdr_hdr {
539 __le32 hdr_len;
540 __le32 setcion_count;
541 /* struct rtw89_fw_dynhdr_sec (nested flexible structures) */
542 } __packed;
543
544 struct rtw89_fw_hdr_section {
545 __le32 w0;
546 __le32 w1;
547 __le32 w2;
548 __le32 w3;
549 } __packed;
550
551 #define FWSECTION_HDR_W0_DL_ADDR GENMASK(31, 0)
552 #define FWSECTION_HDR_W1_METADATA GENMASK(31, 24)
553 #define FWSECTION_HDR_W1_SECTIONTYPE GENMASK(27, 24)
554 #define FWSECTION_HDR_W1_SEC_SIZE GENMASK(23, 0)
555 #define FWSECTION_HDR_W1_CHECKSUM BIT(28)
556 #define FWSECTION_HDR_W1_REDL BIT(29)
557 #define FWSECTION_HDR_W2_MSSC GENMASK(31, 0)
558
559 struct rtw89_fw_hdr {
560 __le32 w0;
561 __le32 w1;
562 __le32 w2;
563 __le32 w3;
564 __le32 w4;
565 __le32 w5;
566 __le32 w6;
567 __le32 w7;
568 struct rtw89_fw_hdr_section sections[];
569 /* struct rtw89_fw_dynhdr_hdr (optional) */
570 } __packed;
571
572 #define FW_HDR_W1_MAJOR_VERSION GENMASK(7, 0)
573 #define FW_HDR_W1_MINOR_VERSION GENMASK(15, 8)
574 #define FW_HDR_W1_SUBVERSION GENMASK(23, 16)
575 #define FW_HDR_W1_SUBINDEX GENMASK(31, 24)
576 #define FW_HDR_W2_COMMITID GENMASK(31, 0)
577 #define FW_HDR_W3_LEN GENMASK(23, 16)
578 #define FW_HDR_W3_HDR_VER GENMASK(31, 24)
579 #define FW_HDR_W4_MONTH GENMASK(7, 0)
580 #define FW_HDR_W4_DATE GENMASK(15, 8)
581 #define FW_HDR_W4_HOUR GENMASK(23, 16)
582 #define FW_HDR_W4_MIN GENMASK(31, 24)
583 #define FW_HDR_W5_YEAR GENMASK(31, 0)
584 #define FW_HDR_W6_SEC_NUM GENMASK(15, 8)
585 #define FW_HDR_W7_PART_SIZE GENMASK(15, 0)
586 #define FW_HDR_W7_DYN_HDR BIT(16)
587 #define FW_HDR_W7_IDMEM_SHARE_MODE GENMASK(21, 18)
588 #define FW_HDR_W7_CMD_VERSERION GENMASK(31, 24)
589
590 struct rtw89_fw_hdr_section_v1 {
591 __le32 w0;
592 __le32 w1;
593 __le32 w2;
594 __le32 w3;
595 } __packed;
596
597 #define FWSECTION_HDR_V1_W0_DL_ADDR GENMASK(31, 0)
598 #define FWSECTION_HDR_V1_W1_METADATA GENMASK(31, 24)
599 #define FWSECTION_HDR_V1_W1_SECTIONTYPE GENMASK(27, 24)
600 #define FWSECTION_HDR_V1_W1_SEC_SIZE GENMASK(23, 0)
601 #define FWSECTION_HDR_V1_W1_CHECKSUM BIT(28)
602 #define FWSECTION_HDR_V1_W1_REDL BIT(29)
603 #define FWSECTION_HDR_V1_W2_MSSC GENMASK(7, 0)
604 #define FORMATTED_MSSC 0xFF
605 #define FORMATTED_MSSC_MASK GENMASK(7, 0)
606 #define FWSECTION_HDR_V1_W2_BBMCU_IDX GENMASK(27, 24)
607
608 struct rtw89_fw_hdr_v1 {
609 __le32 w0;
610 __le32 w1;
611 __le32 w2;
612 __le32 w3;
613 __le32 w4;
614 __le32 w5;
615 __le32 w6;
616 __le32 w7;
617 __le32 w8;
618 __le32 w9;
619 __le32 w10;
620 __le32 w11;
621 struct rtw89_fw_hdr_section_v1 sections[];
622 } __packed;
623
624 #define FW_HDR_V1_W1_MAJOR_VERSION GENMASK(7, 0)
625 #define FW_HDR_V1_W1_MINOR_VERSION GENMASK(15, 8)
626 #define FW_HDR_V1_W1_SUBVERSION GENMASK(23, 16)
627 #define FW_HDR_V1_W1_SUBINDEX GENMASK(31, 24)
628 #define FW_HDR_V1_W2_COMMITID GENMASK(31, 0)
629 #define FW_HDR_V1_W3_CMD_VERSERION GENMASK(23, 16)
630 #define FW_HDR_V1_W3_HDR_VER GENMASK(31, 24)
631 #define FW_HDR_V1_W4_MONTH GENMASK(7, 0)
632 #define FW_HDR_V1_W4_DATE GENMASK(15, 8)
633 #define FW_HDR_V1_W4_HOUR GENMASK(23, 16)
634 #define FW_HDR_V1_W4_MIN GENMASK(31, 24)
635 #define FW_HDR_V1_W5_YEAR GENMASK(15, 0)
636 #define FW_HDR_V1_W5_HDR_SIZE GENMASK(31, 16)
637 #define FW_HDR_V1_W6_SEC_NUM GENMASK(15, 8)
638 #define FW_HDR_V1_W6_DSP_CHKSUM BIT(24)
639 #define FW_HDR_V1_W7_PART_SIZE GENMASK(15, 0)
640 #define FW_HDR_V1_W7_DYN_HDR BIT(16)
641 #define FW_HDR_V1_W7_IDMEM_SHARE_MODE GENMASK(21, 18)
642
643 enum rtw89_fw_mss_pool_rmp_tbl_type {
644 MSS_POOL_RMP_TBL_BITMASK = 0x0,
645 MSS_POOL_RMP_TBL_RECORD = 0x1,
646 };
647
648 #define FWDL_MSS_POOL_DEFKEYSETS_SIZE 8
649
650 struct rtw89_fw_mss_pool_hdr {
651 u8 signature[8]; /* equal to mss_signature[] */
652 __le32 rmp_tbl_offset;
653 __le32 key_raw_offset;
654 u8 defen;
655 u8 rsvd[3];
656 u8 rmpfmt; /* enum rtw89_fw_mss_pool_rmp_tbl_type */
657 u8 mssdev_max;
658 __le16 keypair_num;
659 __le16 msscust_max;
660 __le16 msskey_num_max;
661 __le32 rsvd3;
662 u8 rmp_tbl[];
663 } __packed;
664
665 union rtw89_fw_section_mssc_content {
666 struct {
667 u8 pad[0x20];
668 u8 bit_in_chip_list;
669 u8 ver;
670 } __packed blacklist;
671 struct {
672 u8 pad[58];
673 __le32 v;
674 } __packed sb_sel_ver;
675 struct {
676 u8 pad[60];
677 __le16 v;
678 } __packed key_sign_len;
679 } __packed;
680
681 struct rtw89_fw_blacklist {
682 u8 ver;
683 u8 list[32];
684 };
685
686 extern const struct rtw89_fw_blacklist rtw89_fw_blacklist_default;
687
SET_CTRL_INFO_MACID(void * table,u32 val)688 static inline void SET_CTRL_INFO_MACID(void *table, u32 val)
689 {
690 le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0));
691 }
692
SET_CTRL_INFO_OPERATION(void * table,u32 val)693 static inline void SET_CTRL_INFO_OPERATION(void *table, u32 val)
694 {
695 le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7));
696 }
697 #define SET_CMC_TBL_MASK_DATARATE GENMASK(8, 0)
SET_CMC_TBL_DATARATE(void * table,u32 val)698 static inline void SET_CMC_TBL_DATARATE(void *table, u32 val)
699 {
700 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(8, 0));
701 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATARATE,
702 GENMASK(8, 0));
703 }
704 #define SET_CMC_TBL_MASK_FORCE_TXOP BIT(0)
SET_CMC_TBL_FORCE_TXOP(void * table,u32 val)705 static inline void SET_CMC_TBL_FORCE_TXOP(void *table, u32 val)
706 {
707 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(9));
708 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_FORCE_TXOP,
709 BIT(9));
710 }
711 #define SET_CMC_TBL_MASK_DATA_BW GENMASK(1, 0)
SET_CMC_TBL_DATA_BW(void * table,u32 val)712 static inline void SET_CMC_TBL_DATA_BW(void *table, u32 val)
713 {
714 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(11, 10));
715 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_BW,
716 GENMASK(11, 10));
717 }
718 #define SET_CMC_TBL_MASK_DATA_GI_LTF GENMASK(2, 0)
SET_CMC_TBL_DATA_GI_LTF(void * table,u32 val)719 static inline void SET_CMC_TBL_DATA_GI_LTF(void *table, u32 val)
720 {
721 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 12));
722 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_GI_LTF,
723 GENMASK(14, 12));
724 }
725 #define SET_CMC_TBL_MASK_DARF_TC_INDEX BIT(0)
SET_CMC_TBL_DARF_TC_INDEX(void * table,u32 val)726 static inline void SET_CMC_TBL_DARF_TC_INDEX(void *table, u32 val)
727 {
728 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15));
729 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DARF_TC_INDEX,
730 BIT(15));
731 }
732 #define SET_CMC_TBL_MASK_ARFR_CTRL GENMASK(3, 0)
SET_CMC_TBL_ARFR_CTRL(void * table,u32 val)733 static inline void SET_CMC_TBL_ARFR_CTRL(void *table, u32 val)
734 {
735 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(19, 16));
736 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ARFR_CTRL,
737 GENMASK(19, 16));
738 }
739 #define SET_CMC_TBL_MASK_ACQ_RPT_EN BIT(0)
SET_CMC_TBL_ACQ_RPT_EN(void * table,u32 val)740 static inline void SET_CMC_TBL_ACQ_RPT_EN(void *table, u32 val)
741 {
742 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(20));
743 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ACQ_RPT_EN,
744 BIT(20));
745 }
746 #define SET_CMC_TBL_MASK_MGQ_RPT_EN BIT(0)
SET_CMC_TBL_MGQ_RPT_EN(void * table,u32 val)747 static inline void SET_CMC_TBL_MGQ_RPT_EN(void *table, u32 val)
748 {
749 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(21));
750 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_MGQ_RPT_EN,
751 BIT(21));
752 }
753 #define SET_CMC_TBL_MASK_ULQ_RPT_EN BIT(0)
SET_CMC_TBL_ULQ_RPT_EN(void * table,u32 val)754 static inline void SET_CMC_TBL_ULQ_RPT_EN(void *table, u32 val)
755 {
756 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(22));
757 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ULQ_RPT_EN,
758 BIT(22));
759 }
760 #define SET_CMC_TBL_MASK_TWTQ_RPT_EN BIT(0)
SET_CMC_TBL_TWTQ_RPT_EN(void * table,u32 val)761 static inline void SET_CMC_TBL_TWTQ_RPT_EN(void *table, u32 val)
762 {
763 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(23));
764 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TWTQ_RPT_EN,
765 BIT(23));
766 }
767 #define SET_CMC_TBL_MASK_DISRTSFB BIT(0)
SET_CMC_TBL_DISRTSFB(void * table,u32 val)768 static inline void SET_CMC_TBL_DISRTSFB(void *table, u32 val)
769 {
770 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(25));
771 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISRTSFB,
772 BIT(25));
773 }
774 #define SET_CMC_TBL_MASK_DISDATAFB BIT(0)
SET_CMC_TBL_DISDATAFB(void * table,u32 val)775 static inline void SET_CMC_TBL_DISDATAFB(void *table, u32 val)
776 {
777 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(26));
778 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISDATAFB,
779 BIT(26));
780 }
781 #define SET_CMC_TBL_MASK_TRYRATE BIT(0)
SET_CMC_TBL_TRYRATE(void * table,u32 val)782 static inline void SET_CMC_TBL_TRYRATE(void *table, u32 val)
783 {
784 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(27));
785 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TRYRATE,
786 BIT(27));
787 }
788 #define SET_CMC_TBL_MASK_AMPDU_DENSITY GENMASK(3, 0)
SET_CMC_TBL_AMPDU_DENSITY(void * table,u32 val)789 static inline void SET_CMC_TBL_AMPDU_DENSITY(void *table, u32 val)
790 {
791 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 28));
792 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_AMPDU_DENSITY,
793 GENMASK(31, 28));
794 }
795 #define SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE GENMASK(8, 0)
SET_CMC_TBL_DATA_RTY_LOWEST_RATE(void * table,u32 val)796 static inline void SET_CMC_TBL_DATA_RTY_LOWEST_RATE(void *table, u32 val)
797 {
798 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(8, 0));
799 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE,
800 GENMASK(8, 0));
801 }
802 #define SET_CMC_TBL_MASK_AMPDU_TIME_SEL BIT(0)
SET_CMC_TBL_AMPDU_TIME_SEL(void * table,u32 val)803 static inline void SET_CMC_TBL_AMPDU_TIME_SEL(void *table, u32 val)
804 {
805 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(9));
806 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_TIME_SEL,
807 BIT(9));
808 }
809 #define SET_CMC_TBL_MASK_AMPDU_LEN_SEL BIT(0)
SET_CMC_TBL_AMPDU_LEN_SEL(void * table,u32 val)810 static inline void SET_CMC_TBL_AMPDU_LEN_SEL(void *table, u32 val)
811 {
812 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(10));
813 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_LEN_SEL,
814 BIT(10));
815 }
816 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL BIT(0)
SET_CMC_TBL_RTS_TXCNT_LMT_SEL(void * table,u32 val)817 static inline void SET_CMC_TBL_RTS_TXCNT_LMT_SEL(void *table, u32 val)
818 {
819 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(11));
820 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL,
821 BIT(11));
822 }
823 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT GENMASK(3, 0)
SET_CMC_TBL_RTS_TXCNT_LMT(void * table,u32 val)824 static inline void SET_CMC_TBL_RTS_TXCNT_LMT(void *table, u32 val)
825 {
826 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(15, 12));
827 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT,
828 GENMASK(15, 12));
829 }
830 #define SET_CMC_TBL_MASK_RTSRATE GENMASK(8, 0)
SET_CMC_TBL_RTSRATE(void * table,u32 val)831 static inline void SET_CMC_TBL_RTSRATE(void *table, u32 val)
832 {
833 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(24, 16));
834 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTSRATE,
835 GENMASK(24, 16));
836 }
837 #define SET_CMC_TBL_MASK_VCS_STBC BIT(0)
SET_CMC_TBL_VCS_STBC(void * table,u32 val)838 static inline void SET_CMC_TBL_VCS_STBC(void *table, u32 val)
839 {
840 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(27));
841 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_VCS_STBC,
842 BIT(27));
843 }
844 #define SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE GENMASK(3, 0)
SET_CMC_TBL_RTS_RTY_LOWEST_RATE(void * table,u32 val)845 static inline void SET_CMC_TBL_RTS_RTY_LOWEST_RATE(void *table, u32 val)
846 {
847 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 28));
848 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE,
849 GENMASK(31, 28));
850 }
851 #define SET_CMC_TBL_MASK_DATA_TX_CNT_LMT GENMASK(5, 0)
SET_CMC_TBL_DATA_TX_CNT_LMT(void * table,u32 val)852 static inline void SET_CMC_TBL_DATA_TX_CNT_LMT(void *table, u32 val)
853 {
854 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(5, 0));
855 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TX_CNT_LMT,
856 GENMASK(5, 0));
857 }
858 #define SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL BIT(0)
SET_CMC_TBL_DATA_TXCNT_LMT_SEL(void * table,u32 val)859 static inline void SET_CMC_TBL_DATA_TXCNT_LMT_SEL(void *table, u32 val)
860 {
861 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(6));
862 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL,
863 BIT(6));
864 }
865 #define SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL BIT(0)
SET_CMC_TBL_MAX_AGG_NUM_SEL(void * table,u32 val)866 static inline void SET_CMC_TBL_MAX_AGG_NUM_SEL(void *table, u32 val)
867 {
868 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(7));
869 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL,
870 BIT(7));
871 }
872 #define SET_CMC_TBL_MASK_RTS_EN BIT(0)
SET_CMC_TBL_RTS_EN(void * table,u32 val)873 static inline void SET_CMC_TBL_RTS_EN(void *table, u32 val)
874 {
875 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(8));
876 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_EN,
877 BIT(8));
878 }
879 #define SET_CMC_TBL_MASK_CTS2SELF_EN BIT(0)
SET_CMC_TBL_CTS2SELF_EN(void * table,u32 val)880 static inline void SET_CMC_TBL_CTS2SELF_EN(void *table, u32 val)
881 {
882 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(9));
883 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CTS2SELF_EN,
884 BIT(9));
885 }
886 #define SET_CMC_TBL_MASK_CCA_RTS GENMASK(1, 0)
SET_CMC_TBL_CCA_RTS(void * table,u32 val)887 static inline void SET_CMC_TBL_CCA_RTS(void *table, u32 val)
888 {
889 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(11, 10));
890 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CCA_RTS,
891 GENMASK(11, 10));
892 }
893 #define SET_CMC_TBL_MASK_HW_RTS_EN BIT(0)
SET_CMC_TBL_HW_RTS_EN(void * table,u32 val)894 static inline void SET_CMC_TBL_HW_RTS_EN(void *table, u32 val)
895 {
896 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(12));
897 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_HW_RTS_EN,
898 BIT(12));
899 }
900 #define SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE GENMASK(1, 0)
SET_CMC_TBL_RTS_DROP_DATA_MODE(void * table,u32 val)901 static inline void SET_CMC_TBL_RTS_DROP_DATA_MODE(void *table, u32 val)
902 {
903 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(14, 13));
904 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE,
905 GENMASK(14, 13));
906 }
907 #define SET_CMC_TBL_MASK_AMPDU_MAX_LEN GENMASK(10, 0)
SET_CMC_TBL_AMPDU_MAX_LEN(void * table,u32 val)908 static inline void SET_CMC_TBL_AMPDU_MAX_LEN(void *table, u32 val)
909 {
910 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 16));
911 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_LEN,
912 GENMASK(26, 16));
913 }
914 #define SET_CMC_TBL_MASK_UL_MU_DIS BIT(0)
SET_CMC_TBL_UL_MU_DIS(void * table,u32 val)915 static inline void SET_CMC_TBL_UL_MU_DIS(void *table, u32 val)
916 {
917 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27));
918 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_UL_MU_DIS,
919 BIT(27));
920 }
921 #define SET_CMC_TBL_MASK_AMPDU_MAX_TIME GENMASK(3, 0)
SET_CMC_TBL_AMPDU_MAX_TIME(void * table,u32 val)922 static inline void SET_CMC_TBL_AMPDU_MAX_TIME(void *table, u32 val)
923 {
924 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(31, 28));
925 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_TIME,
926 GENMASK(31, 28));
927 }
928 #define SET_CMC_TBL_MASK_MAX_AGG_NUM GENMASK(7, 0)
SET_CMC_TBL_MAX_AGG_NUM(void * table,u32 val)929 static inline void SET_CMC_TBL_MAX_AGG_NUM(void *table, u32 val)
930 {
931 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(7, 0));
932 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_MAX_AGG_NUM,
933 GENMASK(7, 0));
934 }
935 #define SET_CMC_TBL_MASK_BA_BMAP GENMASK(1, 0)
SET_CMC_TBL_BA_BMAP(void * table,u32 val)936 static inline void SET_CMC_TBL_BA_BMAP(void *table, u32 val)
937 {
938 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(9, 8));
939 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BA_BMAP,
940 GENMASK(9, 8));
941 }
942 #define SET_CMC_TBL_MASK_VO_LFTIME_SEL GENMASK(2, 0)
SET_CMC_TBL_VO_LFTIME_SEL(void * table,u32 val)943 static inline void SET_CMC_TBL_VO_LFTIME_SEL(void *table, u32 val)
944 {
945 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(18, 16));
946 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VO_LFTIME_SEL,
947 GENMASK(18, 16));
948 }
949 #define SET_CMC_TBL_MASK_VI_LFTIME_SEL GENMASK(2, 0)
SET_CMC_TBL_VI_LFTIME_SEL(void * table,u32 val)950 static inline void SET_CMC_TBL_VI_LFTIME_SEL(void *table, u32 val)
951 {
952 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(21, 19));
953 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VI_LFTIME_SEL,
954 GENMASK(21, 19));
955 }
956 #define SET_CMC_TBL_MASK_BE_LFTIME_SEL GENMASK(2, 0)
SET_CMC_TBL_BE_LFTIME_SEL(void * table,u32 val)957 static inline void SET_CMC_TBL_BE_LFTIME_SEL(void *table, u32 val)
958 {
959 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(24, 22));
960 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BE_LFTIME_SEL,
961 GENMASK(24, 22));
962 }
963 #define SET_CMC_TBL_MASK_BK_LFTIME_SEL GENMASK(2, 0)
SET_CMC_TBL_BK_LFTIME_SEL(void * table,u32 val)964 static inline void SET_CMC_TBL_BK_LFTIME_SEL(void *table, u32 val)
965 {
966 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(27, 25));
967 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BK_LFTIME_SEL,
968 GENMASK(27, 25));
969 }
970 #define SET_CMC_TBL_MASK_SECTYPE GENMASK(3, 0)
SET_CMC_TBL_SECTYPE(void * table,u32 val)971 static inline void SET_CMC_TBL_SECTYPE(void *table, u32 val)
972 {
973 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 28));
974 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_SECTYPE,
975 GENMASK(31, 28));
976 }
977 #define SET_CMC_TBL_MASK_MULTI_PORT_ID GENMASK(2, 0)
SET_CMC_TBL_MULTI_PORT_ID(void * table,u32 val)978 static inline void SET_CMC_TBL_MULTI_PORT_ID(void *table, u32 val)
979 {
980 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(2, 0));
981 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MULTI_PORT_ID,
982 GENMASK(2, 0));
983 }
984 #define SET_CMC_TBL_MASK_BMC BIT(0)
SET_CMC_TBL_BMC(void * table,u32 val)985 static inline void SET_CMC_TBL_BMC(void *table, u32 val)
986 {
987 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(3));
988 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_BMC,
989 BIT(3));
990 }
991 #define SET_CMC_TBL_MASK_MBSSID GENMASK(3, 0)
SET_CMC_TBL_MBSSID(void * table,u32 val)992 static inline void SET_CMC_TBL_MBSSID(void *table, u32 val)
993 {
994 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 4));
995 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MBSSID,
996 GENMASK(7, 4));
997 }
998 #define SET_CMC_TBL_MASK_NAVUSEHDR BIT(0)
SET_CMC_TBL_NAVUSEHDR(void * table,u32 val)999 static inline void SET_CMC_TBL_NAVUSEHDR(void *table, u32 val)
1000 {
1001 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8));
1002 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_NAVUSEHDR,
1003 BIT(8));
1004 }
1005 #define SET_CMC_TBL_MASK_TXPWR_MODE GENMASK(2, 0)
SET_CMC_TBL_TXPWR_MODE(void * table,u32 val)1006 static inline void SET_CMC_TBL_TXPWR_MODE(void *table, u32 val)
1007 {
1008 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(11, 9));
1009 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_TXPWR_MODE,
1010 GENMASK(11, 9));
1011 }
1012 #define SET_CMC_TBL_MASK_DATA_DCM BIT(0)
SET_CMC_TBL_DATA_DCM(void * table,u32 val)1013 static inline void SET_CMC_TBL_DATA_DCM(void *table, u32 val)
1014 {
1015 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(12));
1016 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_DCM,
1017 BIT(12));
1018 }
1019 #define SET_CMC_TBL_MASK_DATA_ER BIT(0)
SET_CMC_TBL_DATA_ER(void * table,u32 val)1020 static inline void SET_CMC_TBL_DATA_ER(void *table, u32 val)
1021 {
1022 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(13));
1023 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_ER,
1024 BIT(13));
1025 }
1026 #define SET_CMC_TBL_MASK_DATA_LDPC BIT(0)
SET_CMC_TBL_DATA_LDPC(void * table,u32 val)1027 static inline void SET_CMC_TBL_DATA_LDPC(void *table, u32 val)
1028 {
1029 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(14));
1030 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_LDPC,
1031 BIT(14));
1032 }
1033 #define SET_CMC_TBL_MASK_DATA_STBC BIT(0)
SET_CMC_TBL_DATA_STBC(void * table,u32 val)1034 static inline void SET_CMC_TBL_DATA_STBC(void *table, u32 val)
1035 {
1036 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15));
1037 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_STBC,
1038 BIT(15));
1039 }
1040 #define SET_CMC_TBL_MASK_A_CTRL_BQR BIT(0)
SET_CMC_TBL_A_CTRL_BQR(void * table,u32 val)1041 static inline void SET_CMC_TBL_A_CTRL_BQR(void *table, u32 val)
1042 {
1043 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(16));
1044 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BQR,
1045 BIT(16));
1046 }
1047 #define SET_CMC_TBL_MASK_A_CTRL_UPH BIT(0)
SET_CMC_TBL_A_CTRL_UPH(void * table,u32 val)1048 static inline void SET_CMC_TBL_A_CTRL_UPH(void *table, u32 val)
1049 {
1050 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(17));
1051 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_UPH,
1052 BIT(17));
1053 }
1054 #define SET_CMC_TBL_MASK_A_CTRL_BSR BIT(0)
SET_CMC_TBL_A_CTRL_BSR(void * table,u32 val)1055 static inline void SET_CMC_TBL_A_CTRL_BSR(void *table, u32 val)
1056 {
1057 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(18));
1058 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BSR,
1059 BIT(18));
1060 }
1061 #define SET_CMC_TBL_MASK_A_CTRL_CAS BIT(0)
SET_CMC_TBL_A_CTRL_CAS(void * table,u32 val)1062 static inline void SET_CMC_TBL_A_CTRL_CAS(void *table, u32 val)
1063 {
1064 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(19));
1065 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_CAS,
1066 BIT(19));
1067 }
1068 #define SET_CMC_TBL_MASK_DATA_BW_ER BIT(0)
SET_CMC_TBL_DATA_BW_ER(void * table,u32 val)1069 static inline void SET_CMC_TBL_DATA_BW_ER(void *table, u32 val)
1070 {
1071 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(20));
1072 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_BW_ER,
1073 BIT(20));
1074 }
1075 #define SET_CMC_TBL_MASK_LSIG_TXOP_EN BIT(0)
SET_CMC_TBL_LSIG_TXOP_EN(void * table,u32 val)1076 static inline void SET_CMC_TBL_LSIG_TXOP_EN(void *table, u32 val)
1077 {
1078 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(21));
1079 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_LSIG_TXOP_EN,
1080 BIT(21));
1081 }
1082 #define SET_CMC_TBL_MASK_CTRL_CNT_VLD BIT(0)
SET_CMC_TBL_CTRL_CNT_VLD(void * table,u32 val)1083 static inline void SET_CMC_TBL_CTRL_CNT_VLD(void *table, u32 val)
1084 {
1085 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(27));
1086 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT_VLD,
1087 BIT(27));
1088 }
1089 #define SET_CMC_TBL_MASK_CTRL_CNT GENMASK(3, 0)
SET_CMC_TBL_CTRL_CNT(void * table,u32 val)1090 static inline void SET_CMC_TBL_CTRL_CNT(void *table, u32 val)
1091 {
1092 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 28));
1093 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT,
1094 GENMASK(31, 28));
1095 }
1096 #define SET_CMC_TBL_MASK_RESP_REF_RATE GENMASK(8, 0)
SET_CMC_TBL_RESP_REF_RATE(void * table,u32 val)1097 static inline void SET_CMC_TBL_RESP_REF_RATE(void *table, u32 val)
1098 {
1099 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(8, 0));
1100 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_RESP_REF_RATE,
1101 GENMASK(8, 0));
1102 }
1103 #define SET_CMC_TBL_MASK_ALL_ACK_SUPPORT BIT(0)
SET_CMC_TBL_ALL_ACK_SUPPORT(void * table,u32 val)1104 static inline void SET_CMC_TBL_ALL_ACK_SUPPORT(void *table, u32 val)
1105 {
1106 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(12));
1107 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ALL_ACK_SUPPORT,
1108 BIT(12));
1109 }
1110 #define SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT BIT(0)
SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(void * table,u32 val)1111 static inline void SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(void *table, u32 val)
1112 {
1113 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(13));
1114 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT,
1115 BIT(13));
1116 }
1117 #define SET_CMC_TBL_MASK_NTX_PATH_EN GENMASK(3, 0)
SET_CMC_TBL_NTX_PATH_EN(void * table,u32 val)1118 static inline void SET_CMC_TBL_NTX_PATH_EN(void *table, u32 val)
1119 {
1120 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(19, 16));
1121 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_NTX_PATH_EN,
1122 GENMASK(19, 16));
1123 }
1124 #define SET_CMC_TBL_MASK_PATH_MAP_A GENMASK(1, 0)
SET_CMC_TBL_PATH_MAP_A(void * table,u32 val)1125 static inline void SET_CMC_TBL_PATH_MAP_A(void *table, u32 val)
1126 {
1127 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(21, 20));
1128 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_A,
1129 GENMASK(21, 20));
1130 }
1131 #define SET_CMC_TBL_MASK_PATH_MAP_B GENMASK(1, 0)
SET_CMC_TBL_PATH_MAP_B(void * table,u32 val)1132 static inline void SET_CMC_TBL_PATH_MAP_B(void *table, u32 val)
1133 {
1134 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(23, 22));
1135 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_B,
1136 GENMASK(23, 22));
1137 }
1138 #define SET_CMC_TBL_MASK_PATH_MAP_C GENMASK(1, 0)
SET_CMC_TBL_PATH_MAP_C(void * table,u32 val)1139 static inline void SET_CMC_TBL_PATH_MAP_C(void *table, u32 val)
1140 {
1141 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(25, 24));
1142 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_C,
1143 GENMASK(25, 24));
1144 }
1145 #define SET_CMC_TBL_MASK_PATH_MAP_D GENMASK(1, 0)
SET_CMC_TBL_PATH_MAP_D(void * table,u32 val)1146 static inline void SET_CMC_TBL_PATH_MAP_D(void *table, u32 val)
1147 {
1148 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(27, 26));
1149 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_D,
1150 GENMASK(27, 26));
1151 }
1152 #define SET_CMC_TBL_MASK_ANTSEL_A BIT(0)
SET_CMC_TBL_ANTSEL_A(void * table,u32 val)1153 static inline void SET_CMC_TBL_ANTSEL_A(void *table, u32 val)
1154 {
1155 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(28));
1156 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_A,
1157 BIT(28));
1158 }
1159 #define SET_CMC_TBL_MASK_ANTSEL_B BIT(0)
SET_CMC_TBL_ANTSEL_B(void * table,u32 val)1160 static inline void SET_CMC_TBL_ANTSEL_B(void *table, u32 val)
1161 {
1162 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(29));
1163 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_B,
1164 BIT(29));
1165 }
1166 #define SET_CMC_TBL_MASK_ANTSEL_C BIT(0)
SET_CMC_TBL_ANTSEL_C(void * table,u32 val)1167 static inline void SET_CMC_TBL_ANTSEL_C(void *table, u32 val)
1168 {
1169 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(30));
1170 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_C,
1171 BIT(30));
1172 }
1173 #define SET_CMC_TBL_MASK_ANTSEL_D BIT(0)
SET_CMC_TBL_ANTSEL_D(void * table,u32 val)1174 static inline void SET_CMC_TBL_ANTSEL_D(void *table, u32 val)
1175 {
1176 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(31));
1177 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_D,
1178 BIT(31));
1179 }
1180
1181 #define SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING GENMASK(1, 0)
SET_CMC_TBL_NOMINAL_PKT_PADDING_V1(void * table,u32 val)1182 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING_V1(void *table, u32 val)
1183 {
1184 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(1, 0));
1185 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1186 GENMASK(1, 0));
1187 }
1188
SET_CMC_TBL_NOMINAL_PKT_PADDING40_V1(void * table,u32 val)1189 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40_V1(void *table, u32 val)
1190 {
1191 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(3, 2));
1192 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1193 GENMASK(3, 2));
1194 }
1195
SET_CMC_TBL_NOMINAL_PKT_PADDING80_V1(void * table,u32 val)1196 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80_V1(void *table, u32 val)
1197 {
1198 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(5, 4));
1199 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1200 GENMASK(5, 4));
1201 }
1202
SET_CMC_TBL_NOMINAL_PKT_PADDING160_V1(void * table,u32 val)1203 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160_V1(void *table, u32 val)
1204 {
1205 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 6));
1206 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1207 GENMASK(7, 6));
1208 }
1209
1210 #define SET_CMC_TBL_MASK_ADDR_CAM_INDEX GENMASK(7, 0)
SET_CMC_TBL_ADDR_CAM_INDEX(void * table,u32 val)1211 static inline void SET_CMC_TBL_ADDR_CAM_INDEX(void *table, u32 val)
1212 {
1213 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0));
1214 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ADDR_CAM_INDEX,
1215 GENMASK(7, 0));
1216 }
1217 #define SET_CMC_TBL_MASK_PAID GENMASK(8, 0)
SET_CMC_TBL_PAID(void * table,u32 val)1218 static inline void SET_CMC_TBL_PAID(void *table, u32 val)
1219 {
1220 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(16, 8));
1221 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_PAID,
1222 GENMASK(16, 8));
1223 }
1224 #define SET_CMC_TBL_MASK_ULDL BIT(0)
SET_CMC_TBL_ULDL(void * table,u32 val)1225 static inline void SET_CMC_TBL_ULDL(void *table, u32 val)
1226 {
1227 le32p_replace_bits((__le32 *)(table) + 7, val, BIT(17));
1228 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ULDL,
1229 BIT(17));
1230 }
1231 #define SET_CMC_TBL_MASK_DOPPLER_CTRL GENMASK(1, 0)
SET_CMC_TBL_DOPPLER_CTRL(void * table,u32 val)1232 static inline void SET_CMC_TBL_DOPPLER_CTRL(void *table, u32 val)
1233 {
1234 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(19, 18));
1235 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_DOPPLER_CTRL,
1236 GENMASK(19, 18));
1237 }
SET_CMC_TBL_NOMINAL_PKT_PADDING(void * table,u32 val)1238 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING(void *table, u32 val)
1239 {
1240 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(21, 20));
1241 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1242 GENMASK(21, 20));
1243 }
1244
SET_CMC_TBL_NOMINAL_PKT_PADDING40(void * table,u32 val)1245 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40(void *table, u32 val)
1246 {
1247 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 22));
1248 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1249 GENMASK(23, 22));
1250 }
1251 #define SET_CMC_TBL_MASK_TXPWR_TOLERENCE GENMASK(3, 0)
SET_CMC_TBL_TXPWR_TOLERENCE(void * table,u32 val)1252 static inline void SET_CMC_TBL_TXPWR_TOLERENCE(void *table, u32 val)
1253 {
1254 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(27, 24));
1255 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_TXPWR_TOLERENCE,
1256 GENMASK(27, 24));
1257 }
1258
SET_CMC_TBL_NOMINAL_PKT_PADDING80(void * table,u32 val)1259 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80(void *table, u32 val)
1260 {
1261 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 30));
1262 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1263 GENMASK(31, 30));
1264 }
1265 #define SET_CMC_TBL_MASK_NC GENMASK(2, 0)
SET_CMC_TBL_NC(void * table,u32 val)1266 static inline void SET_CMC_TBL_NC(void *table, u32 val)
1267 {
1268 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(2, 0));
1269 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NC,
1270 GENMASK(2, 0));
1271 }
1272 #define SET_CMC_TBL_MASK_NR GENMASK(2, 0)
SET_CMC_TBL_NR(void * table,u32 val)1273 static inline void SET_CMC_TBL_NR(void *table, u32 val)
1274 {
1275 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(5, 3));
1276 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NR,
1277 GENMASK(5, 3));
1278 }
1279 #define SET_CMC_TBL_MASK_NG GENMASK(1, 0)
SET_CMC_TBL_NG(void * table,u32 val)1280 static inline void SET_CMC_TBL_NG(void *table, u32 val)
1281 {
1282 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(7, 6));
1283 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NG,
1284 GENMASK(7, 6));
1285 }
1286 #define SET_CMC_TBL_MASK_CB GENMASK(1, 0)
SET_CMC_TBL_CB(void * table,u32 val)1287 static inline void SET_CMC_TBL_CB(void *table, u32 val)
1288 {
1289 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(9, 8));
1290 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CB,
1291 GENMASK(9, 8));
1292 }
1293 #define SET_CMC_TBL_MASK_CS GENMASK(1, 0)
SET_CMC_TBL_CS(void * table,u32 val)1294 static inline void SET_CMC_TBL_CS(void *table, u32 val)
1295 {
1296 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(11, 10));
1297 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CS,
1298 GENMASK(11, 10));
1299 }
1300 #define SET_CMC_TBL_MASK_CSI_TXBF_EN BIT(0)
SET_CMC_TBL_CSI_TXBF_EN(void * table,u32 val)1301 static inline void SET_CMC_TBL_CSI_TXBF_EN(void *table, u32 val)
1302 {
1303 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(12));
1304 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_TXBF_EN,
1305 BIT(12));
1306 }
1307 #define SET_CMC_TBL_MASK_CSI_STBC_EN BIT(0)
SET_CMC_TBL_CSI_STBC_EN(void * table,u32 val)1308 static inline void SET_CMC_TBL_CSI_STBC_EN(void *table, u32 val)
1309 {
1310 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(13));
1311 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_STBC_EN,
1312 BIT(13));
1313 }
1314 #define SET_CMC_TBL_MASK_CSI_LDPC_EN BIT(0)
SET_CMC_TBL_CSI_LDPC_EN(void * table,u32 val)1315 static inline void SET_CMC_TBL_CSI_LDPC_EN(void *table, u32 val)
1316 {
1317 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(14));
1318 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_LDPC_EN,
1319 BIT(14));
1320 }
1321 #define SET_CMC_TBL_MASK_CSI_PARA_EN BIT(0)
SET_CMC_TBL_CSI_PARA_EN(void * table,u32 val)1322 static inline void SET_CMC_TBL_CSI_PARA_EN(void *table, u32 val)
1323 {
1324 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(15));
1325 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_PARA_EN,
1326 BIT(15));
1327 }
1328 #define SET_CMC_TBL_MASK_CSI_FIX_RATE GENMASK(8, 0)
SET_CMC_TBL_CSI_FIX_RATE(void * table,u32 val)1329 static inline void SET_CMC_TBL_CSI_FIX_RATE(void *table, u32 val)
1330 {
1331 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(24, 16));
1332 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_FIX_RATE,
1333 GENMASK(24, 16));
1334 }
1335 #define SET_CMC_TBL_MASK_CSI_GI_LTF GENMASK(2, 0)
SET_CMC_TBL_CSI_GI_LTF(void * table,u32 val)1336 static inline void SET_CMC_TBL_CSI_GI_LTF(void *table, u32 val)
1337 {
1338 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(27, 25));
1339 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_GI_LTF,
1340 GENMASK(27, 25));
1341 }
1342
SET_CMC_TBL_NOMINAL_PKT_PADDING160(void * table,u32 val)1343 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160(void *table, u32 val)
1344 {
1345 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(29, 28));
1346 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1347 GENMASK(29, 28));
1348 }
1349
1350 #define SET_CMC_TBL_MASK_CSI_BW GENMASK(1, 0)
SET_CMC_TBL_CSI_BW(void * table,u32 val)1351 static inline void SET_CMC_TBL_CSI_BW(void *table, u32 val)
1352 {
1353 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(31, 30));
1354 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_BW,
1355 GENMASK(31, 30));
1356 }
1357
1358 struct rtw89_h2c_cctlinfo_ud_g7 {
1359 __le32 c0;
1360 __le32 w0;
1361 __le32 w1;
1362 __le32 w2;
1363 __le32 w3;
1364 __le32 w4;
1365 __le32 w5;
1366 __le32 w6;
1367 __le32 w7;
1368 __le32 w8;
1369 __le32 w9;
1370 __le32 w10;
1371 __le32 w11;
1372 __le32 w12;
1373 __le32 w13;
1374 __le32 w14;
1375 __le32 w15;
1376 __le32 m0;
1377 __le32 m1;
1378 __le32 m2;
1379 __le32 m3;
1380 __le32 m4;
1381 __le32 m5;
1382 __le32 m6;
1383 __le32 m7;
1384 __le32 m8;
1385 __le32 m9;
1386 __le32 m10;
1387 __le32 m11;
1388 __le32 m12;
1389 __le32 m13;
1390 __le32 m14;
1391 __le32 m15;
1392 } __packed;
1393
1394 #define CCTLINFO_G7_C0_MACID GENMASK(6, 0)
1395 #define CCTLINFO_G7_C0_OP BIT(7)
1396
1397 #define CCTLINFO_G7_W0_DATARATE GENMASK(11, 0)
1398 #define CCTLINFO_G7_W0_DATA_GI_LTF GENMASK(14, 12)
1399 #define CCTLINFO_G7_W0_TRYRATE BIT(15)
1400 #define CCTLINFO_G7_W0_ARFR_CTRL GENMASK(17, 16)
1401 #define CCTLINFO_G7_W0_DIS_HE1SS_STBC BIT(18)
1402 #define CCTLINFO_G7_W0_ACQ_RPT_EN BIT(20)
1403 #define CCTLINFO_G7_W0_MGQ_RPT_EN BIT(21)
1404 #define CCTLINFO_G7_W0_ULQ_RPT_EN BIT(22)
1405 #define CCTLINFO_G7_W0_TWTQ_RPT_EN BIT(23)
1406 #define CCTLINFO_G7_W0_FORCE_TXOP BIT(24)
1407 #define CCTLINFO_G7_W0_DISRTSFB BIT(25)
1408 #define CCTLINFO_G7_W0_DISDATAFB BIT(26)
1409 #define CCTLINFO_G7_W0_NSTR_EN BIT(27)
1410 #define CCTLINFO_G7_W0_AMPDU_DENSITY GENMASK(31, 28)
1411 #define CCTLINFO_G7_W0_ALL (GENMASK(31, 20) | GENMASK(18, 0))
1412 #define CCTLINFO_G7_W1_DATA_RTY_LOWEST_RATE GENMASK(11, 0)
1413 #define CCTLINFO_G7_W1_RTS_TXCNT_LMT GENMASK(15, 12)
1414 #define CCTLINFO_G7_W1_RTSRATE GENMASK(27, 16)
1415 #define CCTLINFO_G7_W1_RTS_RTY_LOWEST_RATE GENMASK(31, 28)
1416 #define CCTLINFO_G7_W1_ALL GENMASK(31, 0)
1417 #define CCTLINFO_G7_W2_DATA_TX_CNT_LMT GENMASK(5, 0)
1418 #define CCTLINFO_G7_W2_DATA_TXCNT_LMT_SEL BIT(6)
1419 #define CCTLINFO_G7_W2_MAX_AGG_NUM_SEL BIT(7)
1420 #define CCTLINFO_G7_W2_RTS_EN BIT(8)
1421 #define CCTLINFO_G7_W2_CTS2SELF_EN BIT(9)
1422 #define CCTLINFO_G7_W2_CCA_RTS GENMASK(11, 10)
1423 #define CCTLINFO_G7_W2_HW_RTS_EN BIT(12)
1424 #define CCTLINFO_G7_W2_RTS_DROP_DATA_MODE GENMASK(14, 13)
1425 #define CCTLINFO_G7_W2_PRELD_EN BIT(15)
1426 #define CCTLINFO_G7_W2_AMPDU_MAX_LEN GENMASK(26, 16)
1427 #define CCTLINFO_G7_W2_UL_MU_DIS BIT(27)
1428 #define CCTLINFO_G7_W2_AMPDU_MAX_TIME GENMASK(31, 28)
1429 #define CCTLINFO_G7_W2_ALL GENMASK(31, 0)
1430 #define CCTLINFO_G7_W3_MAX_AGG_NUM GENMASK(7, 0)
1431 #define CCTLINFO_G7_W3_DATA_BW GENMASK(10, 8)
1432 #define CCTLINFO_G7_W3_DATA_BW_ER BIT(11)
1433 #define CCTLINFO_G7_W3_BA_BMAP GENMASK(14, 12)
1434 #define CCTLINFO_G7_W3_VCS_STBC BIT(15)
1435 #define CCTLINFO_G7_W3_VO_LFTIME_SEL GENMASK(18, 16)
1436 #define CCTLINFO_G7_W3_VI_LFTIME_SEL GENMASK(21, 19)
1437 #define CCTLINFO_G7_W3_BE_LFTIME_SEL GENMASK(24, 22)
1438 #define CCTLINFO_G7_W3_BK_LFTIME_SEL GENMASK(27, 25)
1439 #define CCTLINFO_G7_W3_AMPDU_TIME_SEL BIT(28)
1440 #define CCTLINFO_G7_W3_AMPDU_LEN_SEL BIT(29)
1441 #define CCTLINFO_G7_W3_RTS_TXCNT_LMT_SEL BIT(30)
1442 #define CCTLINFO_G7_W3_LSIG_TXOP_EN BIT(31)
1443 #define CCTLINFO_G7_W3_ALL GENMASK(31, 0)
1444 #define CCTLINFO_G7_W4_MULTI_PORT_ID GENMASK(2, 0)
1445 #define CCTLINFO_G7_W4_BYPASS_PUNC BIT(3)
1446 #define CCTLINFO_G7_W4_MBSSID GENMASK(7, 4)
1447 #define CCTLINFO_G7_W4_DATA_DCM BIT(8)
1448 #define CCTLINFO_G7_W4_DATA_ER BIT(9)
1449 #define CCTLINFO_G7_W4_DATA_LDPC BIT(10)
1450 #define CCTLINFO_G7_W4_DATA_STBC BIT(11)
1451 #define CCTLINFO_G7_W4_A_CTRL_BQR BIT(12)
1452 #define CCTLINFO_G7_W4_A_CTRL_BSR BIT(14)
1453 #define CCTLINFO_G7_W4_A_CTRL_CAS BIT(15)
1454 #define CCTLINFO_G7_W4_ACT_SUBCH_CBW GENMASK(31, 16)
1455 #define CCTLINFO_G7_W4_ALL (GENMASK(31, 14) | GENMASK(12, 0))
1456 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING0 GENMASK(1, 0)
1457 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING1 GENMASK(3, 2)
1458 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING2 GENMASK(5, 4)
1459 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING3 GENMASK(7, 6)
1460 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING4 GENMASK(9, 8)
1461 #define CCTLINFO_G7_W5_SR_RATE GENMASK(14, 10)
1462 #define CCTLINFO_G7_W5_TID_DISABLE GENMASK(23, 16)
1463 #define CCTLINFO_G7_W5_ADDR_CAM_INDEX GENMASK(31, 24)
1464 #define CCTLINFO_G7_W5_ALL (GENMASK(31, 16) | GENMASK(14, 0))
1465 #define CCTLINFO_G7_W6_AID12_PAID GENMASK(11, 0)
1466 #define CCTLINFO_G7_W6_RESP_REF_RATE GENMASK(23, 12)
1467 #define CCTLINFO_G7_W6_ULDL BIT(31)
1468 #define CCTLINFO_G7_W6_ALL (BIT(31) | GENMASK(23, 0))
1469 #define CCTLINFO_G7_W7_NC GENMASK(2, 0)
1470 #define CCTLINFO_G7_W7_NR GENMASK(5, 3)
1471 #define CCTLINFO_G7_W7_NG GENMASK(7, 6)
1472 #define CCTLINFO_G7_W7_CB GENMASK(9, 8)
1473 #define CCTLINFO_G7_W7_CS GENMASK(11, 10)
1474 #define CCTLINFO_G7_W7_CSI_STBC_EN BIT(13)
1475 #define CCTLINFO_G7_W7_CSI_LDPC_EN BIT(14)
1476 #define CCTLINFO_G7_W7_CSI_PARA_EN BIT(15)
1477 #define CCTLINFO_G7_W7_CSI_FIX_RATE GENMASK(27, 16)
1478 #define CCTLINFO_G7_W7_CSI_BW GENMASK(31, 29)
1479 #define CCTLINFO_G7_W7_ALL (GENMASK(31, 29) | GENMASK(27, 13) | GENMASK(11, 0))
1480 #define CCTLINFO_G7_W8_ALL_ACK_SUPPORT BIT(0)
1481 #define CCTLINFO_G7_W8_BSR_QUEUE_SIZE_FORMAT BIT(1)
1482 #define CCTLINFO_G7_W8_BSR_OM_UPD_EN BIT(2)
1483 #define CCTLINFO_G7_W8_MACID_FWD_IDC BIT(3)
1484 #define CCTLINFO_G7_W8_AZ_SEC_EN BIT(4)
1485 #define CCTLINFO_G7_W8_CSI_SEC_EN BIT(5)
1486 #define CCTLINFO_G7_W8_FIX_UL_ADDRCAM_IDX BIT(6)
1487 #define CCTLINFO_G7_W8_CTRL_CNT_VLD BIT(7)
1488 #define CCTLINFO_G7_W8_CTRL_CNT GENMASK(11, 8)
1489 #define CCTLINFO_G7_W8_RESP_SEC_TYPE GENMASK(15, 12)
1490 #define CCTLINFO_G7_W8_ALL GENMASK(15, 0)
1491 /* W9~13 are reserved */
1492 #define CCTLINFO_G7_W14_VO_CURR_RATE GENMASK(11, 0)
1493 #define CCTLINFO_G7_W14_VI_CURR_RATE GENMASK(23, 12)
1494 #define CCTLINFO_G7_W14_BE_CURR_RATE_L GENMASK(31, 24)
1495 #define CCTLINFO_G7_W14_ALL GENMASK(31, 0)
1496 #define CCTLINFO_G7_W15_BE_CURR_RATE_H GENMASK(3, 0)
1497 #define CCTLINFO_G7_W15_BK_CURR_RATE GENMASK(15, 4)
1498 #define CCTLINFO_G7_W15_MGNT_CURR_RATE GENMASK(27, 16)
1499 #define CCTLINFO_G7_W15_ALL GENMASK(27, 0)
1500
1501 struct rtw89_h2c_bcn_upd {
1502 __le32 w0;
1503 __le32 w1;
1504 __le32 w2;
1505 } __packed;
1506
1507 #define RTW89_H2C_BCN_UPD_W0_PORT GENMASK(7, 0)
1508 #define RTW89_H2C_BCN_UPD_W0_MBSSID GENMASK(15, 8)
1509 #define RTW89_H2C_BCN_UPD_W0_BAND GENMASK(23, 16)
1510 #define RTW89_H2C_BCN_UPD_W0_GRP_IE_OFST GENMASK(31, 24)
1511 #define RTW89_H2C_BCN_UPD_W1_MACID GENMASK(7, 0)
1512 #define RTW89_H2C_BCN_UPD_W1_SSN_SEL GENMASK(9, 8)
1513 #define RTW89_H2C_BCN_UPD_W1_SSN_MODE GENMASK(11, 10)
1514 #define RTW89_H2C_BCN_UPD_W1_RATE GENMASK(20, 12)
1515 #define RTW89_H2C_BCN_UPD_W1_TXPWR GENMASK(23, 21)
1516 #define RTW89_H2C_BCN_UPD_W2_TXINFO_CTRL_EN BIT(0)
1517 #define RTW89_H2C_BCN_UPD_W2_NTX_PATH_EN GENMASK(4, 1)
1518 #define RTW89_H2C_BCN_UPD_W2_PATH_MAP_A GENMASK(6, 5)
1519 #define RTW89_H2C_BCN_UPD_W2_PATH_MAP_B GENMASK(8, 7)
1520 #define RTW89_H2C_BCN_UPD_W2_PATH_MAP_C GENMASK(10, 9)
1521 #define RTW89_H2C_BCN_UPD_W2_PATH_MAP_D GENMASK(12, 11)
1522 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_A BIT(13)
1523 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_B BIT(14)
1524 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_C BIT(15)
1525 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_D BIT(16)
1526 #define RTW89_H2C_BCN_UPD_W2_CSA_OFST GENMASK(31, 17)
1527
1528 struct rtw89_h2c_bcn_upd_be {
1529 __le32 w0;
1530 __le32 w1;
1531 __le32 w2;
1532 __le32 w3;
1533 __le32 w4;
1534 __le32 w5;
1535 __le32 w6;
1536 __le32 w7;
1537 __le32 w8;
1538 __le32 w9;
1539 __le32 w10;
1540 __le32 w11;
1541 __le32 w12;
1542 __le32 w13;
1543 __le32 w14;
1544 __le32 w15;
1545 __le32 w16;
1546 __le32 w17;
1547 __le32 w18;
1548 __le32 w19;
1549 __le32 w20;
1550 __le32 w21;
1551 __le32 w22;
1552 __le32 w23;
1553 __le32 w24;
1554 __le32 w25;
1555 __le32 w26;
1556 __le32 w27;
1557 __le32 w28;
1558 __le32 w29;
1559 } __packed;
1560
1561 #define RTW89_H2C_BCN_UPD_BE_W0_PORT GENMASK(7, 0)
1562 #define RTW89_H2C_BCN_UPD_BE_W0_MBSSID GENMASK(15, 8)
1563 #define RTW89_H2C_BCN_UPD_BE_W0_BAND GENMASK(23, 16)
1564 #define RTW89_H2C_BCN_UPD_BE_W0_GRP_IE_OFST GENMASK(31, 24)
1565 #define RTW89_H2C_BCN_UPD_BE_W1_MACID GENMASK(7, 0)
1566 #define RTW89_H2C_BCN_UPD_BE_W1_SSN_SEL GENMASK(9, 8)
1567 #define RTW89_H2C_BCN_UPD_BE_W1_SSN_MODE GENMASK(11, 10)
1568 #define RTW89_H2C_BCN_UPD_BE_W1_RATE GENMASK(20, 12)
1569 #define RTW89_H2C_BCN_UPD_BE_W1_TXPWR GENMASK(23, 21)
1570 #define RTW89_H2C_BCN_UPD_BE_W1_MACID_EXT GENMASK(31, 24)
1571 #define RTW89_H2C_BCN_UPD_BE_W2_TXINFO_CTRL_EN BIT(0)
1572 #define RTW89_H2C_BCN_UPD_BE_W2_NTX_PATH_EN GENMASK(4, 1)
1573 #define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_A GENMASK(6, 5)
1574 #define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_B GENMASK(8, 7)
1575 #define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_C GENMASK(10, 9)
1576 #define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_D GENMASK(12, 11)
1577 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_A BIT(13)
1578 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_B BIT(14)
1579 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_C BIT(15)
1580 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_D BIT(16)
1581 #define RTW89_H2C_BCN_UPD_BE_W2_CSA_OFST GENMASK(31, 17)
1582 #define RTW89_H2C_BCN_UPD_BE_W3_MLIE_CSA_OFST GENMASK(15, 0)
1583 #define RTW89_H2C_BCN_UPD_BE_W3_CRITICAL_UPD_FLAG_OFST GENMASK(31, 16)
1584 #define RTW89_H2C_BCN_UPD_BE_W4_VAP1_DTIM_CNT_OFST GENMASK(15, 0)
1585 #define RTW89_H2C_BCN_UPD_BE_W4_VAP2_DTIM_CNT_OFST GENMASK(31, 16)
1586 #define RTW89_H2C_BCN_UPD_BE_W5_VAP3_DTIM_CNT_OFST GENMASK(15, 0)
1587 #define RTW89_H2C_BCN_UPD_BE_W5_VAP4_DTIM_CNT_OFST GENMASK(31, 16)
1588 #define RTW89_H2C_BCN_UPD_BE_W6_VAP5_DTIM_CNT_OFST GENMASK(15, 0)
1589 #define RTW89_H2C_BCN_UPD_BE_W6_VAP6_DTIM_CNT_OFST GENMASK(31, 16)
1590 #define RTW89_H2C_BCN_UPD_BE_W7_VAP7_DTIM_CNT_OFST GENMASK(15, 0)
1591 #define RTW89_H2C_BCN_UPD_BE_W7_ECSA_OFST GENMASK(30, 16)
1592 #define RTW89_H2C_BCN_UPD_BE_W7_PROTECTION_KEY_ID BIT(31)
1593
1594 struct rtw89_h2c_role_maintain {
1595 __le32 w0;
1596 };
1597
1598 #define RTW89_H2C_ROLE_MAINTAIN_W0_MACID GENMASK(7, 0)
1599 #define RTW89_H2C_ROLE_MAINTAIN_W0_SELF_ROLE GENMASK(9, 8)
1600 #define RTW89_H2C_ROLE_MAINTAIN_W0_UPD_MODE GENMASK(12, 10)
1601 #define RTW89_H2C_ROLE_MAINTAIN_W0_WIFI_ROLE GENMASK(16, 13)
1602 #define RTW89_H2C_ROLE_MAINTAIN_W0_BAND GENMASK(18, 17)
1603 #define RTW89_H2C_ROLE_MAINTAIN_W0_PORT GENMASK(21, 19)
1604 #define RTW89_H2C_ROLE_MAINTAIN_W0_MACID_EXT GENMASK(31, 24)
1605
1606 enum rtw89_fw_sta_type { /* value of RTW89_H2C_JOININFO_W1_STA_TYPE */
1607 RTW89_FW_N_AC_STA = 0,
1608 RTW89_FW_AX_STA = 1,
1609 RTW89_FW_BE_STA = 2,
1610 };
1611
1612 struct rtw89_h2c_join {
1613 __le32 w0;
1614 } __packed;
1615
1616 struct rtw89_h2c_join_v1 {
1617 __le32 w0;
1618 __le32 w1;
1619 __le32 w2;
1620 } __packed;
1621
1622 #define RTW89_H2C_JOININFO_W0_MACID GENMASK(7, 0)
1623 #define RTW89_H2C_JOININFO_W0_OP BIT(8)
1624 #define RTW89_H2C_JOININFO_W0_BAND BIT(9)
1625 #define RTW89_H2C_JOININFO_W0_WMM GENMASK(11, 10)
1626 #define RTW89_H2C_JOININFO_W0_TGR BIT(12)
1627 #define RTW89_H2C_JOININFO_W0_ISHESTA BIT(13)
1628 #define RTW89_H2C_JOININFO_W0_DLBW GENMASK(15, 14)
1629 #define RTW89_H2C_JOININFO_W0_TF_MAC_PAD GENMASK(17, 16)
1630 #define RTW89_H2C_JOININFO_W0_DL_T_PE GENMASK(20, 18)
1631 #define RTW89_H2C_JOININFO_W0_PORT_ID GENMASK(23, 21)
1632 #define RTW89_H2C_JOININFO_W0_NET_TYPE GENMASK(25, 24)
1633 #define RTW89_H2C_JOININFO_W0_WIFI_ROLE GENMASK(29, 26)
1634 #define RTW89_H2C_JOININFO_W0_SELF_ROLE GENMASK(31, 30)
1635 #define RTW89_H2C_JOININFO_W1_STA_TYPE GENMASK(2, 0)
1636 #define RTW89_H2C_JOININFO_W1_IS_MLD BIT(3)
1637 #define RTW89_H2C_JOININFO_W1_MAIN_MACID GENMASK(11, 4)
1638 #define RTW89_H2C_JOININFO_W1_MLO_MODE BIT(12)
1639 #define RTW89_H2C_JOININFO_W1_EMLSR_CAB BIT(13)
1640 #define RTW89_H2C_JOININFO_W1_NSTR_EN BIT(14)
1641 #define RTW89_H2C_JOININFO_W1_INIT_PWR_STATE BIT(15)
1642 #define RTW89_H2C_JOININFO_W1_EMLSR_PADDING GENMASK(18, 16)
1643 #define RTW89_H2C_JOININFO_W1_EMLSR_TRANS_DELAY GENMASK(21, 19)
1644 #define RTW89_H2C_JOININFO_W2_MACID_EXT GENMASK(7, 0)
1645 #define RTW89_H2C_JOININFO_W2_MAIN_MACID_EXT GENMASK(15, 8)
1646
1647 struct rtw89_h2c_notify_dbcc {
1648 __le32 w0;
1649 } __packed;
1650
1651 #define RTW89_H2C_NOTIFY_DBCC_EN BIT(0)
1652
SET_GENERAL_PKT_MACID(void * h2c,u32 val)1653 static inline void SET_GENERAL_PKT_MACID(void *h2c, u32 val)
1654 {
1655 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1656 }
1657
SET_GENERAL_PKT_PROBRSP_ID(void * h2c,u32 val)1658 static inline void SET_GENERAL_PKT_PROBRSP_ID(void *h2c, u32 val)
1659 {
1660 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1661 }
1662
SET_GENERAL_PKT_PSPOLL_ID(void * h2c,u32 val)1663 static inline void SET_GENERAL_PKT_PSPOLL_ID(void *h2c, u32 val)
1664 {
1665 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));
1666 }
1667
SET_GENERAL_PKT_NULL_ID(void * h2c,u32 val)1668 static inline void SET_GENERAL_PKT_NULL_ID(void *h2c, u32 val)
1669 {
1670 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1671 }
1672
SET_GENERAL_PKT_QOS_NULL_ID(void * h2c,u32 val)1673 static inline void SET_GENERAL_PKT_QOS_NULL_ID(void *h2c, u32 val)
1674 {
1675 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0));
1676 }
1677
SET_GENERAL_PKT_CTS2SELF_ID(void * h2c,u32 val)1678 static inline void SET_GENERAL_PKT_CTS2SELF_ID(void *h2c, u32 val)
1679 {
1680 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8));
1681 }
1682
SET_LOG_CFG_LEVEL(void * h2c,u32 val)1683 static inline void SET_LOG_CFG_LEVEL(void *h2c, u32 val)
1684 {
1685 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1686 }
1687
SET_LOG_CFG_PATH(void * h2c,u32 val)1688 static inline void SET_LOG_CFG_PATH(void *h2c, u32 val)
1689 {
1690 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1691 }
1692
SET_LOG_CFG_COMP(void * h2c,u32 val)1693 static inline void SET_LOG_CFG_COMP(void *h2c, u32 val)
1694 {
1695 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(31, 0));
1696 }
1697
SET_LOG_CFG_COMP_EXT(void * h2c,u32 val)1698 static inline void SET_LOG_CFG_COMP_EXT(void *h2c, u32 val)
1699 {
1700 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(31, 0));
1701 }
1702
1703 struct rtw89_h2c_ba_cam {
1704 __le32 w0;
1705 __le32 w1;
1706 } __packed;
1707
1708 #define RTW89_H2C_BA_CAM_W0_VALID BIT(0)
1709 #define RTW89_H2C_BA_CAM_W0_INIT_REQ BIT(1)
1710 #define RTW89_H2C_BA_CAM_W0_ENTRY_IDX GENMASK(3, 2)
1711 #define RTW89_H2C_BA_CAM_W0_TID GENMASK(7, 4)
1712 #define RTW89_H2C_BA_CAM_W0_MACID GENMASK(15, 8)
1713 #define RTW89_H2C_BA_CAM_W0_BMAP_SIZE GENMASK(19, 16)
1714 #define RTW89_H2C_BA_CAM_W0_SSN GENMASK(31, 20)
1715 #define RTW89_H2C_BA_CAM_W1_UID GENMASK(7, 0)
1716 #define RTW89_H2C_BA_CAM_W1_STD_EN BIT(8)
1717 #define RTW89_H2C_BA_CAM_W1_BAND BIT(9)
1718 #define RTW89_H2C_BA_CAM_W1_ENTRY_IDX_V1 GENMASK(31, 28)
1719
1720 struct rtw89_h2c_ba_cam_v1 {
1721 __le32 w0;
1722 __le32 w1;
1723 } __packed;
1724
1725 #define RTW89_H2C_BA_CAM_V1_W0_VALID BIT(0)
1726 #define RTW89_H2C_BA_CAM_V1_W0_INIT_REQ BIT(1)
1727 #define RTW89_H2C_BA_CAM_V1_W0_TID_MASK GENMASK(7, 4)
1728 #define RTW89_H2C_BA_CAM_V1_W0_MACID_MASK GENMASK(15, 8)
1729 #define RTW89_H2C_BA_CAM_V1_W0_BMAP_SIZE_MASK GENMASK(19, 16)
1730 #define RTW89_H2C_BA_CAM_V1_W0_SSN_MASK GENMASK(31, 20)
1731 #define RTW89_H2C_BA_CAM_V1_W1_UID_VALUE_MASK GENMASK(7, 0)
1732 #define RTW89_H2C_BA_CAM_V1_W1_STD_ENTRY_EN BIT(8)
1733 #define RTW89_H2C_BA_CAM_V1_W1_BAND_SEL BIT(9)
1734 #define RTW89_H2C_BA_CAM_V1_W1_MLD_EN BIT(10)
1735 #define RTW89_H2C_BA_CAM_V1_W1_ENTRY_IDX_MASK GENMASK(31, 24)
1736
1737 struct rtw89_h2c_ba_cam_init {
1738 __le32 w0;
1739 } __packed;
1740
1741 #define RTW89_H2C_BA_CAM_INIT_USERS_MASK GENMASK(7, 0)
1742 #define RTW89_H2C_BA_CAM_INIT_OFFSET_MASK GENMASK(19, 12)
1743 #define RTW89_H2C_BA_CAM_INIT_BAND_SEL BIT(24)
1744
SET_LPS_PARM_MACID(void * h2c,u32 val)1745 static inline void SET_LPS_PARM_MACID(void *h2c, u32 val)
1746 {
1747 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1748 }
1749
SET_LPS_PARM_PSMODE(void * h2c,u32 val)1750 static inline void SET_LPS_PARM_PSMODE(void *h2c, u32 val)
1751 {
1752 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1753 }
1754
SET_LPS_PARM_RLBM(void * h2c,u32 val)1755 static inline void SET_LPS_PARM_RLBM(void *h2c, u32 val)
1756 {
1757 le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16));
1758 }
1759
SET_LPS_PARM_SMARTPS(void * h2c,u32 val)1760 static inline void SET_LPS_PARM_SMARTPS(void *h2c, u32 val)
1761 {
1762 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 20));
1763 }
1764
SET_LPS_PARM_AWAKEINTERVAL(void * h2c,u32 val)1765 static inline void SET_LPS_PARM_AWAKEINTERVAL(void *h2c, u32 val)
1766 {
1767 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1768 }
1769
SET_LPS_PARM_VOUAPSD(void * h2c,u32 val)1770 static inline void SET_LPS_PARM_VOUAPSD(void *h2c, u32 val)
1771 {
1772 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(0));
1773 }
1774
SET_LPS_PARM_VIUAPSD(void * h2c,u32 val)1775 static inline void SET_LPS_PARM_VIUAPSD(void *h2c, u32 val)
1776 {
1777 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(1));
1778 }
1779
SET_LPS_PARM_BEUAPSD(void * h2c,u32 val)1780 static inline void SET_LPS_PARM_BEUAPSD(void *h2c, u32 val)
1781 {
1782 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(2));
1783 }
1784
SET_LPS_PARM_BKUAPSD(void * h2c,u32 val)1785 static inline void SET_LPS_PARM_BKUAPSD(void *h2c, u32 val)
1786 {
1787 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(3));
1788 }
1789
SET_LPS_PARM_LASTRPWM(void * h2c,u32 val)1790 static inline void SET_LPS_PARM_LASTRPWM(void *h2c, u32 val)
1791 {
1792 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8));
1793 }
1794
1795 struct rtw89_h2c_lps_ch_info {
1796 struct {
1797 u8 pri_ch;
1798 u8 central_ch;
1799 u8 bw;
1800 u8 band;
1801 } __packed info[2];
1802
1803 __le32 mlo_dbcc_mode_lps;
1804 } __packed;
1805
1806 struct rtw89_h2c_lps_ml_cmn_info {
1807 u8 fmt_id;
1808 u8 rfe_type;
1809 u8 rsvd0[2];
1810 __le32 mlo_dbcc_mode;
1811 u8 central_ch[RTW89_PHY_NUM];
1812 u8 pri_ch[RTW89_PHY_NUM];
1813 u8 bw[RTW89_PHY_NUM];
1814 u8 band[RTW89_PHY_NUM];
1815 u8 bcn_rate_type[RTW89_PHY_NUM];
1816 u8 rsvd1[2];
1817 __le16 tia_gain[RTW89_PHY_NUM][TIA_GAIN_NUM];
1818 u8 lna_gain[RTW89_PHY_NUM][LNA_GAIN_NUM];
1819 u8 rsvd2[2];
1820 u8 tia_lna_op1db[RTW89_PHY_NUM][LNA_GAIN_NUM + 1];
1821 u8 lna_op1db[RTW89_PHY_NUM][LNA_GAIN_NUM];
1822 u8 dup_bcn_ofst[RTW89_PHY_NUM];
1823 } __packed;
1824
RTW89_SET_FWCMD_CPU_EXCEPTION_TYPE(void * cmd,u32 val)1825 static inline void RTW89_SET_FWCMD_CPU_EXCEPTION_TYPE(void *cmd, u32 val)
1826 {
1827 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 0));
1828 }
1829
RTW89_SET_FWCMD_PKT_DROP_SEL(void * cmd,u32 val)1830 static inline void RTW89_SET_FWCMD_PKT_DROP_SEL(void *cmd, u32 val)
1831 {
1832 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
1833 }
1834
RTW89_SET_FWCMD_PKT_DROP_MACID(void * cmd,u32 val)1835 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID(void *cmd, u32 val)
1836 {
1837 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
1838 }
1839
RTW89_SET_FWCMD_PKT_DROP_BAND(void * cmd,u32 val)1840 static inline void RTW89_SET_FWCMD_PKT_DROP_BAND(void *cmd, u32 val)
1841 {
1842 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
1843 }
1844
RTW89_SET_FWCMD_PKT_DROP_PORT(void * cmd,u32 val)1845 static inline void RTW89_SET_FWCMD_PKT_DROP_PORT(void *cmd, u32 val)
1846 {
1847 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
1848 }
1849
RTW89_SET_FWCMD_PKT_DROP_MBSSID(void * cmd,u32 val)1850 static inline void RTW89_SET_FWCMD_PKT_DROP_MBSSID(void *cmd, u32 val)
1851 {
1852 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 0));
1853 }
1854
RTW89_SET_FWCMD_PKT_DROP_ROLE_A_INFO_TF_TRS(void * cmd,u32 val)1855 static inline void RTW89_SET_FWCMD_PKT_DROP_ROLE_A_INFO_TF_TRS(void *cmd, u32 val)
1856 {
1857 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(15, 8));
1858 }
1859
RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_0(void * cmd,u32 val)1860 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_0(void *cmd, u32 val)
1861 {
1862 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
1863 }
1864
RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_1(void * cmd,u32 val)1865 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_1(void *cmd, u32 val)
1866 {
1867 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0));
1868 }
1869
RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_2(void * cmd,u32 val)1870 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_2(void *cmd, u32 val)
1871 {
1872 le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0));
1873 }
1874
RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_3(void * cmd,u32 val)1875 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_3(void *cmd, u32 val)
1876 {
1877 le32p_replace_bits((__le32 *)cmd + 5, val, GENMASK(31, 0));
1878 }
1879
RTW89_SET_KEEP_ALIVE_ENABLE(void * h2c,u32 val)1880 static inline void RTW89_SET_KEEP_ALIVE_ENABLE(void *h2c, u32 val)
1881 {
1882 le32p_replace_bits((__le32 *)h2c, val, GENMASK(1, 0));
1883 }
1884
RTW89_SET_KEEP_ALIVE_PKT_NULL_ID(void * h2c,u32 val)1885 static inline void RTW89_SET_KEEP_ALIVE_PKT_NULL_ID(void *h2c, u32 val)
1886 {
1887 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1888 }
1889
RTW89_SET_KEEP_ALIVE_PERIOD(void * h2c,u32 val)1890 static inline void RTW89_SET_KEEP_ALIVE_PERIOD(void *h2c, u32 val)
1891 {
1892 le32p_replace_bits((__le32 *)h2c, val, GENMASK(24, 16));
1893 }
1894
RTW89_SET_KEEP_ALIVE_MACID(void * h2c,u32 val)1895 static inline void RTW89_SET_KEEP_ALIVE_MACID(void *h2c, u32 val)
1896 {
1897 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1898 }
1899
RTW89_SET_DISCONNECT_DETECT_ENABLE(void * h2c,u32 val)1900 static inline void RTW89_SET_DISCONNECT_DETECT_ENABLE(void *h2c, u32 val)
1901 {
1902 le32p_replace_bits((__le32 *)h2c, val, BIT(0));
1903 }
1904
RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_EN(void * h2c,u32 val)1905 static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_EN(void *h2c, u32 val)
1906 {
1907 le32p_replace_bits((__le32 *)h2c, val, BIT(1));
1908 }
1909
RTW89_SET_DISCONNECT_DETECT_DISCONNECT(void * h2c,u32 val)1910 static inline void RTW89_SET_DISCONNECT_DETECT_DISCONNECT(void *h2c, u32 val)
1911 {
1912 le32p_replace_bits((__le32 *)h2c, val, BIT(2));
1913 }
1914
RTW89_SET_DISCONNECT_DETECT_MAC_ID(void * h2c,u32 val)1915 static inline void RTW89_SET_DISCONNECT_DETECT_MAC_ID(void *h2c, u32 val)
1916 {
1917 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1918 }
1919
RTW89_SET_DISCONNECT_DETECT_CHECK_PERIOD(void * h2c,u32 val)1920 static inline void RTW89_SET_DISCONNECT_DETECT_CHECK_PERIOD(void *h2c, u32 val)
1921 {
1922 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));
1923 }
1924
RTW89_SET_DISCONNECT_DETECT_TRY_PKT_COUNT(void * h2c,u32 val)1925 static inline void RTW89_SET_DISCONNECT_DETECT_TRY_PKT_COUNT(void *h2c, u32 val)
1926 {
1927 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1928 }
1929
RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_LIMIT(void * h2c,u32 val)1930 static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_LIMIT(void *h2c, u32 val)
1931 {
1932 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0));
1933 }
1934
1935 struct rtw89_h2c_wow_global {
1936 __le32 w0;
1937 struct rtw89_wow_key_info key_info;
1938 } __packed;
1939
1940 #define RTW89_H2C_WOW_GLOBAL_W0_ENABLE BIT(0)
1941 #define RTW89_H2C_WOW_GLOBAL_W0_DROP_ALL_PKT BIT(1)
1942 #define RTW89_H2C_WOW_GLOBAL_W0_RX_PARSE_AFTER_WAKE BIT(2)
1943 #define RTW89_H2C_WOW_GLOBAL_W0_WAKE_BAR_PULLED BIT(3)
1944 #define RTW89_H2C_WOW_GLOBAL_W0_MAC_ID GENMASK(15, 8)
1945 #define RTW89_H2C_WOW_GLOBAL_W0_PAIRWISE_SEC_ALGO GENMASK(23, 16)
1946 #define RTW89_H2C_WOW_GLOBAL_W0_GROUP_SEC_ALGO GENMASK(31, 24)
1947
1948 #define RTW89_MAX_SUPPORT_NL_NUM 16
1949 struct rtw89_h2c_cfg_nlo {
1950 __le32 w0;
1951 u8 nlo_cnt;
1952 u8 rsvd[3];
1953 __le32 patterncheck;
1954 __le32 rsvd1;
1955 __le32 rsvd2;
1956 u8 ssid_len[RTW89_MAX_SUPPORT_NL_NUM];
1957 u8 chiper[RTW89_MAX_SUPPORT_NL_NUM];
1958 u8 rsvd3[24];
1959 u8 ssid[RTW89_MAX_SUPPORT_NL_NUM][IEEE80211_MAX_SSID_LEN];
1960 } __packed;
1961
1962 #define RTW89_H2C_NLO_W0_ENABLE BIT(0)
1963 #define RTW89_H2C_NLO_W0_IGNORE_CIPHER BIT(2)
1964 #define RTW89_H2C_NLO_W0_MACID GENMASK(31, 24)
1965
RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE(void * h2c,u32 val)1966 static inline void RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE(void *h2c, u32 val)
1967 {
1968 le32p_replace_bits((__le32 *)h2c, val, BIT(0));
1969 }
1970
RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE(void * h2c,u32 val)1971 static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE(void *h2c, u32 val)
1972 {
1973 le32p_replace_bits((__le32 *)h2c, val, BIT(1));
1974 }
1975
RTW89_SET_WOW_WAKEUP_CTRL_HW_UNICAST_ENABLE(void * h2c,u32 val)1976 static inline void RTW89_SET_WOW_WAKEUP_CTRL_HW_UNICAST_ENABLE(void *h2c, u32 val)
1977 {
1978 le32p_replace_bits((__le32 *)h2c, val, BIT(2));
1979 }
1980
RTW89_SET_WOW_WAKEUP_CTRL_FW_UNICAST_ENABLE(void * h2c,u32 val)1981 static inline void RTW89_SET_WOW_WAKEUP_CTRL_FW_UNICAST_ENABLE(void *h2c, u32 val)
1982 {
1983 le32p_replace_bits((__le32 *)h2c, val, BIT(3));
1984 }
1985
RTW89_SET_WOW_WAKEUP_CTRL_DEAUTH_ENABLE(void * h2c,u32 val)1986 static inline void RTW89_SET_WOW_WAKEUP_CTRL_DEAUTH_ENABLE(void *h2c, u32 val)
1987 {
1988 le32p_replace_bits((__le32 *)h2c, val, BIT(4));
1989 }
1990
RTW89_SET_WOW_WAKEUP_CTRL_REKEYP_ENABLE(void * h2c,u32 val)1991 static inline void RTW89_SET_WOW_WAKEUP_CTRL_REKEYP_ENABLE(void *h2c, u32 val)
1992 {
1993 le32p_replace_bits((__le32 *)h2c, val, BIT(5));
1994 }
1995
RTW89_SET_WOW_WAKEUP_CTRL_EAP_ENABLE(void * h2c,u32 val)1996 static inline void RTW89_SET_WOW_WAKEUP_CTRL_EAP_ENABLE(void *h2c, u32 val)
1997 {
1998 le32p_replace_bits((__le32 *)h2c, val, BIT(6));
1999 }
2000
RTW89_SET_WOW_WAKEUP_CTRL_ALL_DATA_ENABLE(void * h2c,u32 val)2001 static inline void RTW89_SET_WOW_WAKEUP_CTRL_ALL_DATA_ENABLE(void *h2c, u32 val)
2002 {
2003 le32p_replace_bits((__le32 *)h2c, val, BIT(7));
2004 }
2005
RTW89_SET_WOW_WAKEUP_CTRL_MAC_ID(void * h2c,u32 val)2006 static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAC_ID(void *h2c, u32 val)
2007 {
2008 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
2009 }
2010
RTW89_SET_WOW_CAM_UPD_R_W(void * h2c,u32 val)2011 static inline void RTW89_SET_WOW_CAM_UPD_R_W(void *h2c, u32 val)
2012 {
2013 le32p_replace_bits((__le32 *)h2c, val, BIT(0));
2014 }
2015
RTW89_SET_WOW_CAM_UPD_IDX(void * h2c,u32 val)2016 static inline void RTW89_SET_WOW_CAM_UPD_IDX(void *h2c, u32 val)
2017 {
2018 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 1));
2019 }
2020
RTW89_SET_WOW_CAM_UPD_WKFM1(void * h2c,u32 val)2021 static inline void RTW89_SET_WOW_CAM_UPD_WKFM1(void *h2c, u32 val)
2022 {
2023 le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(31, 0));
2024 }
2025
RTW89_SET_WOW_CAM_UPD_WKFM2(void * h2c,u32 val)2026 static inline void RTW89_SET_WOW_CAM_UPD_WKFM2(void *h2c, u32 val)
2027 {
2028 le32p_replace_bits((__le32 *)h2c + 2, val, GENMASK(31, 0));
2029 }
2030
RTW89_SET_WOW_CAM_UPD_WKFM3(void * h2c,u32 val)2031 static inline void RTW89_SET_WOW_CAM_UPD_WKFM3(void *h2c, u32 val)
2032 {
2033 le32p_replace_bits((__le32 *)h2c + 3, val, GENMASK(31, 0));
2034 }
2035
RTW89_SET_WOW_CAM_UPD_WKFM4(void * h2c,u32 val)2036 static inline void RTW89_SET_WOW_CAM_UPD_WKFM4(void *h2c, u32 val)
2037 {
2038 le32p_replace_bits((__le32 *)h2c + 4, val, GENMASK(31, 0));
2039 }
2040
RTW89_SET_WOW_CAM_UPD_CRC(void * h2c,u32 val)2041 static inline void RTW89_SET_WOW_CAM_UPD_CRC(void *h2c, u32 val)
2042 {
2043 le32p_replace_bits((__le32 *)h2c + 5, val, GENMASK(15, 0));
2044 }
2045
RTW89_SET_WOW_CAM_UPD_NEGATIVE_PATTERN_MATCH(void * h2c,u32 val)2046 static inline void RTW89_SET_WOW_CAM_UPD_NEGATIVE_PATTERN_MATCH(void *h2c, u32 val)
2047 {
2048 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(22));
2049 }
2050
RTW89_SET_WOW_CAM_UPD_SKIP_MAC_HDR(void * h2c,u32 val)2051 static inline void RTW89_SET_WOW_CAM_UPD_SKIP_MAC_HDR(void *h2c, u32 val)
2052 {
2053 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(23));
2054 }
2055
RTW89_SET_WOW_CAM_UPD_UC(void * h2c,u32 val)2056 static inline void RTW89_SET_WOW_CAM_UPD_UC(void *h2c, u32 val)
2057 {
2058 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(24));
2059 }
2060
RTW89_SET_WOW_CAM_UPD_MC(void * h2c,u32 val)2061 static inline void RTW89_SET_WOW_CAM_UPD_MC(void *h2c, u32 val)
2062 {
2063 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(25));
2064 }
2065
RTW89_SET_WOW_CAM_UPD_BC(void * h2c,u32 val)2066 static inline void RTW89_SET_WOW_CAM_UPD_BC(void *h2c, u32 val)
2067 {
2068 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(26));
2069 }
2070
RTW89_SET_WOW_CAM_UPD_VALID(void * h2c,u32 val)2071 static inline void RTW89_SET_WOW_CAM_UPD_VALID(void *h2c, u32 val)
2072 {
2073 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(31));
2074 }
2075
2076 struct rtw89_h2c_wow_gtk_ofld {
2077 __le32 w0;
2078 __le32 w1;
2079 struct rtw89_wow_gtk_info gtk_info;
2080 } __packed;
2081
2082 #define RTW89_H2C_WOW_GTK_OFLD_W0_EN BIT(0)
2083 #define RTW89_H2C_WOW_GTK_OFLD_W0_TKIP_EN BIT(1)
2084 #define RTW89_H2C_WOW_GTK_OFLD_W0_IEEE80211W_EN BIT(2)
2085 #define RTW89_H2C_WOW_GTK_OFLD_W0_PAIRWISE_WAKEUP BIT(3)
2086 #define RTW89_H2C_WOW_GTK_OFLD_W0_NOREKEY_WAKEUP BIT(4)
2087 #define RTW89_H2C_WOW_GTK_OFLD_W0_MAC_ID GENMASK(23, 16)
2088 #define RTW89_H2C_WOW_GTK_OFLD_W0_GTK_RSP_ID GENMASK(31, 24)
2089 #define RTW89_H2C_WOW_GTK_OFLD_W1_PMF_SA_QUERY_ID GENMASK(7, 0)
2090 #define RTW89_H2C_WOW_GTK_OFLD_W1_PMF_BIP_SEC_ALGO GENMASK(9, 8)
2091 #define RTW89_H2C_WOW_GTK_OFLD_W1_ALGO_AKM_SUIT GENMASK(17, 10)
2092
2093 struct rtw89_h2c_arp_offload {
2094 __le32 w0;
2095 __le32 w1;
2096 } __packed;
2097
2098 #define RTW89_H2C_ARP_OFFLOAD_W0_ENABLE BIT(0)
2099 #define RTW89_H2C_ARP_OFFLOAD_W0_ACTION BIT(1)
2100 #define RTW89_H2C_ARP_OFFLOAD_W0_MACID GENMASK(23, 16)
2101 #define RTW89_H2C_ARP_OFFLOAD_W0_PKT_ID GENMASK(31, 24)
2102 #define RTW89_H2C_ARP_OFFLOAD_W1_CONTENT GENMASK(31, 0)
2103
2104 enum rtw89_btc_btf_h2c_class {
2105 BTFC_SET = 0x10,
2106 BTFC_GET = 0x11,
2107 BTFC_FW_EVENT = 0x12,
2108 };
2109
2110 enum rtw89_btc_btf_set {
2111 SET_REPORT_EN = 0x0,
2112 SET_SLOT_TABLE,
2113 SET_MREG_TABLE,
2114 SET_CX_POLICY,
2115 SET_GPIO_DBG,
2116 SET_DRV_INFO,
2117 SET_DRV_EVENT,
2118 SET_BT_WREG_ADDR,
2119 SET_BT_WREG_VAL,
2120 SET_BT_RREG_ADDR,
2121 SET_BT_WL_CH_INFO,
2122 SET_BT_INFO_REPORT,
2123 SET_BT_IGNORE_WLAN_ACT,
2124 SET_BT_TX_PWR,
2125 SET_BT_LNA_CONSTRAIN,
2126 SET_BT_QUERY_DEV_LIST,
2127 SET_BT_QUERY_DEV_INFO,
2128 SET_BT_PSD_REPORT,
2129 SET_H2C_TEST,
2130 SET_IOFLD_RF,
2131 SET_IOFLD_BB,
2132 SET_IOFLD_MAC,
2133 SET_IOFLD_SCBD,
2134 SET_H2C_MACRO,
2135 SET_MAX1,
2136 };
2137
2138 enum rtw89_btc_cxdrvinfo {
2139 CXDRVINFO_INIT = 0,
2140 CXDRVINFO_ROLE,
2141 CXDRVINFO_DBCC,
2142 CXDRVINFO_SMAP,
2143 CXDRVINFO_RFK,
2144 CXDRVINFO_RUN,
2145 CXDRVINFO_CTRL,
2146 CXDRVINFO_SCAN,
2147 CXDRVINFO_TRX, /* WL traffic to WL fw */
2148 CXDRVINFO_TXPWR,
2149 CXDRVINFO_FDDT,
2150 CXDRVINFO_MLO,
2151 CXDRVINFO_OSI,
2152 CXDRVINFO_MAX,
2153 };
2154
2155 enum rtw89_scan_mode {
2156 RTW89_SCAN_IMMEDIATE,
2157 RTW89_SCAN_DELAY,
2158 };
2159
2160 enum rtw89_scan_type {
2161 RTW89_SCAN_ONCE,
2162 RTW89_SCAN_NORMAL,
2163 RTW89_SCAN_NORMAL_SLOW,
2164 RTW89_SCAN_SEAMLESS,
2165 RTW89_SCAN_MAX,
2166 };
2167
RTW89_SET_FWCMD_CXHDR_TYPE(void * cmd,u8 val)2168 static inline void RTW89_SET_FWCMD_CXHDR_TYPE(void *cmd, u8 val)
2169 {
2170 u8p_replace_bits((u8 *)(cmd) + 0, val, GENMASK(7, 0));
2171 }
2172
RTW89_SET_FWCMD_CXHDR_LEN(void * cmd,u8 val)2173 static inline void RTW89_SET_FWCMD_CXHDR_LEN(void *cmd, u8 val)
2174 {
2175 u8p_replace_bits((u8 *)(cmd) + 1, val, GENMASK(7, 0));
2176 }
2177
2178 struct rtw89_h2c_cxhdr {
2179 u8 type;
2180 u8 len;
2181 } __packed;
2182
2183 struct rtw89_h2c_cxhdr_v7 {
2184 u8 type;
2185 u8 ver;
2186 u8 len;
2187 } __packed;
2188
2189 struct rtw89_h2c_cxctrl_v7 {
2190 struct rtw89_h2c_cxhdr_v7 hdr;
2191 struct rtw89_btc_ctrl_v7 ctrl;
2192 } __packed;
2193
2194 #define H2C_LEN_CXDRVHDR sizeof(struct rtw89_h2c_cxhdr)
2195 #define H2C_LEN_CXDRVHDR_V7 sizeof(struct rtw89_h2c_cxhdr_v7)
2196
2197 struct rtw89_btc_wl_role_info_v7_u8 {
2198 u8 connect_cnt;
2199 u8 link_mode;
2200 u8 link_mode_chg;
2201 u8 p2p_2g;
2202
2203 struct rtw89_btc_wl_active_role_v7 active_role[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER];
2204 } __packed;
2205
2206 struct rtw89_btc_wl_role_info_v7_u32 {
2207 __le32 role_map;
2208 __le32 mrole_type;
2209 __le32 mrole_noa_duration;
2210 __le32 dbcc_en;
2211 __le32 dbcc_chg;
2212 __le32 dbcc_2g_phy;
2213 } __packed;
2214
2215 struct rtw89_h2c_cxrole_v7 {
2216 struct rtw89_h2c_cxhdr_v7 hdr;
2217 struct rtw89_btc_wl_role_info_v7_u8 _u8;
2218 struct rtw89_btc_wl_role_info_v7_u32 _u32;
2219 } __packed;
2220
2221 struct rtw89_btc_wl_role_info_v8_u8 {
2222 u8 connect_cnt;
2223 u8 link_mode;
2224 u8 link_mode_chg;
2225 u8 p2p_2g;
2226
2227 u8 pta_req_band;
2228 u8 dbcc_en;
2229 u8 dbcc_chg;
2230 u8 dbcc_2g_phy;
2231
2232 struct rtw89_btc_wl_rlink rlink[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM];
2233 } __packed;
2234
2235 struct rtw89_btc_wl_role_info_v8_u32 {
2236 __le32 role_map;
2237 __le32 mrole_type;
2238 __le32 mrole_noa_duration;
2239 } __packed;
2240
2241 struct rtw89_h2c_cxrole_v8 {
2242 struct rtw89_h2c_cxhdr_v7 hdr;
2243 struct rtw89_btc_wl_role_info_v8_u8 _u8;
2244 struct rtw89_btc_wl_role_info_v8_u32 _u32;
2245 } __packed;
2246
2247 struct rtw89_h2c_cxinit {
2248 struct rtw89_h2c_cxhdr hdr;
2249 u8 ant_type;
2250 u8 ant_num;
2251 u8 ant_iso;
2252 u8 ant_info;
2253 u8 mod_rfe;
2254 u8 mod_cv;
2255 u8 mod_info;
2256 u8 mod_adie_kt;
2257 u8 wl_gch;
2258 u8 info;
2259 u8 rsvd;
2260 u8 rsvd1;
2261 } __packed;
2262
2263 #define RTW89_H2C_CXINIT_ANT_INFO_POS BIT(0)
2264 #define RTW89_H2C_CXINIT_ANT_INFO_DIVERSITY BIT(1)
2265 #define RTW89_H2C_CXINIT_ANT_INFO_BTG_POS GENMASK(3, 2)
2266 #define RTW89_H2C_CXINIT_ANT_INFO_STREAM_CNT GENMASK(7, 4)
2267
2268 #define RTW89_H2C_CXINIT_MOD_INFO_BT_SOLO BIT(0)
2269 #define RTW89_H2C_CXINIT_MOD_INFO_BT_POS BIT(1)
2270 #define RTW89_H2C_CXINIT_MOD_INFO_SW_TYPE BIT(2)
2271 #define RTW89_H2C_CXINIT_MOD_INFO_WA_TYPE GENMASK(5, 3)
2272
2273 #define RTW89_H2C_CXINIT_INFO_WL_ONLY BIT(0)
2274 #define RTW89_H2C_CXINIT_INFO_WL_INITOK BIT(1)
2275 #define RTW89_H2C_CXINIT_INFO_DBCC_EN BIT(2)
2276 #define RTW89_H2C_CXINIT_INFO_CX_OTHER BIT(3)
2277 #define RTW89_H2C_CXINIT_INFO_BT_ONLY BIT(4)
2278
2279 struct rtw89_h2c_cxinit_v7 {
2280 struct rtw89_h2c_cxhdr_v7 hdr;
2281 struct rtw89_btc_init_info_v7 init;
2282 } __packed;
2283
RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(void * cmd,u8 val)2284 static inline void RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(void *cmd, u8 val)
2285 {
2286 u8p_replace_bits((u8 *)(cmd) + 2, val, GENMASK(7, 0));
2287 }
2288
RTW89_SET_FWCMD_CXROLE_LINK_MODE(void * cmd,u8 val)2289 static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE(void *cmd, u8 val)
2290 {
2291 u8p_replace_bits((u8 *)(cmd) + 3, val, GENMASK(7, 0));
2292 }
2293
RTW89_SET_FWCMD_CXROLE_ROLE_NONE(void * cmd,u16 val)2294 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NONE(void *cmd, u16 val)
2295 {
2296 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(0));
2297 }
2298
RTW89_SET_FWCMD_CXROLE_ROLE_STA(void * cmd,u16 val)2299 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_STA(void *cmd, u16 val)
2300 {
2301 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(1));
2302 }
2303
RTW89_SET_FWCMD_CXROLE_ROLE_AP(void * cmd,u16 val)2304 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_AP(void *cmd, u16 val)
2305 {
2306 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(2));
2307 }
2308
RTW89_SET_FWCMD_CXROLE_ROLE_VAP(void * cmd,u16 val)2309 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_VAP(void *cmd, u16 val)
2310 {
2311 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(3));
2312 }
2313
RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(void * cmd,u16 val)2314 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(void *cmd, u16 val)
2315 {
2316 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(4));
2317 }
2318
RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(void * cmd,u16 val)2319 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(void *cmd, u16 val)
2320 {
2321 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(5));
2322 }
2323
RTW89_SET_FWCMD_CXROLE_ROLE_MESH(void * cmd,u16 val)2324 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MESH(void *cmd, u16 val)
2325 {
2326 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(6));
2327 }
2328
RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(void * cmd,u16 val)2329 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(void *cmd, u16 val)
2330 {
2331 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(7));
2332 }
2333
RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(void * cmd,u16 val)2334 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(void *cmd, u16 val)
2335 {
2336 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(8));
2337 }
2338
RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(void * cmd,u16 val)2339 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(void *cmd, u16 val)
2340 {
2341 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(9));
2342 }
2343
RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(void * cmd,u16 val)2344 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(void *cmd, u16 val)
2345 {
2346 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(10));
2347 }
2348
RTW89_SET_FWCMD_CXROLE_ROLE_NAN(void * cmd,u16 val)2349 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NAN(void *cmd, u16 val)
2350 {
2351 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(11));
2352 }
2353
RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(void * cmd,u8 val,int n,u8 offset)2354 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(void *cmd, u8 val, int n, u8 offset)
2355 {
2356 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0));
2357 }
2358
RTW89_SET_FWCMD_CXROLE_ACT_PID(void * cmd,u8 val,int n,u8 offset)2359 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID(void *cmd, u8 val, int n, u8 offset)
2360 {
2361 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1));
2362 }
2363
RTW89_SET_FWCMD_CXROLE_ACT_PHY(void * cmd,u8 val,int n,u8 offset)2364 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY(void *cmd, u8 val, int n, u8 offset)
2365 {
2366 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4));
2367 }
2368
RTW89_SET_FWCMD_CXROLE_ACT_NOA(void * cmd,u8 val,int n,u8 offset)2369 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA(void *cmd, u8 val, int n, u8 offset)
2370 {
2371 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5));
2372 }
2373
RTW89_SET_FWCMD_CXROLE_ACT_BAND(void * cmd,u8 val,int n,u8 offset)2374 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND(void *cmd, u8 val, int n, u8 offset)
2375 {
2376 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6));
2377 }
2378
RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(void * cmd,u8 val,int n,u8 offset)2379 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(void *cmd, u8 val, int n, u8 offset)
2380 {
2381 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0));
2382 }
2383
RTW89_SET_FWCMD_CXROLE_ACT_BW(void * cmd,u8 val,int n,u8 offset)2384 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW(void *cmd, u8 val, int n, u8 offset)
2385 {
2386 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1));
2387 }
2388
RTW89_SET_FWCMD_CXROLE_ACT_ROLE(void * cmd,u8 val,int n,u8 offset)2389 static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE(void *cmd, u8 val, int n, u8 offset)
2390 {
2391 u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0));
2392 }
2393
RTW89_SET_FWCMD_CXROLE_ACT_CH(void * cmd,u8 val,int n,u8 offset)2394 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH(void *cmd, u8 val, int n, u8 offset)
2395 {
2396 u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0));
2397 }
2398
RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(void * cmd,u16 val,int n,u8 offset)2399 static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(void *cmd, u16 val, int n, u8 offset)
2400 {
2401 le16p_replace_bits((__le16 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(15, 0));
2402 }
2403
RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(void * cmd,u16 val,int n,u8 offset)2404 static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(void *cmd, u16 val, int n, u8 offset)
2405 {
2406 le16p_replace_bits((__le16 *)((u8 *)cmd + (12 + (12 + offset) * n)), val, GENMASK(15, 0));
2407 }
2408
RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(void * cmd,u16 val,int n,u8 offset)2409 static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(void *cmd, u16 val, int n, u8 offset)
2410 {
2411 le16p_replace_bits((__le16 *)((u8 *)cmd + (14 + (12 + offset) * n)), val, GENMASK(15, 0));
2412 }
2413
RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(void * cmd,u16 val,int n,u8 offset)2414 static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(void *cmd, u16 val, int n, u8 offset)
2415 {
2416 le16p_replace_bits((__le16 *)((u8 *)cmd + (16 + (12 + offset) * n)), val, GENMASK(15, 0));
2417 }
2418
RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR(void * cmd,u32 val,int n,u8 offset)2419 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR(void *cmd, u32 val, int n, u8 offset)
2420 {
2421 le32p_replace_bits((__le32 *)((u8 *)cmd + (20 + (12 + offset) * n)), val, GENMASK(31, 0));
2422 }
2423
RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED_V2(void * cmd,u8 val,int n,u8 offset)2424 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED_V2(void *cmd, u8 val, int n, u8 offset)
2425 {
2426 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0));
2427 }
2428
RTW89_SET_FWCMD_CXROLE_ACT_PID_V2(void * cmd,u8 val,int n,u8 offset)2429 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID_V2(void *cmd, u8 val, int n, u8 offset)
2430 {
2431 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1));
2432 }
2433
RTW89_SET_FWCMD_CXROLE_ACT_PHY_V2(void * cmd,u8 val,int n,u8 offset)2434 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY_V2(void *cmd, u8 val, int n, u8 offset)
2435 {
2436 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4));
2437 }
2438
RTW89_SET_FWCMD_CXROLE_ACT_NOA_V2(void * cmd,u8 val,int n,u8 offset)2439 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_V2(void *cmd, u8 val, int n, u8 offset)
2440 {
2441 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5));
2442 }
2443
RTW89_SET_FWCMD_CXROLE_ACT_BAND_V2(void * cmd,u8 val,int n,u8 offset)2444 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND_V2(void *cmd, u8 val, int n, u8 offset)
2445 {
2446 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6));
2447 }
2448
RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS_V2(void * cmd,u8 val,int n,u8 offset)2449 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS_V2(void *cmd, u8 val, int n, u8 offset)
2450 {
2451 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0));
2452 }
2453
RTW89_SET_FWCMD_CXROLE_ACT_BW_V2(void * cmd,u8 val,int n,u8 offset)2454 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW_V2(void *cmd, u8 val, int n, u8 offset)
2455 {
2456 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1));
2457 }
2458
RTW89_SET_FWCMD_CXROLE_ACT_ROLE_V2(void * cmd,u8 val,int n,u8 offset)2459 static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE_V2(void *cmd, u8 val, int n, u8 offset)
2460 {
2461 u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0));
2462 }
2463
RTW89_SET_FWCMD_CXROLE_ACT_CH_V2(void * cmd,u8 val,int n,u8 offset)2464 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH_V2(void *cmd, u8 val, int n, u8 offset)
2465 {
2466 u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0));
2467 }
2468
RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR_V2(void * cmd,u32 val,int n,u8 offset)2469 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR_V2(void *cmd, u32 val, int n, u8 offset)
2470 {
2471 le32p_replace_bits((__le32 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(31, 0));
2472 }
2473
RTW89_SET_FWCMD_CXROLE_MROLE_TYPE(void * cmd,u32 val,u8 offset)2474 static inline void RTW89_SET_FWCMD_CXROLE_MROLE_TYPE(void *cmd, u32 val, u8 offset)
2475 {
2476 le32p_replace_bits((__le32 *)((u8 *)cmd + offset), val, GENMASK(31, 0));
2477 }
2478
RTW89_SET_FWCMD_CXROLE_MROLE_NOA(void * cmd,u32 val,u8 offset)2479 static inline void RTW89_SET_FWCMD_CXROLE_MROLE_NOA(void *cmd, u32 val, u8 offset)
2480 {
2481 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 4), val, GENMASK(31, 0));
2482 }
2483
RTW89_SET_FWCMD_CXROLE_DBCC_EN(void * cmd,u32 val,u8 offset)2484 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_EN(void *cmd, u32 val, u8 offset)
2485 {
2486 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(0));
2487 }
2488
RTW89_SET_FWCMD_CXROLE_DBCC_CHG(void * cmd,u32 val,u8 offset)2489 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_CHG(void *cmd, u32 val, u8 offset)
2490 {
2491 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(1));
2492 }
2493
RTW89_SET_FWCMD_CXROLE_DBCC_2G_PHY(void * cmd,u32 val,u8 offset)2494 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_2G_PHY(void *cmd, u32 val, u8 offset)
2495 {
2496 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, GENMASK(3, 2));
2497 }
2498
RTW89_SET_FWCMD_CXROLE_LINK_MODE_CHG(void * cmd,u32 val,u8 offset)2499 static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE_CHG(void *cmd, u32 val, u8 offset)
2500 {
2501 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(4));
2502 }
2503
RTW89_SET_FWCMD_CXCTRL_MANUAL(void * cmd,u32 val)2504 static inline void RTW89_SET_FWCMD_CXCTRL_MANUAL(void *cmd, u32 val)
2505 {
2506 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(0));
2507 }
2508
RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(void * cmd,u32 val)2509 static inline void RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(void *cmd, u32 val)
2510 {
2511 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(1));
2512 }
2513
RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(void * cmd,u32 val)2514 static inline void RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(void *cmd, u32 val)
2515 {
2516 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(2));
2517 }
2518
RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(void * cmd,u32 val)2519 static inline void RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(void *cmd, u32 val)
2520 {
2521 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(18, 3));
2522 }
2523
RTW89_SET_FWCMD_CXTRX_TXLV(void * cmd,u8 val)2524 static inline void RTW89_SET_FWCMD_CXTRX_TXLV(void *cmd, u8 val)
2525 {
2526 u8p_replace_bits((u8 *)cmd + 2, val, GENMASK(7, 0));
2527 }
2528
RTW89_SET_FWCMD_CXTRX_RXLV(void * cmd,u8 val)2529 static inline void RTW89_SET_FWCMD_CXTRX_RXLV(void *cmd, u8 val)
2530 {
2531 u8p_replace_bits((u8 *)cmd + 3, val, GENMASK(7, 0));
2532 }
2533
RTW89_SET_FWCMD_CXTRX_WLRSSI(void * cmd,u8 val)2534 static inline void RTW89_SET_FWCMD_CXTRX_WLRSSI(void *cmd, u8 val)
2535 {
2536 u8p_replace_bits((u8 *)cmd + 4, val, GENMASK(7, 0));
2537 }
2538
RTW89_SET_FWCMD_CXTRX_BTRSSI(void * cmd,u8 val)2539 static inline void RTW89_SET_FWCMD_CXTRX_BTRSSI(void *cmd, u8 val)
2540 {
2541 u8p_replace_bits((u8 *)cmd + 5, val, GENMASK(7, 0));
2542 }
2543
RTW89_SET_FWCMD_CXTRX_TXPWR(void * cmd,s8 val)2544 static inline void RTW89_SET_FWCMD_CXTRX_TXPWR(void *cmd, s8 val)
2545 {
2546 u8p_replace_bits((u8 *)cmd + 6, val, GENMASK(7, 0));
2547 }
2548
RTW89_SET_FWCMD_CXTRX_RXGAIN(void * cmd,s8 val)2549 static inline void RTW89_SET_FWCMD_CXTRX_RXGAIN(void *cmd, s8 val)
2550 {
2551 u8p_replace_bits((u8 *)cmd + 7, val, GENMASK(7, 0));
2552 }
2553
RTW89_SET_FWCMD_CXTRX_BTTXPWR(void * cmd,s8 val)2554 static inline void RTW89_SET_FWCMD_CXTRX_BTTXPWR(void *cmd, s8 val)
2555 {
2556 u8p_replace_bits((u8 *)cmd + 8, val, GENMASK(7, 0));
2557 }
2558
RTW89_SET_FWCMD_CXTRX_BTRXGAIN(void * cmd,s8 val)2559 static inline void RTW89_SET_FWCMD_CXTRX_BTRXGAIN(void *cmd, s8 val)
2560 {
2561 u8p_replace_bits((u8 *)cmd + 9, val, GENMASK(7, 0));
2562 }
2563
RTW89_SET_FWCMD_CXTRX_CN(void * cmd,u8 val)2564 static inline void RTW89_SET_FWCMD_CXTRX_CN(void *cmd, u8 val)
2565 {
2566 u8p_replace_bits((u8 *)cmd + 10, val, GENMASK(7, 0));
2567 }
2568
RTW89_SET_FWCMD_CXTRX_NHM(void * cmd,s8 val)2569 static inline void RTW89_SET_FWCMD_CXTRX_NHM(void *cmd, s8 val)
2570 {
2571 u8p_replace_bits((u8 *)cmd + 11, val, GENMASK(7, 0));
2572 }
2573
RTW89_SET_FWCMD_CXTRX_BTPROFILE(void * cmd,u8 val)2574 static inline void RTW89_SET_FWCMD_CXTRX_BTPROFILE(void *cmd, u8 val)
2575 {
2576 u8p_replace_bits((u8 *)cmd + 12, val, GENMASK(7, 0));
2577 }
2578
RTW89_SET_FWCMD_CXTRX_RSVD2(void * cmd,u8 val)2579 static inline void RTW89_SET_FWCMD_CXTRX_RSVD2(void *cmd, u8 val)
2580 {
2581 u8p_replace_bits((u8 *)cmd + 13, val, GENMASK(7, 0));
2582 }
2583
RTW89_SET_FWCMD_CXTRX_TXRATE(void * cmd,u16 val)2584 static inline void RTW89_SET_FWCMD_CXTRX_TXRATE(void *cmd, u16 val)
2585 {
2586 le16p_replace_bits((__le16 *)((u8 *)cmd + 14), val, GENMASK(15, 0));
2587 }
2588
RTW89_SET_FWCMD_CXTRX_RXRATE(void * cmd,u16 val)2589 static inline void RTW89_SET_FWCMD_CXTRX_RXRATE(void *cmd, u16 val)
2590 {
2591 le16p_replace_bits((__le16 *)((u8 *)cmd + 16), val, GENMASK(15, 0));
2592 }
2593
RTW89_SET_FWCMD_CXTRX_TXTP(void * cmd,u32 val)2594 static inline void RTW89_SET_FWCMD_CXTRX_TXTP(void *cmd, u32 val)
2595 {
2596 le32p_replace_bits((__le32 *)((u8 *)cmd + 18), val, GENMASK(31, 0));
2597 }
2598
RTW89_SET_FWCMD_CXTRX_RXTP(void * cmd,u32 val)2599 static inline void RTW89_SET_FWCMD_CXTRX_RXTP(void *cmd, u32 val)
2600 {
2601 le32p_replace_bits((__le32 *)((u8 *)cmd + 22), val, GENMASK(31, 0));
2602 }
2603
RTW89_SET_FWCMD_CXTRX_RXERRRA(void * cmd,u32 val)2604 static inline void RTW89_SET_FWCMD_CXTRX_RXERRRA(void *cmd, u32 val)
2605 {
2606 le32p_replace_bits((__le32 *)((u8 *)cmd + 26), val, GENMASK(31, 0));
2607 }
2608
RTW89_SET_FWCMD_CXRFK_STATE(void * cmd,u32 val)2609 static inline void RTW89_SET_FWCMD_CXRFK_STATE(void *cmd, u32 val)
2610 {
2611 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(1, 0));
2612 }
2613
RTW89_SET_FWCMD_CXRFK_PATH_MAP(void * cmd,u32 val)2614 static inline void RTW89_SET_FWCMD_CXRFK_PATH_MAP(void *cmd, u32 val)
2615 {
2616 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(5, 2));
2617 }
2618
RTW89_SET_FWCMD_CXRFK_PHY_MAP(void * cmd,u32 val)2619 static inline void RTW89_SET_FWCMD_CXRFK_PHY_MAP(void *cmd, u32 val)
2620 {
2621 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(7, 6));
2622 }
2623
RTW89_SET_FWCMD_CXRFK_BAND(void * cmd,u32 val)2624 static inline void RTW89_SET_FWCMD_CXRFK_BAND(void *cmd, u32 val)
2625 {
2626 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(9, 8));
2627 }
2628
RTW89_SET_FWCMD_CXRFK_TYPE(void * cmd,u32 val)2629 static inline void RTW89_SET_FWCMD_CXRFK_TYPE(void *cmd, u32 val)
2630 {
2631 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(17, 10));
2632 }
2633
RTW89_SET_FWCMD_PACKET_OFLD_PKT_IDX(void * cmd,u32 val)2634 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_IDX(void *cmd, u32 val)
2635 {
2636 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0));
2637 }
2638
RTW89_SET_FWCMD_PACKET_OFLD_PKT_OP(void * cmd,u32 val)2639 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_OP(void *cmd, u32 val)
2640 {
2641 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(10, 8));
2642 }
2643
RTW89_SET_FWCMD_PACKET_OFLD_PKT_LENGTH(void * cmd,u32 val)2644 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_LENGTH(void *cmd, u32 val)
2645 {
2646 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(31, 16));
2647 }
2648
2649 struct rtw89_h2c_chinfo_elem {
2650 __le32 w0;
2651 __le32 w1;
2652 __le32 w2;
2653 __le32 w3;
2654 __le32 w4;
2655 __le32 w5;
2656 __le32 w6;
2657 } __packed;
2658
2659 #define RTW89_H2C_CHINFO_W0_PERIOD GENMASK(7, 0)
2660 #define RTW89_H2C_CHINFO_W0_DWELL GENMASK(15, 8)
2661 #define RTW89_H2C_CHINFO_W0_CENTER_CH GENMASK(23, 16)
2662 #define RTW89_H2C_CHINFO_W0_PRI_CH GENMASK(31, 24)
2663 #define RTW89_H2C_CHINFO_W1_BW GENMASK(2, 0)
2664 #define RTW89_H2C_CHINFO_W1_ACTION GENMASK(7, 3)
2665 #define RTW89_H2C_CHINFO_W1_NUM_PKT GENMASK(11, 8)
2666 #define RTW89_H2C_CHINFO_W1_TX BIT(12)
2667 #define RTW89_H2C_CHINFO_W1_PAUSE_DATA BIT(13)
2668 #define RTW89_H2C_CHINFO_W1_BAND GENMASK(15, 14)
2669 #define RTW89_H2C_CHINFO_W1_PKT_ID GENMASK(23, 16)
2670 #define RTW89_H2C_CHINFO_W1_DFS BIT(24)
2671 #define RTW89_H2C_CHINFO_W1_TX_NULL BIT(25)
2672 #define RTW89_H2C_CHINFO_W1_RANDOM BIT(26)
2673 #define RTW89_H2C_CHINFO_W1_CFG_TX BIT(27)
2674 #define RTW89_H2C_CHINFO_W2_PKT0 GENMASK(7, 0)
2675 #define RTW89_H2C_CHINFO_W2_PKT1 GENMASK(15, 8)
2676 #define RTW89_H2C_CHINFO_W2_PKT2 GENMASK(23, 16)
2677 #define RTW89_H2C_CHINFO_W2_PKT3 GENMASK(31, 24)
2678 #define RTW89_H2C_CHINFO_W3_PKT4 GENMASK(7, 0)
2679 #define RTW89_H2C_CHINFO_W3_PKT5 GENMASK(15, 8)
2680 #define RTW89_H2C_CHINFO_W3_PKT6 GENMASK(23, 16)
2681 #define RTW89_H2C_CHINFO_W3_PKT7 GENMASK(31, 24)
2682 #define RTW89_H2C_CHINFO_W4_POWER_IDX GENMASK(15, 0)
2683
2684 struct rtw89_h2c_chinfo_elem_be {
2685 __le32 w0;
2686 __le32 w1;
2687 __le32 w2;
2688 __le32 w3;
2689 __le32 w4;
2690 __le32 w5;
2691 __le32 w6;
2692 __le32 w7;
2693 } __packed;
2694
2695 #define RTW89_H2C_CHINFO_BE_W0_PERIOD GENMASK(7, 0)
2696 #define RTW89_H2C_CHINFO_BE_W0_DWELL GENMASK(15, 8)
2697 #define RTW89_H2C_CHINFO_BE_W0_CENTER_CH GENMASK(23, 16)
2698 #define RTW89_H2C_CHINFO_BE_W0_PRI_CH GENMASK(31, 24)
2699 #define RTW89_H2C_CHINFO_BE_W1_BW GENMASK(2, 0)
2700 #define RTW89_H2C_CHINFO_BE_W1_CH_BAND GENMASK(4, 3)
2701 #define RTW89_H2C_CHINFO_BE_W1_DFS BIT(5)
2702 #define RTW89_H2C_CHINFO_BE_W1_PAUSE_DATA BIT(6)
2703 #define RTW89_H2C_CHINFO_BE_W1_TX_NULL BIT(7)
2704 #define RTW89_H2C_CHINFO_BE_W1_RANDOM BIT(8)
2705 #define RTW89_H2C_CHINFO_BE_W1_NOTIFY GENMASK(13, 9)
2706 #define RTW89_H2C_CHINFO_BE_W1_PROBE BIT(14)
2707 #define RTW89_H2C_CHINFO_BE_W1_EARLY_LEAVE_CRIT GENMASK(17, 15)
2708 #define RTW89_H2C_CHINFO_BE_W1_CHKPT_TIMER GENMASK(31, 24)
2709 #define RTW89_H2C_CHINFO_BE_W2_EARLY_LEAVE_TIME GENMASK(7, 0)
2710 #define RTW89_H2C_CHINFO_BE_W2_EARLY_LEAVE_TH GENMASK(15, 8)
2711 #define RTW89_H2C_CHINFO_BE_W2_TX_PKT_CTRL GENMASK(31, 16)
2712 #define RTW89_H2C_CHINFO_BE_W3_PKT0 GENMASK(7, 0)
2713 #define RTW89_H2C_CHINFO_BE_W3_PKT1 GENMASK(15, 8)
2714 #define RTW89_H2C_CHINFO_BE_W3_PKT2 GENMASK(23, 16)
2715 #define RTW89_H2C_CHINFO_BE_W3_PKT3 GENMASK(31, 24)
2716 #define RTW89_H2C_CHINFO_BE_W4_PKT4 GENMASK(7, 0)
2717 #define RTW89_H2C_CHINFO_BE_W4_PKT5 GENMASK(15, 8)
2718 #define RTW89_H2C_CHINFO_BE_W4_PKT6 GENMASK(23, 16)
2719 #define RTW89_H2C_CHINFO_BE_W4_PKT7 GENMASK(31, 24)
2720 #define RTW89_H2C_CHINFO_BE_W5_SW_DEF GENMASK(7, 0)
2721 #define RTW89_H2C_CHINFO_BE_W5_FW_PROBE0_SSIDS GENMASK(31, 16)
2722 #define RTW89_H2C_CHINFO_BE_W6_FW_PROBE0_SHORTSSIDS GENMASK(15, 0)
2723 #define RTW89_H2C_CHINFO_BE_W6_FW_PROBE0_BSSIDS GENMASK(31, 16)
2724 #define RTW89_H2C_CHINFO_BE_W7_PERIOD_V1 GENMASK(15, 0)
2725
2726 struct rtw89_h2c_chinfo {
2727 u8 ch_num;
2728 u8 elem_size;
2729 u8 arg;
2730 u8 rsvd0;
2731 struct rtw89_h2c_chinfo_elem elem[] __counted_by(ch_num);
2732 } __packed;
2733
2734 struct rtw89_h2c_chinfo_be {
2735 u8 ch_num;
2736 u8 elem_size;
2737 u8 arg;
2738 u8 rsvd0;
2739 struct rtw89_h2c_chinfo_elem_be elem[] __counted_by(ch_num);
2740 } __packed;
2741
2742 #define RTW89_H2C_CHINFO_ARG_MAC_IDX_MASK BIT(0)
2743 #define RTW89_H2C_CHINFO_ARG_APPEND_MASK BIT(1)
2744
2745 struct rtw89_h2c_scanofld {
2746 __le32 w0;
2747 __le32 w1;
2748 __le32 w2;
2749 __le32 tsf_high;
2750 __le32 tsf_low;
2751 __le32 w5;
2752 __le32 w6;
2753 } __packed;
2754
2755 #define RTW89_H2C_SCANOFLD_W0_MACID GENMASK(7, 0)
2756 #define RTW89_H2C_SCANOFLD_W0_NORM_CY GENMASK(15, 8)
2757 #define RTW89_H2C_SCANOFLD_W0_PORT_ID GENMASK(18, 16)
2758 #define RTW89_H2C_SCANOFLD_W0_BAND BIT(19)
2759 #define RTW89_H2C_SCANOFLD_W0_OPERATION GENMASK(21, 20)
2760 #define RTW89_H2C_SCANOFLD_W0_TARGET_CH_BAND GENMASK(23, 22)
2761 #define RTW89_H2C_SCANOFLD_W1_NOTIFY_END BIT(0)
2762 #define RTW89_H2C_SCANOFLD_W1_TARGET_CH_MODE BIT(1)
2763 #define RTW89_H2C_SCANOFLD_W1_START_MODE BIT(2)
2764 #define RTW89_H2C_SCANOFLD_W1_SCAN_TYPE GENMASK(4, 3)
2765 #define RTW89_H2C_SCANOFLD_W1_TARGET_CH_BW GENMASK(7, 5)
2766 #define RTW89_H2C_SCANOFLD_W1_TARGET_PRI_CH GENMASK(15, 8)
2767 #define RTW89_H2C_SCANOFLD_W1_TARGET_CENTRAL_CH GENMASK(23, 16)
2768 #define RTW89_H2C_SCANOFLD_W1_PROBE_REQ_PKT_ID GENMASK(31, 24)
2769 #define RTW89_H2C_SCANOFLD_W2_NORM_PD GENMASK(15, 0)
2770 #define RTW89_H2C_SCANOFLD_W2_SLOW_PD GENMASK(23, 16)
2771 #define RTW89_H2C_SCANOFLD_W3_TSF_HIGH GENMASK(31, 0)
2772 #define RTW89_H2C_SCANOFLD_W4_TSF_LOW GENMASK(31, 0)
2773
2774 struct rtw89_h2c_scanofld_be_macc_role {
2775 __le32 w0;
2776 } __packed;
2777
2778 #define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_BAND GENMASK(1, 0)
2779 #define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_PORT GENMASK(4, 2)
2780 #define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_MACID GENMASK(23, 8)
2781 #define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_OPCH_END GENMASK(31, 24)
2782
2783 struct rtw89_h2c_scanofld_be_opch {
2784 __le32 w0;
2785 __le32 w1;
2786 __le32 w2;
2787 __le32 w3;
2788 __le32 w4;
2789 } __packed;
2790
2791 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_MACID GENMASK(15, 0)
2792 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_BAND GENMASK(17, 16)
2793 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_PORT GENMASK(20, 18)
2794 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_POLICY GENMASK(22, 21)
2795 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_TXNULL BIT(23)
2796 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_POLICY_VAL GENMASK(31, 24)
2797 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_DURATION GENMASK(7, 0)
2798 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_CH_BAND GENMASK(9, 8)
2799 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_BW GENMASK(12, 10)
2800 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_NOTIFY GENMASK(14, 13)
2801 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_PRI_CH GENMASK(23, 16)
2802 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_CENTRAL_CH GENMASK(31, 24)
2803 #define RTW89_H2C_SCANOFLD_BE_OPCH_W2_PKTS_CTRL GENMASK(7, 0)
2804 #define RTW89_H2C_SCANOFLD_BE_OPCH_W2_SW_DEF GENMASK(15, 8)
2805 #define RTW89_H2C_SCANOFLD_BE_OPCH_W2_SS GENMASK(18, 16)
2806 #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT0 GENMASK(7, 0)
2807 #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT1 GENMASK(15, 8)
2808 #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT2 GENMASK(23, 16)
2809 #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT3 GENMASK(31, 24)
2810 #define RTW89_H2C_SCANOFLD_BE_OPCH_W4_DURATION_V1 GENMASK(15, 0)
2811
2812 struct rtw89_h2c_scanofld_be {
2813 __le32 w0;
2814 __le32 w1;
2815 __le32 w2;
2816 __le32 w3;
2817 __le32 w4;
2818 __le32 w5;
2819 __le32 w6;
2820 __le32 w7;
2821 __le32 w8;
2822 __le32 w9; /* Added after SCAN_OFFLOAD_BE_V1 */
2823 /* struct rtw89_h2c_scanofld_be_macc_role (flexible number) */
2824 /* struct rtw89_h2c_scanofld_be_opch (flexible number) */
2825 } __packed;
2826
2827 #define RTW89_H2C_SCANOFLD_BE_W0_OP GENMASK(1, 0)
2828 #define RTW89_H2C_SCANOFLD_BE_W0_SCAN_MODE GENMASK(3, 2)
2829 #define RTW89_H2C_SCANOFLD_BE_W0_REPEAT GENMASK(5, 4)
2830 #define RTW89_H2C_SCANOFLD_BE_W0_NOTIFY_END BIT(6)
2831 #define RTW89_H2C_SCANOFLD_BE_W0_LEARN_CH BIT(7)
2832 #define RTW89_H2C_SCANOFLD_BE_W0_MACID GENMASK(23, 8)
2833 #define RTW89_H2C_SCANOFLD_BE_W0_PORT GENMASK(26, 24)
2834 #define RTW89_H2C_SCANOFLD_BE_W0_BAND GENMASK(28, 27)
2835 #define RTW89_H2C_SCANOFLD_BE_W0_PROBE_WITH_RATE BIT(29)
2836 #define RTW89_H2C_SCANOFLD_BE_W1_NUM_MACC_ROLE GENMASK(7, 0)
2837 #define RTW89_H2C_SCANOFLD_BE_W1_NUM_OP GENMASK(15, 8)
2838 #define RTW89_H2C_SCANOFLD_BE_W1_NORM_PD GENMASK(31, 16)
2839 #define RTW89_H2C_SCANOFLD_BE_W2_SLOW_PD GENMASK(15, 0)
2840 #define RTW89_H2C_SCANOFLD_BE_W2_NORM_CY GENMASK(23, 16)
2841 #define RTW89_H2C_SCANOFLD_BE_W2_OPCH_END GENMASK(31, 24)
2842 #define RTW89_H2C_SCANOFLD_BE_W3_NUM_SSID GENMASK(7, 0)
2843 #define RTW89_H2C_SCANOFLD_BE_W3_NUM_SHORT_SSID GENMASK(15, 8)
2844 #define RTW89_H2C_SCANOFLD_BE_W3_NUM_BSSID GENMASK(23, 16)
2845 #define RTW89_H2C_SCANOFLD_BE_W3_PROBEID GENMASK(31, 24)
2846 #define RTW89_H2C_SCANOFLD_BE_W4_PROBE_5G GENMASK(7, 0)
2847 #define RTW89_H2C_SCANOFLD_BE_W4_PROBE_6G GENMASK(15, 8)
2848 #define RTW89_H2C_SCANOFLD_BE_W4_DELAY_START GENMASK(31, 16)
2849 #define RTW89_H2C_SCANOFLD_BE_W5_MLO_MODE GENMASK(31, 0)
2850 #define RTW89_H2C_SCANOFLD_BE_W6_CHAN_PROHIB_LOW GENMASK(31, 0)
2851 #define RTW89_H2C_SCANOFLD_BE_W7_CHAN_PROHIB_HIGH GENMASK(31, 0)
2852 #define RTW89_H2C_SCANOFLD_BE_W8_PROBE_RATE_2GHZ GENMASK(7, 0)
2853 #define RTW89_H2C_SCANOFLD_BE_W8_PROBE_RATE_5GHZ GENMASK(15, 8)
2854 #define RTW89_H2C_SCANOFLD_BE_W8_PROBE_RATE_6GHZ GENMASK(23, 16)
2855 #define RTW89_H2C_SCANOFLD_BE_W9_SIZE_CFG GENMASK(7, 0)
2856 #define RTW89_H2C_SCANOFLD_BE_W9_SIZE_MACC GENMASK(15, 8)
2857 #define RTW89_H2C_SCANOFLD_BE_W9_SIZE_OP GENMASK(23, 16)
2858
2859 struct rtw89_h2c_fwips {
2860 __le32 w0;
2861 } __packed;
2862
2863 #define RTW89_H2C_FW_IPS_W0_MACID GENMASK(7, 0)
2864 #define RTW89_H2C_FW_IPS_W0_ENABLE BIT(8)
2865
RTW89_SET_FWCMD_P2P_MACID(void * cmd,u32 val)2866 static inline void RTW89_SET_FWCMD_P2P_MACID(void *cmd, u32 val)
2867 {
2868 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
2869 }
2870
RTW89_SET_FWCMD_P2P_P2PID(void * cmd,u32 val)2871 static inline void RTW89_SET_FWCMD_P2P_P2PID(void *cmd, u32 val)
2872 {
2873 le32p_replace_bits((__le32 *)cmd, val, GENMASK(11, 8));
2874 }
2875
RTW89_SET_FWCMD_P2P_NOAID(void * cmd,u32 val)2876 static inline void RTW89_SET_FWCMD_P2P_NOAID(void *cmd, u32 val)
2877 {
2878 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 12));
2879 }
2880
RTW89_SET_FWCMD_P2P_ACT(void * cmd,u32 val)2881 static inline void RTW89_SET_FWCMD_P2P_ACT(void *cmd, u32 val)
2882 {
2883 le32p_replace_bits((__le32 *)cmd, val, GENMASK(19, 16));
2884 }
2885
RTW89_SET_FWCMD_P2P_TYPE(void * cmd,u32 val)2886 static inline void RTW89_SET_FWCMD_P2P_TYPE(void *cmd, u32 val)
2887 {
2888 le32p_replace_bits((__le32 *)cmd, val, BIT(20));
2889 }
2890
RTW89_SET_FWCMD_P2P_ALL_SLEP(void * cmd,u32 val)2891 static inline void RTW89_SET_FWCMD_P2P_ALL_SLEP(void *cmd, u32 val)
2892 {
2893 le32p_replace_bits((__le32 *)cmd, val, BIT(21));
2894 }
2895
RTW89_SET_FWCMD_NOA_START_TIME(void * cmd,__le32 val)2896 static inline void RTW89_SET_FWCMD_NOA_START_TIME(void *cmd, __le32 val)
2897 {
2898 *((__le32 *)cmd + 1) = val;
2899 }
2900
RTW89_SET_FWCMD_NOA_INTERVAL(void * cmd,__le32 val)2901 static inline void RTW89_SET_FWCMD_NOA_INTERVAL(void *cmd, __le32 val)
2902 {
2903 *((__le32 *)cmd + 2) = val;
2904 }
2905
RTW89_SET_FWCMD_NOA_DURATION(void * cmd,__le32 val)2906 static inline void RTW89_SET_FWCMD_NOA_DURATION(void *cmd, __le32 val)
2907 {
2908 *((__le32 *)cmd + 3) = val;
2909 }
2910
RTW89_SET_FWCMD_NOA_COUNT(void * cmd,u32 val)2911 static inline void RTW89_SET_FWCMD_NOA_COUNT(void *cmd, u32 val)
2912 {
2913 le32p_replace_bits((__le32 *)(cmd) + 4, val, GENMASK(7, 0));
2914 }
2915
RTW89_SET_FWCMD_NOA_CTWINDOW(void * cmd,u32 val)2916 static inline void RTW89_SET_FWCMD_NOA_CTWINDOW(void *cmd, u32 val)
2917 {
2918 u8 ctwnd;
2919
2920 if (!(val & IEEE80211_P2P_OPPPS_ENABLE_BIT))
2921 return;
2922 ctwnd = FIELD_GET(IEEE80211_P2P_OPPPS_CTWINDOW_MASK, val);
2923 le32p_replace_bits((__le32 *)(cmd) + 4, ctwnd, GENMASK(23, 8));
2924 }
2925
RTW89_SET_FWCMD_TSF32_TOGL_BAND(void * cmd,u32 val)2926 static inline void RTW89_SET_FWCMD_TSF32_TOGL_BAND(void *cmd, u32 val)
2927 {
2928 le32p_replace_bits((__le32 *)cmd, val, BIT(0));
2929 }
2930
RTW89_SET_FWCMD_TSF32_TOGL_EN(void * cmd,u32 val)2931 static inline void RTW89_SET_FWCMD_TSF32_TOGL_EN(void *cmd, u32 val)
2932 {
2933 le32p_replace_bits((__le32 *)cmd, val, BIT(1));
2934 }
2935
RTW89_SET_FWCMD_TSF32_TOGL_PORT(void * cmd,u32 val)2936 static inline void RTW89_SET_FWCMD_TSF32_TOGL_PORT(void *cmd, u32 val)
2937 {
2938 le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 2));
2939 }
2940
RTW89_SET_FWCMD_TSF32_TOGL_EARLY(void * cmd,u32 val)2941 static inline void RTW89_SET_FWCMD_TSF32_TOGL_EARLY(void *cmd, u32 val)
2942 {
2943 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 16));
2944 }
2945
2946 enum rtw89_fw_mcc_c2h_rpt_cfg {
2947 RTW89_FW_MCC_C2H_RPT_OFF = 0,
2948 RTW89_FW_MCC_C2H_RPT_FAIL_ONLY = 1,
2949 RTW89_FW_MCC_C2H_RPT_ALL = 2,
2950 };
2951
2952 struct rtw89_fw_mcc_add_req {
2953 u8 macid;
2954 u8 central_ch_seg0;
2955 u8 central_ch_seg1;
2956 u8 primary_ch;
2957 enum rtw89_bandwidth bandwidth: 4;
2958 u32 group: 2;
2959 u32 c2h_rpt: 2;
2960 u32 dis_tx_null: 1;
2961 u32 dis_sw_retry: 1;
2962 u32 in_curr_ch: 1;
2963 u32 sw_retry_count: 3;
2964 u32 tx_null_early: 4;
2965 u32 btc_in_2g: 1;
2966 u32 pta_en: 1;
2967 u32 rfk_by_pass: 1;
2968 u32 ch_band_type: 2;
2969 u32 rsvd0: 9;
2970 u32 duration;
2971 u8 courtesy_en;
2972 u8 courtesy_num;
2973 u8 courtesy_target;
2974 u8 rsvd1;
2975 };
2976
RTW89_SET_FWCMD_ADD_MCC_MACID(void * cmd,u32 val)2977 static inline void RTW89_SET_FWCMD_ADD_MCC_MACID(void *cmd, u32 val)
2978 {
2979 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
2980 }
2981
RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG0(void * cmd,u32 val)2982 static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG0(void *cmd, u32 val)
2983 {
2984 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
2985 }
2986
RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG1(void * cmd,u32 val)2987 static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG1(void *cmd, u32 val)
2988 {
2989 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
2990 }
2991
RTW89_SET_FWCMD_ADD_MCC_PRIMARY_CH(void * cmd,u32 val)2992 static inline void RTW89_SET_FWCMD_ADD_MCC_PRIMARY_CH(void *cmd, u32 val)
2993 {
2994 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
2995 }
2996
RTW89_SET_FWCMD_ADD_MCC_BANDWIDTH(void * cmd,u32 val)2997 static inline void RTW89_SET_FWCMD_ADD_MCC_BANDWIDTH(void *cmd, u32 val)
2998 {
2999 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(3, 0));
3000 }
3001
RTW89_SET_FWCMD_ADD_MCC_GROUP(void * cmd,u32 val)3002 static inline void RTW89_SET_FWCMD_ADD_MCC_GROUP(void *cmd, u32 val)
3003 {
3004 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(5, 4));
3005 }
3006
RTW89_SET_FWCMD_ADD_MCC_C2H_RPT(void * cmd,u32 val)3007 static inline void RTW89_SET_FWCMD_ADD_MCC_C2H_RPT(void *cmd, u32 val)
3008 {
3009 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 6));
3010 }
3011
RTW89_SET_FWCMD_ADD_MCC_DIS_TX_NULL(void * cmd,u32 val)3012 static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_TX_NULL(void *cmd, u32 val)
3013 {
3014 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(8));
3015 }
3016
RTW89_SET_FWCMD_ADD_MCC_DIS_SW_RETRY(void * cmd,u32 val)3017 static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_SW_RETRY(void *cmd, u32 val)
3018 {
3019 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(9));
3020 }
3021
RTW89_SET_FWCMD_ADD_MCC_IN_CURR_CH(void * cmd,u32 val)3022 static inline void RTW89_SET_FWCMD_ADD_MCC_IN_CURR_CH(void *cmd, u32 val)
3023 {
3024 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(10));
3025 }
3026
RTW89_SET_FWCMD_ADD_MCC_SW_RETRY_COUNT(void * cmd,u32 val)3027 static inline void RTW89_SET_FWCMD_ADD_MCC_SW_RETRY_COUNT(void *cmd, u32 val)
3028 {
3029 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(13, 11));
3030 }
3031
RTW89_SET_FWCMD_ADD_MCC_TX_NULL_EARLY(void * cmd,u32 val)3032 static inline void RTW89_SET_FWCMD_ADD_MCC_TX_NULL_EARLY(void *cmd, u32 val)
3033 {
3034 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(17, 14));
3035 }
3036
RTW89_SET_FWCMD_ADD_MCC_BTC_IN_2G(void * cmd,u32 val)3037 static inline void RTW89_SET_FWCMD_ADD_MCC_BTC_IN_2G(void *cmd, u32 val)
3038 {
3039 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(18));
3040 }
3041
RTW89_SET_FWCMD_ADD_MCC_PTA_EN(void * cmd,u32 val)3042 static inline void RTW89_SET_FWCMD_ADD_MCC_PTA_EN(void *cmd, u32 val)
3043 {
3044 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(19));
3045 }
3046
RTW89_SET_FWCMD_ADD_MCC_RFK_BY_PASS(void * cmd,u32 val)3047 static inline void RTW89_SET_FWCMD_ADD_MCC_RFK_BY_PASS(void *cmd, u32 val)
3048 {
3049 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(20));
3050 }
3051
RTW89_SET_FWCMD_ADD_MCC_CH_BAND_TYPE(void * cmd,u32 val)3052 static inline void RTW89_SET_FWCMD_ADD_MCC_CH_BAND_TYPE(void *cmd, u32 val)
3053 {
3054 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(22, 21));
3055 }
3056
RTW89_SET_FWCMD_ADD_MCC_DURATION(void * cmd,u32 val)3057 static inline void RTW89_SET_FWCMD_ADD_MCC_DURATION(void *cmd, u32 val)
3058 {
3059 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
3060 }
3061
RTW89_SET_FWCMD_ADD_MCC_COURTESY_EN(void * cmd,u32 val)3062 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_EN(void *cmd, u32 val)
3063 {
3064 le32p_replace_bits((__le32 *)cmd + 3, val, BIT(0));
3065 }
3066
RTW89_SET_FWCMD_ADD_MCC_COURTESY_NUM(void * cmd,u32 val)3067 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_NUM(void *cmd, u32 val)
3068 {
3069 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(15, 8));
3070 }
3071
RTW89_SET_FWCMD_ADD_MCC_COURTESY_TARGET(void * cmd,u32 val)3072 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_TARGET(void *cmd, u32 val)
3073 {
3074 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(23, 16));
3075 }
3076
3077 enum rtw89_fw_mcc_old_group_actions {
3078 RTW89_FW_MCC_OLD_GROUP_ACT_NONE = 0,
3079 RTW89_FW_MCC_OLD_GROUP_ACT_REPLACE = 1,
3080 };
3081
3082 struct rtw89_fw_mcc_start_req {
3083 u32 group: 2;
3084 u32 btc_in_group: 1;
3085 u32 old_group_action: 2;
3086 u32 old_group: 2;
3087 u32 rsvd0: 9;
3088 u32 notify_cnt: 3;
3089 u32 rsvd1: 2;
3090 u32 notify_rxdbg_en: 1;
3091 u32 rsvd2: 2;
3092 u32 macid: 8;
3093 u32 tsf_low;
3094 u32 tsf_high;
3095 };
3096
RTW89_SET_FWCMD_START_MCC_GROUP(void * cmd,u32 val)3097 static inline void RTW89_SET_FWCMD_START_MCC_GROUP(void *cmd, u32 val)
3098 {
3099 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3100 }
3101
RTW89_SET_FWCMD_START_MCC_BTC_IN_GROUP(void * cmd,u32 val)3102 static inline void RTW89_SET_FWCMD_START_MCC_BTC_IN_GROUP(void *cmd, u32 val)
3103 {
3104 le32p_replace_bits((__le32 *)cmd, val, BIT(2));
3105 }
3106
RTW89_SET_FWCMD_START_MCC_OLD_GROUP_ACTION(void * cmd,u32 val)3107 static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP_ACTION(void *cmd, u32 val)
3108 {
3109 le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 3));
3110 }
3111
RTW89_SET_FWCMD_START_MCC_OLD_GROUP(void * cmd,u32 val)3112 static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP(void *cmd, u32 val)
3113 {
3114 le32p_replace_bits((__le32 *)cmd, val, GENMASK(6, 5));
3115 }
3116
RTW89_SET_FWCMD_START_MCC_NOTIFY_CNT(void * cmd,u32 val)3117 static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_CNT(void *cmd, u32 val)
3118 {
3119 le32p_replace_bits((__le32 *)cmd, val, GENMASK(18, 16));
3120 }
3121
RTW89_SET_FWCMD_START_MCC_NOTIFY_RXDBG_EN(void * cmd,u32 val)3122 static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_RXDBG_EN(void *cmd, u32 val)
3123 {
3124 le32p_replace_bits((__le32 *)cmd, val, BIT(21));
3125 }
3126
RTW89_SET_FWCMD_START_MCC_MACID(void * cmd,u32 val)3127 static inline void RTW89_SET_FWCMD_START_MCC_MACID(void *cmd, u32 val)
3128 {
3129 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3130 }
3131
RTW89_SET_FWCMD_START_MCC_TSF_LOW(void * cmd,u32 val)3132 static inline void RTW89_SET_FWCMD_START_MCC_TSF_LOW(void *cmd, u32 val)
3133 {
3134 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0));
3135 }
3136
RTW89_SET_FWCMD_START_MCC_TSF_HIGH(void * cmd,u32 val)3137 static inline void RTW89_SET_FWCMD_START_MCC_TSF_HIGH(void *cmd, u32 val)
3138 {
3139 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
3140 }
3141
RTW89_SET_FWCMD_STOP_MCC_MACID(void * cmd,u32 val)3142 static inline void RTW89_SET_FWCMD_STOP_MCC_MACID(void *cmd, u32 val)
3143 {
3144 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
3145 }
3146
RTW89_SET_FWCMD_STOP_MCC_GROUP(void * cmd,u32 val)3147 static inline void RTW89_SET_FWCMD_STOP_MCC_GROUP(void *cmd, u32 val)
3148 {
3149 le32p_replace_bits((__le32 *)cmd, val, GENMASK(9, 8));
3150 }
3151
RTW89_SET_FWCMD_STOP_MCC_PREV_GROUPS(void * cmd,u32 val)3152 static inline void RTW89_SET_FWCMD_STOP_MCC_PREV_GROUPS(void *cmd, u32 val)
3153 {
3154 le32p_replace_bits((__le32 *)cmd, val, BIT(10));
3155 }
3156
RTW89_SET_FWCMD_DEL_MCC_GROUP_GROUP(void * cmd,u32 val)3157 static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_GROUP(void *cmd, u32 val)
3158 {
3159 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3160 }
3161
RTW89_SET_FWCMD_DEL_MCC_GROUP_PREV_GROUPS(void * cmd,u32 val)3162 static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_PREV_GROUPS(void *cmd, u32 val)
3163 {
3164 le32p_replace_bits((__le32 *)cmd, val, BIT(2));
3165 }
3166
RTW89_SET_FWCMD_RESET_MCC_GROUP_GROUP(void * cmd,u32 val)3167 static inline void RTW89_SET_FWCMD_RESET_MCC_GROUP_GROUP(void *cmd, u32 val)
3168 {
3169 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3170 }
3171
3172 struct rtw89_fw_mcc_tsf_req {
3173 u8 group: 2;
3174 u8 rsvd0: 6;
3175 u8 macid_x;
3176 u8 macid_y;
3177 u8 rsvd1;
3178 };
3179
RTW89_SET_FWCMD_MCC_REQ_TSF_GROUP(void * cmd,u32 val)3180 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_GROUP(void *cmd, u32 val)
3181 {
3182 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3183 }
3184
RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_X(void * cmd,u32 val)3185 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_X(void *cmd, u32 val)
3186 {
3187 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3188 }
3189
RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_Y(void * cmd,u32 val)3190 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_Y(void *cmd, u32 val)
3191 {
3192 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3193 }
3194
RTW89_SET_FWCMD_MCC_MACID_BITMAP_GROUP(void * cmd,u32 val)3195 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_GROUP(void *cmd, u32 val)
3196 {
3197 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3198 }
3199
RTW89_SET_FWCMD_MCC_MACID_BITMAP_MACID(void * cmd,u32 val)3200 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_MACID(void *cmd, u32 val)
3201 {
3202 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3203 }
3204
RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP_LENGTH(void * cmd,u32 val)3205 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP_LENGTH(void *cmd, u32 val)
3206 {
3207 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3208 }
3209
RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP(void * cmd,u8 * bitmap,u8 len)3210 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP(void *cmd,
3211 u8 *bitmap, u8 len)
3212 {
3213 memcpy((__le32 *)cmd + 1, bitmap, len);
3214 }
3215
RTW89_SET_FWCMD_MCC_SYNC_GROUP(void * cmd,u32 val)3216 static inline void RTW89_SET_FWCMD_MCC_SYNC_GROUP(void *cmd, u32 val)
3217 {
3218 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3219 }
3220
RTW89_SET_FWCMD_MCC_SYNC_MACID_SOURCE(void * cmd,u32 val)3221 static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_SOURCE(void *cmd, u32 val)
3222 {
3223 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3224 }
3225
RTW89_SET_FWCMD_MCC_SYNC_MACID_TARGET(void * cmd,u32 val)3226 static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_TARGET(void *cmd, u32 val)
3227 {
3228 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3229 }
3230
RTW89_SET_FWCMD_MCC_SYNC_SYNC_OFFSET(void * cmd,u32 val)3231 static inline void RTW89_SET_FWCMD_MCC_SYNC_SYNC_OFFSET(void *cmd, u32 val)
3232 {
3233 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3234 }
3235
3236 struct rtw89_fw_mcc_duration {
3237 u32 group: 2;
3238 u32 btc_in_group: 1;
3239 u32 rsvd0: 5;
3240 u32 start_macid: 8;
3241 u32 macid_x: 8;
3242 u32 macid_y: 8;
3243 u32 start_tsf_low;
3244 u32 start_tsf_high;
3245 u32 duration_x;
3246 u32 duration_y;
3247 };
3248
RTW89_SET_FWCMD_MCC_SET_DURATION_GROUP(void * cmd,u32 val)3249 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_GROUP(void *cmd, u32 val)
3250 {
3251 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3252 }
3253
3254 static
RTW89_SET_FWCMD_MCC_SET_DURATION_BTC_IN_GROUP(void * cmd,u32 val)3255 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_BTC_IN_GROUP(void *cmd, u32 val)
3256 {
3257 le32p_replace_bits((__le32 *)cmd, val, BIT(2));
3258 }
3259
3260 static
RTW89_SET_FWCMD_MCC_SET_DURATION_START_MACID(void * cmd,u32 val)3261 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_MACID(void *cmd, u32 val)
3262 {
3263 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3264 }
3265
RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_X(void * cmd,u32 val)3266 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_X(void *cmd, u32 val)
3267 {
3268 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3269 }
3270
RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_Y(void * cmd,u32 val)3271 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_Y(void *cmd, u32 val)
3272 {
3273 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3274 }
3275
3276 static
RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_LOW(void * cmd,u32 val)3277 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_LOW(void *cmd, u32 val)
3278 {
3279 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0));
3280 }
3281
3282 static
RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_HIGH(void * cmd,u32 val)3283 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_HIGH(void *cmd, u32 val)
3284 {
3285 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
3286 }
3287
3288 static
RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_X(void * cmd,u32 val)3289 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_X(void *cmd, u32 val)
3290 {
3291 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0));
3292 }
3293
3294 static
RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_Y(void * cmd,u32 val)3295 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_Y(void *cmd, u32 val)
3296 {
3297 le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0));
3298 }
3299
3300 enum rtw89_h2c_mrc_sch_types {
3301 RTW89_H2C_MRC_SCH_BAND0_ONLY = 0,
3302 RTW89_H2C_MRC_SCH_BAND1_ONLY = 1,
3303 RTW89_H2C_MRC_SCH_DUAL_BAND = 2,
3304 };
3305
3306 enum rtw89_h2c_mrc_role_types {
3307 RTW89_H2C_MRC_ROLE_WIFI = 0,
3308 RTW89_H2C_MRC_ROLE_BT = 1,
3309 RTW89_H2C_MRC_ROLE_EMPTY = 2,
3310 };
3311
3312 #define RTW89_MAC_MRC_MAX_ADD_SLOT_NUM 3
3313 #define RTW89_MAC_MRC_MAX_ADD_ROLE_NUM_PER_SLOT 1 /* before MLO */
3314
3315 struct rtw89_fw_mrc_add_slot_arg {
3316 u16 duration; /* unit: TU */
3317 bool courtesy_en;
3318 u8 courtesy_period;
3319 u8 courtesy_target; /* slot idx */
3320
3321 unsigned int role_num;
3322 struct {
3323 enum rtw89_h2c_mrc_role_types role_type;
3324 bool is_master;
3325 bool en_tx_null;
3326 enum rtw89_band band;
3327 enum rtw89_bandwidth bw;
3328 u8 macid;
3329 u8 central_ch;
3330 u8 primary_ch;
3331 u8 null_early; /* unit: TU */
3332
3333 /* if MLD, for macid: [0, chip::support_mld_num)
3334 * otherwise, for macid: [0, 32)
3335 */
3336 u32 macid_main_bitmap;
3337 /* for MLD, bit X maps to macid: X + chip::support_mld_num */
3338 u32 macid_paired_bitmap;
3339 } roles[RTW89_MAC_MRC_MAX_ADD_ROLE_NUM_PER_SLOT];
3340 };
3341
3342 struct rtw89_fw_mrc_add_arg {
3343 u8 sch_idx;
3344 enum rtw89_h2c_mrc_sch_types sch_type;
3345 bool btc_in_sch;
3346
3347 unsigned int slot_num;
3348 struct rtw89_fw_mrc_add_slot_arg slots[RTW89_MAC_MRC_MAX_ADD_SLOT_NUM];
3349 };
3350
3351 struct rtw89_h2c_mrc_add_role {
3352 __le32 w0;
3353 __le32 w1;
3354 __le32 w2;
3355 __le32 macid_main_bitmap;
3356 __le32 macid_paired_bitmap;
3357 } __packed;
3358
3359 #define RTW89_H2C_MRC_ADD_ROLE_W0_MACID GENMASK(15, 0)
3360 #define RTW89_H2C_MRC_ADD_ROLE_W0_ROLE_TYPE GENMASK(23, 16)
3361 #define RTW89_H2C_MRC_ADD_ROLE_W0_IS_MASTER BIT(24)
3362 #define RTW89_H2C_MRC_ADD_ROLE_W0_IS_ALT_ROLE BIT(25)
3363 #define RTW89_H2C_MRC_ADD_ROLE_W0_TX_NULL_EN BIT(26)
3364 #define RTW89_H2C_MRC_ADD_ROLE_W0_ROLE_ALT_EN BIT(27)
3365 #define RTW89_H2C_MRC_ADD_ROLE_W1_CENTRAL_CH_SEG GENMASK(7, 0)
3366 #define RTW89_H2C_MRC_ADD_ROLE_W1_PRI_CH GENMASK(15, 8)
3367 #define RTW89_H2C_MRC_ADD_ROLE_W1_BW GENMASK(19, 16)
3368 #define RTW89_H2C_MRC_ADD_ROLE_W1_CH_BAND_TYPE GENMASK(21, 20)
3369 #define RTW89_H2C_MRC_ADD_ROLE_W1_RFK_BY_PASS BIT(22)
3370 #define RTW89_H2C_MRC_ADD_ROLE_W1_CAN_BTC BIT(23)
3371 #define RTW89_H2C_MRC_ADD_ROLE_W1_NULL_EARLY GENMASK(31, 24)
3372 #define RTW89_H2C_MRC_ADD_ROLE_W2_ALT_PERIOD GENMASK(7, 0)
3373 #define RTW89_H2C_MRC_ADD_ROLE_W2_ALT_ROLE_TYPE GENMASK(15, 8)
3374 #define RTW89_H2C_MRC_ADD_ROLE_W2_ALT_ROLE_MACID GENMASK(23, 16)
3375
3376 struct rtw89_h2c_mrc_add_slot {
3377 __le32 w0;
3378 __le32 w1;
3379 struct rtw89_h2c_mrc_add_role roles[];
3380 } __packed;
3381
3382 #define RTW89_H2C_MRC_ADD_SLOT_W0_DURATION GENMASK(15, 0)
3383 #define RTW89_H2C_MRC_ADD_SLOT_W0_COURTESY_EN BIT(17)
3384 #define RTW89_H2C_MRC_ADD_SLOT_W0_ROLE_NUM GENMASK(31, 24)
3385 #define RTW89_H2C_MRC_ADD_SLOT_W1_COURTESY_PERIOD GENMASK(7, 0)
3386 #define RTW89_H2C_MRC_ADD_SLOT_W1_COURTESY_TARGET GENMASK(15, 8)
3387
3388 struct rtw89_h2c_mrc_add {
3389 __le32 w0;
3390 /* Logically append flexible struct rtw89_h2c_mrc_add_slot, but there
3391 * are other flexible array inside it. We cannot access them correctly
3392 * through this struct. So, in case misusing, we don't really declare
3393 * it here.
3394 */
3395 } __packed;
3396
3397 #define RTW89_H2C_MRC_ADD_W0_SCH_IDX GENMASK(3, 0)
3398 #define RTW89_H2C_MRC_ADD_W0_SCH_TYPE GENMASK(7, 4)
3399 #define RTW89_H2C_MRC_ADD_W0_SLOT_NUM GENMASK(15, 8)
3400 #define RTW89_H2C_MRC_ADD_W0_BTC_IN_SCH BIT(16)
3401
3402 enum rtw89_h2c_mrc_start_actions {
3403 RTW89_H2C_MRC_START_ACTION_START_NEW = 0,
3404 RTW89_H2C_MRC_START_ACTION_REPLACE_OLD = 1,
3405 };
3406
3407 struct rtw89_fw_mrc_start_arg {
3408 u8 sch_idx;
3409 u8 old_sch_idx;
3410 u64 start_tsf;
3411 enum rtw89_h2c_mrc_start_actions action;
3412 };
3413
3414 struct rtw89_h2c_mrc_start {
3415 __le32 w0;
3416 __le32 start_tsf_low;
3417 __le32 start_tsf_high;
3418 } __packed;
3419
3420 #define RTW89_H2C_MRC_START_W0_SCH_IDX GENMASK(3, 0)
3421 #define RTW89_H2C_MRC_START_W0_OLD_SCH_IDX GENMASK(7, 4)
3422 #define RTW89_H2C_MRC_START_W0_ACTION GENMASK(15, 8)
3423
3424 struct rtw89_h2c_mrc_del {
3425 __le32 w0;
3426 } __packed;
3427
3428 #define RTW89_H2C_MRC_DEL_W0_SCH_IDX GENMASK(3, 0)
3429 #define RTW89_H2C_MRC_DEL_W0_DEL_ALL BIT(4)
3430 #define RTW89_H2C_MRC_DEL_W0_STOP_ONLY BIT(5)
3431 #define RTW89_H2C_MRC_DEL_W0_SPECIFIC_ROLE_EN BIT(6)
3432 #define RTW89_H2C_MRC_DEL_W0_STOP_SLOT_IDX GENMASK(15, 8)
3433 #define RTW89_H2C_MRC_DEL_W0_SPECIFIC_ROLE_MACID GENMASK(31, 16)
3434
3435 #define RTW89_MAC_MRC_MAX_REQ_TSF_NUM 2
3436
3437 struct rtw89_fw_mrc_req_tsf_arg {
3438 unsigned int num;
3439 struct {
3440 u8 band;
3441 u8 port;
3442 } infos[RTW89_MAC_MRC_MAX_REQ_TSF_NUM];
3443 };
3444
3445 struct rtw89_h2c_mrc_req_tsf {
3446 u8 req_tsf_num;
3447 u8 infos[] __counted_by(req_tsf_num);
3448 } __packed;
3449
3450 #define RTW89_H2C_MRC_REQ_TSF_INFO_BAND GENMASK(3, 0)
3451 #define RTW89_H2C_MRC_REQ_TSF_INFO_PORT GENMASK(7, 4)
3452
3453 enum rtw89_h2c_mrc_upd_bitmap_actions {
3454 RTW89_H2C_MRC_UPD_BITMAP_ACTION_DEL = 0,
3455 RTW89_H2C_MRC_UPD_BITMAP_ACTION_ADD = 1,
3456 };
3457
3458 struct rtw89_fw_mrc_upd_bitmap_arg {
3459 u8 sch_idx;
3460 u8 macid;
3461 u8 client_macid;
3462 enum rtw89_h2c_mrc_upd_bitmap_actions action;
3463 };
3464
3465 struct rtw89_h2c_mrc_upd_bitmap {
3466 __le32 w0;
3467 __le32 w1;
3468 } __packed;
3469
3470 #define RTW89_H2C_MRC_UPD_BITMAP_W0_SCH_IDX GENMASK(3, 0)
3471 #define RTW89_H2C_MRC_UPD_BITMAP_W0_ACTION BIT(4)
3472 #define RTW89_H2C_MRC_UPD_BITMAP_W0_MACID GENMASK(31, 16)
3473 #define RTW89_H2C_MRC_UPD_BITMAP_W1_CLIENT_MACID GENMASK(15, 0)
3474
3475 struct rtw89_fw_mrc_sync_arg {
3476 u8 offset; /* unit: TU */
3477 struct {
3478 u8 band;
3479 u8 port;
3480 } src, dest;
3481 };
3482
3483 struct rtw89_h2c_mrc_sync {
3484 __le32 w0;
3485 __le32 w1;
3486 } __packed;
3487
3488 #define RTW89_H2C_MRC_SYNC_W0_SYNC_EN BIT(0)
3489 #define RTW89_H2C_MRC_SYNC_W0_SRC_PORT GENMASK(11, 8)
3490 #define RTW89_H2C_MRC_SYNC_W0_SRC_BAND GENMASK(15, 12)
3491 #define RTW89_H2C_MRC_SYNC_W0_DEST_PORT GENMASK(19, 16)
3492 #define RTW89_H2C_MRC_SYNC_W0_DEST_BAND GENMASK(23, 20)
3493 #define RTW89_H2C_MRC_SYNC_W1_OFFSET GENMASK(15, 0)
3494
3495 struct rtw89_fw_mrc_upd_duration_arg {
3496 u8 sch_idx;
3497 u64 start_tsf;
3498
3499 unsigned int slot_num;
3500 struct {
3501 u8 slot_idx;
3502 u16 duration; /* unit: TU */
3503 } slots[RTW89_MAC_MRC_MAX_ADD_SLOT_NUM];
3504 };
3505
3506 struct rtw89_h2c_mrc_upd_duration {
3507 __le32 w0;
3508 __le32 start_tsf_low;
3509 __le32 start_tsf_high;
3510 __le32 slots[];
3511 } __packed;
3512
3513 #define RTW89_H2C_MRC_UPD_DURATION_W0_SCH_IDX GENMASK(3, 0)
3514 #define RTW89_H2C_MRC_UPD_DURATION_W0_SLOT_NUM GENMASK(15, 8)
3515 #define RTW89_H2C_MRC_UPD_DURATION_W0_BTC_IN_SCH BIT(16)
3516 #define RTW89_H2C_MRC_UPD_DURATION_SLOT_SLOT_IDX GENMASK(7, 0)
3517 #define RTW89_H2C_MRC_UPD_DURATION_SLOT_DURATION GENMASK(31, 16)
3518
3519 struct rtw89_h2c_wow_aoac {
3520 __le32 w0;
3521 } __packed;
3522
3523 struct rtw89_h2c_ap_info {
3524 __le32 w0;
3525 } __packed;
3526
3527 #define RTW89_H2C_AP_INFO_W0_PWR_INT_EN BIT(0)
3528
3529 #define RTW89_C2H_HEADER_LEN 8
3530
3531 struct rtw89_c2h_hdr {
3532 __le32 w0;
3533 __le32 w1;
3534 } __packed;
3535
3536 #define RTW89_C2H_HDR_W0_CATEGORY GENMASK(1, 0)
3537 #define RTW89_C2H_HDR_W0_CLASS GENMASK(7, 2)
3538 #define RTW89_C2H_HDR_W0_FUNC GENMASK(15, 8)
3539 #define RTW89_C2H_HDR_W1_LEN GENMASK(13, 0)
3540
3541 struct rtw89_fw_c2h_attr {
3542 u8 category;
3543 u8 class;
3544 u8 func;
3545 u16 len;
3546 };
3547
RTW89_SKB_C2H_CB(struct sk_buff * skb)3548 static inline struct rtw89_fw_c2h_attr *RTW89_SKB_C2H_CB(struct sk_buff *skb)
3549 {
3550 static_assert(sizeof(skb->cb) >= sizeof(struct rtw89_fw_c2h_attr));
3551
3552 return (struct rtw89_fw_c2h_attr *)skb->cb;
3553 }
3554
3555 struct rtw89_c2h_done_ack {
3556 __le32 w0;
3557 __le32 w1;
3558 __le32 w2;
3559 } __packed;
3560
3561 #define RTW89_C2H_DONE_ACK_W2_CAT GENMASK(1, 0)
3562 #define RTW89_C2H_DONE_ACK_W2_CLASS GENMASK(7, 2)
3563 #define RTW89_C2H_DONE_ACK_W2_FUNC GENMASK(15, 8)
3564 #define RTW89_C2H_DONE_ACK_W2_H2C_RETURN GENMASK(23, 16)
3565 #define RTW89_C2H_DONE_ACK_W2_H2C_SEQ GENMASK(31, 24)
3566
3567 #define RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h) \
3568 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
3569 #define RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h) \
3570 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2))
3571 #define RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h) \
3572 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3573 #define RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h) \
3574 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16))
3575
3576 struct rtw89_fw_c2h_log_fmt {
3577 __le16 signature;
3578 u8 feature;
3579 u8 syntax;
3580 __le32 fmt_id;
3581 u8 file_num;
3582 __le16 line_num;
3583 u8 argc;
3584 union {
3585 DECLARE_FLEX_ARRAY(u8, raw);
3586 DECLARE_FLEX_ARRAY(__le32, argv);
3587 } __packed u;
3588 } __packed;
3589
3590 #define RTW89_C2H_FW_FORMATTED_LOG_MIN_LEN 11
3591 #define RTW89_C2H_FW_LOG_FEATURE_PARA_INT BIT(2)
3592 #define RTW89_C2H_FW_LOG_MAX_PARA_NUM 16
3593 #define RTW89_C2H_FW_LOG_SIGNATURE 0xA5A5
3594 #define RTW89_C2H_FW_LOG_STR_BUF_SIZE 512
3595
3596 struct rtw89_c2h_mac_bcnfltr_rpt {
3597 __le32 w0;
3598 __le32 w1;
3599 __le32 w2;
3600 } __packed;
3601
3602 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID GENMASK(7, 0)
3603 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE GENMASK(9, 8)
3604 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT GENMASK(11, 10)
3605 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA GENMASK(23, 16)
3606
3607 struct rtw89_c2h_ra_rpt {
3608 struct rtw89_c2h_hdr hdr;
3609 __le32 w2;
3610 __le32 w3;
3611 } __packed;
3612
3613 #define RTW89_C2H_RA_RPT_W2_MACID GENMASK(15, 0)
3614 #define RTW89_C2H_RA_RPT_W2_RETRY_RATIO GENMASK(23, 16)
3615 #define RTW89_C2H_RA_RPT_W2_MCSNSS_B7 BIT(31)
3616 #define RTW89_C2H_RA_RPT_W3_MCSNSS GENMASK(6, 0)
3617 #define RTW89_C2H_RA_RPT_W3_MD_SEL GENMASK(9, 8)
3618 #define RTW89_C2H_RA_RPT_W3_GILTF GENMASK(12, 10)
3619 #define RTW89_C2H_RA_RPT_W3_BW GENMASK(14, 13)
3620 #define RTW89_C2H_RA_RPT_W3_MD_SEL_B2 BIT(15)
3621 #define RTW89_C2H_RA_RPT_W3_BW_B2 BIT(16)
3622
3623 /* For WiFi 6 chips:
3624 * VHT, HE, HT-old: [6:4]: NSS, [3:0]: MCS
3625 * HT-new: [6:5]: NA, [4:0]: MCS
3626 * For WiFi 7 chips (V1):
3627 * HT, VHT, HE, EHT: [7:5]: NSS, [4:0]: MCS
3628 */
3629 #define RTW89_RA_RATE_MASK_NSS GENMASK(6, 4)
3630 #define RTW89_RA_RATE_MASK_MCS GENMASK(3, 0)
3631 #define RTW89_RA_RATE_MASK_NSS_V1 GENMASK(7, 5)
3632 #define RTW89_RA_RATE_MASK_MCS_V1 GENMASK(4, 0)
3633 #define RTW89_RA_RATE_MASK_HT_MCS GENMASK(4, 0)
3634 #define RTW89_MK_HT_RATE(nss, mcs) (FIELD_PREP(GENMASK(4, 3), nss) | \
3635 FIELD_PREP(GENMASK(2, 0), mcs))
3636
3637 #define RTW89_GET_MAC_C2H_PKTOFLD_ID(c2h) \
3638 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0))
3639 #define RTW89_GET_MAC_C2H_PKTOFLD_OP(c2h) \
3640 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(10, 8))
3641 #define RTW89_GET_MAC_C2H_PKTOFLD_LEN(c2h) \
3642 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 16))
3643
3644 struct rtw89_c2h_scanofld {
3645 __le32 w0;
3646 __le32 w1;
3647 __le32 w2;
3648 __le32 w3;
3649 __le32 w4;
3650 __le32 w5;
3651 __le32 w6;
3652 __le32 w7;
3653 __le32 w8;
3654 } __packed;
3655
3656 #define RTW89_C2H_SCANOFLD_W2_PRI_CH GENMASK(7, 0)
3657 #define RTW89_C2H_SCANOFLD_W2_RSN GENMASK(19, 16)
3658 #define RTW89_C2H_SCANOFLD_W2_STATUS GENMASK(23, 20)
3659 #define RTW89_C2H_SCANOFLD_W2_PERIOD GENMASK(31, 24)
3660 #define RTW89_C2H_SCANOFLD_W5_TX_FAIL GENMASK(3, 0)
3661 #define RTW89_C2H_SCANOFLD_W5_AIR_DENSITY GENMASK(7, 4)
3662 #define RTW89_C2H_SCANOFLD_W5_BAND GENMASK(25, 24)
3663 #define RTW89_C2H_SCANOFLD_W5_MAC_IDX BIT(26)
3664 #define RTW89_C2H_SCANOFLD_W6_SW_DEF GENMASK(7, 0)
3665 #define RTW89_C2H_SCANOFLD_W6_EXPECT_PERIOD GENMASK(15, 8)
3666 #define RTW89_C2H_SCANOFLD_W6_FW_DEF GENMASK(23, 16)
3667 #define RTW89_C2H_SCANOFLD_W7_REPORT_TSF GENMASK(31, 0)
3668 #define RTW89_C2H_SCANOFLD_W8_PERIOD_V1 GENMASK(15, 0)
3669 #define RTW89_C2H_SCANOFLD_W8_EXPECT_PERIOD_V1 GENMASK(31, 16)
3670
3671 #define RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h) \
3672 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
3673 #define RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h) \
3674 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3675
3676 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h) \
3677 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
3678 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h) \
3679 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2))
3680 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h) \
3681 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3682
3683 struct rtw89_mac_mcc_tsf_rpt {
3684 u32 macid_x;
3685 u32 macid_y;
3686 u32 tsf_x_low;
3687 u32 tsf_x_high;
3688 u32 tsf_y_low;
3689 u32 tsf_y_high;
3690 };
3691
3692 static_assert(sizeof(struct rtw89_mac_mcc_tsf_rpt) <= RTW89_COMPLETION_BUF_SIZE);
3693
3694 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h) \
3695 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0))
3696 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h) \
3697 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3698 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h) \
3699 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(17, 16))
3700 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h) \
3701 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0))
3702 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h) \
3703 le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0))
3704 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h) \
3705 le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(31, 0))
3706 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h) \
3707 le32_get_bits(*((const __le32 *)(c2h) + 6), GENMASK(31, 0))
3708
3709 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h) \
3710 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(5, 0))
3711 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h) \
3712 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 6))
3713 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h) \
3714 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3715 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h) \
3716 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0))
3717 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h) \
3718 le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0))
3719
3720 struct rtw89_mac_mrc_tsf_rpt {
3721 unsigned int num;
3722 u64 tsfs[RTW89_MAC_MRC_MAX_REQ_TSF_NUM];
3723 };
3724
3725 static_assert(sizeof(struct rtw89_mac_mrc_tsf_rpt) <= RTW89_COMPLETION_BUF_SIZE);
3726
3727 struct rtw89_c2h_mrc_tsf_rpt_info {
3728 __le32 tsf_low;
3729 __le32 tsf_high;
3730 } __packed;
3731
3732 struct rtw89_c2h_mrc_tsf_rpt {
3733 struct rtw89_c2h_hdr hdr;
3734 __le32 w2;
3735 struct rtw89_c2h_mrc_tsf_rpt_info infos[];
3736 } __packed;
3737
3738 #define RTW89_C2H_MRC_TSF_RPT_W2_REQ_TSF_NUM GENMASK(7, 0)
3739
3740 struct rtw89_c2h_mrc_status_rpt {
3741 struct rtw89_c2h_hdr hdr;
3742 __le32 w2;
3743 __le32 tsf_low;
3744 __le32 tsf_high;
3745 } __packed;
3746
3747 #define RTW89_C2H_MRC_STATUS_RPT_W2_STATUS GENMASK(5, 0)
3748 #define RTW89_C2H_MRC_STATUS_RPT_W2_SCH_IDX GENMASK(7, 6)
3749
3750 struct rtw89_c2h_pkt_ofld_rsp {
3751 __le32 w0;
3752 __le32 w1;
3753 __le32 w2;
3754 } __packed;
3755
3756 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_ID GENMASK(7, 0)
3757 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_OP GENMASK(10, 8)
3758 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_LEN GENMASK(31, 16)
3759
3760 struct rtw89_c2h_tx_duty_rpt {
3761 struct rtw89_c2h_hdr c2h_hdr;
3762 __le32 w2;
3763 } __packed;
3764
3765 #define RTW89_C2H_TX_DUTY_RPT_W2_TIMER_ERR GENMASK(2, 0)
3766
3767 struct rtw89_c2h_wow_aoac_report {
3768 struct rtw89_c2h_hdr c2h_hdr;
3769 u8 rpt_ver;
3770 u8 sec_type;
3771 u8 key_idx;
3772 u8 pattern_idx;
3773 u8 rekey_ok;
3774 u8 rsvd1[3];
3775 u8 ptk_tx_iv[8];
3776 u8 eapol_key_replay_count[8];
3777 u8 gtk[32];
3778 u8 ptk_rx_iv[8];
3779 u8 gtk_rx_iv[4][8];
3780 __le64 igtk_key_id;
3781 __le64 igtk_ipn;
3782 u8 igtk[32];
3783 u8 csa_pri_ch;
3784 u8 csa_bw_ch_offset;
3785 u8 csa_ch_band_chsw_failed;
3786 u8 csa_rsvd1;
3787 } __packed;
3788
3789 #define RTW89_C2H_WOW_AOAC_RPT_REKEY_IDX BIT(0)
3790
3791 struct rtw89_c2h_pwr_int_notify {
3792 struct rtw89_c2h_hdr hdr;
3793 __le32 w2;
3794 } __packed;
3795
3796 #define RTW89_C2H_PWR_INT_NOTIFY_W2_MACID GENMASK(15, 0)
3797 #define RTW89_C2H_PWR_INT_NOTIFY_W2_PWR_STATUS BIT(16)
3798
3799 struct rtw89_h2c_tx_duty {
3800 __le32 w0;
3801 __le32 w1;
3802 } __packed;
3803
3804 #define RTW89_H2C_TX_DUTY_W0_PAUSE_INTVL_MASK GENMASK(15, 0)
3805 #define RTW89_H2C_TX_DUTY_W0_TX_INTVL_MASK GENMASK(31, 16)
3806 #define RTW89_H2C_TX_DUTY_W1_STOP BIT(0)
3807
3808 struct rtw89_h2c_bcnfltr {
3809 __le32 w0;
3810 } __packed;
3811
3812 #define RTW89_H2C_BCNFLTR_W0_MON_RSSI BIT(0)
3813 #define RTW89_H2C_BCNFLTR_W0_MON_BCN BIT(1)
3814 #define RTW89_H2C_BCNFLTR_W0_MON_EN BIT(2)
3815 #define RTW89_H2C_BCNFLTR_W0_MODE GENMASK(4, 3)
3816 #define RTW89_H2C_BCNFLTR_W0_BCN_LOSS_CNT GENMASK(11, 8)
3817 #define RTW89_H2C_BCNFLTR_W0_RSSI_HYST GENMASK(15, 12)
3818 #define RTW89_H2C_BCNFLTR_W0_RSSI_THRESHOLD GENMASK(23, 16)
3819 #define RTW89_H2C_BCNFLTR_W0_MAC_ID GENMASK(31, 24)
3820
3821 struct rtw89_h2c_ofld_rssi {
3822 __le32 w0;
3823 __le32 w1;
3824 } __packed;
3825
3826 #define RTW89_H2C_OFLD_RSSI_W0_MACID GENMASK(7, 0)
3827 #define RTW89_H2C_OFLD_RSSI_W0_NUM GENMASK(15, 8)
3828 #define RTW89_H2C_OFLD_RSSI_W1_VAL GENMASK(7, 0)
3829
3830 struct rtw89_h2c_ofld {
3831 __le32 w0;
3832 } __packed;
3833
3834 #define RTW89_H2C_OFLD_W0_MAC_ID GENMASK(7, 0)
3835 #define RTW89_H2C_OFLD_W0_TX_TP GENMASK(17, 8)
3836 #define RTW89_H2C_OFLD_W0_RX_TP GENMASK(27, 18)
3837
3838 #define RTW89_MFW_SIG 0xFF
3839
3840 struct rtw89_mfw_info {
3841 u8 cv;
3842 u8 type; /* enum rtw89_fw_type */
3843 u8 mp;
3844 u8 rsvd;
3845 __le32 shift;
3846 __le32 size;
3847 u8 rsvd2[4];
3848 } __packed;
3849
3850 struct rtw89_mfw_hdr {
3851 u8 sig; /* RTW89_MFW_SIG */
3852 u8 fw_nr;
3853 u8 rsvd0[2];
3854 struct {
3855 u8 major;
3856 u8 minor;
3857 u8 sub;
3858 u8 idx;
3859 } ver;
3860 u8 rsvd1[8];
3861 struct rtw89_mfw_info info[];
3862 } __packed;
3863
3864 struct rtw89_fw_logsuit_hdr {
3865 __le32 rsvd;
3866 __le32 count;
3867 __le32 ids[];
3868 } __packed;
3869
3870 #define RTW89_FW_ELEMENT_ALIGN 16
3871
3872 enum rtw89_fw_element_id {
3873 RTW89_FW_ELEMENT_ID_BBMCU0 = 0,
3874 RTW89_FW_ELEMENT_ID_BBMCU1 = 1,
3875 RTW89_FW_ELEMENT_ID_BB_REG = 2,
3876 RTW89_FW_ELEMENT_ID_BB_GAIN = 3,
3877 RTW89_FW_ELEMENT_ID_RADIO_A = 4,
3878 RTW89_FW_ELEMENT_ID_RADIO_B = 5,
3879 RTW89_FW_ELEMENT_ID_RADIO_C = 6,
3880 RTW89_FW_ELEMENT_ID_RADIO_D = 7,
3881 RTW89_FW_ELEMENT_ID_RF_NCTL = 8,
3882 RTW89_FW_ELEMENT_ID_TXPWR_BYRATE = 9,
3883 RTW89_FW_ELEMENT_ID_TXPWR_LMT_2GHZ = 10,
3884 RTW89_FW_ELEMENT_ID_TXPWR_LMT_5GHZ = 11,
3885 RTW89_FW_ELEMENT_ID_TXPWR_LMT_6GHZ = 12,
3886 RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_2GHZ = 13,
3887 RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_5GHZ = 14,
3888 RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_6GHZ = 15,
3889 RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT = 16,
3890 RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT_RU = 17,
3891 RTW89_FW_ELEMENT_ID_TXPWR_TRK = 18,
3892 RTW89_FW_ELEMENT_ID_RFKLOG_FMT = 19,
3893 RTW89_FW_ELEMENT_ID_REGD = 20,
3894
3895 RTW89_FW_ELEMENT_ID_NUM,
3896 };
3897
3898 #define BITS_OF_RTW89_TXPWR_FW_ELEMENTS_NO_6GHZ \
3899 (BIT(RTW89_FW_ELEMENT_ID_TXPWR_BYRATE) | \
3900 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_2GHZ) | \
3901 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_5GHZ) | \
3902 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_2GHZ) | \
3903 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_5GHZ) | \
3904 BIT(RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT) | \
3905 BIT(RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT_RU))
3906
3907 #define BITS_OF_RTW89_TXPWR_FW_ELEMENTS \
3908 (BITS_OF_RTW89_TXPWR_FW_ELEMENTS_NO_6GHZ | \
3909 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_6GHZ) | \
3910 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_6GHZ))
3911
3912 #define RTW89_AX_GEN_DEF_NEEDED_FW_ELEMENTS_NO_6GHZ \
3913 (BIT(RTW89_FW_ELEMENT_ID_BB_REG) | \
3914 BIT(RTW89_FW_ELEMENT_ID_RADIO_A) | \
3915 BIT(RTW89_FW_ELEMENT_ID_RADIO_B) | \
3916 BIT(RTW89_FW_ELEMENT_ID_RF_NCTL) | \
3917 BIT(RTW89_FW_ELEMENT_ID_TXPWR_TRK) | \
3918 BITS_OF_RTW89_TXPWR_FW_ELEMENTS_NO_6GHZ)
3919
3920 #define RTW89_BE_GEN_DEF_NEEDED_FW_ELEMENTS (BIT(RTW89_FW_ELEMENT_ID_BBMCU0) | \
3921 BIT(RTW89_FW_ELEMENT_ID_BB_REG) | \
3922 BIT(RTW89_FW_ELEMENT_ID_RADIO_A) | \
3923 BIT(RTW89_FW_ELEMENT_ID_RADIO_B) | \
3924 BIT(RTW89_FW_ELEMENT_ID_RF_NCTL) | \
3925 BIT(RTW89_FW_ELEMENT_ID_TXPWR_TRK) | \
3926 BITS_OF_RTW89_TXPWR_FW_ELEMENTS)
3927
3928 struct __rtw89_fw_txpwr_element {
3929 u8 rsvd0;
3930 u8 rsvd1;
3931 u8 rfe_type;
3932 u8 ent_sz;
3933 __le32 num_ents;
3934 u8 content[];
3935 } __packed;
3936
3937 struct __rtw89_fw_regd_element {
3938 u8 rsvd0;
3939 u8 rsvd1;
3940 u8 rsvd2;
3941 u8 ent_sz;
3942 __le32 num_ents;
3943 u8 content[];
3944 } __packed;
3945
3946 enum rtw89_fw_txpwr_trk_type {
3947 __RTW89_FW_TXPWR_TRK_TYPE_6GHZ_START = 0,
3948 RTW89_FW_TXPWR_TRK_TYPE_6GB_N = 0,
3949 RTW89_FW_TXPWR_TRK_TYPE_6GB_P = 1,
3950 RTW89_FW_TXPWR_TRK_TYPE_6GA_N = 2,
3951 RTW89_FW_TXPWR_TRK_TYPE_6GA_P = 3,
3952 __RTW89_FW_TXPWR_TRK_TYPE_6GHZ_MAX = 3,
3953
3954 __RTW89_FW_TXPWR_TRK_TYPE_5GHZ_START = 4,
3955 RTW89_FW_TXPWR_TRK_TYPE_5GB_N = 4,
3956 RTW89_FW_TXPWR_TRK_TYPE_5GB_P = 5,
3957 RTW89_FW_TXPWR_TRK_TYPE_5GA_N = 6,
3958 RTW89_FW_TXPWR_TRK_TYPE_5GA_P = 7,
3959 __RTW89_FW_TXPWR_TRK_TYPE_5GHZ_MAX = 7,
3960
3961 __RTW89_FW_TXPWR_TRK_TYPE_2GHZ_START = 8,
3962 RTW89_FW_TXPWR_TRK_TYPE_2GB_N = 8,
3963 RTW89_FW_TXPWR_TRK_TYPE_2GB_P = 9,
3964 RTW89_FW_TXPWR_TRK_TYPE_2GA_N = 10,
3965 RTW89_FW_TXPWR_TRK_TYPE_2GA_P = 11,
3966 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_N = 12,
3967 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_P = 13,
3968 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_N = 14,
3969 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_P = 15,
3970 __RTW89_FW_TXPWR_TRK_TYPE_2GHZ_MAX = 15,
3971
3972 RTW89_FW_TXPWR_TRK_TYPE_NR,
3973 };
3974
3975 struct rtw89_fw_txpwr_track_cfg {
3976 const s8 (*delta[RTW89_FW_TXPWR_TRK_TYPE_NR])[DELTA_SWINGIDX_SIZE];
3977 };
3978
3979 #define RTW89_DEFAULT_NEEDED_FW_TXPWR_TRK_6GHZ \
3980 (BIT(RTW89_FW_TXPWR_TRK_TYPE_6GB_N) | \
3981 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GB_P) | \
3982 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GA_N) | \
3983 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GA_P))
3984 #define RTW89_DEFAULT_NEEDED_FW_TXPWR_TRK_5GHZ \
3985 (BIT(RTW89_FW_TXPWR_TRK_TYPE_5GB_N) | \
3986 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GB_P) | \
3987 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GA_N) | \
3988 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GA_P))
3989 #define RTW89_DEFAULT_NEEDED_FW_TXPWR_TRK_2GHZ \
3990 (BIT(RTW89_FW_TXPWR_TRK_TYPE_2GB_N) | \
3991 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GB_P) | \
3992 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GA_N) | \
3993 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GA_P) | \
3994 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_N) | \
3995 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_P) | \
3996 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_N) | \
3997 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_P))
3998
3999 struct rtw89_fw_element_hdr {
4000 __le32 id; /* enum rtw89_fw_element_id */
4001 __le32 size; /* exclude header size */
4002 u8 ver[4];
4003 __le32 rsvd0;
4004 __le32 rsvd1;
4005 __le32 rsvd2;
4006 union {
4007 struct {
4008 u8 priv[8];
4009 u8 contents[];
4010 } __packed common;
4011 struct {
4012 u8 idx;
4013 u8 rsvd[7];
4014 struct {
4015 __le32 addr;
4016 __le32 data;
4017 } __packed regs[];
4018 } __packed reg2;
4019 struct {
4020 u8 cv;
4021 u8 priv[7];
4022 u8 contents[];
4023 } __packed bbmcu;
4024 struct {
4025 __le32 bitmap; /* bitmap of enum rtw89_fw_txpwr_trk_type */
4026 __le32 rsvd;
4027 s8 contents[][DELTA_SWINGIDX_SIZE];
4028 } __packed txpwr_trk;
4029 struct {
4030 u8 nr;
4031 u8 rsvd[3];
4032 u8 rfk_id; /* enum rtw89_phy_c2h_rfk_log_func */
4033 u8 rsvd1[3];
4034 __le16 offset[];
4035 } __packed rfk_log_fmt;
4036 struct __rtw89_fw_txpwr_element txpwr;
4037 struct __rtw89_fw_regd_element regd;
4038 } __packed u;
4039 } __packed;
4040
4041 struct fwcmd_hdr {
4042 __le32 hdr0;
4043 __le32 hdr1;
4044 };
4045
4046 union rtw89_compat_fw_hdr {
4047 struct rtw89_mfw_hdr mfw_hdr;
4048 struct rtw89_fw_hdr fw_hdr;
4049 };
4050
rtw89_compat_fw_hdr_ver_code(const void * fw_buf)4051 static inline u32 rtw89_compat_fw_hdr_ver_code(const void *fw_buf)
4052 {
4053 const union rtw89_compat_fw_hdr *compat = (typeof(compat))fw_buf;
4054
4055 if (compat->mfw_hdr.sig == RTW89_MFW_SIG)
4056 return RTW89_MFW_HDR_VER_CODE(&compat->mfw_hdr);
4057 else
4058 return RTW89_FW_HDR_VER_CODE(&compat->fw_hdr);
4059 }
4060
rtw89_fw_get_filename(char * buf,size_t size,const char * fw_basename,int fw_format)4061 static inline void rtw89_fw_get_filename(char *buf, size_t size,
4062 const char *fw_basename, int fw_format)
4063 {
4064 if (fw_format <= 0)
4065 snprintf(buf, size, "%s.bin", fw_basename);
4066 else
4067 snprintf(buf, size, "%s-%d.bin", fw_basename, fw_format);
4068 }
4069
4070 #define RTW89_H2C_RF_PAGE_SIZE 500
4071 #define RTW89_H2C_RF_PAGE_NUM 3
4072 struct rtw89_fw_h2c_rf_reg_info {
4073 enum rtw89_rf_path rf_path;
4074 __le32 rtw89_phy_config_rf_h2c[RTW89_H2C_RF_PAGE_NUM][RTW89_H2C_RF_PAGE_SIZE];
4075 u16 curr_idx;
4076 };
4077
4078 #define H2C_SEC_CAM_LEN 24
4079
4080 #define H2C_HEADER_LEN 8
4081 #define H2C_HDR_CAT GENMASK(1, 0)
4082 #define H2C_HDR_CLASS GENMASK(7, 2)
4083 #define H2C_HDR_FUNC GENMASK(15, 8)
4084 #define H2C_HDR_DEL_TYPE GENMASK(19, 16)
4085 #define H2C_HDR_H2C_SEQ GENMASK(31, 24)
4086 #define H2C_HDR_TOTAL_LEN GENMASK(13, 0)
4087 #define H2C_HDR_REC_ACK BIT(14)
4088 #define H2C_HDR_DONE_ACK BIT(15)
4089
4090 #define FWCMD_TYPE_H2C 0
4091
4092 #define H2C_CAT_TEST 0x0
4093
4094 /* CLASS 5 - FW STATUS TEST */
4095 #define H2C_CL_FW_STATUS_TEST 0x5
4096 #define H2C_FUNC_CPU_EXCEPTION 0x1
4097
4098 #define H2C_CAT_MAC 0x1
4099
4100 /* CLASS 0 - FW INFO */
4101 #define H2C_CL_FW_INFO 0x0
4102 #define H2C_FUNC_LOG_CFG 0x0
4103 #define H2C_FUNC_MAC_GENERAL_PKT 0x1
4104
4105 /* CLASS 1 - WOW */
4106 #define H2C_CL_MAC_WOW 0x1
4107 enum rtw89_wow_h2c_func {
4108 H2C_FUNC_KEEP_ALIVE = 0x0,
4109 H2C_FUNC_DISCONNECT_DETECT = 0x1,
4110 H2C_FUNC_WOW_GLOBAL = 0x2,
4111 H2C_FUNC_GTK_OFLD = 0x3,
4112 H2C_FUNC_ARP_OFLD = 0x4,
4113 H2C_FUNC_NLO = 0x7,
4114 H2C_FUNC_WAKEUP_CTRL = 0x8,
4115 H2C_FUNC_WOW_CAM_UPD = 0xC,
4116 H2C_FUNC_AOAC_REPORT_REQ = 0xD,
4117
4118 NUM_OF_RTW89_WOW_H2C_FUNC,
4119 };
4120
4121 #define RTW89_WOW_WAIT_COND(tag, func) \
4122 ((tag) * NUM_OF_RTW89_WOW_H2C_FUNC + (func))
4123
4124 #define RTW89_WOW_WAIT_COND_AOAC \
4125 RTW89_WOW_WAIT_COND(0 /* don't care */, H2C_FUNC_AOAC_REPORT_REQ)
4126
4127 /* CLASS 2 - PS */
4128 #define H2C_CL_MAC_PS 0x2
4129 enum rtw89_ps_h2c_func {
4130 H2C_FUNC_MAC_LPS_PARM = 0x0,
4131 H2C_FUNC_P2P_ACT = 0x1,
4132 H2C_FUNC_IPS_CFG = 0x3,
4133
4134 NUM_OF_RTW89_PS_H2C_FUNC,
4135 };
4136
4137 #define RTW89_PS_WAIT_COND(tag, func) \
4138 ((tag) * NUM_OF_RTW89_PS_H2C_FUNC + (func))
4139
4140 #define RTW89_PS_WAIT_COND_IPS_CFG \
4141 RTW89_PS_WAIT_COND(0 /* don't care */, H2C_FUNC_IPS_CFG)
4142
4143 /* CLASS 3 - FW download */
4144 #define H2C_CL_MAC_FWDL 0x3
4145 #define H2C_FUNC_MAC_FWHDR_DL 0x0
4146
4147 /* CLASS 5 - Frame Exchange */
4148 #define H2C_CL_MAC_FR_EXCHG 0x5
4149 #define H2C_FUNC_MAC_CCTLINFO_UD 0x2
4150 #define H2C_FUNC_MAC_BCN_UPD 0x5
4151 #define H2C_FUNC_MAC_DCTLINFO_UD_V1 0x9
4152 #define H2C_FUNC_MAC_CCTLINFO_UD_V1 0xa
4153 #define H2C_FUNC_MAC_DCTLINFO_UD_V2 0xc
4154 #define H2C_FUNC_MAC_BCN_UPD_BE 0xd
4155 #define H2C_FUNC_MAC_CCTLINFO_UD_G7 0x11
4156
4157 /* CLASS 6 - Address CAM */
4158 #define H2C_CL_MAC_ADDR_CAM_UPDATE 0x6
4159 #define H2C_FUNC_MAC_ADDR_CAM_UPD 0x0
4160
4161 /* CLASS 8 - Media Status Report */
4162 #define H2C_CL_MAC_MEDIA_RPT 0x8
4163 #define H2C_FUNC_MAC_JOININFO 0x0
4164 #define H2C_FUNC_MAC_FWROLE_MAINTAIN 0x4
4165 #define H2C_FUNC_NOTIFY_DBCC 0x5
4166
4167 /* CLASS 9 - FW offload */
4168 #define H2C_CL_MAC_FW_OFLD 0x9
4169 enum rtw89_fw_ofld_h2c_func {
4170 H2C_FUNC_PACKET_OFLD = 0x1,
4171 H2C_FUNC_MAC_MACID_PAUSE = 0x8,
4172 H2C_FUNC_USR_EDCA = 0xF,
4173 H2C_FUNC_TSF32_TOGL = 0x10,
4174 H2C_FUNC_OFLD_CFG = 0x14,
4175 H2C_FUNC_ADD_SCANOFLD_CH = 0x16,
4176 H2C_FUNC_SCANOFLD = 0x17,
4177 H2C_FUNC_TX_DUTY = 0x18,
4178 H2C_FUNC_PKT_DROP = 0x1b,
4179 H2C_FUNC_CFG_BCNFLTR = 0x1e,
4180 H2C_FUNC_OFLD_RSSI = 0x1f,
4181 H2C_FUNC_OFLD_TP = 0x20,
4182 H2C_FUNC_MAC_MACID_PAUSE_SLEEP = 0x28,
4183 H2C_FUNC_SCANOFLD_BE = 0x2c,
4184
4185 NUM_OF_RTW89_FW_OFLD_H2C_FUNC,
4186 };
4187
4188 #define RTW89_FW_OFLD_WAIT_COND(tag, func) \
4189 ((tag) * NUM_OF_RTW89_FW_OFLD_H2C_FUNC + (func))
4190
4191 #define RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(pkt_id, pkt_op) \
4192 RTW89_FW_OFLD_WAIT_COND(RTW89_PKT_OFLD_WAIT_TAG(pkt_id, pkt_op), \
4193 H2C_FUNC_PACKET_OFLD)
4194
4195 #define RTW89_SCANOFLD_WAIT_COND_ADD_CH RTW89_FW_OFLD_WAIT_COND(0, H2C_FUNC_ADD_SCANOFLD_CH)
4196
4197 #define RTW89_SCANOFLD_WAIT_COND_START RTW89_FW_OFLD_WAIT_COND(0, H2C_FUNC_SCANOFLD)
4198 #define RTW89_SCANOFLD_WAIT_COND_STOP RTW89_FW_OFLD_WAIT_COND(1, H2C_FUNC_SCANOFLD)
4199 #define RTW89_SCANOFLD_BE_WAIT_COND_START RTW89_FW_OFLD_WAIT_COND(0, H2C_FUNC_SCANOFLD_BE)
4200 #define RTW89_SCANOFLD_BE_WAIT_COND_STOP RTW89_FW_OFLD_WAIT_COND(1, H2C_FUNC_SCANOFLD_BE)
4201
4202
4203 /* CLASS 10 - Security CAM */
4204 #define H2C_CL_MAC_SEC_CAM 0xa
4205 #define H2C_FUNC_MAC_SEC_UPD 0x1
4206
4207 /* CLASS 12 - BA CAM */
4208 #define H2C_CL_BA_CAM 0xc
4209 #define H2C_FUNC_MAC_BA_CAM 0x0
4210 #define H2C_FUNC_MAC_BA_CAM_V1 0x1
4211 #define H2C_FUNC_MAC_BA_CAM_INIT 0x2
4212
4213 /* CLASS 14 - MCC */
4214 #define H2C_CL_MCC 0xe
4215 enum rtw89_mcc_h2c_func {
4216 H2C_FUNC_ADD_MCC = 0x0,
4217 H2C_FUNC_START_MCC = 0x1,
4218 H2C_FUNC_STOP_MCC = 0x2,
4219 H2C_FUNC_DEL_MCC_GROUP = 0x3,
4220 H2C_FUNC_RESET_MCC_GROUP = 0x4,
4221 H2C_FUNC_MCC_REQ_TSF = 0x5,
4222 H2C_FUNC_MCC_MACID_BITMAP = 0x6,
4223 H2C_FUNC_MCC_SYNC = 0x7,
4224 H2C_FUNC_MCC_SET_DURATION = 0x8,
4225
4226 NUM_OF_RTW89_MCC_H2C_FUNC,
4227 };
4228
4229 #define RTW89_MCC_WAIT_COND(group, func) \
4230 ((group) * NUM_OF_RTW89_MCC_H2C_FUNC + (func))
4231
4232 /* CLASS 24 - MRC */
4233 #define H2C_CL_MRC 0x18
4234 enum rtw89_mrc_h2c_func {
4235 H2C_FUNC_MRC_REQ_TSF = 0x0,
4236 H2C_FUNC_ADD_MRC = 0x1,
4237 H2C_FUNC_START_MRC = 0x2,
4238 H2C_FUNC_DEL_MRC = 0x3,
4239 H2C_FUNC_MRC_SYNC = 0x4,
4240 H2C_FUNC_MRC_UPD_DURATION = 0x5,
4241 H2C_FUNC_MRC_UPD_BITMAP = 0x6,
4242
4243 NUM_OF_RTW89_MRC_H2C_FUNC,
4244 };
4245
4246 /* can consider MRC's sch_idx as MCC's group */
4247 #define RTW89_MRC_WAIT_COND(sch_idx, func) \
4248 ((sch_idx) * NUM_OF_RTW89_MRC_H2C_FUNC + (func))
4249
4250 #define RTW89_MRC_WAIT_COND_REQ_TSF \
4251 RTW89_MRC_WAIT_COND(0 /* don't care */, H2C_FUNC_MRC_REQ_TSF)
4252
4253 /* CLASS 36 - AP */
4254 #define H2C_CL_AP 0x24
4255 #define H2C_FUNC_AP_INFO 0x0
4256
4257 #define H2C_CAT_OUTSRC 0x2
4258
4259 #define H2C_CL_OUTSRC_RA 0x1
4260 #define H2C_FUNC_OUTSRC_RA_MACIDCFG 0x0
4261
4262 #define H2C_CL_OUTSRC_DM 0x2
4263 #define H2C_FUNC_FW_LPS_CH_INFO 0xb
4264 #define H2C_FUNC_FW_LPS_ML_CMN_INFO 0xe
4265
4266 #define H2C_CL_OUTSRC_RF_REG_A 0x8
4267 #define H2C_CL_OUTSRC_RF_REG_B 0x9
4268 #define H2C_CL_OUTSRC_RF_FW_NOTIFY 0xa
4269 #define H2C_FUNC_OUTSRC_RF_GET_MCCCH 0x2
4270 #define H2C_CL_OUTSRC_RF_FW_RFK 0xb
4271
4272 enum rtw89_rfk_offload_h2c_func {
4273 H2C_FUNC_RFK_TSSI_OFFLOAD = 0x0,
4274 H2C_FUNC_RFK_IQK_OFFLOAD = 0x1,
4275 H2C_FUNC_RFK_DPK_OFFLOAD = 0x3,
4276 H2C_FUNC_RFK_TXGAPK_OFFLOAD = 0x4,
4277 H2C_FUNC_RFK_DACK_OFFLOAD = 0x5,
4278 H2C_FUNC_RFK_RXDCK_OFFLOAD = 0x6,
4279 H2C_FUNC_RFK_PRE_NOTIFY = 0x8,
4280 };
4281
4282 struct rtw89_fw_h2c_rf_get_mccch {
4283 __le32 ch_0;
4284 __le32 ch_1;
4285 __le32 band_0;
4286 __le32 band_1;
4287 __le32 current_channel;
4288 __le32 current_band_type;
4289 } __packed;
4290
4291 #define NUM_OF_RTW89_FW_RFK_PATH 2
4292 #define NUM_OF_RTW89_FW_RFK_TBL 3
4293
4294 struct rtw89_fw_h2c_rfk_pre_info_common {
4295 struct {
4296 __le32 ch[NUM_OF_RTW89_FW_RFK_PATH][NUM_OF_RTW89_FW_RFK_TBL];
4297 __le32 band[NUM_OF_RTW89_FW_RFK_PATH][NUM_OF_RTW89_FW_RFK_TBL];
4298 } __packed dbcc;
4299
4300 __le32 mlo_mode;
4301 struct {
4302 __le32 cur_ch[NUM_OF_RTW89_FW_RFK_PATH];
4303 __le32 cur_band[NUM_OF_RTW89_FW_RFK_PATH];
4304 } __packed tbl;
4305
4306 __le32 phy_idx;
4307 } __packed;
4308
4309 struct rtw89_fw_h2c_rfk_pre_info_v0 {
4310 struct rtw89_fw_h2c_rfk_pre_info_common common;
4311
4312 __le32 cur_band;
4313 __le32 cur_bw;
4314 __le32 cur_center_ch;
4315
4316 __le32 ktbl_sel0;
4317 __le32 ktbl_sel1;
4318 __le32 rfmod0;
4319 __le32 rfmod1;
4320
4321 __le32 mlo_1_1;
4322 __le32 rfe_type;
4323 __le32 drv_mode;
4324
4325 struct {
4326 __le32 ch[NUM_OF_RTW89_FW_RFK_PATH];
4327 __le32 band[NUM_OF_RTW89_FW_RFK_PATH];
4328 } __packed mlo;
4329 } __packed;
4330
4331 struct rtw89_fw_h2c_rfk_pre_info_v1 {
4332 struct rtw89_fw_h2c_rfk_pre_info_common common;
4333 __le32 mlo_1_1;
4334 } __packed;
4335
4336 struct rtw89_fw_h2c_rfk_pre_info {
4337 struct rtw89_fw_h2c_rfk_pre_info_v1 base_v1;
4338 __le32 cur_bandwidth[NUM_OF_RTW89_FW_RFK_PATH];
4339 } __packed;
4340
4341 struct rtw89_h2c_rf_tssi {
4342 __le16 len;
4343 u8 phy;
4344 u8 ch;
4345 u8 bw;
4346 u8 band;
4347 u8 hwtx_en;
4348 u8 cv;
4349 s8 curr_tssi_cck_de[2];
4350 s8 curr_tssi_cck_de_20m[2];
4351 s8 curr_tssi_cck_de_40m[2];
4352 s8 curr_tssi_efuse_cck_de[2];
4353 s8 curr_tssi_ofdm_de[2];
4354 s8 curr_tssi_ofdm_de_20m[2];
4355 s8 curr_tssi_ofdm_de_40m[2];
4356 s8 curr_tssi_ofdm_de_80m[2];
4357 s8 curr_tssi_ofdm_de_160m[2];
4358 s8 curr_tssi_ofdm_de_320m[2];
4359 s8 curr_tssi_efuse_ofdm_de[2];
4360 s8 curr_tssi_ofdm_de_diff_20m[2];
4361 s8 curr_tssi_ofdm_de_diff_80m[2];
4362 s8 curr_tssi_ofdm_de_diff_160m[2];
4363 s8 curr_tssi_ofdm_de_diff_320m[2];
4364 s8 curr_tssi_trim_de[2];
4365 u8 pg_thermal[2];
4366 u8 ftable[2][128];
4367 u8 tssi_mode;
4368 } __packed;
4369
4370 struct rtw89_h2c_rf_iqk {
4371 __le32 phy_idx;
4372 __le32 dbcc;
4373 } __packed;
4374
4375 struct rtw89_h2c_rf_dpk {
4376 u8 len;
4377 u8 phy;
4378 u8 dpk_enable;
4379 u8 kpath;
4380 u8 cur_band;
4381 u8 cur_bw;
4382 u8 cur_ch;
4383 u8 dpk_dbg_en;
4384 } __packed;
4385
4386 struct rtw89_h2c_rf_txgapk {
4387 u8 len;
4388 u8 ktype;
4389 u8 phy;
4390 u8 kpath;
4391 u8 band;
4392 u8 bw;
4393 u8 ch;
4394 u8 cv;
4395 } __packed;
4396
4397 struct rtw89_h2c_rf_dack {
4398 __le32 len;
4399 __le32 phy;
4400 __le32 type;
4401 } __packed;
4402
4403 struct rtw89_h2c_rf_rxdck_v0 {
4404 u8 len;
4405 u8 phy;
4406 u8 is_afe;
4407 u8 kpath;
4408 u8 cur_band;
4409 u8 cur_bw;
4410 u8 cur_ch;
4411 u8 rxdck_dbg_en;
4412 } __packed;
4413
4414 struct rtw89_h2c_rf_rxdck {
4415 struct rtw89_h2c_rf_rxdck_v0 v0;
4416 u8 is_chl_k;
4417 } __packed;
4418
4419 enum rtw89_rf_log_type {
4420 RTW89_RF_RUN_LOG = 0,
4421 RTW89_RF_RPT_LOG = 1,
4422 };
4423
4424 struct rtw89_c2h_rf_log_hdr {
4425 u8 type; /* enum rtw89_rf_log_type */
4426 __le16 len;
4427 u8 content[];
4428 } __packed;
4429
4430 struct rtw89_c2h_rf_run_log {
4431 __le32 fmt_idx;
4432 __le32 arg[4];
4433 } __packed;
4434
4435 struct rtw89_c2h_rf_iqk_rpt_log {
4436 bool iqk_tx_fail[2];
4437 bool iqk_rx_fail[2];
4438 bool is_iqk_init;
4439 bool is_reload;
4440 bool is_wb_txiqk[2];
4441 bool is_wb_rxiqk[2];
4442 bool is_nbiqk;
4443 bool txiqk_en;
4444 bool rxiqk_en;
4445 bool lok_en;
4446 bool iqk_xym_en;
4447 bool iqk_sram_en;
4448 bool iqk_fft_en;
4449 bool is_fw_iqk;
4450 bool is_iqk_enable;
4451 bool iqk_cfir_en;
4452 bool thermal_rek_en;
4453 u8 iqk_band[2];
4454 u8 iqk_ch[2];
4455 u8 iqk_bw[2];
4456 u8 iqk_times;
4457 u8 version;
4458 u8 phy;
4459 u8 fwk_status;
4460 u8 rsvd;
4461 __le32 reload_cnt;
4462 __le32 iqk_fail_cnt;
4463 __le32 lok_idac[2];
4464 __le32 lok_vbuf[2];
4465 __le32 rftxgain[2][4];
4466 __le32 rfrxgain[2][4];
4467 __le32 tx_xym[2][4];
4468 __le32 rx_xym[2][4];
4469 } __packed;
4470
4471 struct rtw89_c2h_rf_dpk_rpt_log {
4472 u8 ver;
4473 u8 idx[2];
4474 u8 band[2];
4475 u8 bw[2];
4476 u8 ch[2];
4477 u8 path_ok[2];
4478 u8 txagc[2];
4479 u8 ther[2];
4480 u8 gs[2];
4481 u8 dc_i[4];
4482 u8 dc_q[4];
4483 u8 corr_val[2];
4484 u8 corr_idx[2];
4485 u8 is_timeout[2];
4486 u8 rxbb_ov[2];
4487 u8 rsvd;
4488 } __packed;
4489
4490 struct rtw89_c2h_rf_dack_rpt_log {
4491 u8 fwdack_ver;
4492 u8 fwdack_info_ver;
4493 u8 msbk_d[2][2][16];
4494 u8 dadck_d[2][2];
4495 u8 cdack_d[2][2][2];
4496 u8 addck2_hd[2][2][2];
4497 u8 addck2_ld[2][2][2];
4498 u8 adgaink_d[2][2];
4499 u8 biask_hd[2][2];
4500 u8 biask_ld[2][2];
4501 u8 addck_timeout;
4502 u8 cdack_timeout;
4503 u8 dadck_timeout;
4504 u8 msbk_timeout;
4505 u8 adgaink_timeout;
4506 u8 wbadcdck_timeout;
4507 u8 drck_timeout;
4508 u8 dack_fail;
4509 u8 wbdck_d[2];
4510 u8 rck_d;
4511 } __packed;
4512
4513 struct rtw89_c2h_rf_rxdck_rpt_log {
4514 u8 ver;
4515 u8 band[2];
4516 u8 bw[2];
4517 u8 ch[2];
4518 u8 timeout[2];
4519 } __packed;
4520
4521 struct rtw89_c2h_rf_tssi_rpt_log {
4522 s8 alignment_power[2][2][4];
4523 u8 alignment_power_cw_h[2][2][4];
4524 u8 alignment_power_cw_l[2][2][4];
4525 u8 tssi_alimk_state[2][2];
4526 u8 default_txagc_offset[2][2];
4527 } __packed;
4528
4529 struct rtw89_c2h_rf_txgapk_rpt_log {
4530 __le32 r0x8010[2];
4531 __le32 chk_cnt;
4532 u8 track_d[2][17];
4533 u8 power_d[2][17];
4534 u8 is_txgapk_ok;
4535 u8 chk_id;
4536 u8 ver;
4537 u8 rsv1;
4538 } __packed;
4539
4540 struct rtw89_c2h_rfk_report {
4541 struct rtw89_c2h_hdr hdr;
4542 u8 state; /* enum rtw89_rfk_report_state */
4543 u8 version;
4544 } __packed;
4545
4546 struct rtw89_c2h_rf_tas_info {
4547 struct rtw89_c2h_hdr hdr;
4548 __le32 cur_idx;
4549 __le16 txpwr_history[20];
4550 } __packed;
4551
4552 #define RTW89_FW_RSVD_PLE_SIZE 0x800
4553
4554 #define RTW89_FW_BACKTRACE_INFO_SIZE 8
4555 #define RTW89_VALID_FW_BACKTRACE_SIZE(_size) \
4556 ((_size) % RTW89_FW_BACKTRACE_INFO_SIZE == 0)
4557
4558 #define RTW89_FW_BACKTRACE_MAX_SIZE 512 /* 8 * 64 (entries) */
4559 #define RTW89_FW_BACKTRACE_KEY 0xBACEBACE
4560
4561 #define FWDL_WAIT_CNT 400000
4562
4563 int rtw89_fw_check_rdy(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type);
4564 int rtw89_fw_recognize(struct rtw89_dev *rtwdev);
4565 int rtw89_fw_recognize_elements(struct rtw89_dev *rtwdev);
4566 const struct firmware *
4567 rtw89_early_fw_feature_recognize(struct device *device,
4568 const struct rtw89_chip_info *chip,
4569 struct rtw89_fw_info *early_fw,
4570 int *used_fw_format);
4571 int rtw89_fw_download(struct rtw89_dev *rtwdev, enum rtw89_fw_type type,
4572 bool include_bb);
4573 void rtw89_load_firmware_work(struct work_struct *work);
4574 void rtw89_unload_firmware(struct rtw89_dev *rtwdev);
4575 int rtw89_wait_firmware_completion(struct rtw89_dev *rtwdev);
4576 int rtw89_fw_log_prepare(struct rtw89_dev *rtwdev);
4577 void rtw89_fw_log_dump(struct rtw89_dev *rtwdev, u8 *buf, u32 len);
4578 void rtw89_h2c_pkt_set_hdr(struct rtw89_dev *rtwdev, struct sk_buff *skb,
4579 u8 type, u8 cat, u8 class, u8 func,
4580 bool rack, bool dack, u32 len);
4581 int rtw89_fw_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev,
4582 struct rtw89_vif_link *rtwvif_link,
4583 struct rtw89_sta_link *rtwsta_link);
4584 int rtw89_fw_h2c_default_cmac_tbl_g7(struct rtw89_dev *rtwdev,
4585 struct rtw89_vif_link *rtwvif_link,
4586 struct rtw89_sta_link *rtwsta_link);
4587 int rtw89_fw_h2c_default_dmac_tbl_v2(struct rtw89_dev *rtwdev,
4588 struct rtw89_vif_link *rtwvif_link,
4589 struct rtw89_sta_link *rtwsta_link);
4590 int rtw89_fw_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev,
4591 struct rtw89_vif_link *rtwvif_link,
4592 struct rtw89_sta_link *rtwsta_link);
4593 int rtw89_fw_h2c_assoc_cmac_tbl_g7(struct rtw89_dev *rtwdev,
4594 struct rtw89_vif_link *rtwvif_link,
4595 struct rtw89_sta_link *rtwsta_link);
4596 int rtw89_fw_h2c_ampdu_cmac_tbl_g7(struct rtw89_dev *rtwdev,
4597 struct rtw89_vif_link *rtwvif_link,
4598 struct rtw89_sta_link *rtwsta_link);
4599 int rtw89_fw_h2c_txtime_cmac_tbl(struct rtw89_dev *rtwdev,
4600 struct rtw89_sta_link *rtwsta_link);
4601 int rtw89_fw_h2c_txtime_cmac_tbl_g7(struct rtw89_dev *rtwdev,
4602 struct rtw89_sta_link *rtwsta_link);
4603 int rtw89_fw_h2c_txpath_cmac_tbl(struct rtw89_dev *rtwdev,
4604 struct rtw89_sta_link *rtwsta_link);
4605 int rtw89_fw_h2c_update_beacon(struct rtw89_dev *rtwdev,
4606 struct rtw89_vif_link *rtwvif_link);
4607 int rtw89_fw_h2c_update_beacon_be(struct rtw89_dev *rtwdev,
4608 struct rtw89_vif_link *rtwvif_link);
4609 int rtw89_fw_h2c_cam(struct rtw89_dev *rtwdev, struct rtw89_vif_link *vif,
4610 struct rtw89_sta_link *rtwsta_link, const u8 *scan_mac_addr);
4611 int rtw89_fw_h2c_dctl_sec_cam_v1(struct rtw89_dev *rtwdev,
4612 struct rtw89_vif_link *rtwvif_link,
4613 struct rtw89_sta_link *rtwsta_link);
4614 int rtw89_fw_h2c_dctl_sec_cam_v2(struct rtw89_dev *rtwdev,
4615 struct rtw89_vif_link *rtwvif_link,
4616 struct rtw89_sta_link *rtwsta_link);
4617 void rtw89_fw_c2h_irqsafe(struct rtw89_dev *rtwdev, struct sk_buff *c2h);
4618 void rtw89_fw_c2h_work(struct wiphy *wiphy, struct wiphy_work *work);
4619 int rtw89_fw_h2c_role_maintain(struct rtw89_dev *rtwdev,
4620 struct rtw89_vif_link *rtwvif_link,
4621 struct rtw89_sta_link *rtwsta_link,
4622 enum rtw89_upd_mode upd_mode);
4623 int rtw89_fw_h2c_join_info(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4624 struct rtw89_sta_link *rtwsta_link, bool dis_conn);
4625 int rtw89_fw_h2c_notify_dbcc(struct rtw89_dev *rtwdev, bool en);
4626 int rtw89_fw_h2c_macid_pause(struct rtw89_dev *rtwdev, u8 sh, u8 grp,
4627 bool pause);
4628 int rtw89_fw_h2c_set_edca(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4629 u8 ac, u32 val);
4630 int rtw89_fw_h2c_set_ofld_cfg(struct rtw89_dev *rtwdev);
4631 int rtw89_fw_h2c_tx_duty(struct rtw89_dev *rtwdev, u8 lv);
4632 int rtw89_fw_h2c_set_bcn_fltr_cfg(struct rtw89_dev *rtwdev,
4633 struct rtw89_vif_link *rtwvif_link,
4634 bool connect);
4635 int rtw89_fw_h2c_rssi_offload(struct rtw89_dev *rtwdev,
4636 struct rtw89_rx_phy_ppdu *phy_ppdu);
4637 int rtw89_fw_h2c_tp_offload(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link);
4638 int rtw89_fw_h2c_ra(struct rtw89_dev *rtwdev, struct rtw89_ra_info *ra, bool csi);
4639 int rtw89_fw_h2c_cxdrv_init(struct rtw89_dev *rtwdev, u8 type);
4640 int rtw89_fw_h2c_cxdrv_init_v7(struct rtw89_dev *rtwdev, u8 type);
4641 int rtw89_fw_h2c_cxdrv_role(struct rtw89_dev *rtwdev, u8 type);
4642 int rtw89_fw_h2c_cxdrv_role_v1(struct rtw89_dev *rtwdev, u8 type);
4643 int rtw89_fw_h2c_cxdrv_role_v2(struct rtw89_dev *rtwdev, u8 type);
4644 int rtw89_fw_h2c_cxdrv_role_v7(struct rtw89_dev *rtwdev, u8 type);
4645 int rtw89_fw_h2c_cxdrv_role_v8(struct rtw89_dev *rtwdev, u8 type);
4646 int rtw89_fw_h2c_cxdrv_ctrl(struct rtw89_dev *rtwdev, u8 type);
4647 int rtw89_fw_h2c_cxdrv_ctrl_v7(struct rtw89_dev *rtwdev, u8 type);
4648 int rtw89_fw_h2c_cxdrv_trx(struct rtw89_dev *rtwdev, u8 type);
4649 int rtw89_fw_h2c_cxdrv_rfk(struct rtw89_dev *rtwdev, u8 type);
4650 int rtw89_fw_h2c_del_pkt_offload(struct rtw89_dev *rtwdev, u8 id);
4651 int rtw89_fw_h2c_add_pkt_offload(struct rtw89_dev *rtwdev, u8 *id,
4652 struct sk_buff *skb_ofld);
4653 int rtw89_fw_h2c_scan_offload_ax(struct rtw89_dev *rtwdev,
4654 struct rtw89_scan_option *opt,
4655 struct rtw89_vif_link *vif,
4656 bool wowlan);
4657 int rtw89_fw_h2c_scan_offload_be(struct rtw89_dev *rtwdev,
4658 struct rtw89_scan_option *opt,
4659 struct rtw89_vif_link *vif,
4660 bool wowlan);
4661 int rtw89_fw_h2c_rf_reg(struct rtw89_dev *rtwdev,
4662 struct rtw89_fw_h2c_rf_reg_info *info,
4663 u16 len, u8 page);
4664 int rtw89_fw_h2c_rf_ntfy_mcc(struct rtw89_dev *rtwdev);
4665 int rtw89_fw_h2c_rf_pre_ntfy(struct rtw89_dev *rtwdev,
4666 enum rtw89_phy_idx phy_idx);
4667 int rtw89_fw_h2c_rf_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
4668 const struct rtw89_chan *chan, enum rtw89_tssi_mode tssi_mode);
4669 int rtw89_fw_h2c_rf_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
4670 const struct rtw89_chan *chan);
4671 int rtw89_fw_h2c_rf_dpk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
4672 const struct rtw89_chan *chan);
4673 int rtw89_fw_h2c_rf_txgapk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
4674 const struct rtw89_chan *chan);
4675 int rtw89_fw_h2c_rf_dack(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
4676 const struct rtw89_chan *chan);
4677 int rtw89_fw_h2c_rf_rxdck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
4678 const struct rtw89_chan *chan, bool is_chl_k);
4679 int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev,
4680 u8 h2c_class, u8 h2c_func, u8 *buf, u16 len,
4681 bool rack, bool dack);
4682 int rtw89_fw_h2c_raw(struct rtw89_dev *rtwdev, const u8 *buf, u16 len);
4683 void rtw89_fw_send_all_early_h2c(struct rtw89_dev *rtwdev);
4684 void __rtw89_fw_free_all_early_h2c(struct rtw89_dev *rtwdev);
4685 void rtw89_fw_free_all_early_h2c(struct rtw89_dev *rtwdev);
4686 int rtw89_fw_h2c_general_pkt(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4687 u8 macid);
4688 void rtw89_fw_release_general_pkt_list_vif(struct rtw89_dev *rtwdev,
4689 struct rtw89_vif_link *rtwvif_link,
4690 bool notify_fw);
4691 void rtw89_fw_release_general_pkt_list(struct rtw89_dev *rtwdev, bool notify_fw);
4692 int rtw89_fw_h2c_ba_cam(struct rtw89_dev *rtwdev,
4693 struct rtw89_vif_link *rtwvif_link,
4694 struct rtw89_sta_link *rtwsta_link,
4695 bool valid, struct ieee80211_ampdu_params *params);
4696 int rtw89_fw_h2c_ba_cam_v1(struct rtw89_dev *rtwdev,
4697 struct rtw89_vif_link *rtwvif_link,
4698 struct rtw89_sta_link *rtwsta_link,
4699 bool valid, struct ieee80211_ampdu_params *params);
4700 void rtw89_fw_h2c_init_dynamic_ba_cam_v0_ext(struct rtw89_dev *rtwdev);
4701 int rtw89_fw_h2c_init_ba_cam_users(struct rtw89_dev *rtwdev, u8 users,
4702 u8 offset, u8 mac_idx);
4703
4704 int rtw89_fw_h2c_lps_parm(struct rtw89_dev *rtwdev,
4705 struct rtw89_lps_parm *lps_param);
4706 int rtw89_fw_h2c_lps_ch_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
4707 int rtw89_fw_h2c_lps_ml_cmn_info(struct rtw89_dev *rtwdev,
4708 struct rtw89_vif *rtwvif);
4709 int rtw89_fw_h2c_fwips(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4710 bool enable);
4711 struct sk_buff *rtw89_fw_h2c_alloc_skb_with_hdr(struct rtw89_dev *rtwdev, u32 len);
4712 struct sk_buff *rtw89_fw_h2c_alloc_skb_no_hdr(struct rtw89_dev *rtwdev, u32 len);
4713 int rtw89_fw_msg_reg(struct rtw89_dev *rtwdev,
4714 struct rtw89_mac_h2c_info *h2c_info,
4715 struct rtw89_mac_c2h_info *c2h_info);
4716 int rtw89_fw_h2c_fw_log(struct rtw89_dev *rtwdev, bool enable);
4717 void rtw89_fw_st_dbg_dump(struct rtw89_dev *rtwdev);
4718 void rtw89_hw_scan_start(struct rtw89_dev *rtwdev,
4719 struct rtw89_vif_link *rtwvif_link,
4720 struct ieee80211_scan_request *scan_req);
4721 void rtw89_hw_scan_complete(struct rtw89_dev *rtwdev,
4722 struct rtw89_vif_link *rtwvif_link,
4723 bool aborted);
4724 int rtw89_hw_scan_offload(struct rtw89_dev *rtwdev,
4725 struct rtw89_vif_link *rtwvif_link,
4726 bool enable);
4727 void rtw89_hw_scan_abort(struct rtw89_dev *rtwdev,
4728 struct rtw89_vif_link *rtwvif_link);
4729 int rtw89_hw_scan_add_chan_list_ax(struct rtw89_dev *rtwdev,
4730 struct rtw89_vif_link *rtwvif_link, bool connected);
4731 int rtw89_pno_scan_add_chan_list_ax(struct rtw89_dev *rtwdev,
4732 struct rtw89_vif_link *rtwvif_link);
4733 int rtw89_hw_scan_add_chan_list_be(struct rtw89_dev *rtwdev,
4734 struct rtw89_vif_link *rtwvif_link, bool connected);
4735 int rtw89_pno_scan_add_chan_list_be(struct rtw89_dev *rtwdev,
4736 struct rtw89_vif_link *rtwvif_link);
4737 int rtw89_fw_h2c_trigger_cpu_exception(struct rtw89_dev *rtwdev);
4738 int rtw89_fw_h2c_pkt_drop(struct rtw89_dev *rtwdev,
4739 const struct rtw89_pkt_drop_params *params);
4740 int rtw89_fw_h2c_p2p_act(struct rtw89_dev *rtwdev,
4741 struct rtw89_vif_link *rtwvif_link,
4742 struct ieee80211_bss_conf *bss_conf,
4743 struct ieee80211_p2p_noa_desc *desc,
4744 u8 act, u8 noa_id);
4745 int rtw89_fw_h2c_tsf32_toggle(struct rtw89_dev *rtwdev,
4746 struct rtw89_vif_link *rtwvif_link,
4747 bool en);
4748 int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4749 bool enable);
4750 int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev,
4751 struct rtw89_vif_link *rtwvif_link, bool enable);
4752 int rtw89_fw_h2c_cfg_pno(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4753 bool enable);
4754 int rtw89_fw_h2c_keep_alive(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4755 bool enable);
4756 int rtw89_fw_h2c_arp_offload(struct rtw89_dev *rtwdev,
4757 struct rtw89_vif_link *rtwvif_link, bool enable);
4758 int rtw89_fw_h2c_disconnect_detect(struct rtw89_dev *rtwdev,
4759 struct rtw89_vif_link *rtwvif_link, bool enable);
4760 int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4761 bool enable);
4762 int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev,
4763 struct rtw89_vif_link *rtwvif_link, bool enable);
4764 int rtw89_fw_wow_cam_update(struct rtw89_dev *rtwdev,
4765 struct rtw89_wow_cam_info *cam_info);
4766 int rtw89_fw_h2c_wow_gtk_ofld(struct rtw89_dev *rtwdev,
4767 struct rtw89_vif_link *rtwvif_link,
4768 bool enable);
4769 int rtw89_fw_h2c_wow_request_aoac(struct rtw89_dev *rtwdev);
4770 int rtw89_fw_h2c_add_mcc(struct rtw89_dev *rtwdev,
4771 const struct rtw89_fw_mcc_add_req *p);
4772 int rtw89_fw_h2c_start_mcc(struct rtw89_dev *rtwdev,
4773 const struct rtw89_fw_mcc_start_req *p);
4774 int rtw89_fw_h2c_stop_mcc(struct rtw89_dev *rtwdev, u8 group, u8 macid,
4775 bool prev_groups);
4776 int rtw89_fw_h2c_del_mcc_group(struct rtw89_dev *rtwdev, u8 group,
4777 bool prev_groups);
4778 int rtw89_fw_h2c_reset_mcc_group(struct rtw89_dev *rtwdev, u8 group);
4779 int rtw89_fw_h2c_mcc_req_tsf(struct rtw89_dev *rtwdev,
4780 const struct rtw89_fw_mcc_tsf_req *req,
4781 struct rtw89_mac_mcc_tsf_rpt *rpt);
4782 int rtw89_fw_h2c_mcc_macid_bitmap(struct rtw89_dev *rtwdev, u8 group, u8 macid,
4783 u8 *bitmap);
4784 int rtw89_fw_h2c_mcc_sync(struct rtw89_dev *rtwdev, u8 group, u8 source,
4785 u8 target, u8 offset);
4786 int rtw89_fw_h2c_mcc_set_duration(struct rtw89_dev *rtwdev,
4787 const struct rtw89_fw_mcc_duration *p);
4788 int rtw89_fw_h2c_mrc_add(struct rtw89_dev *rtwdev,
4789 const struct rtw89_fw_mrc_add_arg *arg);
4790 int rtw89_fw_h2c_mrc_start(struct rtw89_dev *rtwdev,
4791 const struct rtw89_fw_mrc_start_arg *arg);
4792 int rtw89_fw_h2c_mrc_del(struct rtw89_dev *rtwdev, u8 sch_idx, u8 slot_idx);
4793 int rtw89_fw_h2c_mrc_req_tsf(struct rtw89_dev *rtwdev,
4794 const struct rtw89_fw_mrc_req_tsf_arg *arg,
4795 struct rtw89_mac_mrc_tsf_rpt *rpt);
4796 int rtw89_fw_h2c_mrc_upd_bitmap(struct rtw89_dev *rtwdev,
4797 const struct rtw89_fw_mrc_upd_bitmap_arg *arg);
4798 int rtw89_fw_h2c_mrc_sync(struct rtw89_dev *rtwdev,
4799 const struct rtw89_fw_mrc_sync_arg *arg);
4800 int rtw89_fw_h2c_mrc_upd_duration(struct rtw89_dev *rtwdev,
4801 const struct rtw89_fw_mrc_upd_duration_arg *arg);
4802 int rtw89_fw_h2c_ap_info_refcount(struct rtw89_dev *rtwdev, bool en);
4803
rtw89_fw_h2c_init_ba_cam(struct rtw89_dev * rtwdev)4804 static inline void rtw89_fw_h2c_init_ba_cam(struct rtw89_dev *rtwdev)
4805 {
4806 const struct rtw89_chip_info *chip = rtwdev->chip;
4807
4808 if (chip->bacam_ver == RTW89_BACAM_V0_EXT)
4809 rtw89_fw_h2c_init_dynamic_ba_cam_v0_ext(rtwdev);
4810 }
4811
rtw89_chip_h2c_default_cmac_tbl(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)4812 static inline int rtw89_chip_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev,
4813 struct rtw89_vif_link *rtwvif_link,
4814 struct rtw89_sta_link *rtwsta_link)
4815 {
4816 const struct rtw89_chip_info *chip = rtwdev->chip;
4817
4818 return chip->ops->h2c_default_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
4819 }
4820
rtw89_chip_h2c_default_dmac_tbl(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)4821 static inline int rtw89_chip_h2c_default_dmac_tbl(struct rtw89_dev *rtwdev,
4822 struct rtw89_vif_link *rtwvif_link,
4823 struct rtw89_sta_link *rtwsta_link)
4824 {
4825 const struct rtw89_chip_info *chip = rtwdev->chip;
4826
4827 if (chip->ops->h2c_default_dmac_tbl)
4828 return chip->ops->h2c_default_dmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
4829
4830 return 0;
4831 }
4832
rtw89_chip_h2c_update_beacon(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)4833 static inline int rtw89_chip_h2c_update_beacon(struct rtw89_dev *rtwdev,
4834 struct rtw89_vif_link *rtwvif_link)
4835 {
4836 const struct rtw89_chip_info *chip = rtwdev->chip;
4837
4838 return chip->ops->h2c_update_beacon(rtwdev, rtwvif_link);
4839 }
4840
rtw89_chip_h2c_assoc_cmac_tbl(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)4841 static inline int rtw89_chip_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev,
4842 struct rtw89_vif_link *rtwvif_link,
4843 struct rtw89_sta_link *rtwsta_link)
4844 {
4845 const struct rtw89_chip_info *chip = rtwdev->chip;
4846
4847 return chip->ops->h2c_assoc_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
4848 }
4849
4850 static inline
rtw89_chip_h2c_ampdu_link_cmac_tbl(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)4851 int rtw89_chip_h2c_ampdu_link_cmac_tbl(struct rtw89_dev *rtwdev,
4852 struct rtw89_vif_link *rtwvif_link,
4853 struct rtw89_sta_link *rtwsta_link)
4854 {
4855 const struct rtw89_chip_info *chip = rtwdev->chip;
4856
4857 if (chip->ops->h2c_ampdu_cmac_tbl)
4858 return chip->ops->h2c_ampdu_cmac_tbl(rtwdev, rtwvif_link,
4859 rtwsta_link);
4860
4861 return 0;
4862 }
4863
rtw89_chip_h2c_ampdu_cmac_tbl(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,struct rtw89_sta * rtwsta)4864 static inline int rtw89_chip_h2c_ampdu_cmac_tbl(struct rtw89_dev *rtwdev,
4865 struct rtw89_vif *rtwvif,
4866 struct rtw89_sta *rtwsta)
4867 {
4868 struct rtw89_vif_link *rtwvif_link;
4869 struct rtw89_sta_link *rtwsta_link;
4870 unsigned int link_id;
4871 int ret;
4872
4873 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) {
4874 rtwvif_link = rtwsta_link->rtwvif_link;
4875 ret = rtw89_chip_h2c_ampdu_link_cmac_tbl(rtwdev, rtwvif_link,
4876 rtwsta_link);
4877 if (ret)
4878 return ret;
4879 }
4880
4881 return 0;
4882 }
4883
4884 static inline
rtw89_chip_h2c_txtime_cmac_tbl(struct rtw89_dev * rtwdev,struct rtw89_sta_link * rtwsta_link)4885 int rtw89_chip_h2c_txtime_cmac_tbl(struct rtw89_dev *rtwdev,
4886 struct rtw89_sta_link *rtwsta_link)
4887 {
4888 const struct rtw89_chip_info *chip = rtwdev->chip;
4889
4890 return chip->ops->h2c_txtime_cmac_tbl(rtwdev, rtwsta_link);
4891 }
4892
4893 static inline
rtw89_chip_h2c_ba_cam(struct rtw89_dev * rtwdev,struct rtw89_sta * rtwsta,bool valid,struct ieee80211_ampdu_params * params)4894 int rtw89_chip_h2c_ba_cam(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
4895 bool valid, struct ieee80211_ampdu_params *params)
4896 {
4897 const struct rtw89_chip_info *chip = rtwdev->chip;
4898 struct rtw89_vif_link *rtwvif_link;
4899 struct rtw89_sta_link *rtwsta_link;
4900 unsigned int link_id;
4901 int ret;
4902
4903 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) {
4904 rtwvif_link = rtwsta_link->rtwvif_link;
4905 ret = chip->ops->h2c_ba_cam(rtwdev, rtwvif_link, rtwsta_link,
4906 valid, params);
4907 if (ret)
4908 return ret;
4909 }
4910
4911 return 0;
4912 }
4913
4914 /* Must consider compatibility; don't insert new in the mid.
4915 * Fill each field's default value in rtw89_regd_entcpy().
4916 */
4917 struct rtw89_fw_regd_entry {
4918 u8 alpha2_0;
4919 u8 alpha2_1;
4920 u8 rule_2ghz;
4921 u8 rule_5ghz;
4922 u8 rule_6ghz;
4923 __le32 fmap;
4924 } __packed;
4925
4926 /* must consider compatibility; don't insert new in the mid */
4927 struct rtw89_fw_txpwr_byrate_entry {
4928 u8 band;
4929 u8 nss;
4930 u8 rs;
4931 u8 shf;
4932 u8 len;
4933 __le32 data;
4934 u8 bw;
4935 u8 ofdma;
4936 } __packed;
4937
4938 /* must consider compatibility; don't insert new in the mid */
4939 struct rtw89_fw_txpwr_lmt_2ghz_entry {
4940 u8 bw;
4941 u8 nt;
4942 u8 rs;
4943 u8 bf;
4944 u8 regd;
4945 u8 ch_idx;
4946 s8 v;
4947 } __packed;
4948
4949 /* must consider compatibility; don't insert new in the mid */
4950 struct rtw89_fw_txpwr_lmt_5ghz_entry {
4951 u8 bw;
4952 u8 nt;
4953 u8 rs;
4954 u8 bf;
4955 u8 regd;
4956 u8 ch_idx;
4957 s8 v;
4958 } __packed;
4959
4960 /* must consider compatibility; don't insert new in the mid */
4961 struct rtw89_fw_txpwr_lmt_6ghz_entry {
4962 u8 bw;
4963 u8 nt;
4964 u8 rs;
4965 u8 bf;
4966 u8 regd;
4967 u8 reg_6ghz_power;
4968 u8 ch_idx;
4969 s8 v;
4970 } __packed;
4971
4972 /* must consider compatibility; don't insert new in the mid */
4973 struct rtw89_fw_txpwr_lmt_ru_2ghz_entry {
4974 u8 ru;
4975 u8 nt;
4976 u8 regd;
4977 u8 ch_idx;
4978 s8 v;
4979 } __packed;
4980
4981 /* must consider compatibility; don't insert new in the mid */
4982 struct rtw89_fw_txpwr_lmt_ru_5ghz_entry {
4983 u8 ru;
4984 u8 nt;
4985 u8 regd;
4986 u8 ch_idx;
4987 s8 v;
4988 } __packed;
4989
4990 /* must consider compatibility; don't insert new in the mid */
4991 struct rtw89_fw_txpwr_lmt_ru_6ghz_entry {
4992 u8 ru;
4993 u8 nt;
4994 u8 regd;
4995 u8 reg_6ghz_power;
4996 u8 ch_idx;
4997 s8 v;
4998 } __packed;
4999
5000 /* must consider compatibility; don't insert new in the mid */
5001 struct rtw89_fw_tx_shape_lmt_entry {
5002 u8 band;
5003 u8 tx_shape_rs;
5004 u8 regd;
5005 u8 v;
5006 } __packed;
5007
5008 /* must consider compatibility; don't insert new in the mid */
5009 struct rtw89_fw_tx_shape_lmt_ru_entry {
5010 u8 band;
5011 u8 regd;
5012 u8 v;
5013 } __packed;
5014
5015 const struct rtw89_rfe_parms *
5016 rtw89_load_rfe_data_from_fw(struct rtw89_dev *rtwdev,
5017 const struct rtw89_rfe_parms *init);
5018
5019 enum rtw89_wow_wakeup_ver {
5020 RTW89_WOW_REASON_V0,
5021 RTW89_WOW_REASON_V1,
5022 RTW89_WOW_REASON_NUM,
5023 };
5024
5025 #endif
5026