1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics 2025 - All Rights Reserved 4 */ 5 6 #include <linux/bitfield.h> 7 #include <linux/clk.h> 8 #include <linux/delay.h> 9 #include <linux/dma-mapping.h> 10 #include <linux/dmaengine.h> 11 #include <linux/err.h> 12 #include <linux/errno.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/iopoll.h> 17 #include <linux/mfd/syscon.h> 18 #include <linux/module.h> 19 #include <linux/mutex.h> 20 #include <linux/of.h> 21 #include <linux/of_address.h> 22 #include <linux/of_device.h> 23 #include <linux/of_reserved_mem.h> 24 #include <linux/pinctrl/consumer.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/reset.h> 28 #include <linux/sizes.h> 29 #include <linux/spi/spi-mem.h> 30 #include <linux/types.h> 31 32 #define OSPI_CR 0x00 33 #define CR_EN BIT(0) 34 #define CR_ABORT BIT(1) 35 #define CR_DMAEN BIT(2) 36 #define CR_FTHRES_SHIFT 8 37 #define CR_SMIE BIT(19) 38 #define CR_APMS BIT(22) 39 #define CR_CSSEL BIT(24) 40 #define CR_FMODE_MASK GENMASK(29, 28) 41 #define CR_FMODE_INDW (0U) 42 #define CR_FMODE_INDR (1U) 43 #define CR_FMODE_APM (2U) 44 #define CR_FMODE_MM (3U) 45 46 #define OSPI_DCR1 0x08 47 #define DCR1_DLYBYP BIT(3) 48 #define DCR1_DEVSIZE_MASK GENMASK(20, 16) 49 #define DCR1_MTYP_MASK GENMASK(26, 24) 50 #define DCR1_MTYP_MX_MODE 1 51 #define DCR1_MTYP_HP_MEMMODE 4 52 53 #define OSPI_DCR2 0x0c 54 #define DCR2_PRESC_MASK GENMASK(7, 0) 55 56 #define OSPI_SR 0x20 57 #define SR_TEF BIT(0) 58 #define SR_TCF BIT(1) 59 #define SR_FTF BIT(2) 60 #define SR_SMF BIT(3) 61 #define SR_BUSY BIT(5) 62 63 #define OSPI_FCR 0x24 64 #define FCR_CTEF BIT(0) 65 #define FCR_CTCF BIT(1) 66 #define FCR_CSMF BIT(3) 67 68 #define OSPI_DLR 0x40 69 #define OSPI_AR 0x48 70 #define OSPI_DR 0x50 71 #define OSPI_PSMKR 0x80 72 #define OSPI_PSMAR 0x88 73 74 #define OSPI_CCR 0x100 75 #define CCR_IMODE_MASK GENMASK(2, 0) 76 #define CCR_IDTR BIT(3) 77 #define CCR_ISIZE_MASK GENMASK(5, 4) 78 #define CCR_ADMODE_MASK GENMASK(10, 8) 79 #define CCR_ADMODE_8LINES 4 80 #define CCR_ADDTR BIT(11) 81 #define CCR_ADSIZE_MASK GENMASK(13, 12) 82 #define CCR_ADSIZE_32BITS 3 83 #define CCR_DMODE_MASK GENMASK(26, 24) 84 #define CCR_DMODE_8LINES 4 85 #define CCR_DQSE BIT(29) 86 #define CCR_DDTR BIT(27) 87 #define CCR_BUSWIDTH_0 0x0 88 #define CCR_BUSWIDTH_1 0x1 89 #define CCR_BUSWIDTH_2 0x2 90 #define CCR_BUSWIDTH_4 0x3 91 #define CCR_BUSWIDTH_8 0x4 92 93 #define OSPI_TCR 0x108 94 #define TCR_DCYC_MASK GENMASK(4, 0) 95 #define TCR_DHQC BIT(28) 96 #define TCR_SSHIFT BIT(30) 97 98 #define OSPI_IR 0x110 99 100 #define STM32_OSPI_MAX_MMAP_SZ SZ_256M 101 #define STM32_OSPI_MAX_NORCHIP 2 102 103 #define STM32_FIFO_TIMEOUT_US 30000 104 #define STM32_ABT_TIMEOUT_US 100000 105 #define STM32_COMP_TIMEOUT_MS 5000 106 #define STM32_BUSY_TIMEOUT_US 100000 107 #define STM32_WAIT_CMD_TIMEOUT_US 5000 108 109 #define STM32_AUTOSUSPEND_DELAY -1 110 111 struct stm32_ospi { 112 struct device *dev; 113 struct spi_controller *ctrl; 114 struct clk *clk; 115 struct reset_control *rstc; 116 117 struct completion match_completion; 118 119 struct dma_chan *dma_chtx; 120 struct dma_chan *dma_chrx; 121 struct completion dma_completion; 122 123 void __iomem *regs_base; 124 void __iomem *mm_base; 125 phys_addr_t regs_phys_base; 126 resource_size_t mm_size; 127 u32 clk_rate; 128 u32 fmode; 129 u32 cr_reg; 130 u32 dcr_reg; 131 u32 flash_presc[STM32_OSPI_MAX_NORCHIP]; 132 int irq; 133 unsigned long status_timeout; 134 135 /* 136 * To protect device configuration, could be different between 137 * 2 flash access 138 */ 139 struct mutex lock; 140 }; 141 142 static void stm32_ospi_read_fifo(void *val, void __iomem *addr, u8 len) 143 { 144 switch (len) { 145 case sizeof(u32): 146 *((u32 *)val) = readl_relaxed(addr); 147 break; 148 case sizeof(u16): 149 *((u16 *)val) = readw_relaxed(addr); 150 break; 151 case sizeof(u8): 152 *((u8 *)val) = readb_relaxed(addr); 153 } 154 } 155 156 static void stm32_ospi_write_fifo(void *val, void __iomem *addr, u8 len) 157 { 158 switch (len) { 159 case sizeof(u32): 160 writel_relaxed(*((u32 *)val), addr); 161 break; 162 case sizeof(u16): 163 writew_relaxed(*((u16 *)val), addr); 164 break; 165 case sizeof(u8): 166 writeb_relaxed(*((u8 *)val), addr); 167 } 168 } 169 170 static int stm32_ospi_abort(struct stm32_ospi *ospi) 171 { 172 void __iomem *regs_base = ospi->regs_base; 173 u32 cr; 174 int timeout; 175 176 cr = readl_relaxed(regs_base + OSPI_CR) | CR_ABORT; 177 writel_relaxed(cr, regs_base + OSPI_CR); 178 179 /* wait clear of abort bit by hw */ 180 timeout = readl_relaxed_poll_timeout_atomic(regs_base + OSPI_CR, 181 cr, !(cr & CR_ABORT), 1, 182 STM32_ABT_TIMEOUT_US); 183 184 if (timeout) 185 dev_err(ospi->dev, "%s abort timeout:%d\n", __func__, timeout); 186 187 return timeout; 188 } 189 190 static int stm32_ospi_poll(struct stm32_ospi *ospi, void *buf, u32 len, bool read) 191 { 192 void __iomem *regs_base = ospi->regs_base; 193 void (*fifo)(void *val, void __iomem *addr, u8 len); 194 u32 sr; 195 int ret; 196 u8 step; 197 198 if (read) 199 fifo = stm32_ospi_read_fifo; 200 else 201 fifo = stm32_ospi_write_fifo; 202 203 while (len) { 204 ret = readl_relaxed_poll_timeout_atomic(regs_base + OSPI_SR, 205 sr, sr & SR_FTF, 1, 206 STM32_FIFO_TIMEOUT_US); 207 if (ret) { 208 dev_err(ospi->dev, "fifo timeout (len:%d stat:%#x)\n", 209 len, sr); 210 return ret; 211 } 212 213 if (len >= sizeof(u32)) 214 step = sizeof(u32); 215 else if (len >= sizeof(u16)) 216 step = sizeof(u16); 217 else 218 step = sizeof(u8); 219 220 fifo(buf, regs_base + OSPI_DR, step); 221 len -= step; 222 buf += step; 223 } 224 225 return 0; 226 } 227 228 static int stm32_ospi_wait_nobusy(struct stm32_ospi *ospi) 229 { 230 u32 sr; 231 232 return readl_relaxed_poll_timeout_atomic(ospi->regs_base + OSPI_SR, 233 sr, !(sr & SR_BUSY), 1, 234 STM32_BUSY_TIMEOUT_US); 235 } 236 237 static int stm32_ospi_wait_cmd(struct stm32_ospi *ospi) 238 { 239 void __iomem *regs_base = ospi->regs_base; 240 u32 sr; 241 int err = 0; 242 243 if (ospi->fmode == CR_FMODE_APM) 244 goto out; 245 246 err = readl_relaxed_poll_timeout_atomic(ospi->regs_base + OSPI_SR, sr, 247 (sr & (SR_TEF | SR_TCF)), 1, 248 STM32_WAIT_CMD_TIMEOUT_US); 249 250 if (sr & SR_TCF) 251 /* avoid false timeout */ 252 err = 0; 253 if (sr & SR_TEF) 254 err = -EIO; 255 256 out: 257 /* clear flags */ 258 writel_relaxed(FCR_CTCF | FCR_CTEF, regs_base + OSPI_FCR); 259 260 if (!err) 261 err = stm32_ospi_wait_nobusy(ospi); 262 263 return err; 264 } 265 266 static void stm32_ospi_dma_callback(void *arg) 267 { 268 struct completion *dma_completion = arg; 269 270 complete(dma_completion); 271 } 272 273 static irqreturn_t stm32_ospi_irq(int irq, void *dev_id) 274 { 275 struct stm32_ospi *ospi = (struct stm32_ospi *)dev_id; 276 void __iomem *regs_base = ospi->regs_base; 277 u32 cr, sr; 278 279 cr = readl_relaxed(regs_base + OSPI_CR); 280 sr = readl_relaxed(regs_base + OSPI_SR); 281 282 if (sr & SR_SMF) { 283 /* disable irq */ 284 cr &= ~CR_SMIE; 285 writel_relaxed(cr, regs_base + OSPI_CR); 286 complete(&ospi->match_completion); 287 } 288 289 return IRQ_HANDLED; 290 } 291 292 static int stm32_ospi_dma_setup(struct stm32_ospi *ospi, 293 struct dma_slave_config *dma_cfg) 294 { 295 struct dma_slave_caps caps; 296 int ret = 0; 297 298 if (dma_cfg && ospi->dma_chrx) { 299 ret = dma_get_slave_caps(ospi->dma_chrx, &caps); 300 if (ret) 301 return ret; 302 303 dma_cfg->src_maxburst = caps.max_burst / dma_cfg->src_addr_width; 304 305 if (dmaengine_slave_config(ospi->dma_chrx, dma_cfg)) { 306 dev_err(ospi->dev, "dma rx config failed\n"); 307 dma_release_channel(ospi->dma_chrx); 308 ospi->dma_chrx = NULL; 309 } 310 } 311 312 if (dma_cfg && ospi->dma_chtx) { 313 ret = dma_get_slave_caps(ospi->dma_chtx, &caps); 314 if (ret) 315 return ret; 316 317 dma_cfg->dst_maxburst = caps.max_burst / dma_cfg->dst_addr_width; 318 319 if (dmaengine_slave_config(ospi->dma_chtx, dma_cfg)) { 320 dev_err(ospi->dev, "dma tx config failed\n"); 321 dma_release_channel(ospi->dma_chtx); 322 ospi->dma_chtx = NULL; 323 } 324 } 325 326 init_completion(&ospi->dma_completion); 327 328 return ret; 329 } 330 331 static int stm32_ospi_tx_mm(struct stm32_ospi *ospi, 332 const struct spi_mem_op *op) 333 { 334 memcpy_fromio(op->data.buf.in, ospi->mm_base + op->addr.val, 335 op->data.nbytes); 336 return 0; 337 } 338 339 static int stm32_ospi_tx_dma(struct stm32_ospi *ospi, 340 const struct spi_mem_op *op) 341 { 342 struct dma_async_tx_descriptor *desc; 343 void __iomem *regs_base = ospi->regs_base; 344 enum dma_transfer_direction dma_dir; 345 struct dma_chan *dma_ch; 346 struct sg_table sgt; 347 dma_cookie_t cookie; 348 u32 cr, t_out; 349 int err; 350 351 if (op->data.dir == SPI_MEM_DATA_IN) { 352 dma_dir = DMA_DEV_TO_MEM; 353 dma_ch = ospi->dma_chrx; 354 } else { 355 dma_dir = DMA_MEM_TO_DEV; 356 dma_ch = ospi->dma_chtx; 357 } 358 359 /* 360 * Spi_map_buf return -EINVAL if the buffer is not DMA-able 361 * (DMA-able: in vmalloc | kmap | virt_addr_valid) 362 */ 363 err = spi_controller_dma_map_mem_op_data(ospi->ctrl, op, &sgt); 364 if (err) 365 return err; 366 367 desc = dmaengine_prep_slave_sg(dma_ch, sgt.sgl, sgt.nents, 368 dma_dir, DMA_PREP_INTERRUPT); 369 if (!desc) { 370 err = -ENOMEM; 371 goto out_unmap; 372 } 373 374 cr = readl_relaxed(regs_base + OSPI_CR); 375 376 reinit_completion(&ospi->dma_completion); 377 desc->callback = stm32_ospi_dma_callback; 378 desc->callback_param = &ospi->dma_completion; 379 cookie = dmaengine_submit(desc); 380 err = dma_submit_error(cookie); 381 if (err) 382 goto out; 383 384 dma_async_issue_pending(dma_ch); 385 386 writel_relaxed(cr | CR_DMAEN, regs_base + OSPI_CR); 387 388 t_out = sgt.nents * STM32_COMP_TIMEOUT_MS; 389 if (!wait_for_completion_timeout(&ospi->dma_completion, 390 msecs_to_jiffies(t_out))) 391 err = -ETIMEDOUT; 392 393 if (err) 394 dmaengine_terminate_all(dma_ch); 395 396 out: 397 writel_relaxed(cr & ~CR_DMAEN, regs_base + OSPI_CR); 398 out_unmap: 399 spi_controller_dma_unmap_mem_op_data(ospi->ctrl, op, &sgt); 400 401 return err; 402 } 403 404 static int stm32_ospi_xfer(struct stm32_ospi *ospi, const struct spi_mem_op *op) 405 { 406 u8 *buf; 407 408 if (!op->data.nbytes) 409 return 0; 410 411 if (ospi->fmode == CR_FMODE_MM) 412 return stm32_ospi_tx_mm(ospi, op); 413 else if (((op->data.dir == SPI_MEM_DATA_IN && ospi->dma_chrx) || 414 (op->data.dir == SPI_MEM_DATA_OUT && ospi->dma_chtx)) && 415 op->data.nbytes > 8) 416 if (!stm32_ospi_tx_dma(ospi, op)) 417 return 0; 418 419 if (op->data.dir == SPI_MEM_DATA_IN) 420 buf = op->data.buf.in; 421 else 422 buf = (void *)op->data.buf.out; 423 424 return stm32_ospi_poll(ospi, buf, op->data.nbytes, 425 op->data.dir == SPI_MEM_DATA_IN); 426 } 427 428 static int stm32_ospi_wait_poll_status(struct stm32_ospi *ospi, 429 const struct spi_mem_op *op) 430 { 431 void __iomem *regs_base = ospi->regs_base; 432 u32 cr; 433 434 reinit_completion(&ospi->match_completion); 435 cr = readl_relaxed(regs_base + OSPI_CR); 436 writel_relaxed(cr | CR_SMIE, regs_base + OSPI_CR); 437 438 if (!wait_for_completion_timeout(&ospi->match_completion, 439 msecs_to_jiffies(ospi->status_timeout))) { 440 u32 sr = readl_relaxed(regs_base + OSPI_SR); 441 442 /* Avoid false timeout */ 443 if (!(sr & SR_SMF)) 444 return -ETIMEDOUT; 445 } 446 447 writel_relaxed(FCR_CSMF, regs_base + OSPI_FCR); 448 449 return 0; 450 } 451 452 static int stm32_ospi_get_mode(u8 buswidth) 453 { 454 switch (buswidth) { 455 case 8: 456 return CCR_BUSWIDTH_8; 457 case 4: 458 return CCR_BUSWIDTH_4; 459 default: 460 return buswidth; 461 } 462 } 463 464 static int stm32_ospi_send(struct spi_device *spi, const struct spi_mem_op *op) 465 { 466 struct stm32_ospi *ospi = spi_controller_get_devdata(spi->controller); 467 void __iomem *regs_base = ospi->regs_base; 468 u32 ccr, cr, dcr2, tcr; 469 int timeout, err = 0, err_poll_status = 0; 470 u8 cs = spi->chip_select[ffs(spi->cs_index_mask) - 1]; 471 472 cr = readl_relaxed(ospi->regs_base + OSPI_CR); 473 FIELD_MODIFY(CR_CSSEL, &cr, cs); 474 475 FIELD_MODIFY(CR_FMODE_MASK, &cr, ospi->fmode); 476 writel_relaxed(cr, regs_base + OSPI_CR); 477 478 if (op->data.nbytes) 479 writel_relaxed(op->data.nbytes - 1, regs_base + OSPI_DLR); 480 481 /* set prescaler */ 482 dcr2 = readl_relaxed(regs_base + OSPI_DCR2); 483 dcr2 |= FIELD_PREP(DCR2_PRESC_MASK, ospi->flash_presc[cs]); 484 writel_relaxed(dcr2, regs_base + OSPI_DCR2); 485 486 ccr = FIELD_PREP(CCR_IMODE_MASK, stm32_ospi_get_mode(op->cmd.buswidth)); 487 488 if (op->addr.nbytes) { 489 ccr |= FIELD_PREP(CCR_ADMODE_MASK, 490 stm32_ospi_get_mode(op->addr.buswidth)); 491 ccr |= FIELD_PREP(CCR_ADSIZE_MASK, op->addr.nbytes - 1); 492 } 493 494 tcr = TCR_SSHIFT; 495 if (op->dummy.buswidth && op->dummy.nbytes) { 496 tcr |= FIELD_PREP(TCR_DCYC_MASK, 497 op->dummy.nbytes * 8 / op->dummy.buswidth); 498 } 499 writel_relaxed(tcr, regs_base + OSPI_TCR); 500 501 if (op->data.nbytes) { 502 ccr |= FIELD_PREP(CCR_DMODE_MASK, 503 stm32_ospi_get_mode(op->data.buswidth)); 504 } 505 506 writel_relaxed(ccr, regs_base + OSPI_CCR); 507 508 /* set instruction, must be set after ccr register update */ 509 writel_relaxed(op->cmd.opcode, regs_base + OSPI_IR); 510 511 if (op->addr.nbytes && ospi->fmode != CR_FMODE_MM) 512 writel_relaxed(op->addr.val, regs_base + OSPI_AR); 513 514 if (ospi->fmode == CR_FMODE_APM) 515 err_poll_status = stm32_ospi_wait_poll_status(ospi, op); 516 517 err = stm32_ospi_xfer(ospi, op); 518 519 /* 520 * Abort in: 521 * -error case 522 * -read memory map: prefetching must be stopped if we read the last 523 * byte of device (device size - fifo size). like device size is not 524 * knows, the prefetching is always stop. 525 */ 526 if (err || err_poll_status || ospi->fmode == CR_FMODE_MM) 527 goto abort; 528 529 /* Wait end of tx in indirect mode */ 530 err = stm32_ospi_wait_cmd(ospi); 531 if (err) 532 goto abort; 533 534 return 0; 535 536 abort: 537 timeout = stm32_ospi_abort(ospi); 538 writel_relaxed(FCR_CTCF | FCR_CSMF, regs_base + OSPI_FCR); 539 540 if (err || err_poll_status || timeout) 541 dev_err(ospi->dev, "%s err:%d err_poll_status:%d abort timeout:%d\n", 542 __func__, err, err_poll_status, timeout); 543 544 return err; 545 } 546 547 static int stm32_ospi_poll_status(struct spi_mem *mem, 548 const struct spi_mem_op *op, 549 u16 mask, u16 match, 550 unsigned long initial_delay_us, 551 unsigned long polling_rate_us, 552 unsigned long timeout_ms) 553 { 554 struct stm32_ospi *ospi = spi_controller_get_devdata(mem->spi->controller); 555 void __iomem *regs_base = ospi->regs_base; 556 int ret; 557 558 ret = pm_runtime_resume_and_get(ospi->dev); 559 if (ret < 0) 560 return ret; 561 562 mutex_lock(&ospi->lock); 563 564 writel_relaxed(mask, regs_base + OSPI_PSMKR); 565 writel_relaxed(match, regs_base + OSPI_PSMAR); 566 ospi->fmode = CR_FMODE_APM; 567 ospi->status_timeout = timeout_ms; 568 569 ret = stm32_ospi_send(mem->spi, op); 570 mutex_unlock(&ospi->lock); 571 572 pm_runtime_put_autosuspend(ospi->dev); 573 574 return ret; 575 } 576 577 static int stm32_ospi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) 578 { 579 struct stm32_ospi *ospi = spi_controller_get_devdata(mem->spi->controller); 580 int ret; 581 582 ret = pm_runtime_resume_and_get(ospi->dev); 583 if (ret < 0) 584 return ret; 585 586 mutex_lock(&ospi->lock); 587 if (op->data.dir == SPI_MEM_DATA_IN && op->data.nbytes) 588 ospi->fmode = CR_FMODE_INDR; 589 else 590 ospi->fmode = CR_FMODE_INDW; 591 592 ret = stm32_ospi_send(mem->spi, op); 593 mutex_unlock(&ospi->lock); 594 595 pm_runtime_put_autosuspend(ospi->dev); 596 597 return ret; 598 } 599 600 static int stm32_ospi_dirmap_create(struct spi_mem_dirmap_desc *desc) 601 { 602 struct stm32_ospi *ospi = spi_controller_get_devdata(desc->mem->spi->controller); 603 604 if (desc->info.op_tmpl->data.dir == SPI_MEM_DATA_OUT) 605 return -EOPNOTSUPP; 606 607 /* Should never happen, as mm_base == null is an error probe exit condition */ 608 if (!ospi->mm_base && desc->info.op_tmpl->data.dir == SPI_MEM_DATA_IN) 609 return -EOPNOTSUPP; 610 611 if (!ospi->mm_size) 612 return -EOPNOTSUPP; 613 614 return 0; 615 } 616 617 static ssize_t stm32_ospi_dirmap_read(struct spi_mem_dirmap_desc *desc, 618 u64 offs, size_t len, void *buf) 619 { 620 struct stm32_ospi *ospi = spi_controller_get_devdata(desc->mem->spi->controller); 621 struct spi_mem_op op; 622 u32 addr_max; 623 int ret; 624 625 ret = pm_runtime_resume_and_get(ospi->dev); 626 if (ret < 0) 627 return ret; 628 629 mutex_lock(&ospi->lock); 630 /* 631 * Make a local copy of desc op_tmpl and complete dirmap rdesc 632 * spi_mem_op template with offs, len and *buf in order to get 633 * all needed transfer information into struct spi_mem_op 634 */ 635 memcpy(&op, desc->info.op_tmpl, sizeof(struct spi_mem_op)); 636 dev_dbg(ospi->dev, "%s len = 0x%zx offs = 0x%llx buf = 0x%p\n", __func__, len, offs, buf); 637 638 op.data.nbytes = len; 639 op.addr.val = desc->info.offset + offs; 640 op.data.buf.in = buf; 641 642 addr_max = op.addr.val + op.data.nbytes + 1; 643 if (addr_max < ospi->mm_size && op.addr.buswidth) 644 ospi->fmode = CR_FMODE_MM; 645 else 646 ospi->fmode = CR_FMODE_INDR; 647 648 ret = stm32_ospi_send(desc->mem->spi, &op); 649 mutex_unlock(&ospi->lock); 650 651 pm_runtime_put_autosuspend(ospi->dev); 652 653 return ret ?: len; 654 } 655 656 static int stm32_ospi_transfer_one_message(struct spi_controller *ctrl, 657 struct spi_message *msg) 658 { 659 struct stm32_ospi *ospi = spi_controller_get_devdata(ctrl); 660 struct spi_transfer *transfer; 661 struct spi_device *spi = msg->spi; 662 struct spi_mem_op op; 663 struct gpio_desc *cs_gpiod = spi->cs_gpiod[ffs(spi->cs_index_mask) - 1]; 664 int ret = 0; 665 666 if (!cs_gpiod) 667 return -EOPNOTSUPP; 668 669 ret = pm_runtime_resume_and_get(ospi->dev); 670 if (ret < 0) 671 return ret; 672 673 mutex_lock(&ospi->lock); 674 675 gpiod_set_value_cansleep(cs_gpiod, true); 676 677 list_for_each_entry(transfer, &msg->transfers, transfer_list) { 678 u8 dummy_bytes = 0; 679 680 memset(&op, 0, sizeof(op)); 681 682 dev_dbg(ospi->dev, "tx_buf:%p tx_nbits:%d rx_buf:%p rx_nbits:%d len:%d dummy_data:%d\n", 683 transfer->tx_buf, transfer->tx_nbits, 684 transfer->rx_buf, transfer->rx_nbits, 685 transfer->len, transfer->dummy_data); 686 687 /* 688 * OSPI hardware supports dummy bytes transfer. 689 * If current transfer is dummy byte, merge it with the next 690 * transfer in order to take into account OSPI block constraint 691 */ 692 if (transfer->dummy_data) { 693 op.dummy.buswidth = transfer->tx_nbits; 694 op.dummy.nbytes = transfer->len; 695 dummy_bytes = transfer->len; 696 697 /* If happens, means that message is not correctly built */ 698 if (list_is_last(&transfer->transfer_list, &msg->transfers)) { 699 ret = -EINVAL; 700 goto end_of_transfer; 701 } 702 703 transfer = list_next_entry(transfer, transfer_list); 704 } 705 706 op.data.nbytes = transfer->len; 707 708 if (transfer->rx_buf) { 709 ospi->fmode = CR_FMODE_INDR; 710 op.data.buswidth = transfer->rx_nbits; 711 op.data.dir = SPI_MEM_DATA_IN; 712 op.data.buf.in = transfer->rx_buf; 713 } else { 714 ospi->fmode = CR_FMODE_INDW; 715 op.data.buswidth = transfer->tx_nbits; 716 op.data.dir = SPI_MEM_DATA_OUT; 717 op.data.buf.out = transfer->tx_buf; 718 } 719 720 ret = stm32_ospi_send(spi, &op); 721 if (ret) 722 goto end_of_transfer; 723 724 msg->actual_length += transfer->len + dummy_bytes; 725 } 726 727 end_of_transfer: 728 gpiod_set_value_cansleep(cs_gpiod, false); 729 730 mutex_unlock(&ospi->lock); 731 732 msg->status = ret; 733 spi_finalize_current_message(ctrl); 734 735 pm_runtime_put_autosuspend(ospi->dev); 736 737 return ret; 738 } 739 740 static int stm32_ospi_setup(struct spi_device *spi) 741 { 742 struct spi_controller *ctrl = spi->controller; 743 struct stm32_ospi *ospi = spi_controller_get_devdata(ctrl); 744 void __iomem *regs_base = ospi->regs_base; 745 int ret; 746 u8 cs = spi->chip_select[ffs(spi->cs_index_mask) - 1]; 747 748 if (ctrl->busy) 749 return -EBUSY; 750 751 if (!spi->max_speed_hz) 752 return -EINVAL; 753 754 ret = pm_runtime_resume_and_get(ospi->dev); 755 if (ret < 0) 756 return ret; 757 758 ospi->flash_presc[cs] = DIV_ROUND_UP(ospi->clk_rate, spi->max_speed_hz) - 1; 759 760 mutex_lock(&ospi->lock); 761 762 ospi->cr_reg = CR_APMS | 3 << CR_FTHRES_SHIFT | CR_EN; 763 writel_relaxed(ospi->cr_reg, regs_base + OSPI_CR); 764 765 /* set dcr fsize to max address */ 766 ospi->dcr_reg = DCR1_DEVSIZE_MASK | DCR1_DLYBYP; 767 writel_relaxed(ospi->dcr_reg, regs_base + OSPI_DCR1); 768 769 mutex_unlock(&ospi->lock); 770 771 pm_runtime_put_autosuspend(ospi->dev); 772 773 return 0; 774 } 775 776 /* 777 * No special host constraint, so use default spi_mem_default_supports_op 778 * to check supported mode. 779 */ 780 static const struct spi_controller_mem_ops stm32_ospi_mem_ops = { 781 .exec_op = stm32_ospi_exec_op, 782 .dirmap_create = stm32_ospi_dirmap_create, 783 .dirmap_read = stm32_ospi_dirmap_read, 784 .poll_status = stm32_ospi_poll_status, 785 }; 786 787 static int stm32_ospi_get_resources(struct platform_device *pdev) 788 { 789 struct device *dev = &pdev->dev; 790 struct stm32_ospi *ospi = platform_get_drvdata(pdev); 791 struct resource *res, _res; 792 int ret; 793 794 ospi->regs_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 795 if (IS_ERR(ospi->regs_base)) 796 return PTR_ERR(ospi->regs_base); 797 798 ospi->regs_phys_base = res->start; 799 800 ospi->clk = devm_clk_get(dev, NULL); 801 if (IS_ERR(ospi->clk)) 802 return dev_err_probe(dev, PTR_ERR(ospi->clk), 803 "Can't get clock\n"); 804 805 ospi->clk_rate = clk_get_rate(ospi->clk); 806 if (!ospi->clk_rate) { 807 dev_err(dev, "Invalid clock rate\n"); 808 return -EINVAL; 809 } 810 811 ospi->irq = platform_get_irq(pdev, 0); 812 if (ospi->irq < 0) 813 return ospi->irq; 814 815 ret = devm_request_irq(dev, ospi->irq, stm32_ospi_irq, 0, 816 dev_name(dev), ospi); 817 if (ret) { 818 dev_err(dev, "Failed to request irq\n"); 819 return ret; 820 } 821 822 ospi->rstc = devm_reset_control_array_get_exclusive_released(dev); 823 if (IS_ERR(ospi->rstc)) 824 return dev_err_probe(dev, PTR_ERR(ospi->rstc), 825 "Can't get reset\n"); 826 827 ospi->dma_chrx = dma_request_chan(dev, "rx"); 828 if (IS_ERR(ospi->dma_chrx)) { 829 ret = PTR_ERR(ospi->dma_chrx); 830 ospi->dma_chrx = NULL; 831 if (ret == -EPROBE_DEFER) 832 goto err_dma; 833 } 834 835 ospi->dma_chtx = dma_request_chan(dev, "tx"); 836 if (IS_ERR(ospi->dma_chtx)) { 837 ret = PTR_ERR(ospi->dma_chtx); 838 ospi->dma_chtx = NULL; 839 if (ret == -EPROBE_DEFER) 840 goto err_dma; 841 } 842 843 res = &_res; 844 ret = of_reserved_mem_region_to_resource(dev->of_node, 0, res); 845 if (!ret) { 846 ospi->mm_size = resource_size(res); 847 ospi->mm_base = devm_ioremap_resource(dev, res); 848 if (IS_ERR(ospi->mm_base)) { 849 dev_err(dev, "unable to map memory region: %pR\n", res); 850 ret = PTR_ERR(ospi->mm_base); 851 goto err_dma; 852 } 853 854 if (ospi->mm_size > STM32_OSPI_MAX_MMAP_SZ) { 855 dev_err(dev, "Memory map size outsize bounds\n"); 856 ret = -EINVAL; 857 goto err_dma; 858 } 859 } else { 860 dev_info(dev, "No memory-map region found\n"); 861 } 862 863 init_completion(&ospi->match_completion); 864 865 return 0; 866 867 err_dma: 868 dev_info(dev, "Can't get all resources (%d)\n", ret); 869 870 if (ospi->dma_chtx) 871 dma_release_channel(ospi->dma_chtx); 872 if (ospi->dma_chrx) 873 dma_release_channel(ospi->dma_chrx); 874 875 return ret; 876 }; 877 878 static int stm32_ospi_probe(struct platform_device *pdev) 879 { 880 struct device *dev = &pdev->dev; 881 struct spi_controller *ctrl; 882 struct stm32_ospi *ospi; 883 struct dma_slave_config dma_cfg; 884 struct device_node *child; 885 int ret; 886 u8 spi_flash_count = 0; 887 888 /* 889 * Flash subnodes sanity check: 890 * 1 or 2 spi-nand/spi-nor flashes => supported 891 * All other flash node configuration => not supported 892 */ 893 for_each_available_child_of_node(dev->of_node, child) { 894 if (of_device_is_compatible(child, "jedec,spi-nor") || 895 of_device_is_compatible(child, "spi-nand")) 896 spi_flash_count++; 897 } 898 899 if (spi_flash_count == 0 || spi_flash_count > 2) { 900 dev_err(dev, "Incorrect DT flash node\n"); 901 return -ENODEV; 902 } 903 904 ctrl = devm_spi_alloc_host(dev, sizeof(*ospi)); 905 if (!ctrl) 906 return -ENOMEM; 907 908 ospi = spi_controller_get_devdata(ctrl); 909 ospi->ctrl = ctrl; 910 911 ospi->dev = &pdev->dev; 912 platform_set_drvdata(pdev, ospi); 913 914 ret = stm32_ospi_get_resources(pdev); 915 if (ret) 916 return ret; 917 918 memset(&dma_cfg, 0, sizeof(dma_cfg)); 919 dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 920 dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 921 dma_cfg.src_addr = ospi->regs_phys_base + OSPI_DR; 922 dma_cfg.dst_addr = ospi->regs_phys_base + OSPI_DR; 923 ret = stm32_ospi_dma_setup(ospi, &dma_cfg); 924 if (ret) 925 goto err_dma_free; 926 927 mutex_init(&ospi->lock); 928 929 ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | 930 SPI_TX_DUAL | SPI_TX_QUAD | 931 SPI_TX_OCTAL | SPI_RX_OCTAL; 932 ctrl->flags = SPI_CONTROLLER_HALF_DUPLEX; 933 ctrl->setup = stm32_ospi_setup; 934 ctrl->bus_num = -1; 935 ctrl->mem_ops = &stm32_ospi_mem_ops; 936 ctrl->use_gpio_descriptors = true; 937 ctrl->transfer_one_message = stm32_ospi_transfer_one_message; 938 ctrl->num_chipselect = STM32_OSPI_MAX_NORCHIP; 939 940 pm_runtime_enable(ospi->dev); 941 pm_runtime_set_autosuspend_delay(ospi->dev, STM32_AUTOSUSPEND_DELAY); 942 pm_runtime_use_autosuspend(ospi->dev); 943 944 ret = pm_runtime_resume_and_get(ospi->dev); 945 if (ret < 0) 946 goto err_pm_enable; 947 948 ret = reset_control_acquire(ospi->rstc); 949 if (ret) { 950 dev_err_probe(dev, ret, "Can not acquire reset %d\n", ret); 951 goto err_pm_resume; 952 } 953 954 reset_control_assert(ospi->rstc); 955 udelay(2); 956 reset_control_deassert(ospi->rstc); 957 958 ret = spi_register_controller(ctrl); 959 if (ret) { 960 /* Disable ospi */ 961 writel_relaxed(0, ospi->regs_base + OSPI_CR); 962 goto err_reset_control; 963 } 964 965 pm_runtime_put_autosuspend(ospi->dev); 966 967 return 0; 968 969 err_reset_control: 970 reset_control_release(ospi->rstc); 971 err_pm_resume: 972 pm_runtime_put_sync_suspend(ospi->dev); 973 974 err_pm_enable: 975 pm_runtime_force_suspend(ospi->dev); 976 mutex_destroy(&ospi->lock); 977 err_dma_free: 978 if (ospi->dma_chtx) 979 dma_release_channel(ospi->dma_chtx); 980 if (ospi->dma_chrx) 981 dma_release_channel(ospi->dma_chrx); 982 983 return ret; 984 } 985 986 static void stm32_ospi_remove(struct platform_device *pdev) 987 { 988 struct stm32_ospi *ospi = platform_get_drvdata(pdev); 989 990 pm_runtime_resume_and_get(ospi->dev); 991 992 spi_unregister_controller(ospi->ctrl); 993 /* Disable ospi */ 994 writel_relaxed(0, ospi->regs_base + OSPI_CR); 995 mutex_destroy(&ospi->lock); 996 997 if (ospi->dma_chtx) 998 dma_release_channel(ospi->dma_chtx); 999 if (ospi->dma_chrx) 1000 dma_release_channel(ospi->dma_chrx); 1001 1002 reset_control_release(ospi->rstc); 1003 1004 pm_runtime_put_sync_suspend(ospi->dev); 1005 pm_runtime_force_suspend(ospi->dev); 1006 } 1007 1008 static int stm32_ospi_suspend(struct device *dev) 1009 { 1010 struct stm32_ospi *ospi = dev_get_drvdata(dev); 1011 1012 pinctrl_pm_select_sleep_state(dev); 1013 1014 reset_control_release(ospi->rstc); 1015 1016 return pm_runtime_force_suspend(ospi->dev); 1017 } 1018 1019 static int stm32_ospi_resume(struct device *dev) 1020 { 1021 struct stm32_ospi *ospi = dev_get_drvdata(dev); 1022 void __iomem *regs_base = ospi->regs_base; 1023 int ret; 1024 1025 ret = pm_runtime_force_resume(ospi->dev); 1026 if (ret < 0) 1027 return ret; 1028 1029 pinctrl_pm_select_default_state(dev); 1030 1031 ret = pm_runtime_resume_and_get(ospi->dev); 1032 if (ret < 0) 1033 return ret; 1034 1035 ret = reset_control_acquire(ospi->rstc); 1036 if (ret) { 1037 dev_err(dev, "Can not acquire reset\n"); 1038 return ret; 1039 } 1040 1041 writel_relaxed(ospi->cr_reg, regs_base + OSPI_CR); 1042 writel_relaxed(ospi->dcr_reg, regs_base + OSPI_DCR1); 1043 pm_runtime_put_autosuspend(ospi->dev); 1044 1045 return 0; 1046 } 1047 1048 static int stm32_ospi_runtime_suspend(struct device *dev) 1049 { 1050 struct stm32_ospi *ospi = dev_get_drvdata(dev); 1051 1052 clk_disable_unprepare(ospi->clk); 1053 1054 return 0; 1055 } 1056 1057 static int stm32_ospi_runtime_resume(struct device *dev) 1058 { 1059 struct stm32_ospi *ospi = dev_get_drvdata(dev); 1060 1061 return clk_prepare_enable(ospi->clk); 1062 } 1063 1064 static const struct dev_pm_ops stm32_ospi_pm_ops = { 1065 SYSTEM_SLEEP_PM_OPS(stm32_ospi_suspend, stm32_ospi_resume) 1066 RUNTIME_PM_OPS(stm32_ospi_runtime_suspend, stm32_ospi_runtime_resume, NULL) 1067 }; 1068 1069 static const struct of_device_id stm32_ospi_of_match[] = { 1070 { .compatible = "st,stm32mp25-ospi" }, 1071 {}, 1072 }; 1073 MODULE_DEVICE_TABLE(of, stm32_ospi_of_match); 1074 1075 static struct platform_driver stm32_ospi_driver = { 1076 .probe = stm32_ospi_probe, 1077 .remove = stm32_ospi_remove, 1078 .driver = { 1079 .name = "stm32-ospi", 1080 .pm = pm_ptr(&stm32_ospi_pm_ops), 1081 .of_match_table = stm32_ospi_of_match, 1082 }, 1083 }; 1084 module_platform_driver(stm32_ospi_driver); 1085 1086 MODULE_DESCRIPTION("STMicroelectronics STM32 OCTO SPI driver"); 1087 MODULE_LICENSE("GPL"); 1088