xref: /linux/drivers/net/ethernet/freescale/fs_enet/fs_enet.h (revision 9410645520e9b820069761f3450ef6661418e279)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef FS_ENET_H
3 #define FS_ENET_H
4 
5 #include <linux/clk.h>
6 #include <linux/netdevice.h>
7 #include <linux/types.h>
8 #include <linux/list.h>
9 #include <linux/phy.h>
10 #include <linux/phylink.h>
11 #include <linux/dma-mapping.h>
12 
13 #ifdef CONFIG_CPM1
14 #include <asm/cpm1.h>
15 #endif
16 
17 #if defined(CONFIG_FS_ENET_HAS_FEC)
18 #include <asm/cpm.h>
19 
20 #if defined(CONFIG_FS_ENET_MPC5121_FEC)
21 /* MPC5121 FEC has different register layout */
22 struct fec {
23 	u32 fec_reserved0;
24 	u32 fec_ievent;			/* Interrupt event reg */
25 	u32 fec_imask;			/* Interrupt mask reg */
26 	u32 fec_reserved1;
27 	u32 fec_r_des_active;		/* Receive descriptor reg */
28 	u32 fec_x_des_active;		/* Transmit descriptor reg */
29 	u32 fec_reserved2[3];
30 	u32 fec_ecntrl;			/* Ethernet control reg */
31 	u32 fec_reserved3[6];
32 	u32 fec_mii_data;		/* MII manage frame reg */
33 	u32 fec_mii_speed;		/* MII speed control reg */
34 	u32 fec_reserved4[7];
35 	u32 fec_mib_ctrlstat;		/* MIB control/status reg */
36 	u32 fec_reserved5[7];
37 	u32 fec_r_cntrl;		/* Receive control reg */
38 	u32 fec_reserved6[15];
39 	u32 fec_x_cntrl;		/* Transmit Control reg */
40 	u32 fec_reserved7[7];
41 	u32 fec_addr_low;		/* Low 32bits MAC address */
42 	u32 fec_addr_high;		/* High 16bits MAC address */
43 	u32 fec_opd;			/* Opcode + Pause duration */
44 	u32 fec_reserved8[10];
45 	u32 fec_hash_table_high;	/* High 32bits hash table */
46 	u32 fec_hash_table_low;		/* Low 32bits hash table */
47 	u32 fec_grp_hash_table_high;	/* High 32bits hash table */
48 	u32 fec_grp_hash_table_low;	/* Low 32bits hash table */
49 	u32 fec_reserved9[7];
50 	u32 fec_x_wmrk;			/* FIFO transmit water mark */
51 	u32 fec_reserved10;
52 	u32 fec_r_bound;		/* FIFO receive bound reg */
53 	u32 fec_r_fstart;		/* FIFO receive start reg */
54 	u32 fec_reserved11[11];
55 	u32 fec_r_des_start;		/* Receive descriptor ring */
56 	u32 fec_x_des_start;		/* Transmit descriptor ring */
57 	u32 fec_r_buff_size;		/* Maximum receive buff size */
58 	u32 fec_reserved12[26];
59 	u32 fec_dma_control;		/* DMA Endian and other ctrl */
60 };
61 #endif
62 
63 struct fec_info {
64 	struct fec __iomem *fecp;
65 	u32 mii_speed;
66 };
67 #endif
68 
69 #ifdef CONFIG_CPM2
70 #include <asm/cpm2.h>
71 #endif
72 
73 /* hw driver ops */
74 struct fs_ops {
75 	int (*setup_data)(struct net_device *dev);
76 	int (*allocate_bd)(struct net_device *dev);
77 	void (*free_bd)(struct net_device *dev);
78 	void (*cleanup_data)(struct net_device *dev);
79 	void (*set_multicast_list)(struct net_device *dev);
80 	void (*restart)(struct net_device *dev, phy_interface_t interface,
81 			int speed, int duplex);
82 	void (*stop)(struct net_device *dev);
83 	void (*napi_clear_event)(struct net_device *dev);
84 	void (*napi_enable)(struct net_device *dev);
85 	void (*napi_disable)(struct net_device *dev);
86 	void (*rx_bd_done)(struct net_device *dev);
87 	void (*tx_kickstart)(struct net_device *dev);
88 	u32 (*get_int_events)(struct net_device *dev);
89 	void (*clear_int_events)(struct net_device *dev, u32 int_events);
90 	void (*ev_error)(struct net_device *dev, u32 int_events);
91 	int (*get_regs)(struct net_device *dev, void *p, int *sizep);
92 	int (*get_regs_len)(struct net_device *dev);
93 	void (*tx_restart)(struct net_device *dev);
94 };
95 
96 /* The FEC stores dest/src/type, data, and checksum for receive packets.
97  */
98 #define MAX_MTU 1508		/* Allow fullsized pppoe packets over VLAN */
99 #define MIN_MTU 46		/* this is data size */
100 #define CRC_LEN 4
101 
102 #define PKT_MAXBUF_SIZE		(MAX_MTU+ETH_HLEN+CRC_LEN)
103 #define PKT_MINBUF_SIZE		(MIN_MTU+ETH_HLEN+CRC_LEN)
104 
105 /* Must be a multiple of 32 (to cover both FEC & FCC) */
106 #define PKT_MAXBLR_SIZE		((PKT_MAXBUF_SIZE + 31) & ~31)
107 /* This is needed so that invalidate_xxx wont invalidate too much */
108 #define ENET_RX_ALIGN  16
109 #define ENET_RX_FRSIZE L1_CACHE_ALIGN(PKT_MAXBUF_SIZE + ENET_RX_ALIGN - 1)
110 
111 struct fs_platform_info {
112 	/* device specific information */
113 	u32 cp_command;		/* CPM page/sblock/mcn */
114 
115 	u32 dpram_offset;
116 
117 	int rx_ring, tx_ring;	/* number of buffers on rx	*/
118 	int rx_copybreak;	/* limit we copy small frames	*/
119 	int napi_weight;	/* NAPI weight			*/
120 };
121 
122 struct fs_enet_private {
123 	struct napi_struct napi;
124 	struct device *dev;	/* pointer back to the device (must be initialized first) */
125 	struct net_device *ndev;
126 	spinlock_t lock;	/* during all ops except TX pckt processing */
127 	spinlock_t tx_lock;	/* during fs_start_xmit and fs_tx         */
128 	struct fs_platform_info *fpi;
129 	struct work_struct timeout_work;
130 	const struct fs_ops *ops;
131 	int rx_ring, tx_ring;
132 	dma_addr_t ring_mem_addr;
133 	void __iomem *ring_base;
134 	struct sk_buff **rx_skbuff;
135 	struct sk_buff **tx_skbuff;
136 	char *mapped_as_page;
137 	cbd_t __iomem *rx_bd_base;	/* Address of Rx and Tx buffers.    */
138 	cbd_t __iomem *tx_bd_base;
139 	cbd_t __iomem *dirty_tx;	/* ring entries to be free()ed.     */
140 	cbd_t __iomem *cur_rx;
141 	cbd_t __iomem *cur_tx;
142 	int tx_free;
143 	u32 msg_enable;
144 	struct phylink *phylink;
145 	struct phylink_config phylink_config;
146 	int interrupt;
147 
148 	/* event masks */
149 	u32 ev_napi;		/* mask of NAPI events */
150 	u32 ev;			/* event mask          */
151 	u32 ev_err;		/* error event mask       */
152 
153 	u16 bd_rx_empty;	/* mask of BD rx empty	  */
154 	u16 bd_rx_err;		/* mask of BD rx errors   */
155 
156 	union {
157 		struct {
158 			int idx;		/* FEC1 = 0, FEC2 = 1  */
159 			void __iomem *fecp;	/* hw registers        */
160 			u32 hthi, htlo;		/* state for multicast */
161 		} fec;
162 
163 		struct {
164 			int idx;		/* FCC1-3 = 0-2	       */
165 			void __iomem *fccp;	/* hw registers	       */
166 			void __iomem *ep;	/* parameter ram       */
167 			void __iomem *fcccp;	/* hw registers cont.  */
168 			void __iomem *mem;	/* FCC DPRAM */
169 			u32 gaddrh, gaddrl;	/* group address       */
170 		} fcc;
171 
172 		struct {
173 			int idx;		/* FEC1 = 0, FEC2 = 1  */
174 			void __iomem *sccp;	/* hw registers        */
175 			void __iomem *ep;	/* parameter ram       */
176 			u32 hthi, htlo;		/* state for multicast */
177 		} scc;
178 
179 	};
180 };
181 
182 /***************************************************************************/
183 
184 void fs_init_bds(struct net_device *dev);
185 void fs_cleanup_bds(struct net_device *dev);
186 
187 /***************************************************************************/
188 
189 #define DRV_MODULE_NAME		"fs_enet"
190 #define PFX DRV_MODULE_NAME	": "
191 
192 /***************************************************************************/
193 /* buffer descriptor access macros */
194 
195 /* access macros */
196 #if defined(CONFIG_CPM1)
197 /* for a CPM1 __raw_xxx's are sufficient */
198 #define __cbd_out32(addr, x)	__raw_writel(x, addr)
199 #define __cbd_out16(addr, x)	__raw_writew(x, addr)
200 #define __cbd_in32(addr)	__raw_readl(addr)
201 #define __cbd_in16(addr)	__raw_readw(addr)
202 #else
203 /* for others play it safe */
204 #define __cbd_out32(addr, x)	out_be32(addr, x)
205 #define __cbd_out16(addr, x)	out_be16(addr, x)
206 #define __cbd_in32(addr)	in_be32(addr)
207 #define __cbd_in16(addr)	in_be16(addr)
208 #endif
209 
210 /* write */
211 #define CBDW_SC(_cbd, _sc) 		__cbd_out16(&(_cbd)->cbd_sc, (_sc))
212 #define CBDW_DATLEN(_cbd, _datlen)	__cbd_out16(&(_cbd)->cbd_datlen, (_datlen))
213 #define CBDW_BUFADDR(_cbd, _bufaddr)	__cbd_out32(&(_cbd)->cbd_bufaddr, (_bufaddr))
214 
215 /* read */
216 #define CBDR_SC(_cbd) 			__cbd_in16(&(_cbd)->cbd_sc)
217 #define CBDR_DATLEN(_cbd)		__cbd_in16(&(_cbd)->cbd_datlen)
218 #define CBDR_BUFADDR(_cbd)		__cbd_in32(&(_cbd)->cbd_bufaddr)
219 
220 /* set bits */
221 #define CBDS_SC(_cbd, _sc) 		CBDW_SC(_cbd, CBDR_SC(_cbd) | (_sc))
222 
223 /* clear bits */
224 #define CBDC_SC(_cbd, _sc) 		CBDW_SC(_cbd, CBDR_SC(_cbd) & ~(_sc))
225 
226 /*******************************************************************/
227 
228 extern const struct fs_ops fs_fec_ops;
229 extern const struct fs_ops fs_fcc_ops;
230 extern const struct fs_ops fs_scc_ops;
231 
232 /*******************************************************************/
233 
234 #endif
235