1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2018-2024 Linaro Ltd. 5 */ 6 #ifndef _IPA_REG_H_ 7 #define _IPA_REG_H_ 8 9 #include "reg.h" 10 11 struct platform_device; 12 13 struct ipa; 14 15 /** 16 * DOC: IPA Registers 17 * 18 * IPA registers are located within the "ipa-reg" address space defined by 19 * Device Tree. Each register has a specified offset within that space, 20 * which is mapped into virtual memory space in ipa_mem_init(). Each 21 * has a unique identifer, taken from the ipa_reg_id enumerated type. 22 * All IPA registers are 32 bits wide. 23 * 24 * Certain "parameterized" register types are duplicated for a number of 25 * instances of something. For example, each IPA endpoint has an set of 26 * registers defining its configuration. The offset to an endpoint's set 27 * of registers is computed based on an "base" offset, plus an endpoint's 28 * ID multiplied and a "stride" value for the register. Similarly, some 29 * registers have an offset that depends on execution environment. In 30 * this case, the stride is multiplied by a member of the gsi_ee_id 31 * enumerated type. 32 * 33 * Each version of IPA implements an array of ipa_reg structures indexed 34 * by register ID. Each entry in the array specifies the base offset and 35 * (for parameterized registers) a non-zero stride value. Not all versions 36 * of IPA define all registers. The offset for a register is returned by 37 * reg_offset() when the register's ipa_reg structure is supplied; 38 * zero is returned for an undefined register (this should never happen). 39 * 40 * Some registers encode multiple fields within them. Each field in 41 * such a register has a unique identifier (from an enumerated type). 42 * The position and width of the fields in a register are defined by 43 * an array of field masks, indexed by field ID. Two functions are 44 * used to access register fields; both take an ipa_reg structure as 45 * argument. To encode a value to be represented in a register field, 46 * the value and field ID are passed to reg_encode(). To extract 47 * a value encoded in a register field, the field ID is passed to 48 * reg_decode(). In addition, for single-bit fields, reg_bit() 49 * can be used to either encode the bit value, or to generate a mask 50 * used to extract the bit value. 51 */ 52 53 /* enum ipa_reg_id - IPA register IDs */ 54 enum ipa_reg_id { 55 COMP_CFG, 56 CLKON_CFG, 57 ROUTE, 58 SHARED_MEM_SIZE, 59 QSB_MAX_WRITES, 60 QSB_MAX_READS, 61 FILT_ROUT_HASH_EN, /* IPA v4.2 */ 62 FILT_ROUT_HASH_FLUSH, /* Not IPA v4.2 nor IPA v5.0+ */ 63 FILT_ROUT_CACHE_FLUSH, /* IPA v5.0+ */ 64 STATE_AGGR_ACTIVE, 65 IPA_BCR, /* Not IPA v4.5+ */ 66 LOCAL_PKT_PROC_CNTXT, 67 AGGR_FORCE_CLOSE, 68 COUNTER_CFG, /* Not IPA v4.5+ */ 69 IPA_TX_CFG, /* IPA v3.5+ */ 70 FLAVOR_0, /* IPA v3.5+ */ 71 IDLE_INDICATION_CFG, /* IPA v3.5+ */ 72 QTIME_TIMESTAMP_CFG, /* IPA v4.5+ */ 73 TIMERS_XO_CLK_DIV_CFG, /* IPA v4.5+ */ 74 TIMERS_PULSE_GRAN_CFG, /* IPA v4.5+ */ 75 SRC_RSRC_GRP_01_RSRC_TYPE, 76 SRC_RSRC_GRP_23_RSRC_TYPE, 77 SRC_RSRC_GRP_45_RSRC_TYPE, /* Not IPA v3.5+; IPA v4.5, IPA v5.0 */ 78 SRC_RSRC_GRP_67_RSRC_TYPE, /* Not IPA v3.5+; IPA v5.0 */ 79 DST_RSRC_GRP_01_RSRC_TYPE, 80 DST_RSRC_GRP_23_RSRC_TYPE, 81 DST_RSRC_GRP_45_RSRC_TYPE, /* Not IPA v3.5+; IPA v4.5, IPA v5.0 */ 82 DST_RSRC_GRP_67_RSRC_TYPE, /* Not IPA v3.5+; IPA v5.0 */ 83 ENDP_INIT_CTRL, /* Not IPA v4.2+ for TX, not IPA v4.0+ for RX */ 84 ENDP_INIT_CFG, 85 ENDP_INIT_NAT, /* TX only */ 86 ENDP_INIT_HDR, 87 ENDP_INIT_HDR_EXT, 88 ENDP_INIT_HDR_METADATA_MASK, /* RX only */ 89 ENDP_INIT_MODE, /* TX only */ 90 ENDP_INIT_AGGR, 91 ENDP_INIT_HOL_BLOCK_EN, /* RX only */ 92 ENDP_INIT_HOL_BLOCK_TIMER, /* RX only */ 93 ENDP_INIT_DEAGGR, /* TX only */ 94 ENDP_INIT_RSRC_GRP, 95 ENDP_INIT_SEQ, /* TX only */ 96 ENDP_STATUS, 97 ENDP_FILTER_ROUTER_HSH_CFG, /* Not IPA v4.2 */ 98 ENDP_FILTER_CACHE_CFG, /* IPA v5.0+ */ 99 ENDP_ROUTER_CACHE_CFG, /* IPA v5.0+ */ 100 /* The IRQ registers that follow are only used for GSI_EE_AP */ 101 IPA_IRQ_STTS, 102 IPA_IRQ_EN, 103 IPA_IRQ_CLR, 104 IPA_IRQ_UC, 105 IRQ_SUSPEND_INFO, 106 IRQ_SUSPEND_EN, /* IPA v3.1+ */ 107 IRQ_SUSPEND_CLR, /* IPA v3.1+ */ 108 IPA_REG_ID_COUNT, /* Last; not an ID */ 109 }; 110 111 /* COMP_CFG register */ 112 enum ipa_reg_comp_cfg_field_id { 113 COMP_CFG_ENABLE, /* Not IPA v4.0+ */ 114 RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS, /* IPA v4.7+ */ 115 GSI_SNOC_BYPASS_DIS, 116 GEN_QMB_0_SNOC_BYPASS_DIS, 117 GEN_QMB_1_SNOC_BYPASS_DIS, 118 IPA_DCMP_FAST_CLK_EN, /* Not IPA v4.5+ */ 119 IPA_QMB_SELECT_CONS_EN, /* IPA v4.0+ */ 120 IPA_QMB_SELECT_PROD_EN, /* IPA v4.0+ */ 121 GSI_MULTI_INORDER_RD_DIS, /* IPA v4.0+ */ 122 GSI_MULTI_INORDER_WR_DIS, /* IPA v4.0+ */ 123 GEN_QMB_0_MULTI_INORDER_RD_DIS, /* IPA v4.0+ */ 124 GEN_QMB_1_MULTI_INORDER_RD_DIS, /* IPA v4.0+ */ 125 GEN_QMB_0_MULTI_INORDER_WR_DIS, /* IPA v4.0+ */ 126 GEN_QMB_1_MULTI_INORDER_WR_DIS, /* IPA v4.0+ */ 127 GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS, /* IPA v4.0+ */ 128 GSI_SNOC_CNOC_LOOP_PROT_DISABLE, /* IPA v4.0+ */ 129 GSI_MULTI_AXI_MASTERS_DIS, /* IPA v4.0+ */ 130 IPA_QMB_SELECT_GLOBAL_EN, /* IPA v4.0+ */ 131 QMB_RAM_RD_CACHE_DISABLE, /* IPA v4.9+ */ 132 GENQMB_AOOOWR, /* IPA v4.9+ */ 133 IF_OUT_OF_BUF_STOP_RESET_MASK_EN, /* IPA v4.9+ */ 134 GEN_QMB_1_DYNAMIC_ASIZE, /* IPA v4.9+ */ 135 GEN_QMB_0_DYNAMIC_ASIZE, /* IPA v4.9+ */ 136 ATOMIC_FETCHER_ARB_LOCK_DIS, /* IPA v4.0+ */ 137 FULL_FLUSH_WAIT_RS_CLOSURE_EN, /* IPA v4.5+ */ 138 }; 139 140 /* CLKON_CFG register */ 141 enum ipa_reg_clkon_cfg_field_id { 142 CLKON_RX, 143 CLKON_PROC, 144 TX_WRAPPER, 145 CLKON_MISC, 146 RAM_ARB, 147 FTCH_HPS, 148 FTCH_DPS, 149 CLKON_HPS, 150 CLKON_DPS, 151 RX_HPS_CMDQS, 152 HPS_DPS_CMDQS, 153 DPS_TX_CMDQS, 154 RSRC_MNGR, 155 CTX_HANDLER, 156 ACK_MNGR, 157 D_DCPH, 158 H_DCPH, 159 CLKON_DCMP, /* IPA v4.5+ */ 160 NTF_TX_CMDQS, /* IPA v3.5+ */ 161 CLKON_TX_0, /* IPA v3.5+ */ 162 CLKON_TX_1, /* IPA v3.5+ */ 163 CLKON_FNR, /* IPA v3.5.1+ */ 164 QSB2AXI_CMDQ_L, /* IPA v4.0+ */ 165 AGGR_WRAPPER, /* IPA v4.0+ */ 166 RAM_SLAVEWAY, /* IPA v4.0+ */ 167 CLKON_QMB, /* IPA v4.0+ */ 168 WEIGHT_ARB, /* IPA v4.0+ */ 169 GSI_IF, /* IPA v4.0+ */ 170 CLKON_GLOBAL, /* IPA v4.0+ */ 171 GLOBAL_2X_CLK, /* IPA v4.0+ */ 172 DPL_FIFO, /* IPA v4.5+ */ 173 DRBIP, /* IPA v4.7+ */ 174 }; 175 176 /* ROUTE register */ 177 enum ipa_reg_route_field_id { 178 ROUTE_DIS, 179 ROUTE_DEF_PIPE, 180 ROUTE_DEF_HDR_TABLE, 181 ROUTE_DEF_HDR_OFST, 182 ROUTE_FRAG_DEF_PIPE, 183 ROUTE_DEF_RETAIN_HDR, 184 }; 185 186 /* SHARED_MEM_SIZE register */ 187 enum ipa_reg_shared_mem_size_field_id { 188 MEM_SIZE, 189 MEM_BADDR, 190 }; 191 192 /* QSB_MAX_WRITES register */ 193 enum ipa_reg_qsb_max_writes_field_id { 194 GEN_QMB_0_MAX_WRITES, 195 GEN_QMB_1_MAX_WRITES, 196 }; 197 198 /* QSB_MAX_READS register */ 199 enum ipa_reg_qsb_max_reads_field_id { 200 GEN_QMB_0_MAX_READS, 201 GEN_QMB_1_MAX_READS, 202 GEN_QMB_0_MAX_READS_BEATS, /* IPA v4.0+ */ 203 GEN_QMB_1_MAX_READS_BEATS, /* IPA v4.0+ */ 204 }; 205 206 /* FILT_ROUT_HASH_EN and FILT_ROUT_HASH_FLUSH registers */ 207 enum ipa_reg_filt_rout_hash_field_id { 208 IPV6_ROUTER_HASH, 209 IPV6_FILTER_HASH, 210 IPV4_ROUTER_HASH, 211 IPV4_FILTER_HASH, 212 }; 213 214 /* FILT_ROUT_CACHE_FLUSH register */ 215 enum ipa_reg_filt_rout_cache_field_id { 216 ROUTER_CACHE, 217 FILTER_CACHE, 218 }; 219 220 /* BCR register */ 221 enum ipa_bcr_compat { 222 BCR_CMDQ_L_LACK_ONE_ENTRY = 0x0, /* Not IPA v4.2+ */ 223 BCR_TX_NOT_USING_BRESP = 0x1, /* Not IPA v4.2+ */ 224 BCR_TX_SUSPEND_IRQ_ASSERT_ONCE = 0x2, /* Not IPA v4.0+ */ 225 BCR_SUSPEND_L2_IRQ = 0x3, /* Not IPA v4.2+ */ 226 BCR_HOLB_DROP_L2_IRQ = 0x4, /* Not IPA v4.2+ */ 227 BCR_DUAL_TX = 0x5, /* IPA v3.5+ */ 228 BCR_ENABLE_FILTER_DATA_CACHE = 0x6, /* IPA v3.5+ */ 229 BCR_NOTIF_PRIORITY_OVER_ZLT = 0x7, /* IPA v3.5+ */ 230 BCR_FILTER_PREFETCH_EN = 0x8, /* IPA v3.5+ */ 231 BCR_ROUTER_PREFETCH_EN = 0x9, /* IPA v3.5+ */ 232 }; 233 234 /* LOCAL_PKT_PROC_CNTXT register */ 235 enum ipa_reg_local_pkt_proc_cntxt_field_id { 236 IPA_BASE_ADDR, 237 }; 238 239 /* COUNTER_CFG register */ 240 enum ipa_reg_counter_cfg_field_id { 241 EOT_COAL_GRANULARITY, /* Not IPA v3.5+ */ 242 AGGR_GRANULARITY, 243 }; 244 245 /* IPA_TX_CFG register */ 246 enum ipa_reg_ipa_tx_cfg_field_id { 247 TX0_PREFETCH_DISABLE, /* Not IPA v4.0+ */ 248 TX1_PREFETCH_DISABLE, /* Not IPA v4.0+ */ 249 PREFETCH_ALMOST_EMPTY_SIZE, /* Not IPA v4.0+ */ 250 PREFETCH_ALMOST_EMPTY_SIZE_TX0, /* IPA v4.0+ */ 251 DMAW_SCND_OUTSD_PRED_THRESHOLD, /* IPA v4.0+ */ 252 DMAW_SCND_OUTSD_PRED_EN, /* IPA v4.0+ */ 253 DMAW_MAX_BEATS_256_DIS, /* IPA v4.0+ */ 254 PA_MASK_EN, /* IPA v4.0+ */ 255 PREFETCH_ALMOST_EMPTY_SIZE_TX1, /* IPA v4.0+ */ 256 DUAL_TX_ENABLE, /* IPA v4.5+ */ 257 SSPND_PA_NO_START_STATE, /* IPA v4,2+, not IPA v4.5 */ 258 SSPND_PA_NO_BQ_STATE, /* IPA v4.2 only */ 259 HOLB_STICKY_DROP_EN, /* IPA v5.0+ */ 260 }; 261 262 /* FLAVOR_0 register */ 263 enum ipa_reg_flavor_0_field_id { 264 MAX_PIPES, 265 MAX_CONS_PIPES, 266 MAX_PROD_PIPES, 267 PROD_LOWEST, 268 }; 269 270 /* IDLE_INDICATION_CFG register */ 271 enum ipa_reg_idle_indication_cfg_field_id { 272 ENTER_IDLE_DEBOUNCE_THRESH, 273 CONST_NON_IDLE_ENABLE, 274 }; 275 276 /* QTIME_TIMESTAMP_CFG register */ 277 enum ipa_reg_qtime_timestamp_cfg_field_id { 278 DPL_TIMESTAMP_LSB, /* Not IPA v5.5+ */ 279 DPL_TIMESTAMP_SEL, /* Not IPA v5.5+ */ 280 TAG_TIMESTAMP_LSB, 281 NAT_TIMESTAMP_LSB, 282 }; 283 284 /* TIMERS_XO_CLK_DIV_CFG register */ 285 enum ipa_reg_timers_xo_clk_div_cfg_field_id { 286 DIV_VALUE, 287 DIV_ENABLE, 288 }; 289 290 /* TIMERS_PULSE_GRAN_CFG register */ 291 enum ipa_reg_timers_pulse_gran_cfg_field_id { 292 PULSE_GRAN_0, 293 PULSE_GRAN_1, 294 PULSE_GRAN_2, 295 PULSE_GRAN_3, 296 }; 297 298 /* Values for IPA_GRAN_x fields of TIMERS_PULSE_GRAN_CFG */ 299 enum ipa_pulse_gran { 300 IPA_GRAN_10_US = 0x0, 301 IPA_GRAN_20_US = 0x1, 302 IPA_GRAN_50_US = 0x2, 303 IPA_GRAN_100_US = 0x3, 304 IPA_GRAN_1_MS = 0x4, 305 IPA_GRAN_10_MS = 0x5, 306 IPA_GRAN_100_MS = 0x6, 307 IPA_GRAN_655350_US = 0x7, 308 }; 309 310 /* {SRC,DST}_RSRC_GRP_{01,23,45,67}_RSRC_TYPE registers */ 311 enum ipa_reg_rsrc_grp_rsrc_type_field_id { 312 X_MIN_LIM, 313 X_MAX_LIM, 314 Y_MIN_LIM, 315 Y_MAX_LIM, 316 }; 317 318 /* ENDP_INIT_CTRL register */ 319 enum ipa_reg_endp_init_ctrl_field_id { 320 ENDP_SUSPEND, /* Not IPA v4.0+ */ 321 ENDP_DELAY, /* Not IPA v4.2+ */ 322 }; 323 324 /* ENDP_INIT_CFG register */ 325 enum ipa_reg_endp_init_cfg_field_id { 326 FRAG_OFFLOAD_EN, 327 CS_OFFLOAD_EN, 328 CS_METADATA_HDR_OFFSET, 329 CS_GEN_QMB_MASTER_SEL, 330 PIPE_REPLICATE_EN, /* IPA v5.5+ */ 331 }; 332 333 /** enum ipa_cs_offload_en - ENDP_INIT_CFG register CS_OFFLOAD_EN field value */ 334 enum ipa_cs_offload_en { 335 IPA_CS_OFFLOAD_NONE = 0x0, 336 IPA_CS_OFFLOAD_UL /* TX */ = 0x1, /* Not IPA v4.5+ */ 337 IPA_CS_OFFLOAD_DL /* RX */ = 0x2, /* Not IPA v4.5+ */ 338 IPA_CS_OFFLOAD_INLINE /* TX and RX */ = 0x1, /* IPA v4.5+ */ 339 }; 340 341 /* ENDP_INIT_NAT register */ 342 enum ipa_reg_endp_init_nat_field_id { 343 NAT_EN, 344 }; 345 346 /** enum ipa_nat_type - ENDP_INIT_NAT register NAT_EN field value */ 347 enum ipa_nat_type { 348 IPA_NAT_TYPE_BYPASS = 0, 349 IPA_NAT_TYPE_SRC = 1, 350 IPA_NAT_TYPE_DST = 2, 351 }; 352 353 /* ENDP_INIT_HDR register */ 354 enum ipa_reg_endp_init_hdr_field_id { 355 HDR_LEN, 356 HDR_OFST_METADATA_VALID, 357 HDR_OFST_METADATA, 358 HDR_ADDITIONAL_CONST_LEN, 359 HDR_OFST_PKT_SIZE_VALID, 360 HDR_OFST_PKT_SIZE, 361 HDR_A5_MUX, /* Not IPA v4.9+ */ 362 HDR_LEN_INC_DEAGG_HDR, 363 HDR_METADATA_REG_VALID, /* Not IPA v4.5+ */ 364 HDR_LEN_MSB, /* IPA v4.5+ */ 365 HDR_OFST_METADATA_MSB, /* IPA v4.5+ */ 366 }; 367 368 /* ENDP_INIT_HDR_EXT register */ 369 enum ipa_reg_endp_init_hdr_ext_field_id { 370 HDR_ENDIANNESS, 371 HDR_TOTAL_LEN_OR_PAD_VALID, 372 HDR_TOTAL_LEN_OR_PAD, 373 HDR_PAYLOAD_LEN_INC_PADDING, 374 HDR_TOTAL_LEN_OR_PAD_OFFSET, 375 HDR_PAD_TO_ALIGNMENT, 376 HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB, /* IPA v4.5+ */ 377 HDR_OFST_PKT_SIZE_MSB, /* IPA v4.5+ */ 378 HDR_ADDITIONAL_CONST_LEN_MSB, /* IPA v4.5+ */ 379 HDR_BYTES_TO_REMOVE_VALID, /* IPA v5.0+ */ 380 HDR_BYTES_TO_REMOVE, /* IPA v5.0+ */ 381 }; 382 383 /* ENDP_INIT_MODE register */ 384 enum ipa_reg_endp_init_mode_field_id { 385 ENDP_MODE, 386 DCPH_ENABLE, /* IPA v4.5+ */ 387 DEST_PIPE_INDEX, 388 BYTE_THRESHOLD, 389 PIPE_REPLICATION_EN, /* Not IPA v5.5+ */ 390 PAD_EN, 391 HDR_FTCH_DISABLE, /* IPA v4.5+ */ 392 DRBIP_ACL_ENABLE, /* IPA v4.9+ */ 393 }; 394 395 /** enum ipa_mode - ENDP_INIT_MODE register MODE field value */ 396 enum ipa_mode { 397 IPA_BASIC = 0x0, 398 IPA_ENABLE_FRAMING_HDLC = 0x1, 399 IPA_ENABLE_DEFRAMING_HDLC = 0x2, 400 IPA_DMA = 0x3, 401 }; 402 403 /* ENDP_INIT_AGGR register */ 404 enum ipa_reg_endp_init_aggr_field_id { 405 AGGR_EN, 406 AGGR_TYPE, 407 BYTE_LIMIT, 408 TIME_LIMIT, 409 PKT_LIMIT, 410 SW_EOF_ACTIVE, 411 FORCE_CLOSE, 412 HARD_BYTE_LIMIT_EN, 413 AGGR_GRAN_SEL, 414 AGGR_COAL_L2, /* IPA v5.5+ */ 415 }; 416 417 /** enum ipa_aggr_en - ENDP_INIT_AGGR register AGGR_EN field value */ 418 enum ipa_aggr_en { 419 IPA_BYPASS_AGGR /* TX and RX */ = 0x0, 420 IPA_ENABLE_AGGR /* RX */ = 0x1, 421 IPA_ENABLE_DEAGGR /* TX */ = 0x2, 422 }; 423 424 /** enum ipa_aggr_type - ENDP_INIT_AGGR register AGGR_TYPE field value */ 425 enum ipa_aggr_type { 426 IPA_MBIM_16 = 0x0, 427 IPA_HDLC = 0x1, 428 IPA_TLP = 0x2, 429 IPA_RNDIS = 0x3, 430 IPA_GENERIC = 0x4, 431 IPA_COALESCE = 0x5, 432 IPA_QCMAP = 0x6, 433 }; 434 435 /* ENDP_INIT_HOL_BLOCK_EN register */ 436 enum ipa_reg_endp_init_hol_block_en_field_id { 437 HOL_BLOCK_EN, 438 }; 439 440 /* ENDP_INIT_HOL_BLOCK_TIMER register */ 441 enum ipa_reg_endp_init_hol_block_timer_field_id { 442 TIMER_BASE_VALUE, /* Not IPA v4.5+ */ 443 TIMER_SCALE, /* IPA v4.2 only */ 444 TIMER_LIMIT, /* IPA v4.5+ */ 445 TIMER_GRAN_SEL, /* IPA v4.5+ */ 446 }; 447 448 /* ENDP_INIT_DEAGGR register */ 449 enum ipa_reg_endp_deaggr_field_id { 450 DEAGGR_HDR_LEN, 451 SYSPIPE_ERR_DETECTION, 452 PACKET_OFFSET_VALID, 453 PACKET_OFFSET_LOCATION, 454 IGNORE_MIN_PKT_ERR, 455 MAX_PACKET_LEN, 456 }; 457 458 /* ENDP_INIT_RSRC_GRP register */ 459 enum ipa_reg_endp_init_rsrc_grp_field_id { 460 ENDP_RSRC_GRP, 461 }; 462 463 /* ENDP_INIT_SEQ register */ 464 enum ipa_reg_endp_init_seq_field_id { 465 SEQ_TYPE, 466 SEQ_REP_TYPE, /* Not IPA v4.5+ */ 467 }; 468 469 /** 470 * enum ipa_seq_type - HPS and DPS sequencer type 471 * @IPA_SEQ_DMA: Perform DMA only 472 * @IPA_SEQ_1_PASS: One pass through the pipeline 473 * @IPA_SEQ_2_PASS_SKIP_LAST_UC: Two passes, skip the microcprocessor 474 * @IPA_SEQ_1_PASS_SKIP_LAST_UC: One pass, skip the microcprocessor 475 * @IPA_SEQ_2_PASS: Two passes through the pipeline 476 * @IPA_SEQ_3_PASS_SKIP_LAST_UC: Three passes, skip the microcprocessor 477 * @IPA_SEQ_DECIPHER: Optional deciphering step (combined) 478 * 479 * The low-order byte of the sequencer type register defines the number of 480 * passes a packet takes through the IPA pipeline. The last pass through can 481 * optionally skip the microprocessor. Deciphering is optional for all types; 482 * if enabled, an additional mask (two bits) is added to the type value. 483 * 484 * Note: not all combinations of ipa_seq_type and ipa_seq_rep_type are 485 * supported (or meaningful). 486 */ 487 enum ipa_seq_type { 488 IPA_SEQ_DMA = 0x00, 489 IPA_SEQ_1_PASS = 0x02, 490 IPA_SEQ_2_PASS_SKIP_LAST_UC = 0x04, 491 IPA_SEQ_1_PASS_SKIP_LAST_UC = 0x06, 492 IPA_SEQ_2_PASS = 0x0a, 493 IPA_SEQ_3_PASS_SKIP_LAST_UC = 0x0c, 494 /* The next value can be ORed with the above */ 495 IPA_SEQ_DECIPHER = 0x11, 496 }; 497 498 /** 499 * enum ipa_seq_rep_type - replicated packet sequencer type 500 * @IPA_SEQ_REP_DMA_PARSER: DMA parser for replicated packets 501 * 502 * This goes in the second byte of the endpoint sequencer type register. 503 * 504 * Note: not all combinations of ipa_seq_type and ipa_seq_rep_type are 505 * supported (or meaningful). 506 */ 507 enum ipa_seq_rep_type { 508 IPA_SEQ_REP_DMA_PARSER = 0x08, 509 }; 510 511 /* ENDP_STATUS register */ 512 enum ipa_reg_endp_status_field_id { 513 STATUS_EN, 514 STATUS_ENDP, 515 STATUS_LOCATION, /* Not IPA v4.5+ */ 516 STATUS_PKT_SUPPRESS, /* IPA v4.0+ */ 517 }; 518 519 /* ENDP_FILTER_ROUTER_HSH_CFG register */ 520 enum ipa_reg_endp_filter_router_hsh_cfg_field_id { 521 FILTER_HASH_MSK_SRC_ID, 522 FILTER_HASH_MSK_SRC_IP, 523 FILTER_HASH_MSK_DST_IP, 524 FILTER_HASH_MSK_SRC_PORT, 525 FILTER_HASH_MSK_DST_PORT, 526 FILTER_HASH_MSK_PROTOCOL, 527 FILTER_HASH_MSK_METADATA, 528 FILTER_HASH_MSK_ALL, /* Bitwise OR of the above 6 fields */ 529 530 ROUTER_HASH_MSK_SRC_ID, 531 ROUTER_HASH_MSK_SRC_IP, 532 ROUTER_HASH_MSK_DST_IP, 533 ROUTER_HASH_MSK_SRC_PORT, 534 ROUTER_HASH_MSK_DST_PORT, 535 ROUTER_HASH_MSK_PROTOCOL, 536 ROUTER_HASH_MSK_METADATA, 537 ROUTER_HASH_MSK_ALL, /* Bitwise OR of the above 6 fields */ 538 }; 539 540 /* ENDP_FILTER_CACHE_CFG and ENDP_ROUTER_CACHE_CFG registers */ 541 enum ipa_reg_endp_cache_cfg_field_id { 542 CACHE_MSK_SRC_ID, 543 CACHE_MSK_SRC_IP, 544 CACHE_MSK_DST_IP, 545 CACHE_MSK_SRC_PORT, 546 CACHE_MSK_DST_PORT, 547 CACHE_MSK_PROTOCOL, 548 CACHE_MSK_METADATA, 549 }; 550 551 /* IPA_IRQ_STTS, IPA_IRQ_EN, and IPA_IRQ_CLR registers */ 552 /** 553 * enum ipa_irq_id - Bit positions representing type of IPA IRQ 554 * @IPA_IRQ_UC_0: Microcontroller event interrupt 555 * @IPA_IRQ_UC_1: Microcontroller response interrupt 556 * @IPA_IRQ_TX_SUSPEND: Data ready interrupt 557 * @IPA_IRQ_COUNT: Number of IRQ ids (must be last) 558 * 559 * IRQ types not described above are not currently used. 560 * 561 * @IPA_IRQ_BAD_SNOC_ACCESS: (Not currently used) 562 * @IPA_IRQ_EOT_COAL: (Not currently used) 563 * @IPA_IRQ_UC_2: (Not currently used) 564 * @IPA_IRQ_UC_3: (Not currently used) 565 * @IPA_IRQ_UC_IN_Q_NOT_EMPTY: (Not currently used) 566 * @IPA_IRQ_UC_RX_CMD_Q_NOT_FULL: (Not currently used) 567 * @IPA_IRQ_PROC_UC_ACK_Q_NOT_EMPTY: (Not currently used) 568 * @IPA_IRQ_RX_ERR: (Not currently used) 569 * @IPA_IRQ_DEAGGR_ERR: (Not currently used) 570 * @IPA_IRQ_TX_ERR: (Not currently used) 571 * @IPA_IRQ_STEP_MODE: (Not currently used) 572 * @IPA_IRQ_PROC_ERR: (Not currently used) 573 * @IPA_IRQ_TX_HOLB_DROP: (Not currently used) 574 * @IPA_IRQ_BAM_GSI_IDLE: (Not currently used) 575 * @IPA_IRQ_PIPE_YELLOW_BELOW: (Not currently used) 576 * @IPA_IRQ_PIPE_RED_BELOW: (Not currently used) 577 * @IPA_IRQ_PIPE_YELLOW_ABOVE: (Not currently used) 578 * @IPA_IRQ_PIPE_RED_ABOVE: (Not currently used) 579 * @IPA_IRQ_UCP: (Not currently used) 580 * @IPA_IRQ_DCMP: (Not currently used) 581 * @IPA_IRQ_GSI_EE: (Not currently used) 582 * @IPA_IRQ_GSI_IPA_IF_TLV_RCVD: (Not currently used) 583 * @IPA_IRQ_GSI_UC: (Not currently used) 584 * @IPA_IRQ_TLV_LEN_MIN_DSM: (Not currently used) 585 * @IPA_IRQ_DRBIP_PKT_EXCEED_MAX_SIZE_EN: (Not currently used) 586 * @IPA_IRQ_DRBIP_DATA_SCTR_CFG_ERROR_EN: (Not currently used) 587 * @IPA_IRQ_DRBIP_IMM_CMD_NO_FLSH_HZRD_EN: (Not currently used) 588 * @IPA_IRQ_ERROR_NON_FATAL: (Not currently used) 589 * @IPA_IRQ_ERROR_FATAL: (Not currently used) 590 */ 591 enum ipa_irq_id { 592 IPA_IRQ_BAD_SNOC_ACCESS = 0x0, /* Not IPA v5.5+ */ 593 IPA_IRQ_EOT_COAL = 0x1, /* Not IPA v3.5+ */ 594 IPA_IRQ_UC_0 = 0x2, 595 IPA_IRQ_UC_1 = 0x3, 596 IPA_IRQ_UC_2 = 0x4, 597 IPA_IRQ_UC_3 = 0x5, 598 IPA_IRQ_UC_IN_Q_NOT_EMPTY = 0x6, 599 IPA_IRQ_UC_RX_CMD_Q_NOT_FULL = 0x7, 600 IPA_IRQ_PROC_UC_ACK_Q_NOT_EMPTY = 0x8, 601 IPA_IRQ_RX_ERR = 0x9, /* Not IPA v5.5+ */ 602 IPA_IRQ_DEAGGR_ERR = 0xa, /* Not IPA v5.5+ */ 603 IPA_IRQ_TX_ERR = 0xb, /* Not IPA v5.5+ */ 604 IPA_IRQ_STEP_MODE = 0xc, /* Not IPA v5.5+ */ 605 IPA_IRQ_PROC_ERR = 0xd, /* Not IPA v5.5+ */ 606 IPA_IRQ_TX_SUSPEND = 0xe, 607 IPA_IRQ_TX_HOLB_DROP = 0xf, 608 IPA_IRQ_BAM_GSI_IDLE = 0x10, 609 IPA_IRQ_PIPE_YELLOW_BELOW = 0x11, 610 IPA_IRQ_PIPE_RED_BELOW = 0x12, 611 IPA_IRQ_PIPE_YELLOW_ABOVE = 0x13, 612 IPA_IRQ_PIPE_RED_ABOVE = 0x14, 613 IPA_IRQ_UCP = 0x15, 614 IPA_IRQ_DCMP = 0x16, /* Not IPA v4.5+ */ 615 IPA_IRQ_GSI_EE = 0x17, 616 IPA_IRQ_GSI_IPA_IF_TLV_RCVD = 0x18, 617 IPA_IRQ_GSI_UC = 0x19, 618 IPA_IRQ_TLV_LEN_MIN_DSM = 0x1a, /* IPA v4.5-v5.2 */ 619 IPA_IRQ_DRBIP_PKT_EXCEED_MAX_SIZE_EN = 0x1b, /* IPA v4.9-v5.2 */ 620 IPA_IRQ_DRBIP_DATA_SCTR_CFG_ERROR_EN = 0x1c, /* IPA v4.9-v5.2 */ 621 IPA_IRQ_DRBIP_IMM_CMD_NO_FLSH_HZRD_EN = 0x1d, /* IPA v4.9-v5.2 */ 622 IPA_IRQ_ERROR_NON_FATAL = 0x1e, /* IPA v5.5+ */ 623 IPA_IRQ_ERROR_FATAL = 0x1f, /* IPA v5.5+ */ 624 IPA_IRQ_COUNT, /* Last; not an id */ 625 }; 626 627 /* IPA_IRQ_UC register */ 628 enum ipa_reg_ipa_irq_uc_field_id { 629 UC_INTR, 630 }; 631 632 extern const struct regs ipa_regs_v3_1; 633 extern const struct regs ipa_regs_v3_5_1; 634 extern const struct regs ipa_regs_v4_2; 635 extern const struct regs ipa_regs_v4_5; 636 extern const struct regs ipa_regs_v4_7; 637 extern const struct regs ipa_regs_v4_9; 638 extern const struct regs ipa_regs_v4_11; 639 extern const struct regs ipa_regs_v5_0; 640 extern const struct regs ipa_regs_v5_5; 641 642 const struct reg *ipa_reg(struct ipa *ipa, enum ipa_reg_id reg_id); 643 644 int ipa_reg_init(struct ipa *ipa, struct platform_device *pdev); 645 void ipa_reg_exit(struct ipa *ipa); 646 647 #endif /* _IPA_REG_H_ */ 648