1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. 3 4 #define CREATE_TRACE_POINTS 5 #include <trace/events/qcom_geni_i2c.h> 6 7 #include <linux/acpi.h> 8 #include <linux/clk.h> 9 #include <linux/dmaengine.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/dma/qcom-gpi-dma.h> 12 #include <linux/err.h> 13 #include <linux/i2c.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/soc/qcom/geni-se.h> 21 #include <linux/spinlock.h> 22 #include <linux/units.h> 23 24 #define SE_I2C_TX_TRANS_LEN 0x26c 25 #define SE_I2C_RX_TRANS_LEN 0x270 26 #define SE_I2C_SCL_COUNTERS 0x278 27 28 #define SE_I2C_ERR (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN |\ 29 M_GP_IRQ_1_EN | M_GP_IRQ_3_EN | M_GP_IRQ_4_EN) 30 #define SE_I2C_ABORT BIT(1) 31 32 /* M_CMD OP codes for I2C */ 33 #define I2C_WRITE 0x1 34 #define I2C_READ 0x2 35 #define I2C_WRITE_READ 0x3 36 #define I2C_ADDR_ONLY 0x4 37 #define I2C_BUS_CLEAR 0x6 38 #define I2C_STOP_ON_BUS 0x7 39 /* M_CMD params for I2C */ 40 #define PRE_CMD_DELAY BIT(0) 41 #define TIMESTAMP_BEFORE BIT(1) 42 #define STOP_STRETCH BIT(2) 43 #define TIMESTAMP_AFTER BIT(3) 44 #define POST_COMMAND_DELAY BIT(4) 45 #define IGNORE_ADD_NACK BIT(6) 46 #define READ_FINISHED_WITH_ACK BIT(7) 47 #define BYPASS_ADDR_PHASE BIT(8) 48 #define SLV_ADDR_MSK GENMASK(15, 9) 49 #define SLV_ADDR_SHFT 9 50 /* I2C SCL COUNTER fields */ 51 #define HIGH_COUNTER_MSK GENMASK(29, 20) 52 #define HIGH_COUNTER_SHFT 20 53 #define LOW_COUNTER_MSK GENMASK(19, 10) 54 #define LOW_COUNTER_SHFT 10 55 #define CYCLE_COUNTER_MSK GENMASK(9, 0) 56 57 #define I2C_PACK_TX BIT(0) 58 #define I2C_PACK_RX BIT(1) 59 60 enum geni_i2c_err_code { 61 GP_IRQ0, 62 ADDR_NACK, 63 DATA_NACK, 64 GP_IRQ2, 65 BUS_PROTO, 66 ARB_LOST, 67 GP_IRQ5, 68 GENI_OVERRUN, 69 GENI_ILLEGAL_CMD, 70 GENI_ABORT_DONE, 71 GENI_TIMEOUT, 72 }; 73 74 #define DM_I2C_CB_ERR ((BIT(ADDR_NACK) | BIT(BUS_PROTO) | BIT(ARB_LOST)) \ 75 << 5) 76 77 #define I2C_AUTO_SUSPEND_DELAY 250 78 #define PACKING_BYTES_PW 4 79 80 #define ABORT_TIMEOUT HZ 81 #define CANCEL_TIMEOUT HZ 82 #define XFER_TIMEOUT HZ 83 #define RST_TIMEOUT HZ 84 85 #define GENI_SE_CLK_32MHZ (32 * HZ_PER_MHZ) 86 #define GENI_SE_CLK_19P2MHZ 19200000UL 87 88 struct geni_i2c_desc { 89 bool no_dma_support; 90 unsigned int tx_fifo_depth; 91 int (*resources_init)(struct geni_se *se); 92 int (*set_rate)(struct geni_se *se, unsigned long freq); 93 int (*power_on)(struct geni_se *se); 94 int (*power_off)(struct geni_se *se); 95 }; 96 97 #define QCOM_I2C_MIN_NUM_OF_MSGS_MULTI_DESC 2 98 99 /** 100 * struct geni_i2c_gpi_multi_desc_xfer - Structure for multi transfer support 101 * 102 * @msg_idx_cnt: Current message index being processed in the transfer 103 * @unmap_msg_cnt: Number of messages that have been unmapped 104 * @irq_cnt: Number of transfer completion interrupts received 105 * @dma_buf: Array of virtual addresses for DMA-safe buffers 106 * @dma_addr: Array of DMA addresses corresponding to the buffers 107 */ 108 struct geni_i2c_gpi_multi_desc_xfer { 109 u32 msg_idx_cnt; 110 u32 unmap_msg_cnt; 111 u32 irq_cnt; 112 void **dma_buf; 113 dma_addr_t *dma_addr; 114 }; 115 116 struct geni_i2c_dev { 117 struct geni_se se; 118 u32 tx_wm; 119 int irq; 120 int err; 121 struct i2c_adapter adap; 122 struct completion done; 123 struct completion abort_done; 124 struct completion cancel_done; 125 struct completion tx_reset_done; 126 struct completion rx_reset_done; 127 struct i2c_msg *cur; 128 int cur_wr; 129 int cur_rd; 130 spinlock_t lock; 131 u32 clk_freq_out; 132 const struct geni_i2c_clk_fld *clk_fld; 133 u32 clk_idx; 134 void *dma_buf; 135 size_t xfer_len; 136 dma_addr_t dma_addr; 137 struct dma_chan *tx_c; 138 struct dma_chan *rx_c; 139 bool no_dma; 140 bool gpi_mode; 141 bool is_tx_multi_desc_xfer; 142 u32 num_msgs; 143 struct geni_i2c_gpi_multi_desc_xfer i2c_multi_desc_config; 144 const struct geni_i2c_desc *dev_data; 145 }; 146 147 struct geni_i2c_err_log { 148 int err; 149 const char *msg; 150 }; 151 152 static const struct geni_i2c_err_log gi2c_log[] = { 153 [GP_IRQ0] = {-EIO, "Unknown I2C err GP_IRQ0"}, 154 [ADDR_NACK] = {-ENXIO, "NACK: target device unresponsive, check its power/reset-ln"}, 155 [DATA_NACK] = {-EIO, "Data NACK: TX transfer NACK"}, 156 [GP_IRQ2] = {-EIO, "Unknown I2C err GP IRQ2"}, 157 [BUS_PROTO] = {-EPROTO, "Bus proto err, noisy/unexpected start/stop"}, 158 [ARB_LOST] = {-EAGAIN, "Bus arbitration lost, clock line undriveable"}, 159 [GP_IRQ5] = {-EIO, "Unknown I2C err GP IRQ5"}, 160 [GENI_OVERRUN] = {-EIO, "Cmd overrun, check GENI cmd-state machine"}, 161 [GENI_ILLEGAL_CMD] = {-EIO, "Illegal cmd, check GENI cmd-state machine"}, 162 [GENI_ABORT_DONE] = {-ETIMEDOUT, "Abort after timeout successful"}, 163 [GENI_TIMEOUT] = {-ETIMEDOUT, "I2C TXN timed out"}, 164 }; 165 166 struct geni_i2c_clk_fld { 167 u32 clk_freq_out; 168 u8 clk_div; 169 u8 t_high_cnt; 170 u8 t_low_cnt; 171 u8 t_cycle_cnt; 172 }; 173 174 /* 175 * Hardware uses the underlying formula to calculate time periods of 176 * SCL clock cycle. Firmware uses some additional cycles excluded from the 177 * below formula and it is confirmed that the time periods are within 178 * specification limits. 179 * 180 * time of high period of SCL: t_high = (t_high_cnt * clk_div) / source_clock 181 * time of low period of SCL: t_low = (t_low_cnt * clk_div) / source_clock 182 * time of full period of SCL: t_cycle = (t_cycle_cnt * clk_div) / source_clock 183 * clk_freq_out = t / t_cycle 184 * source_clock = 19.2 MHz 185 */ 186 static const struct geni_i2c_clk_fld geni_i2c_clk_map_19p2mhz[] = { 187 { I2C_MAX_STANDARD_MODE_FREQ, 7, 10, 12, 26 }, 188 { I2C_MAX_FAST_MODE_FREQ, 2, 5, 11, 22 }, 189 { I2C_MAX_FAST_MODE_PLUS_FREQ, 1, 2, 8, 18 }, 190 {} 191 }; 192 193 /* source_clock = 32 MHz */ 194 static const struct geni_i2c_clk_fld geni_i2c_clk_map_32mhz[] = { 195 { I2C_MAX_STANDARD_MODE_FREQ, 12, 9, 10, 26 }, 196 { I2C_MAX_FAST_MODE_FREQ, 4, 3, 9, 19 }, 197 { I2C_MAX_FAST_MODE_PLUS_FREQ, 2, 3, 5, 15 }, 198 {} 199 }; 200 201 static int geni_i2c_clk_map_idx(struct geni_i2c_dev *gi2c) 202 { 203 const struct geni_i2c_clk_fld *itr; 204 unsigned long req_freq, res_freq; 205 int ret; 206 207 /* 208 * Use 32 MHz only if already selected, otherwise use 19.2 MHz. 209 * Preferring 32 MHz merely because DFS supports it breaks I2C 210 * transfers on X1E80100 CRD. 211 */ 212 if (clk_get_rate(gi2c->se.clk) == GENI_SE_CLK_32MHZ) { 213 req_freq = GENI_SE_CLK_32MHZ; 214 itr = geni_i2c_clk_map_32mhz; 215 } else { 216 req_freq = GENI_SE_CLK_19P2MHZ; 217 itr = geni_i2c_clk_map_19p2mhz; 218 } 219 220 ret = geni_se_clk_freq_match(&gi2c->se, req_freq, &gi2c->clk_idx, 221 &res_freq, true); 222 if (ret) 223 return dev_err_probe(gi2c->se.dev, ret, 224 "Failed to find SE source clock %lu Hz\n", 225 req_freq); 226 if (res_freq != req_freq) { 227 dev_err(gi2c->se.dev, "Unsupported SE source clock %lu Hz\n", 228 res_freq); 229 return -EINVAL; 230 } 231 232 while (itr->clk_freq_out != 0) { 233 if (itr->clk_freq_out == gi2c->clk_freq_out) { 234 gi2c->clk_fld = itr; 235 dev_dbg(gi2c->se.dev, 236 "I2C clk selected: freq: %u Hz, clk_idx: %u\n", 237 gi2c->clk_freq_out, gi2c->clk_idx); 238 return 0; 239 } 240 itr++; 241 } 242 243 dev_err(gi2c->se.dev, "Unsupported I2C output frequency %u Hz\n", gi2c->clk_freq_out); 244 245 return -EINVAL; 246 } 247 248 static int qcom_geni_i2c_conf(struct geni_se *se, unsigned long freq) 249 { 250 struct geni_i2c_dev *gi2c = dev_get_drvdata(se->dev); 251 const struct geni_i2c_clk_fld *itr = gi2c->clk_fld; 252 u32 val; 253 254 writel_relaxed(gi2c->clk_idx, gi2c->se.base + SE_GENI_CLK_SEL); 255 256 val = (itr->clk_div << CLK_DIV_SHFT) | SER_CLK_EN; 257 writel_relaxed(val, gi2c->se.base + GENI_SER_M_CLK_CFG); 258 259 val = itr->t_high_cnt << HIGH_COUNTER_SHFT; 260 val |= itr->t_low_cnt << LOW_COUNTER_SHFT; 261 val |= itr->t_cycle_cnt; 262 writel_relaxed(val, gi2c->se.base + SE_I2C_SCL_COUNTERS); 263 trace_geni_i2c_bus_setup(gi2c->se.dev, gi2c->clk_freq_out, 264 itr->clk_div, itr->t_high_cnt, 265 itr->t_low_cnt, itr->t_cycle_cnt); 266 return 0; 267 } 268 269 static void geni_i2c_err_misc(struct geni_i2c_dev *gi2c) 270 { 271 u32 m_cmd = readl_relaxed(gi2c->se.base + SE_GENI_M_CMD0); 272 u32 m_stat = readl_relaxed(gi2c->se.base + SE_GENI_M_IRQ_STATUS); 273 u32 geni_s = readl_relaxed(gi2c->se.base + SE_GENI_STATUS); 274 u32 geni_ios = readl_relaxed(gi2c->se.base + SE_GENI_IOS); 275 u32 dma = readl_relaxed(gi2c->se.base + SE_GENI_DMA_MODE_EN); 276 u32 rx_st, tx_st; 277 278 if (dma) { 279 rx_st = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT); 280 tx_st = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT); 281 } else { 282 rx_st = readl_relaxed(gi2c->se.base + SE_GENI_RX_FIFO_STATUS); 283 tx_st = readl_relaxed(gi2c->se.base + SE_GENI_TX_FIFO_STATUS); 284 } 285 dev_dbg(gi2c->se.dev, "DMA:%d tx_stat:0x%x, rx_stat:0x%x, irq-stat:0x%x\n", 286 dma, tx_st, rx_st, m_stat); 287 dev_dbg(gi2c->se.dev, "m_cmd:0x%x, geni_status:0x%x, geni_ios:0x%x\n", 288 m_cmd, geni_s, geni_ios); 289 } 290 291 static void geni_i2c_err(struct geni_i2c_dev *gi2c, int err) 292 { 293 if (!gi2c->err) 294 gi2c->err = gi2c_log[err].err; 295 if (gi2c->cur) 296 dev_dbg(gi2c->se.dev, "len:%d, slv-addr:0x%x, RD/WR:%d\n", 297 gi2c->cur->len, gi2c->cur->addr, gi2c->cur->flags); 298 299 trace_geni_i2c_err(gi2c->se.dev, gi2c_log[err].err, gi2c_log[err].msg); 300 301 switch (err) { 302 case GENI_ABORT_DONE: 303 case ADDR_NACK: 304 case DATA_NACK: 305 case GENI_TIMEOUT: 306 dev_dbg(gi2c->se.dev, "%s\n", gi2c_log[err].msg); 307 break; 308 default: 309 dev_err(gi2c->se.dev, "%s\n", gi2c_log[err].msg); 310 geni_i2c_err_misc(gi2c); 311 break; 312 } 313 } 314 315 static void geni_i2c_check_addr_data_nack(struct geni_i2c_dev *gi2c) 316 { 317 if (!readl_relaxed(gi2c->se.base + SE_GENI_M_GP_LENGTH)) 318 geni_i2c_err(gi2c, ADDR_NACK); 319 else if (!(gi2c->cur->flags & I2C_M_RD)) 320 geni_i2c_err(gi2c, DATA_NACK); 321 } 322 323 static irqreturn_t geni_i2c_irq(int irq, void *dev) 324 { 325 struct geni_i2c_dev *gi2c = dev; 326 void __iomem *base = gi2c->se.base; 327 int j, p; 328 u32 m_stat; 329 u32 rx_st; 330 u32 dm_tx_st; 331 u32 dm_rx_st; 332 u32 dma; 333 u32 val; 334 struct i2c_msg *cur; 335 336 spin_lock(&gi2c->lock); 337 m_stat = readl_relaxed(base + SE_GENI_M_IRQ_STATUS); 338 rx_st = readl_relaxed(base + SE_GENI_RX_FIFO_STATUS); 339 dm_tx_st = readl_relaxed(base + SE_DMA_TX_IRQ_STAT); 340 dm_rx_st = readl_relaxed(base + SE_DMA_RX_IRQ_STAT); 341 dma = readl_relaxed(base + SE_GENI_DMA_MODE_EN); 342 cur = gi2c->cur; 343 344 trace_geni_i2c_irq(gi2c->se.dev, m_stat, rx_st, dm_tx_st, dm_rx_st); 345 346 if (!cur || 347 m_stat & (M_CMD_FAILURE_EN | M_CMD_ABORT_EN) || 348 dm_rx_st & (DM_I2C_CB_ERR)) { 349 if (m_stat & M_GP_IRQ_1_EN) 350 geni_i2c_check_addr_data_nack(gi2c); 351 if (m_stat & M_GP_IRQ_3_EN) 352 geni_i2c_err(gi2c, BUS_PROTO); 353 if (m_stat & M_GP_IRQ_4_EN) 354 geni_i2c_err(gi2c, ARB_LOST); 355 if (m_stat & M_CMD_OVERRUN_EN) 356 geni_i2c_err(gi2c, GENI_OVERRUN); 357 if (m_stat & M_ILLEGAL_CMD_EN) 358 geni_i2c_err(gi2c, GENI_ILLEGAL_CMD); 359 if (m_stat & M_CMD_ABORT_EN) 360 geni_i2c_err(gi2c, GENI_ABORT_DONE); 361 if (m_stat & M_GP_IRQ_0_EN) 362 geni_i2c_err(gi2c, GP_IRQ0); 363 364 /* Disable the TX Watermark interrupt to stop TX */ 365 if (!dma) 366 writel_relaxed(0, base + SE_GENI_TX_WATERMARK_REG); 367 } else if (dma) { 368 dev_dbg(gi2c->se.dev, "i2c dma tx:0x%x, dma rx:0x%x\n", 369 dm_tx_st, dm_rx_st); 370 } else if (cur->flags & I2C_M_RD && 371 m_stat & (M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN)) { 372 u32 rxcnt = rx_st & RX_FIFO_WC_MSK; 373 374 for (j = 0; j < rxcnt; j++) { 375 p = 0; 376 val = readl_relaxed(base + SE_GENI_RX_FIFOn); 377 while (gi2c->cur_rd < cur->len && p < sizeof(val)) { 378 cur->buf[gi2c->cur_rd++] = val & 0xff; 379 val >>= 8; 380 p++; 381 } 382 if (gi2c->cur_rd == cur->len) 383 break; 384 } 385 } else if (!(cur->flags & I2C_M_RD) && 386 m_stat & M_TX_FIFO_WATERMARK_EN) { 387 for (j = 0; j < gi2c->tx_wm; j++) { 388 u32 temp; 389 390 val = 0; 391 p = 0; 392 while (gi2c->cur_wr < cur->len && p < sizeof(val)) { 393 temp = cur->buf[gi2c->cur_wr++]; 394 val |= temp << (p * 8); 395 p++; 396 } 397 writel_relaxed(val, base + SE_GENI_TX_FIFOn); 398 /* TX Complete, Disable the TX Watermark interrupt */ 399 if (gi2c->cur_wr == cur->len) { 400 writel_relaxed(0, base + SE_GENI_TX_WATERMARK_REG); 401 break; 402 } 403 } 404 } 405 406 if (m_stat) 407 writel_relaxed(m_stat, base + SE_GENI_M_IRQ_CLEAR); 408 409 if (dma && dm_tx_st) 410 writel_relaxed(dm_tx_st, base + SE_DMA_TX_IRQ_CLR); 411 if (dma && dm_rx_st) 412 writel_relaxed(dm_rx_st, base + SE_DMA_RX_IRQ_CLR); 413 414 /* if this is err with done-bit not set, handle that through timeout. */ 415 if (m_stat & M_CMD_DONE_EN || 416 dm_tx_st & TX_DMA_DONE || 417 dm_rx_st & RX_DMA_DONE) 418 complete(&gi2c->done); 419 if (m_stat & M_CMD_CANCEL_EN) 420 complete(&gi2c->cancel_done); 421 if (m_stat & M_CMD_ABORT_EN) 422 complete(&gi2c->abort_done); 423 if (dm_tx_st & TX_RESET_DONE) 424 complete(&gi2c->tx_reset_done); 425 if (dm_rx_st & RX_RESET_DONE) 426 complete(&gi2c->rx_reset_done); 427 428 spin_unlock(&gi2c->lock); 429 430 return IRQ_HANDLED; 431 } 432 433 static void geni_i2c_abort_xfer(struct geni_i2c_dev *gi2c) 434 { 435 unsigned long time_left = ABORT_TIMEOUT; 436 unsigned long flags; 437 438 reinit_completion(&gi2c->abort_done); 439 440 spin_lock_irqsave(&gi2c->lock, flags); 441 geni_se_abort_m_cmd(&gi2c->se); 442 spin_unlock_irqrestore(&gi2c->lock, flags); 443 444 time_left = wait_for_completion_timeout(&gi2c->abort_done, time_left); 445 if (!time_left) 446 dev_err(gi2c->se.dev, "Timeout abort_m_cmd\n"); 447 } 448 449 static void geni_i2c_cancel_xfer(struct geni_i2c_dev *gi2c) 450 { 451 unsigned long time_left = msecs_to_jiffies(CANCEL_TIMEOUT); 452 unsigned long flags; 453 454 reinit_completion(&gi2c->cancel_done); 455 456 spin_lock_irqsave(&gi2c->lock, flags); 457 if (!gi2c->err) 458 geni_i2c_err(gi2c, GENI_TIMEOUT); 459 gi2c->cur = NULL; 460 geni_se_cancel_m_cmd(&gi2c->se); 461 spin_unlock_irqrestore(&gi2c->lock, flags); 462 463 time_left = wait_for_completion_timeout(&gi2c->cancel_done, time_left); 464 if (!time_left) { 465 dev_err(gi2c->se.dev, "Timeout cancel_m_cmd\n"); 466 geni_i2c_abort_xfer(gi2c); 467 } 468 } 469 470 static void geni_i2c_rx_fsm_rst(struct geni_i2c_dev *gi2c) 471 { 472 unsigned long time_left = RST_TIMEOUT; 473 474 reinit_completion(&gi2c->rx_reset_done); 475 writel_relaxed(1, gi2c->se.base + SE_DMA_RX_FSM_RST); 476 477 time_left = wait_for_completion_timeout(&gi2c->rx_reset_done, time_left); 478 if (!time_left) 479 dev_err(gi2c->se.dev, "Timeout resetting RX_FSM\n"); 480 } 481 482 static void geni_i2c_tx_fsm_rst(struct geni_i2c_dev *gi2c) 483 { 484 unsigned long time_left = RST_TIMEOUT; 485 486 reinit_completion(&gi2c->tx_reset_done); 487 writel_relaxed(1, gi2c->se.base + SE_DMA_TX_FSM_RST); 488 489 time_left = wait_for_completion_timeout(&gi2c->tx_reset_done, time_left); 490 if (!time_left) 491 dev_err(gi2c->se.dev, "Timeout resetting TX_FSM\n"); 492 } 493 494 static void geni_i2c_rx_msg_cleanup(struct geni_i2c_dev *gi2c, 495 struct i2c_msg *cur) 496 { 497 gi2c->cur_rd = 0; 498 if (gi2c->dma_buf) { 499 if (gi2c->err && gi2c->err != gi2c_log[ADDR_NACK].err) 500 geni_i2c_rx_fsm_rst(gi2c); 501 geni_se_rx_dma_unprep(&gi2c->se, gi2c->dma_addr, gi2c->xfer_len); 502 i2c_put_dma_safe_msg_buf(gi2c->dma_buf, cur, !gi2c->err); 503 } 504 } 505 506 static void geni_i2c_tx_msg_cleanup(struct geni_i2c_dev *gi2c, 507 struct i2c_msg *cur) 508 { 509 gi2c->cur_wr = 0; 510 if (gi2c->dma_buf) { 511 if (gi2c->err && gi2c->err != gi2c_log[ADDR_NACK].err) 512 geni_i2c_tx_fsm_rst(gi2c); 513 geni_se_tx_dma_unprep(&gi2c->se, gi2c->dma_addr, gi2c->xfer_len); 514 i2c_put_dma_safe_msg_buf(gi2c->dma_buf, cur, !gi2c->err); 515 } 516 } 517 518 static int geni_i2c_rx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg, 519 u32 m_param) 520 { 521 dma_addr_t rx_dma = 0; 522 unsigned long time_left; 523 void *dma_buf; 524 struct geni_se *se = &gi2c->se; 525 size_t len = msg->len; 526 struct i2c_msg *cur; 527 528 dma_buf = gi2c->no_dma ? NULL : i2c_get_dma_safe_msg_buf(msg, 32); 529 if (dma_buf) 530 geni_se_select_mode(se, GENI_SE_DMA); 531 else 532 geni_se_select_mode(se, GENI_SE_FIFO); 533 534 writel_relaxed(len, se->base + SE_I2C_RX_TRANS_LEN); 535 geni_se_setup_m_cmd(se, I2C_READ, m_param); 536 537 if (dma_buf && geni_se_rx_dma_prep(se, dma_buf, len, &rx_dma)) { 538 geni_se_select_mode(se, GENI_SE_FIFO); 539 i2c_put_dma_safe_msg_buf(dma_buf, msg, false); 540 dma_buf = NULL; 541 } else { 542 gi2c->xfer_len = len; 543 gi2c->dma_addr = rx_dma; 544 gi2c->dma_buf = dma_buf; 545 } 546 547 cur = gi2c->cur; 548 time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT); 549 if (!time_left || (gi2c->err && gi2c->err != gi2c_log[ADDR_NACK].err)) 550 geni_i2c_cancel_xfer(gi2c); 551 552 geni_i2c_rx_msg_cleanup(gi2c, cur); 553 554 return gi2c->err; 555 } 556 557 static int geni_i2c_tx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg, 558 u32 m_param) 559 { 560 dma_addr_t tx_dma = 0; 561 unsigned long time_left; 562 void *dma_buf; 563 struct geni_se *se = &gi2c->se; 564 size_t len = msg->len; 565 struct i2c_msg *cur; 566 567 dma_buf = gi2c->no_dma ? NULL : i2c_get_dma_safe_msg_buf(msg, 32); 568 if (dma_buf) 569 geni_se_select_mode(se, GENI_SE_DMA); 570 else 571 geni_se_select_mode(se, GENI_SE_FIFO); 572 573 writel_relaxed(len, se->base + SE_I2C_TX_TRANS_LEN); 574 geni_se_setup_m_cmd(se, I2C_WRITE, m_param); 575 576 if (dma_buf && geni_se_tx_dma_prep(se, dma_buf, len, &tx_dma)) { 577 geni_se_select_mode(se, GENI_SE_FIFO); 578 i2c_put_dma_safe_msg_buf(dma_buf, msg, false); 579 dma_buf = NULL; 580 } else { 581 gi2c->xfer_len = len; 582 gi2c->dma_addr = tx_dma; 583 gi2c->dma_buf = dma_buf; 584 } 585 586 if (!dma_buf) /* Get FIFO IRQ */ 587 writel_relaxed(1, se->base + SE_GENI_TX_WATERMARK_REG); 588 589 cur = gi2c->cur; 590 time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT); 591 if (!time_left || (gi2c->err && gi2c->err != gi2c_log[ADDR_NACK].err)) 592 geni_i2c_cancel_xfer(gi2c); 593 594 geni_i2c_tx_msg_cleanup(gi2c, cur); 595 596 return gi2c->err; 597 } 598 599 static void i2c_gpi_cb_result(void *cb, const struct dmaengine_result *result) 600 { 601 struct geni_i2c_dev *gi2c = cb; 602 struct geni_i2c_gpi_multi_desc_xfer *tx_multi_xfer; 603 604 if (result->result != DMA_TRANS_NOERROR) { 605 dev_err(gi2c->se.dev, "DMA txn failed:%d\n", result->result); 606 gi2c->err = -EIO; 607 } else if (result->residue) { 608 dev_dbg(gi2c->se.dev, "DMA xfer has pending: %d\n", result->residue); 609 } 610 611 if (gi2c->is_tx_multi_desc_xfer) { 612 tx_multi_xfer = &gi2c->i2c_multi_desc_config; 613 tx_multi_xfer->irq_cnt++; 614 } 615 616 complete(&gi2c->done); 617 } 618 619 static void geni_i2c_gpi_unmap(struct geni_i2c_dev *gi2c, struct i2c_msg *msg, 620 void *tx_buf, dma_addr_t tx_addr, 621 void *rx_buf, dma_addr_t rx_addr) 622 { 623 if (tx_buf) { 624 dma_unmap_single(gi2c->se.dev->parent, tx_addr, msg->len, DMA_TO_DEVICE); 625 i2c_put_dma_safe_msg_buf(tx_buf, msg, !gi2c->err); 626 } 627 628 if (rx_buf) { 629 dma_unmap_single(gi2c->se.dev->parent, rx_addr, msg->len, DMA_FROM_DEVICE); 630 i2c_put_dma_safe_msg_buf(rx_buf, msg, !gi2c->err); 631 } 632 } 633 634 /** 635 * geni_i2c_gpi_multi_desc_unmap() - Unmaps DMA buffers post multi message TX transfers 636 * @gi2c: I2C dev handle 637 * @msgs: Array of I2C messages 638 * @peripheral: Pointer to gpi_i2c_config 639 */ 640 static void geni_i2c_gpi_multi_desc_unmap(struct geni_i2c_dev *gi2c, struct i2c_msg msgs[], 641 struct gpi_i2c_config *peripheral) 642 { 643 u32 msg_xfer_cnt, wr_idx = 0; 644 struct geni_i2c_gpi_multi_desc_xfer *tx_multi_xfer = &gi2c->i2c_multi_desc_config; 645 646 msg_xfer_cnt = gi2c->err ? tx_multi_xfer->msg_idx_cnt : tx_multi_xfer->irq_cnt; 647 648 /* Unmap the processed DMA buffers based on the received interrupt count */ 649 for (; tx_multi_xfer->unmap_msg_cnt < msg_xfer_cnt; tx_multi_xfer->unmap_msg_cnt++) { 650 wr_idx = tx_multi_xfer->unmap_msg_cnt; 651 geni_i2c_gpi_unmap(gi2c, &msgs[wr_idx], 652 tx_multi_xfer->dma_buf[wr_idx], 653 tx_multi_xfer->dma_addr[wr_idx], 654 NULL, 0); 655 656 if (tx_multi_xfer->unmap_msg_cnt == gi2c->num_msgs - 1) { 657 kfree(tx_multi_xfer->dma_buf); 658 kfree(tx_multi_xfer->dma_addr); 659 break; 660 } 661 } 662 } 663 664 /** 665 * geni_i2c_gpi_multi_xfer_timeout_handler() - Handles multi message transfer timeout 666 * @dev: Pointer to the corresponding dev node 667 * @multi_xfer: Pointer to the geni_i2c_gpi_multi_desc_xfer 668 * @transfer_timeout_msecs: Timeout value in milliseconds 669 * @transfer_comp: Completion object of the transfer 670 * 671 * This function waits for the completion of each processed transfer messages 672 * based on the interrupts generated upon transfer completion. 673 * 674 * Return: On success returns 0, -ETIMEDOUT on timeout. 675 */ 676 static int geni_i2c_gpi_multi_xfer_timeout_handler(struct device *dev, 677 struct geni_i2c_gpi_multi_desc_xfer *multi_xfer, 678 u32 transfer_timeout_msecs, 679 struct completion *transfer_comp) 680 { 681 int i; 682 u32 time_left; 683 684 for (i = 0; i < multi_xfer->msg_idx_cnt - 1; i++) { 685 reinit_completion(transfer_comp); 686 687 if (multi_xfer->msg_idx_cnt != multi_xfer->irq_cnt) { 688 time_left = wait_for_completion_timeout(transfer_comp, 689 transfer_timeout_msecs); 690 if (!time_left) { 691 dev_err(dev, "%s: Transfer timeout\n", __func__); 692 return -ETIMEDOUT; 693 } 694 } 695 } 696 return 0; 697 } 698 699 static int geni_i2c_gpi(struct geni_i2c_dev *gi2c, struct i2c_msg msgs[], 700 struct dma_slave_config *config, dma_addr_t *dma_addr_p, 701 void **buf, unsigned int op, struct dma_chan *dma_chan) 702 { 703 struct gpi_i2c_config *peripheral; 704 unsigned int flags; 705 void *dma_buf = NULL; 706 dma_addr_t addr = 0; 707 enum dma_data_direction map_dirn; 708 enum dma_transfer_direction dma_dirn; 709 struct dma_async_tx_descriptor *desc; 710 int ret; 711 struct geni_i2c_gpi_multi_desc_xfer *gi2c_gpi_xfer; 712 dma_cookie_t cookie; 713 u32 msg_idx; 714 715 peripheral = config->peripheral_config; 716 gi2c_gpi_xfer = &gi2c->i2c_multi_desc_config; 717 msg_idx = gi2c_gpi_xfer->msg_idx_cnt; 718 719 /* 720 * Skip TX DMA mapping for a read message (I2C_M_RD) to avoid 721 * programming an extra TX DMA TRE that would cause an unintended 722 * write cycle on the I2C bus before the actual read operation. 723 */ 724 if (op == I2C_WRITE && msgs[msg_idx].flags & I2C_M_RD) { 725 peripheral->multi_msg = true; 726 goto skip_tx_dma_map; 727 } 728 729 dma_buf = i2c_get_dma_safe_msg_buf(&msgs[msg_idx], 1); 730 if (!dma_buf) { 731 ret = -ENOMEM; 732 goto out; 733 } 734 735 if (op == I2C_WRITE) 736 map_dirn = DMA_TO_DEVICE; 737 else 738 map_dirn = DMA_FROM_DEVICE; 739 740 addr = dma_map_single(gi2c->se.dev->parent, dma_buf, 741 msgs[msg_idx].len, map_dirn); 742 if (dma_mapping_error(gi2c->se.dev->parent, addr)) { 743 i2c_put_dma_safe_msg_buf(dma_buf, &msgs[msg_idx], false); 744 ret = -ENOMEM; 745 goto out; 746 } 747 748 skip_tx_dma_map: 749 if (gi2c->is_tx_multi_desc_xfer) { 750 flags = DMA_CTRL_ACK; 751 752 /* BEI bit to be cleared for last TRE */ 753 if (msg_idx == gi2c->num_msgs - 1) 754 flags |= DMA_PREP_INTERRUPT; 755 } else { 756 flags = DMA_PREP_INTERRUPT | DMA_CTRL_ACK; 757 } 758 759 /* set the length as message for rx txn */ 760 peripheral->rx_len = msgs[msg_idx].len; 761 peripheral->op = op; 762 763 ret = dmaengine_slave_config(dma_chan, config); 764 if (ret) { 765 dev_err(gi2c->se.dev, "dma config error: %d for op:%d\n", ret, op); 766 goto err_config; 767 } 768 769 peripheral->set_config = 0; 770 peripheral->multi_msg = true; 771 772 if (op == I2C_WRITE) 773 dma_dirn = DMA_MEM_TO_DEV; 774 else 775 dma_dirn = DMA_DEV_TO_MEM; 776 777 desc = dmaengine_prep_slave_single(dma_chan, addr, msgs[msg_idx].len, 778 dma_dirn, flags); 779 if (!desc && !(flags & DMA_PREP_INTERRUPT)) { 780 /* Retry with interrupt if not enough TREs */ 781 flags |= DMA_PREP_INTERRUPT; 782 desc = dmaengine_prep_slave_single(dma_chan, addr, msgs[msg_idx].len, 783 dma_dirn, flags); 784 } 785 786 if (!desc) { 787 dev_err(gi2c->se.dev, "prep_slave_sg failed\n"); 788 ret = -EIO; 789 goto err_config; 790 } 791 792 desc->callback_result = i2c_gpi_cb_result; 793 desc->callback_param = gi2c; 794 795 if (!((msgs[msg_idx].flags & I2C_M_RD) && op == I2C_WRITE)) 796 gi2c_gpi_xfer->msg_idx_cnt++; 797 798 cookie = dmaengine_submit(desc); 799 if (dma_submit_error(cookie)) { 800 dev_err(gi2c->se.dev, 801 "%s: dmaengine_submit failed (%d)\n", __func__, cookie); 802 ret = -EINVAL; 803 goto err_config; 804 } 805 806 if (gi2c->is_tx_multi_desc_xfer) { 807 gi2c_gpi_xfer->dma_buf[msg_idx] = dma_buf; 808 gi2c_gpi_xfer->dma_addr[msg_idx] = addr; 809 810 dma_async_issue_pending(gi2c->tx_c); 811 812 if ((msg_idx == (gi2c->num_msgs - 1)) || flags & DMA_PREP_INTERRUPT) { 813 ret = geni_i2c_gpi_multi_xfer_timeout_handler(gi2c->se.dev, gi2c_gpi_xfer, 814 XFER_TIMEOUT, &gi2c->done); 815 if (ret) { 816 dev_err(gi2c->se.dev, 817 "I2C multi write msg transfer timeout: %d\n", 818 ret); 819 gi2c->err = ret; 820 return ret; 821 } 822 } 823 } else { 824 /* Non multi descriptor message transfer */ 825 *buf = dma_buf; 826 *dma_addr_p = addr; 827 } 828 return 0; 829 830 err_config: 831 /* Avoid DMA unmap as the write operation skipped DMA mapping */ 832 if (dma_buf) { 833 dma_unmap_single(gi2c->se.dev->parent, addr, 834 msgs[msg_idx].len, map_dirn); 835 i2c_put_dma_safe_msg_buf(dma_buf, &msgs[msg_idx], false); 836 } 837 838 out: 839 gi2c->err = ret; 840 return ret; 841 } 842 843 static int geni_i2c_gpi_xfer(struct geni_i2c_dev *gi2c, struct i2c_msg msgs[], int num) 844 { 845 struct dma_slave_config config = {}; 846 struct gpi_i2c_config peripheral = {}; 847 int i, ret = 0; 848 unsigned long time_left; 849 dma_addr_t tx_addr, rx_addr; 850 void *tx_buf = NULL, *rx_buf = NULL; 851 struct geni_i2c_gpi_multi_desc_xfer *tx_multi_xfer; 852 const struct geni_i2c_clk_fld *itr = gi2c->clk_fld; 853 854 config.peripheral_config = &peripheral; 855 config.peripheral_size = sizeof(peripheral); 856 857 peripheral.pack_enable = I2C_PACK_TX | I2C_PACK_RX; 858 peripheral.cycle_count = itr->t_cycle_cnt; 859 peripheral.high_count = itr->t_high_cnt; 860 peripheral.low_count = itr->t_low_cnt; 861 peripheral.clk_div = itr->clk_div; 862 peripheral.set_config = 1; 863 peripheral.multi_msg = false; 864 865 trace_geni_i2c_bus_setup(gi2c->se.dev, gi2c->clk_freq_out, 866 itr->clk_div, itr->t_high_cnt, 867 itr->t_low_cnt, itr->t_cycle_cnt); 868 869 gi2c->num_msgs = num; 870 gi2c->is_tx_multi_desc_xfer = false; 871 872 tx_multi_xfer = &gi2c->i2c_multi_desc_config; 873 memset(tx_multi_xfer, 0, sizeof(struct geni_i2c_gpi_multi_desc_xfer)); 874 875 /* 876 * If number of write messages are two and higher then 877 * configure hardware for multi descriptor transfers with BEI. 878 */ 879 if (num >= QCOM_I2C_MIN_NUM_OF_MSGS_MULTI_DESC) { 880 gi2c->is_tx_multi_desc_xfer = true; 881 for (i = 0; i < num; i++) { 882 if (msgs[i].flags & I2C_M_RD) { 883 /* 884 * Multi descriptor transfer with BEI 885 * support is enabled for write transfers. 886 * TODO: Add BEI optimization support for 887 * read transfers later. 888 */ 889 gi2c->is_tx_multi_desc_xfer = false; 890 break; 891 } 892 } 893 } 894 895 if (gi2c->is_tx_multi_desc_xfer) { 896 tx_multi_xfer->dma_buf = kcalloc(num, sizeof(void *), GFP_KERNEL); 897 tx_multi_xfer->dma_addr = kzalloc_objs(dma_addr_t, num); 898 if (!tx_multi_xfer->dma_buf || !tx_multi_xfer->dma_addr) { 899 ret = -ENOMEM; 900 goto err; 901 } 902 } 903 904 for (i = 0; i < num; i++) { 905 gi2c->cur = &msgs[i]; 906 gi2c->err = 0; 907 reinit_completion(&gi2c->done); 908 dev_dbg(gi2c->se.dev, "msg[%d].len:%d\n", i, gi2c->cur->len); 909 910 peripheral.stretch = 0; 911 if (i < num - 1) 912 peripheral.stretch = 1; 913 914 peripheral.addr = msgs[i].addr; 915 if (i > 0 && (!(msgs[i].flags & I2C_M_RD))) 916 peripheral.multi_msg = false; 917 918 ret = geni_i2c_gpi(gi2c, msgs, &config, 919 &tx_addr, &tx_buf, I2C_WRITE, gi2c->tx_c); 920 if (ret) 921 goto err; 922 923 if (msgs[i].flags & I2C_M_RD) { 924 ret = geni_i2c_gpi(gi2c, msgs, &config, 925 &rx_addr, &rx_buf, I2C_READ, gi2c->rx_c); 926 if (ret) 927 goto err; 928 929 dma_async_issue_pending(gi2c->rx_c); 930 } 931 932 if (!gi2c->is_tx_multi_desc_xfer) { 933 dma_async_issue_pending(gi2c->tx_c); 934 time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT); 935 if (!time_left) { 936 dev_err(gi2c->se.dev, "%s:I2C timeout\n", __func__); 937 gi2c->err = -ETIMEDOUT; 938 } 939 } 940 941 if (gi2c->err) { 942 ret = gi2c->err; 943 goto err; 944 } 945 946 if (!gi2c->is_tx_multi_desc_xfer) 947 geni_i2c_gpi_unmap(gi2c, &msgs[i], tx_buf, tx_addr, rx_buf, rx_addr); 948 else if (tx_multi_xfer->unmap_msg_cnt != tx_multi_xfer->irq_cnt) 949 geni_i2c_gpi_multi_desc_unmap(gi2c, msgs, &peripheral); 950 } 951 952 return num; 953 954 err: 955 dev_err(gi2c->se.dev, "GPI transfer failed: %d\n", ret); 956 dmaengine_terminate_sync(gi2c->rx_c); 957 dmaengine_terminate_sync(gi2c->tx_c); 958 if (gi2c->is_tx_multi_desc_xfer) 959 geni_i2c_gpi_multi_desc_unmap(gi2c, msgs, &peripheral); 960 else 961 geni_i2c_gpi_unmap(gi2c, &msgs[i], tx_buf, tx_addr, rx_buf, rx_addr); 962 963 return ret; 964 } 965 966 static int geni_i2c_fifo_xfer(struct geni_i2c_dev *gi2c, 967 struct i2c_msg msgs[], int num) 968 { 969 int i, ret = 0; 970 971 for (i = 0; i < num; i++) { 972 u32 m_param = i < (num - 1) ? STOP_STRETCH : 0; 973 974 m_param |= ((msgs[i].addr << SLV_ADDR_SHFT) & SLV_ADDR_MSK); 975 976 gi2c->cur = &msgs[i]; 977 gi2c->err = 0; 978 reinit_completion(&gi2c->done); 979 if (msgs[i].flags & I2C_M_RD) 980 ret = geni_i2c_rx_one_msg(gi2c, &msgs[i], m_param); 981 else 982 ret = geni_i2c_tx_one_msg(gi2c, &msgs[i], m_param); 983 984 if (ret) 985 return ret; 986 } 987 988 return num; 989 } 990 991 static int geni_i2c_xfer(struct i2c_adapter *adap, 992 struct i2c_msg msgs[], 993 int num) 994 { 995 struct geni_i2c_dev *gi2c = i2c_get_adapdata(adap); 996 int ret; 997 998 ret = pm_runtime_resume_and_get(gi2c->se.dev); 999 if (ret < 0) { 1000 dev_err(gi2c->se.dev, "error turning SE resources:%d\n", ret); 1001 /* Set device in suspended since resume failed */ 1002 pm_runtime_set_suspended(gi2c->se.dev); 1003 return ret; 1004 } 1005 1006 ret = gi2c->dev_data->set_rate(&gi2c->se, gi2c->clk_freq_out); 1007 if (ret) 1008 goto out_pm; 1009 1010 if (gi2c->gpi_mode) 1011 ret = geni_i2c_gpi_xfer(gi2c, msgs, num); 1012 else 1013 ret = geni_i2c_fifo_xfer(gi2c, msgs, num); 1014 1015 out_pm: 1016 pm_runtime_put_autosuspend(gi2c->se.dev); 1017 gi2c->cur = NULL; 1018 gi2c->err = 0; 1019 return ret; 1020 } 1021 1022 static u32 geni_i2c_func(struct i2c_adapter *adap) 1023 { 1024 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 1025 } 1026 1027 static const struct i2c_algorithm geni_i2c_algo = { 1028 .xfer = geni_i2c_xfer, 1029 .functionality = geni_i2c_func, 1030 }; 1031 1032 static void release_gpi_dma(struct geni_i2c_dev *gi2c) 1033 { 1034 if (gi2c->rx_c) 1035 dma_release_channel(gi2c->rx_c); 1036 1037 if (gi2c->tx_c) 1038 dma_release_channel(gi2c->tx_c); 1039 } 1040 1041 static int setup_gpi_dma(struct geni_i2c_dev *gi2c) 1042 { 1043 int ret; 1044 1045 geni_se_select_mode(&gi2c->se, GENI_GPI_DMA); 1046 gi2c->tx_c = dma_request_chan(gi2c->se.dev, "tx"); 1047 if (IS_ERR(gi2c->tx_c)) { 1048 ret = dev_err_probe(gi2c->se.dev, PTR_ERR(gi2c->tx_c), 1049 "Failed to get tx DMA ch\n"); 1050 goto err_tx; 1051 } 1052 1053 gi2c->rx_c = dma_request_chan(gi2c->se.dev, "rx"); 1054 if (IS_ERR(gi2c->rx_c)) { 1055 ret = dev_err_probe(gi2c->se.dev, PTR_ERR(gi2c->rx_c), 1056 "Failed to get rx DMA ch\n"); 1057 goto err_rx; 1058 } 1059 1060 dev_dbg(gi2c->se.dev, "Grabbed GPI dma channels\n"); 1061 return 0; 1062 1063 err_rx: 1064 dma_release_channel(gi2c->tx_c); 1065 err_tx: 1066 return ret; 1067 } 1068 1069 static int geni_i2c_init(struct geni_i2c_dev *gi2c) 1070 { 1071 u32 proto, tx_depth; 1072 bool fifo_disable; 1073 int ret; 1074 1075 ret = pm_runtime_resume_and_get(gi2c->se.dev); 1076 if (ret < 0) 1077 return dev_err_probe(gi2c->se.dev, ret, "error turning on device\n"); 1078 1079 proto = geni_se_read_proto(&gi2c->se); 1080 if (proto == GENI_SE_INVALID_PROTO) { 1081 ret = geni_load_se_firmware(&gi2c->se, GENI_SE_I2C); 1082 if (ret) { 1083 dev_err_probe(gi2c->se.dev, ret, "i2c firmware load failed ret: %d\n", ret); 1084 goto err; 1085 } 1086 } else if (proto != GENI_SE_I2C) { 1087 ret = dev_err_probe(gi2c->se.dev, -ENXIO, "Invalid proto %d\n", proto); 1088 goto err; 1089 } 1090 1091 if (gi2c->dev_data->no_dma_support) { 1092 fifo_disable = false; 1093 gi2c->no_dma = true; 1094 } else { 1095 fifo_disable = readl_relaxed(gi2c->se.base + GENI_IF_DISABLE_RO) & FIFO_IF_DISABLE; 1096 } 1097 1098 if (fifo_disable) { 1099 /* FIFO is disabled, so we can only use GPI DMA */ 1100 gi2c->gpi_mode = true; 1101 ret = setup_gpi_dma(gi2c); 1102 if (ret) 1103 goto err; 1104 1105 dev_dbg(gi2c->se.dev, "Using GPI DMA mode for I2C\n"); 1106 } else { 1107 gi2c->gpi_mode = false; 1108 tx_depth = geni_se_get_tx_fifo_depth(&gi2c->se); 1109 1110 /* I2C Master Hub Serial Elements doesn't have the HW_PARAM_0 register */ 1111 if (!tx_depth && gi2c->se.core_clk) 1112 tx_depth = gi2c->dev_data->tx_fifo_depth; 1113 1114 if (!tx_depth) { 1115 ret = dev_err_probe(gi2c->se.dev, -EINVAL, 1116 "Invalid TX FIFO depth\n"); 1117 goto err; 1118 } 1119 1120 gi2c->tx_wm = tx_depth - 1; 1121 geni_se_init(&gi2c->se, gi2c->tx_wm, tx_depth); 1122 geni_se_config_packing(&gi2c->se, BITS_PER_BYTE, 1123 PACKING_BYTES_PW, true, true, true); 1124 1125 dev_dbg(gi2c->se.dev, "i2c fifo/se-dma mode. fifo depth:%d\n", tx_depth); 1126 } 1127 1128 err: 1129 pm_runtime_put(gi2c->se.dev); 1130 return ret; 1131 } 1132 1133 static int geni_i2c_resources_init(struct geni_se *se) 1134 { 1135 struct geni_i2c_dev *gi2c = dev_get_drvdata(se->dev); 1136 int ret; 1137 1138 ret = geni_se_resources_init(&gi2c->se); 1139 if (ret) 1140 return ret; 1141 1142 ret = geni_i2c_clk_map_idx(gi2c); 1143 if (ret) 1144 return ret; 1145 1146 return geni_icc_set_bw_ab(&gi2c->se, GENI_DEFAULT_BW, GENI_DEFAULT_BW, 1147 Bps_to_icc(gi2c->clk_freq_out)); 1148 } 1149 1150 static int geni_i2c_probe(struct platform_device *pdev) 1151 { 1152 struct geni_i2c_dev *gi2c; 1153 int ret; 1154 struct device *dev = &pdev->dev; 1155 1156 gi2c = devm_kzalloc(dev, sizeof(*gi2c), GFP_KERNEL); 1157 if (!gi2c) 1158 return -ENOMEM; 1159 1160 gi2c->se.dev = dev; 1161 gi2c->se.wrapper = dev_get_drvdata(dev->parent); 1162 gi2c->se.base = devm_platform_ioremap_resource(pdev, 0); 1163 if (IS_ERR(gi2c->se.base)) 1164 return PTR_ERR(gi2c->se.base); 1165 1166 gi2c->dev_data = device_get_match_data(&pdev->dev); 1167 if (!gi2c->dev_data) 1168 return -EINVAL; 1169 1170 ret = device_property_read_u32(dev, "clock-frequency", 1171 &gi2c->clk_freq_out); 1172 if (ret) { 1173 dev_info(dev, "Bus frequency not specified, default to 100kHz.\n"); 1174 gi2c->clk_freq_out = I2C_MAX_STANDARD_MODE_FREQ; 1175 } 1176 1177 gi2c->irq = platform_get_irq(pdev, 0); 1178 if (gi2c->irq < 0) 1179 return gi2c->irq; 1180 1181 gi2c->adap.algo = &geni_i2c_algo; 1182 init_completion(&gi2c->done); 1183 init_completion(&gi2c->abort_done); 1184 init_completion(&gi2c->cancel_done); 1185 init_completion(&gi2c->tx_reset_done); 1186 init_completion(&gi2c->rx_reset_done); 1187 spin_lock_init(&gi2c->lock); 1188 platform_set_drvdata(pdev, gi2c); 1189 1190 ret = gi2c->dev_data->resources_init(&gi2c->se); 1191 if (ret) 1192 return ret; 1193 1194 /* Keep interrupts disabled initially to allow for low-power modes */ 1195 ret = devm_request_irq(dev, gi2c->irq, geni_i2c_irq, IRQF_NO_AUTOEN, 1196 dev_name(dev), gi2c); 1197 if (ret) 1198 return ret; 1199 1200 i2c_set_adapdata(&gi2c->adap, gi2c); 1201 gi2c->adap.dev.parent = dev; 1202 device_set_node(&gi2c->adap.dev, dev_fwnode(dev)); 1203 strscpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name)); 1204 1205 pm_runtime_set_suspended(dev); 1206 pm_runtime_set_autosuspend_delay(dev, I2C_AUTO_SUSPEND_DELAY); 1207 pm_runtime_use_autosuspend(dev); 1208 1209 ret = devm_pm_runtime_enable(dev); 1210 if (ret) 1211 return ret; 1212 1213 ret = geni_i2c_init(gi2c); 1214 if (ret < 0) 1215 return ret; 1216 1217 ret = i2c_add_adapter(&gi2c->adap); 1218 if (ret) { 1219 release_gpi_dma(gi2c); 1220 return dev_err_probe(dev, ret, "Error adding i2c adapter\n"); 1221 } 1222 1223 dev_dbg(dev, "Geni-I2C adaptor successfully added\n"); 1224 1225 return 0; 1226 } 1227 1228 static void geni_i2c_remove(struct platform_device *pdev) 1229 { 1230 struct geni_i2c_dev *gi2c = platform_get_drvdata(pdev); 1231 1232 i2c_del_adapter(&gi2c->adap); 1233 release_gpi_dma(gi2c); 1234 } 1235 1236 static void geni_i2c_shutdown(struct platform_device *pdev) 1237 { 1238 struct geni_i2c_dev *gi2c = platform_get_drvdata(pdev); 1239 1240 /* Make client i2c transfers start failing */ 1241 i2c_mark_adapter_suspended(&gi2c->adap); 1242 } 1243 1244 static int geni_i2c_runtime_suspend(struct device *dev) 1245 { 1246 int ret = 0; 1247 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev); 1248 1249 disable_irq(gi2c->irq); 1250 1251 if (gi2c->dev_data->power_off) { 1252 ret = gi2c->dev_data->power_off(&gi2c->se); 1253 if (ret) { 1254 enable_irq(gi2c->irq); 1255 return ret; 1256 } 1257 } 1258 1259 return 0; 1260 } 1261 1262 static int geni_i2c_runtime_resume(struct device *dev) 1263 { 1264 int ret = 0; 1265 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev); 1266 1267 if (gi2c->dev_data->power_on) { 1268 ret = gi2c->dev_data->power_on(&gi2c->se); 1269 if (ret) 1270 return ret; 1271 } 1272 1273 enable_irq(gi2c->irq); 1274 1275 return 0; 1276 } 1277 1278 static int geni_i2c_suspend_noirq(struct device *dev) 1279 { 1280 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev); 1281 int ret; 1282 1283 i2c_mark_adapter_suspended(&gi2c->adap); 1284 1285 ret = pm_runtime_force_suspend(dev); 1286 if (ret) 1287 i2c_mark_adapter_resumed(&gi2c->adap); 1288 1289 return ret; 1290 } 1291 1292 static int geni_i2c_resume_noirq(struct device *dev) 1293 { 1294 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev); 1295 int ret; 1296 1297 ret = pm_runtime_force_resume(dev); 1298 if (ret) 1299 return ret; 1300 1301 i2c_mark_adapter_resumed(&gi2c->adap); 1302 return 0; 1303 } 1304 1305 static const struct dev_pm_ops geni_i2c_pm_ops = { 1306 NOIRQ_SYSTEM_SLEEP_PM_OPS(geni_i2c_suspend_noirq, 1307 geni_i2c_resume_noirq) 1308 RUNTIME_PM_OPS(geni_i2c_runtime_suspend, geni_i2c_runtime_resume, 1309 NULL) 1310 }; 1311 1312 static const struct geni_i2c_desc geni_i2c = { 1313 .resources_init = geni_i2c_resources_init, 1314 .set_rate = qcom_geni_i2c_conf, 1315 .power_on = geni_se_resources_activate, 1316 .power_off = geni_se_resources_deactivate, 1317 }; 1318 1319 static const struct geni_i2c_desc i2c_master_hub = { 1320 .no_dma_support = true, 1321 .tx_fifo_depth = 16, 1322 .resources_init = geni_i2c_resources_init, 1323 .set_rate = qcom_geni_i2c_conf, 1324 .power_on = geni_se_resources_activate, 1325 .power_off = geni_se_resources_deactivate, 1326 }; 1327 1328 static const struct geni_i2c_desc sa8255p_geni_i2c = { 1329 .resources_init = geni_se_domain_attach, 1330 .set_rate = geni_se_set_perf_opp, 1331 }; 1332 1333 #ifdef CONFIG_ACPI 1334 static const struct acpi_device_id geni_i2c_acpi_match[] = { 1335 { .id = "QCOM0220", .driver_data = (kernel_ulong_t)&geni_i2c }, 1336 { .id = "QCOM0411", .driver_data = (kernel_ulong_t)&geni_i2c }, 1337 { } 1338 }; 1339 MODULE_DEVICE_TABLE(acpi, geni_i2c_acpi_match); 1340 #endif 1341 1342 static const struct of_device_id geni_i2c_dt_match[] = { 1343 { .compatible = "qcom,geni-i2c", .data = &geni_i2c }, 1344 { .compatible = "qcom,geni-i2c-master-hub", .data = &i2c_master_hub }, 1345 { .compatible = "qcom,sa8255p-geni-i2c", .data = &sa8255p_geni_i2c }, 1346 {} 1347 }; 1348 MODULE_DEVICE_TABLE(of, geni_i2c_dt_match); 1349 1350 static struct platform_driver geni_i2c_driver = { 1351 .probe = geni_i2c_probe, 1352 .remove = geni_i2c_remove, 1353 .shutdown = geni_i2c_shutdown, 1354 .driver = { 1355 .name = "geni_i2c", 1356 .pm = &geni_i2c_pm_ops, 1357 .of_match_table = geni_i2c_dt_match, 1358 .acpi_match_table = ACPI_PTR(geni_i2c_acpi_match), 1359 }, 1360 }; 1361 1362 module_platform_driver(geni_i2c_driver); 1363 1364 MODULE_DESCRIPTION("I2C Controller Driver for GENI based QUP cores"); 1365 MODULE_LICENSE("GPL v2"); 1366