1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * BPF JIT compiler for ARM64 4 * 5 * Copyright (C) 2014-2016 Zi Shen Lim <zlim.lnx@gmail.com> 6 */ 7 8 #define pr_fmt(fmt) "bpf_jit: " fmt 9 10 #include <linux/arm-smccc.h> 11 #include <linux/bitfield.h> 12 #include <linux/bpf.h> 13 #include <linux/cfi.h> 14 #include <linux/filter.h> 15 #include <linux/memory.h> 16 #include <linux/printk.h> 17 #include <linux/slab.h> 18 19 #include <asm/asm-extable.h> 20 #include <asm/byteorder.h> 21 #include <asm/cpufeature.h> 22 #include <asm/debug-monitors.h> 23 #include <asm/insn.h> 24 #include <asm/text-patching.h> 25 #include <asm/set_memory.h> 26 27 #include "bpf_jit.h" 28 29 #define TMP_REG_1 (MAX_BPF_JIT_REG + 0) 30 #define TMP_REG_2 (MAX_BPF_JIT_REG + 1) 31 #define TCCNT_PTR (MAX_BPF_JIT_REG + 2) 32 #define TMP_REG_3 (MAX_BPF_JIT_REG + 3) 33 #define PRIVATE_SP (MAX_BPF_JIT_REG + 4) 34 #define ARENA_VM_START (MAX_BPF_JIT_REG + 5) 35 36 #define check_imm(bits, imm) do { \ 37 if ((((imm) > 0) && ((imm) >> ((bits) - 1))) || \ 38 (((imm) < 0) && (~(imm) >> ((bits) - 1)))) { \ 39 pr_info("[%2d] imm=%d(0x%x) out of range\n", \ 40 i, imm, imm); \ 41 return -EINVAL; \ 42 } \ 43 } while (0) 44 #define check_imm19(imm) check_imm(19, imm) 45 #define check_imm26(imm) check_imm(26, imm) 46 47 /* Map BPF registers to A64 registers */ 48 static const int bpf2a64[] = { 49 /* return value from in-kernel function, and exit value from eBPF */ 50 [BPF_REG_0] = A64_R(8), 51 /* arguments from eBPF program to in-kernel function */ 52 [BPF_REG_1] = A64_R(0), 53 [BPF_REG_2] = A64_R(1), 54 [BPF_REG_3] = A64_R(2), 55 [BPF_REG_4] = A64_R(3), 56 [BPF_REG_5] = A64_R(4), 57 /* callee saved registers that in-kernel function will preserve */ 58 [BPF_REG_6] = A64_R(19), 59 [BPF_REG_7] = A64_R(20), 60 [BPF_REG_8] = A64_R(21), 61 [BPF_REG_9] = A64_R(22), 62 /* read-only frame pointer to access stack */ 63 [BPF_REG_FP] = A64_R(25), 64 /* temporary registers for BPF JIT */ 65 [TMP_REG_1] = A64_R(10), 66 [TMP_REG_2] = A64_R(11), 67 [TMP_REG_3] = A64_R(12), 68 /* tail_call_cnt_ptr */ 69 [TCCNT_PTR] = A64_R(26), 70 /* temporary register for blinding constants */ 71 [BPF_REG_AX] = A64_R(9), 72 /* callee saved register for private stack pointer */ 73 [PRIVATE_SP] = A64_R(27), 74 /* callee saved register for kern_vm_start address */ 75 [ARENA_VM_START] = A64_R(28), 76 }; 77 78 struct jit_ctx { 79 const struct bpf_prog *prog; 80 int idx; 81 int epilogue_offset; 82 int *offset; 83 int exentry_idx; 84 int nr_used_callee_reg; 85 u8 used_callee_reg[8]; /* r6~r9, fp, arena_vm_start */ 86 __le32 *image; 87 __le32 *ro_image; 88 u32 stack_size; 89 u16 stack_arg_size; 90 u64 user_vm_start; 91 u64 arena_vm_start; 92 bool fp_used; 93 bool priv_sp_used; 94 bool write; 95 }; 96 97 struct bpf_plt { 98 u32 insn_ldr; /* load target */ 99 u32 insn_br; /* branch to target */ 100 u64 target; /* target value */ 101 }; 102 103 #define PLT_TARGET_SIZE sizeof_field(struct bpf_plt, target) 104 #define PLT_TARGET_OFFSET offsetof(struct bpf_plt, target) 105 106 /* Memory size/value to protect private stack overflow/underflow */ 107 #define PRIV_STACK_GUARD_SZ 16 108 #define PRIV_STACK_GUARD_VAL 0xEB9F12345678eb9fULL 109 110 static inline void emit(const u32 insn, struct jit_ctx *ctx) 111 { 112 if (ctx->image != NULL && ctx->write) 113 ctx->image[ctx->idx] = cpu_to_le32(insn); 114 115 ctx->idx++; 116 } 117 118 static inline void emit_u32_data(const u32 data, struct jit_ctx *ctx) 119 { 120 if (ctx->image != NULL && ctx->write) 121 ctx->image[ctx->idx] = (__force __le32)data; 122 123 ctx->idx++; 124 } 125 126 static inline void emit_a64_mov_i(const int is64, const int reg, 127 const s32 val, struct jit_ctx *ctx) 128 { 129 u16 hi = val >> 16; 130 u16 lo = val & 0xffff; 131 132 if (hi & 0x8000) { 133 if (hi == 0xffff) { 134 emit(A64_MOVN(is64, reg, (u16)~lo, 0), ctx); 135 } else { 136 emit(A64_MOVN(is64, reg, (u16)~hi, 16), ctx); 137 if (lo != 0xffff) 138 emit(A64_MOVK(is64, reg, lo, 0), ctx); 139 } 140 } else { 141 emit(A64_MOVZ(is64, reg, lo, 0), ctx); 142 if (hi) 143 emit(A64_MOVK(is64, reg, hi, 16), ctx); 144 } 145 } 146 147 static int i64_i16_blocks(const u64 val, bool inverse) 148 { 149 return (((val >> 0) & 0xffff) != (inverse ? 0xffff : 0x0000)) + 150 (((val >> 16) & 0xffff) != (inverse ? 0xffff : 0x0000)) + 151 (((val >> 32) & 0xffff) != (inverse ? 0xffff : 0x0000)) + 152 (((val >> 48) & 0xffff) != (inverse ? 0xffff : 0x0000)); 153 } 154 155 static inline void emit_a64_mov_i64(const int reg, const u64 val, 156 struct jit_ctx *ctx) 157 { 158 u64 nrm_tmp = val, rev_tmp = ~val; 159 bool inverse; 160 int shift; 161 162 if (!(nrm_tmp >> 32)) 163 return emit_a64_mov_i(0, reg, (u32)val, ctx); 164 165 inverse = i64_i16_blocks(nrm_tmp, true) < i64_i16_blocks(nrm_tmp, false); 166 shift = max(round_down((inverse ? (fls64(rev_tmp) - 1) : 167 (fls64(nrm_tmp) - 1)), 16), 0); 168 if (inverse) 169 emit(A64_MOVN(1, reg, (rev_tmp >> shift) & 0xffff, shift), ctx); 170 else 171 emit(A64_MOVZ(1, reg, (nrm_tmp >> shift) & 0xffff, shift), ctx); 172 shift -= 16; 173 while (shift >= 0) { 174 if (((nrm_tmp >> shift) & 0xffff) != (inverse ? 0xffff : 0x0000)) 175 emit(A64_MOVK(1, reg, (nrm_tmp >> shift) & 0xffff, shift), ctx); 176 shift -= 16; 177 } 178 } 179 180 static inline void emit_bti(u32 insn, struct jit_ctx *ctx) 181 { 182 if (IS_ENABLED(CONFIG_ARM64_BTI_KERNEL)) 183 emit(insn, ctx); 184 } 185 186 static inline void emit_kcfi(u32 hash, struct jit_ctx *ctx) 187 { 188 if (IS_ENABLED(CONFIG_CFI)) 189 emit_u32_data(hash, ctx); 190 } 191 192 /* 193 * Kernel addresses in the vmalloc space use at most 48 bits, and the 194 * remaining bits are guaranteed to be 0x1. So we can compose the address 195 * with a fixed length movn/movk/movk sequence. 196 */ 197 static inline void emit_addr_mov_i64(const int reg, const u64 val, 198 struct jit_ctx *ctx) 199 { 200 u64 tmp = val; 201 int shift = 0; 202 203 emit(A64_MOVN(1, reg, ~tmp & 0xffff, shift), ctx); 204 while (shift < 32) { 205 tmp >>= 16; 206 shift += 16; 207 emit(A64_MOVK(1, reg, tmp & 0xffff, shift), ctx); 208 } 209 } 210 211 static bool should_emit_indirect_call(long target, const struct jit_ctx *ctx) 212 { 213 long offset; 214 215 /* when ctx->ro_image is not allocated or the target is unknown, 216 * emit indirect call 217 */ 218 if (!ctx->ro_image || !target) 219 return true; 220 221 offset = target - (long)&ctx->ro_image[ctx->idx]; 222 return offset < -SZ_128M || offset >= SZ_128M; 223 } 224 225 static void emit_direct_call(u64 target, struct jit_ctx *ctx) 226 { 227 u32 insn; 228 unsigned long pc; 229 230 pc = (unsigned long)&ctx->ro_image[ctx->idx]; 231 insn = aarch64_insn_gen_branch_imm(pc, target, AARCH64_INSN_BRANCH_LINK); 232 emit(insn, ctx); 233 } 234 235 static void emit_indirect_call(u64 target, struct jit_ctx *ctx) 236 { 237 u8 tmp; 238 239 tmp = bpf2a64[TMP_REG_1]; 240 emit_addr_mov_i64(tmp, target, ctx); 241 emit(A64_BLR(tmp), ctx); 242 } 243 244 static void emit_call(u64 target, struct jit_ctx *ctx) 245 { 246 if (should_emit_indirect_call((long)target, ctx)) 247 emit_indirect_call(target, ctx); 248 else 249 emit_direct_call(target, ctx); 250 } 251 252 static inline int bpf2a64_offset(int bpf_insn, int off, 253 const struct jit_ctx *ctx) 254 { 255 /* BPF JMP offset is relative to the next instruction */ 256 bpf_insn++; 257 /* 258 * Whereas arm64 branch instructions encode the offset 259 * from the branch itself, so we must subtract 1 from the 260 * instruction offset. 261 */ 262 return ctx->offset[bpf_insn + off] - (ctx->offset[bpf_insn] - 1); 263 } 264 265 static void jit_fill_hole(void *area, unsigned int size) 266 { 267 __le32 *ptr; 268 /* We are guaranteed to have aligned memory. */ 269 for (ptr = area; size >= sizeof(u32); size -= sizeof(u32)) 270 *ptr++ = cpu_to_le32(AARCH64_BREAK_FAULT); 271 } 272 273 int bpf_arch_text_invalidate(void *dst, size_t len) 274 { 275 if (!aarch64_insn_set(dst, AARCH64_BREAK_FAULT, len)) 276 return -EINVAL; 277 278 return 0; 279 } 280 281 static inline int epilogue_offset(const struct jit_ctx *ctx) 282 { 283 int to = ctx->epilogue_offset; 284 int from = ctx->idx; 285 286 return to - from; 287 } 288 289 static bool is_addsub_imm(u32 imm) 290 { 291 /* Either imm12 or shifted imm12. */ 292 return !(imm & ~0xfff) || !(imm & ~0xfff000); 293 } 294 295 static inline void emit_a64_add_i(const bool is64, const int dst, const int src, 296 const int tmp, const s32 imm, struct jit_ctx *ctx) 297 { 298 if (is_addsub_imm(imm)) { 299 emit(A64_ADD_I(is64, dst, src, imm), ctx); 300 } else if (is_addsub_imm(-(u32)imm)) { 301 emit(A64_SUB_I(is64, dst, src, -imm), ctx); 302 } else { 303 emit_a64_mov_i(is64, tmp, imm, ctx); 304 emit(A64_ADD(is64, dst, src, tmp), ctx); 305 } 306 } 307 308 /* 309 * There are 3 types of AArch64 LDR/STR (immediate) instruction: 310 * Post-index, Pre-index, Unsigned offset. 311 * 312 * For BPF ldr/str, the "unsigned offset" type is sufficient. 313 * 314 * "Unsigned offset" type LDR(immediate) format: 315 * 316 * 3 2 1 0 317 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 318 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 319 * |x x|1 1 1 0 0 1 0 1| imm12 | Rn | Rt | 320 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 321 * scale 322 * 323 * "Unsigned offset" type STR(immediate) format: 324 * 3 2 1 0 325 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 326 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 327 * |x x|1 1 1 0 0 1 0 0| imm12 | Rn | Rt | 328 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 329 * scale 330 * 331 * The offset is calculated from imm12 and scale in the following way: 332 * 333 * offset = (u64)imm12 << scale 334 */ 335 static bool is_lsi_offset(int offset, int scale) 336 { 337 if (offset < 0) 338 return false; 339 340 if (offset > (0xFFF << scale)) 341 return false; 342 343 if (offset & ((1 << scale) - 1)) 344 return false; 345 346 return true; 347 } 348 349 /* generated main prog prologue: 350 * bti c // if CONFIG_ARM64_BTI_KERNEL 351 * mov x9, lr 352 * nop // POKE_OFFSET 353 * paciasp // if CONFIG_ARM64_PTR_AUTH_KERNEL 354 * stp x29, lr, [sp, #-16]! 355 * mov x29, sp 356 * stp xzr, x26, [sp, #-16]! 357 * mov x26, sp 358 * // PROLOGUE_OFFSET 359 * // save callee-saved registers 360 */ 361 static void prepare_bpf_tail_call_cnt(struct jit_ctx *ctx) 362 { 363 const bool is_main_prog = !bpf_is_subprog(ctx->prog); 364 const u8 ptr = bpf2a64[TCCNT_PTR]; 365 366 if (is_main_prog) { 367 /* Initialize tail_call_cnt. */ 368 emit(A64_PUSH(A64_ZR, ptr, A64_SP), ctx); 369 emit(A64_MOV(1, ptr, A64_SP), ctx); 370 } else 371 emit(A64_PUSH(ptr, ptr, A64_SP), ctx); 372 } 373 374 static void find_used_callee_regs(struct jit_ctx *ctx) 375 { 376 int i; 377 const struct bpf_prog *prog = ctx->prog; 378 const struct bpf_insn *insn = &prog->insnsi[0]; 379 int reg_used = 0; 380 381 for (i = 0; i < prog->len; i++, insn++) { 382 if (insn->dst_reg == BPF_REG_6 || insn->src_reg == BPF_REG_6) 383 reg_used |= 1; 384 385 if (insn->dst_reg == BPF_REG_7 || insn->src_reg == BPF_REG_7) 386 reg_used |= 2; 387 388 if (insn->dst_reg == BPF_REG_8 || insn->src_reg == BPF_REG_8) 389 reg_used |= 4; 390 391 if (insn->dst_reg == BPF_REG_9 || insn->src_reg == BPF_REG_9) 392 reg_used |= 8; 393 394 if (insn->dst_reg == BPF_REG_FP || insn->src_reg == BPF_REG_FP) { 395 ctx->fp_used = true; 396 reg_used |= 16; 397 } 398 } 399 400 i = 0; 401 if (reg_used & 1) 402 ctx->used_callee_reg[i++] = bpf2a64[BPF_REG_6]; 403 404 if (reg_used & 2) 405 ctx->used_callee_reg[i++] = bpf2a64[BPF_REG_7]; 406 407 if (reg_used & 4) 408 ctx->used_callee_reg[i++] = bpf2a64[BPF_REG_8]; 409 410 if (reg_used & 8) 411 ctx->used_callee_reg[i++] = bpf2a64[BPF_REG_9]; 412 413 if (reg_used & 16) { 414 ctx->used_callee_reg[i++] = bpf2a64[BPF_REG_FP]; 415 if (ctx->priv_sp_used) 416 ctx->used_callee_reg[i++] = bpf2a64[PRIVATE_SP]; 417 } 418 419 if (ctx->arena_vm_start) 420 ctx->used_callee_reg[i++] = bpf2a64[ARENA_VM_START]; 421 422 ctx->nr_used_callee_reg = i; 423 } 424 425 /* Save callee-saved registers */ 426 static void push_callee_regs(struct jit_ctx *ctx) 427 { 428 int reg1, reg2, i; 429 430 /* 431 * Program acting as exception boundary should save all ARM64 432 * Callee-saved registers as the exception callback needs to recover 433 * all ARM64 Callee-saved registers in its epilogue. 434 */ 435 if (ctx->prog->aux->exception_boundary) { 436 emit(A64_PUSH(A64_R(19), A64_R(20), A64_SP), ctx); 437 emit(A64_PUSH(A64_R(21), A64_R(22), A64_SP), ctx); 438 emit(A64_PUSH(A64_R(23), A64_R(24), A64_SP), ctx); 439 emit(A64_PUSH(A64_R(25), A64_R(26), A64_SP), ctx); 440 emit(A64_PUSH(A64_R(27), A64_R(28), A64_SP), ctx); 441 ctx->fp_used = true; 442 } else { 443 find_used_callee_regs(ctx); 444 for (i = 0; i + 1 < ctx->nr_used_callee_reg; i += 2) { 445 reg1 = ctx->used_callee_reg[i]; 446 reg2 = ctx->used_callee_reg[i + 1]; 447 emit(A64_PUSH(reg1, reg2, A64_SP), ctx); 448 } 449 if (i < ctx->nr_used_callee_reg) { 450 reg1 = ctx->used_callee_reg[i]; 451 /* keep SP 16-byte aligned */ 452 emit(A64_PUSH(reg1, A64_ZR, A64_SP), ctx); 453 } 454 } 455 } 456 457 /* Restore callee-saved registers */ 458 static void pop_callee_regs(struct jit_ctx *ctx) 459 { 460 struct bpf_prog_aux *aux = ctx->prog->aux; 461 int reg1, reg2, i; 462 463 /* 464 * Program acting as exception boundary pushes R23 and R24 in addition 465 * to BPF callee-saved registers. Exception callback uses the boundary 466 * program's stack frame, so recover these extra registers in the above 467 * two cases. 468 */ 469 if (aux->exception_boundary || aux->exception_cb) { 470 emit(A64_POP(A64_R(27), A64_R(28), A64_SP), ctx); 471 emit(A64_POP(A64_R(25), A64_R(26), A64_SP), ctx); 472 emit(A64_POP(A64_R(23), A64_R(24), A64_SP), ctx); 473 emit(A64_POP(A64_R(21), A64_R(22), A64_SP), ctx); 474 emit(A64_POP(A64_R(19), A64_R(20), A64_SP), ctx); 475 } else { 476 i = ctx->nr_used_callee_reg - 1; 477 if (ctx->nr_used_callee_reg % 2 != 0) { 478 reg1 = ctx->used_callee_reg[i]; 479 emit(A64_POP(reg1, A64_ZR, A64_SP), ctx); 480 i--; 481 } 482 while (i > 0) { 483 reg1 = ctx->used_callee_reg[i - 1]; 484 reg2 = ctx->used_callee_reg[i]; 485 emit(A64_POP(reg1, reg2, A64_SP), ctx); 486 i -= 2; 487 } 488 } 489 } 490 491 static void emit_percpu_ptr(const u8 dst_reg, void __percpu *ptr, 492 struct jit_ctx *ctx) 493 { 494 const u8 tmp = bpf2a64[TMP_REG_1]; 495 496 emit_a64_mov_i64(dst_reg, (__force const u64)ptr, ctx); 497 if (cpus_have_cap(ARM64_HAS_VIRT_HOST_EXTN)) 498 emit(A64_MRS_TPIDR_EL2(tmp), ctx); 499 else 500 emit(A64_MRS_TPIDR_EL1(tmp), ctx); 501 emit(A64_ADD(1, dst_reg, dst_reg, tmp), ctx); 502 } 503 504 #define BTI_INSNS (IS_ENABLED(CONFIG_ARM64_BTI_KERNEL) ? 1 : 0) 505 #define PAC_INSNS (IS_ENABLED(CONFIG_ARM64_PTR_AUTH_KERNEL) ? 1 : 0) 506 507 /* Offset of nop instruction in bpf prog entry to be poked */ 508 #define POKE_OFFSET (BTI_INSNS + 1) 509 510 /* Tail call offset to jump into */ 511 #define PROLOGUE_OFFSET (BTI_INSNS + 2 + PAC_INSNS + 4) 512 513 static int build_prologue(struct jit_ctx *ctx, bool ebpf_from_cbpf) 514 { 515 const struct bpf_prog *prog = ctx->prog; 516 const bool is_main_prog = !bpf_is_subprog(prog); 517 const u8 fp = bpf2a64[BPF_REG_FP]; 518 const u8 arena_vm_base = bpf2a64[ARENA_VM_START]; 519 const u8 priv_sp = bpf2a64[PRIVATE_SP]; 520 void __percpu *priv_stack_ptr; 521 int cur_offset; 522 523 /* 524 * BPF prog stack layout 525 * 526 * high 527 * original A64_SP => 0:+-----+ BPF prologue 528 * |FP/LR| 529 * current A64_FP => -16:+-----+ 530 * | ... | callee saved registers 531 * BPF fp register => -64:+-----+ <= (BPF_FP) 532 * | | 533 * | ... | BPF prog stack 534 * | | 535 * +-----+ <= (BPF_FP - prog->aux->stack_depth) 536 * |RSVD | padding 537 * +-----+ <= (BPF_FP - ctx->stack_size) 538 * | | 539 * | ... | outgoing stack args (9+, if any) 540 * | | 541 * current A64_SP => +-----+ 542 * | | 543 * | ... | Function call stack 544 * | | 545 * +-----+ 546 * low 547 * 548 * Stack args 6-8 are passed in x5-x7, args 9+ at [SP]. 549 * Incoming args 9+ are at [A64_FP + 16], [A64_FP + 24], ... 550 * (above the saved FP/LR pair pushed in the callee prologue). 551 */ 552 553 emit_kcfi(is_main_prog ? cfi_bpf_hash : cfi_bpf_subprog_hash, ctx); 554 const int idx0 = ctx->idx; 555 556 /* bpf function may be invoked by 3 instruction types: 557 * 1. bl, attached via freplace to bpf prog via short jump 558 * 2. br, attached via freplace to bpf prog via long jump 559 * 3. blr, working as a function pointer, used by emit_call. 560 * So BTI_JC should used here to support both br and blr. 561 */ 562 emit_bti(A64_BTI_JC, ctx); 563 564 emit(A64_MOV(1, A64_R(9), A64_LR), ctx); 565 emit(A64_NOP, ctx); 566 567 if (!prog->aux->exception_cb) { 568 /* Sign lr */ 569 if (IS_ENABLED(CONFIG_ARM64_PTR_AUTH_KERNEL)) 570 emit(A64_PACIASP, ctx); 571 572 /* Save FP and LR registers to stay align with ARM64 AAPCS */ 573 emit(A64_PUSH(A64_FP, A64_LR, A64_SP), ctx); 574 emit(A64_MOV(1, A64_FP, A64_SP), ctx); 575 576 prepare_bpf_tail_call_cnt(ctx); 577 578 if (!ebpf_from_cbpf && is_main_prog) { 579 cur_offset = ctx->idx - idx0; 580 if (cur_offset != PROLOGUE_OFFSET) { 581 pr_err_once("PROLOGUE_OFFSET = %d, expected %d!\n", 582 cur_offset, PROLOGUE_OFFSET); 583 return -1; 584 } 585 /* BTI landing pad for the tail call, done with a BR */ 586 emit_bti(A64_BTI_J, ctx); 587 } 588 push_callee_regs(ctx); 589 } else { 590 /* 591 * Exception callback receives FP of Main Program as third 592 * parameter 593 */ 594 emit(A64_MOV(1, A64_FP, A64_R(2)), ctx); 595 /* 596 * Main Program already pushed the frame record and the 597 * callee-saved registers. The exception callback will not push 598 * anything and re-use the main program's stack. 599 * 600 * 12 registers are on the stack 601 */ 602 emit(A64_SUB_I(1, A64_SP, A64_FP, 96), ctx); 603 /* The callback may use its own BPF stack, set up fp for it. */ 604 ctx->fp_used = true; 605 } 606 607 /* Stack must be multiples of 16B */ 608 ctx->stack_size = round_up(prog->aux->stack_depth, 16); 609 610 if (ctx->fp_used) { 611 if (ctx->priv_sp_used) { 612 /* Set up private stack pointer */ 613 priv_stack_ptr = prog->aux->priv_stack_ptr + PRIV_STACK_GUARD_SZ; 614 emit_percpu_ptr(priv_sp, priv_stack_ptr, ctx); 615 emit(A64_ADD_I(1, fp, priv_sp, ctx->stack_size), ctx); 616 } else { 617 /* Set up BPF prog stack base register */ 618 emit(A64_MOV(1, fp, A64_SP), ctx); 619 } 620 } 621 622 /* Set up function call stack */ 623 if (ctx->stack_size && !ctx->priv_sp_used) 624 emit(A64_SUB_I(1, A64_SP, A64_SP, ctx->stack_size), ctx); 625 626 if (ctx->stack_arg_size) 627 emit(A64_SUB_I(1, A64_SP, A64_SP, ctx->stack_arg_size), ctx); 628 629 if (ctx->arena_vm_start) 630 emit_a64_mov_i64(arena_vm_base, ctx->arena_vm_start, ctx); 631 632 return 0; 633 } 634 635 static int emit_bpf_tail_call(struct jit_ctx *ctx) 636 { 637 /* bpf_tail_call(void *prog_ctx, struct bpf_array *array, u64 index) */ 638 const u8 r2 = bpf2a64[BPF_REG_2]; 639 const u8 r3 = bpf2a64[BPF_REG_3]; 640 641 const u8 tmp = bpf2a64[TMP_REG_1]; 642 const u8 prg = bpf2a64[TMP_REG_2]; 643 const u8 tcc = bpf2a64[TMP_REG_3]; 644 const u8 ptr = bpf2a64[TCCNT_PTR]; 645 size_t off; 646 __le32 *branch1 = NULL; 647 __le32 *branch2 = NULL; 648 __le32 *branch3 = NULL; 649 650 /* if (index >= array->map.max_entries) 651 * goto out; 652 */ 653 off = offsetof(struct bpf_array, map.max_entries); 654 emit_a64_mov_i64(tmp, off, ctx); 655 emit(A64_LDR32(tmp, r2, tmp), ctx); 656 emit(A64_MOV(0, r3, r3), ctx); 657 emit(A64_CMP(0, r3, tmp), ctx); 658 branch1 = ctx->image + ctx->idx; 659 emit(A64_NOP, ctx); 660 661 /* 662 * if ((*tail_call_cnt_ptr) >= MAX_TAIL_CALL_CNT) 663 * goto out; 664 */ 665 emit_a64_mov_i64(tmp, MAX_TAIL_CALL_CNT, ctx); 666 emit(A64_LDR64I(tcc, ptr, 0), ctx); 667 emit(A64_CMP(1, tcc, tmp), ctx); 668 branch2 = ctx->image + ctx->idx; 669 emit(A64_NOP, ctx); 670 671 /* (*tail_call_cnt_ptr)++; */ 672 emit(A64_ADD_I(1, tcc, tcc, 1), ctx); 673 674 /* prog = array->ptrs[index]; 675 * if (prog == NULL) 676 * goto out; 677 */ 678 off = offsetof(struct bpf_array, ptrs); 679 emit_a64_mov_i64(tmp, off, ctx); 680 emit(A64_ADD(1, tmp, r2, tmp), ctx); 681 emit(A64_LSL(1, prg, r3, 3), ctx); 682 emit(A64_LDR64(prg, tmp, prg), ctx); 683 branch3 = ctx->image + ctx->idx; 684 emit(A64_NOP, ctx); 685 686 /* Update tail_call_cnt if the slot is populated. */ 687 emit(A64_STR64I(tcc, ptr, 0), ctx); 688 689 if (ctx->stack_arg_size) 690 emit(A64_ADD_I(1, A64_SP, A64_SP, ctx->stack_arg_size), ctx); 691 692 /* restore SP */ 693 if (ctx->stack_size && !ctx->priv_sp_used) 694 emit(A64_ADD_I(1, A64_SP, A64_SP, ctx->stack_size), ctx); 695 696 pop_callee_regs(ctx); 697 698 /* goto *(prog->bpf_func + prologue_offset); */ 699 off = offsetof(struct bpf_prog, bpf_func); 700 emit_a64_mov_i64(tmp, off, ctx); 701 emit(A64_LDR64(tmp, prg, tmp), ctx); 702 emit(A64_ADD_I(1, tmp, tmp, sizeof(u32) * PROLOGUE_OFFSET), ctx); 703 emit(A64_BR(tmp), ctx); 704 705 if (ctx->image) { 706 off = &ctx->image[ctx->idx] - branch1; 707 *branch1 = cpu_to_le32(A64_B_(A64_COND_CS, off)); 708 709 off = &ctx->image[ctx->idx] - branch2; 710 *branch2 = cpu_to_le32(A64_B_(A64_COND_CS, off)); 711 712 off = &ctx->image[ctx->idx] - branch3; 713 *branch3 = cpu_to_le32(A64_CBZ(1, prg, off)); 714 } 715 716 return 0; 717 } 718 719 static int emit_atomic_ld_st(const struct bpf_insn *insn, struct jit_ctx *ctx) 720 { 721 const s32 imm = insn->imm; 722 const s16 off = insn->off; 723 const u8 code = insn->code; 724 const bool arena = BPF_MODE(code) == BPF_PROBE_ATOMIC; 725 const u8 arena_vm_base = bpf2a64[ARENA_VM_START]; 726 const u8 dst = bpf2a64[insn->dst_reg]; 727 const u8 src = bpf2a64[insn->src_reg]; 728 const u8 tmp = bpf2a64[TMP_REG_1]; 729 u8 reg; 730 731 switch (imm) { 732 case BPF_LOAD_ACQ: 733 reg = src; 734 break; 735 case BPF_STORE_REL: 736 reg = dst; 737 break; 738 default: 739 pr_err_once("unknown atomic load/store op code %02x\n", imm); 740 return -EINVAL; 741 } 742 743 if (off) { 744 emit_a64_add_i(1, tmp, reg, tmp, off, ctx); 745 reg = tmp; 746 } 747 if (arena) { 748 emit(A64_ADD(1, tmp, reg, arena_vm_base), ctx); 749 reg = tmp; 750 } 751 752 switch (imm) { 753 case BPF_LOAD_ACQ: 754 switch (BPF_SIZE(code)) { 755 case BPF_B: 756 emit(A64_LDARB(dst, reg), ctx); 757 break; 758 case BPF_H: 759 emit(A64_LDARH(dst, reg), ctx); 760 break; 761 case BPF_W: 762 emit(A64_LDAR32(dst, reg), ctx); 763 break; 764 case BPF_DW: 765 emit(A64_LDAR64(dst, reg), ctx); 766 break; 767 } 768 break; 769 case BPF_STORE_REL: 770 switch (BPF_SIZE(code)) { 771 case BPF_B: 772 emit(A64_STLRB(src, reg), ctx); 773 break; 774 case BPF_H: 775 emit(A64_STLRH(src, reg), ctx); 776 break; 777 case BPF_W: 778 emit(A64_STLR32(src, reg), ctx); 779 break; 780 case BPF_DW: 781 emit(A64_STLR64(src, reg), ctx); 782 break; 783 } 784 break; 785 default: 786 pr_err_once("unexpected atomic load/store op code %02x\n", 787 imm); 788 return -EINVAL; 789 } 790 791 return 0; 792 } 793 794 static int emit_lse_atomic(const struct bpf_insn *insn, struct jit_ctx *ctx) 795 { 796 const u8 code = insn->code; 797 const u8 arena_vm_base = bpf2a64[ARENA_VM_START]; 798 const u8 dst = bpf2a64[insn->dst_reg]; 799 const u8 src = bpf2a64[insn->src_reg]; 800 const u8 tmp = bpf2a64[TMP_REG_1]; 801 const u8 tmp2 = bpf2a64[TMP_REG_2]; 802 const bool isdw = BPF_SIZE(code) == BPF_DW; 803 const bool arena = BPF_MODE(code) == BPF_PROBE_ATOMIC; 804 const s16 off = insn->off; 805 u8 reg = dst; 806 807 if (off) { 808 emit_a64_add_i(1, tmp, reg, tmp, off, ctx); 809 reg = tmp; 810 } 811 if (arena) { 812 emit(A64_ADD(1, tmp, reg, arena_vm_base), ctx); 813 reg = tmp; 814 } 815 816 switch (insn->imm) { 817 /* lock *(u32/u64 *)(dst_reg + off) <op>= src_reg */ 818 case BPF_ADD: 819 emit(A64_STADD(isdw, reg, src), ctx); 820 break; 821 case BPF_AND: 822 emit(A64_MVN(isdw, tmp2, src), ctx); 823 emit(A64_STCLR(isdw, reg, tmp2), ctx); 824 break; 825 case BPF_OR: 826 emit(A64_STSET(isdw, reg, src), ctx); 827 break; 828 case BPF_XOR: 829 emit(A64_STEOR(isdw, reg, src), ctx); 830 break; 831 /* src_reg = atomic_fetch_<op>(dst_reg + off, src_reg) */ 832 case BPF_ADD | BPF_FETCH: 833 emit(A64_LDADDAL(isdw, src, reg, src), ctx); 834 break; 835 case BPF_AND | BPF_FETCH: 836 emit(A64_MVN(isdw, tmp2, src), ctx); 837 emit(A64_LDCLRAL(isdw, src, reg, tmp2), ctx); 838 break; 839 case BPF_OR | BPF_FETCH: 840 emit(A64_LDSETAL(isdw, src, reg, src), ctx); 841 break; 842 case BPF_XOR | BPF_FETCH: 843 emit(A64_LDEORAL(isdw, src, reg, src), ctx); 844 break; 845 /* src_reg = atomic_xchg(dst_reg + off, src_reg); */ 846 case BPF_XCHG: 847 emit(A64_SWPAL(isdw, src, reg, src), ctx); 848 break; 849 /* r0 = atomic_cmpxchg(dst_reg + off, r0, src_reg); */ 850 case BPF_CMPXCHG: 851 emit(A64_CASAL(isdw, src, reg, bpf2a64[BPF_REG_0]), ctx); 852 break; 853 default: 854 pr_err_once("unknown atomic op code %02x\n", insn->imm); 855 return -EINVAL; 856 } 857 858 return 0; 859 } 860 861 static int emit_ll_sc_atomic(const struct bpf_insn *insn, struct jit_ctx *ctx) 862 { 863 const u8 code = insn->code; 864 const u8 dst = bpf2a64[insn->dst_reg]; 865 const u8 src = bpf2a64[insn->src_reg]; 866 const u8 tmp = bpf2a64[TMP_REG_1]; 867 const u8 tmp2 = bpf2a64[TMP_REG_2]; 868 const u8 tmp3 = bpf2a64[TMP_REG_3]; 869 const int i = insn - ctx->prog->insnsi; 870 const s32 imm = insn->imm; 871 const s16 off = insn->off; 872 const bool isdw = BPF_SIZE(code) == BPF_DW; 873 u8 reg = dst; 874 s32 jmp_offset; 875 876 if (BPF_MODE(code) == BPF_PROBE_ATOMIC) { 877 /* ll_sc based atomics don't support unsafe pointers yet. */ 878 pr_err_once("unknown atomic opcode %02x\n", code); 879 return -EINVAL; 880 } 881 882 if (off) { 883 emit_a64_add_i(1, tmp, reg, tmp, off, ctx); 884 reg = tmp; 885 } 886 887 if (imm == BPF_ADD || imm == BPF_AND || 888 imm == BPF_OR || imm == BPF_XOR) { 889 /* lock *(u32/u64 *)(dst_reg + off) <op>= src_reg */ 890 emit(A64_LDXR(isdw, tmp2, reg), ctx); 891 if (imm == BPF_ADD) 892 emit(A64_ADD(isdw, tmp2, tmp2, src), ctx); 893 else if (imm == BPF_AND) 894 emit(A64_AND(isdw, tmp2, tmp2, src), ctx); 895 else if (imm == BPF_OR) 896 emit(A64_ORR(isdw, tmp2, tmp2, src), ctx); 897 else 898 emit(A64_EOR(isdw, tmp2, tmp2, src), ctx); 899 emit(A64_STXR(isdw, tmp2, reg, tmp3), ctx); 900 jmp_offset = -3; 901 check_imm19(jmp_offset); 902 emit(A64_CBNZ(0, tmp3, jmp_offset), ctx); 903 } else if (imm == (BPF_ADD | BPF_FETCH) || 904 imm == (BPF_AND | BPF_FETCH) || 905 imm == (BPF_OR | BPF_FETCH) || 906 imm == (BPF_XOR | BPF_FETCH)) { 907 /* src_reg = atomic_fetch_<op>(dst_reg + off, src_reg) */ 908 const u8 ax = bpf2a64[BPF_REG_AX]; 909 910 emit(A64_MOV(isdw, ax, src), ctx); 911 emit(A64_LDXR(isdw, src, reg), ctx); 912 if (imm == (BPF_ADD | BPF_FETCH)) 913 emit(A64_ADD(isdw, tmp2, src, ax), ctx); 914 else if (imm == (BPF_AND | BPF_FETCH)) 915 emit(A64_AND(isdw, tmp2, src, ax), ctx); 916 else if (imm == (BPF_OR | BPF_FETCH)) 917 emit(A64_ORR(isdw, tmp2, src, ax), ctx); 918 else 919 emit(A64_EOR(isdw, tmp2, src, ax), ctx); 920 emit(A64_STLXR(isdw, tmp2, reg, tmp3), ctx); 921 jmp_offset = -3; 922 check_imm19(jmp_offset); 923 emit(A64_CBNZ(0, tmp3, jmp_offset), ctx); 924 emit(A64_DMB_ISH, ctx); 925 } else if (imm == BPF_XCHG) { 926 /* src_reg = atomic_xchg(dst_reg + off, src_reg); */ 927 emit(A64_MOV(isdw, tmp2, src), ctx); 928 emit(A64_LDXR(isdw, src, reg), ctx); 929 emit(A64_STLXR(isdw, tmp2, reg, tmp3), ctx); 930 jmp_offset = -2; 931 check_imm19(jmp_offset); 932 emit(A64_CBNZ(0, tmp3, jmp_offset), ctx); 933 emit(A64_DMB_ISH, ctx); 934 } else if (imm == BPF_CMPXCHG) { 935 /* r0 = atomic_cmpxchg(dst_reg + off, r0, src_reg); */ 936 const u8 r0 = bpf2a64[BPF_REG_0]; 937 938 emit(A64_MOV(isdw, tmp2, r0), ctx); 939 emit(A64_LDXR(isdw, r0, reg), ctx); 940 emit(A64_EOR(isdw, tmp3, r0, tmp2), ctx); 941 jmp_offset = 4; 942 check_imm19(jmp_offset); 943 emit(A64_CBNZ(isdw, tmp3, jmp_offset), ctx); 944 emit(A64_STLXR(isdw, src, reg, tmp3), ctx); 945 jmp_offset = -4; 946 check_imm19(jmp_offset); 947 emit(A64_CBNZ(0, tmp3, jmp_offset), ctx); 948 emit(A64_DMB_ISH, ctx); 949 } else { 950 pr_err_once("unknown atomic op code %02x\n", imm); 951 return -EINVAL; 952 } 953 954 return 0; 955 } 956 957 void dummy_tramp(void); 958 959 asm ( 960 " .pushsection .text, \"ax\", @progbits\n" 961 " .global dummy_tramp\n" 962 " .type dummy_tramp, %function\n" 963 "dummy_tramp:" 964 #if IS_ENABLED(CONFIG_ARM64_BTI_KERNEL) 965 " bti j\n" /* dummy_tramp is called via "br x10" */ 966 #endif 967 " mov x10, x30\n" 968 " mov x30, x9\n" 969 " ret x10\n" 970 " .size dummy_tramp, .-dummy_tramp\n" 971 " .popsection\n" 972 ); 973 974 /* build a plt initialized like this: 975 * 976 * plt: 977 * ldr tmp, target 978 * br tmp 979 * target: 980 * .quad dummy_tramp 981 * 982 * when a long jump trampoline is attached, target is filled with the 983 * trampoline address, and when the trampoline is removed, target is 984 * restored to dummy_tramp address. 985 */ 986 static void build_plt(struct jit_ctx *ctx) 987 { 988 const u8 tmp = bpf2a64[TMP_REG_1]; 989 struct bpf_plt *plt = NULL; 990 991 /* make sure target is 64-bit aligned */ 992 if ((ctx->idx + PLT_TARGET_OFFSET / AARCH64_INSN_SIZE) % 2) 993 emit(A64_NOP, ctx); 994 995 plt = (struct bpf_plt *)(ctx->image + ctx->idx); 996 /* plt is called via bl, no BTI needed here */ 997 emit(A64_LDR64LIT(tmp, 2 * AARCH64_INSN_SIZE), ctx); 998 emit(A64_BR(tmp), ctx); 999 1000 if (ctx->image) 1001 plt->target = (u64)&dummy_tramp; 1002 } 1003 1004 /* Clobbers BPF registers 1-4, aka x0-x3 */ 1005 static void __maybe_unused build_bhb_mitigation(struct jit_ctx *ctx) 1006 { 1007 const u8 r1 = bpf2a64[BPF_REG_1]; /* aka x0 */ 1008 u8 k = get_spectre_bhb_loop_value(); 1009 1010 if (!IS_ENABLED(CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY) || 1011 cpu_mitigations_off() || __nospectre_bhb || 1012 arm64_get_spectre_v2_state() == SPECTRE_VULNERABLE) 1013 return; 1014 1015 if (ns_capable_noaudit(&init_user_ns, CAP_SYS_ADMIN)) 1016 return; 1017 1018 if (supports_clearbhb(SCOPE_SYSTEM)) { 1019 emit(aarch64_insn_gen_hint(AARCH64_INSN_HINT_CLEARBHB), ctx); 1020 return; 1021 } 1022 1023 if (k) { 1024 emit_a64_mov_i64(r1, k, ctx); 1025 emit(A64_B(1), ctx); 1026 emit(A64_SUBS_I(true, r1, r1, 1), ctx); 1027 emit(A64_B_(A64_COND_NE, -2), ctx); 1028 emit(aarch64_insn_gen_dsb(AARCH64_INSN_MB_ISH), ctx); 1029 emit(aarch64_insn_get_isb_value(), ctx); 1030 } 1031 1032 if (is_spectre_bhb_fw_mitigated()) { 1033 emit(A64_ORR_I(false, r1, AARCH64_INSN_REG_ZR, 1034 ARM_SMCCC_ARCH_WORKAROUND_3), ctx); 1035 switch (arm_smccc_1_1_get_conduit()) { 1036 case SMCCC_CONDUIT_HVC: 1037 emit(aarch64_insn_get_hvc_value(), ctx); 1038 break; 1039 case SMCCC_CONDUIT_SMC: 1040 emit(aarch64_insn_get_smc_value(), ctx); 1041 break; 1042 default: 1043 pr_err_once("Firmware mitigation enabled with unknown conduit\n"); 1044 } 1045 } 1046 } 1047 1048 static void build_epilogue(struct jit_ctx *ctx, bool was_classic) 1049 { 1050 const u8 r0 = bpf2a64[BPF_REG_0]; 1051 const u8 ptr = bpf2a64[TCCNT_PTR]; 1052 1053 if (ctx->stack_arg_size) 1054 emit(A64_ADD_I(1, A64_SP, A64_SP, ctx->stack_arg_size), ctx); 1055 1056 /* We're done with BPF stack */ 1057 if (ctx->stack_size && !ctx->priv_sp_used) 1058 emit(A64_ADD_I(1, A64_SP, A64_SP, ctx->stack_size), ctx); 1059 1060 pop_callee_regs(ctx); 1061 1062 emit(A64_POP(A64_ZR, ptr, A64_SP), ctx); 1063 1064 if (was_classic) 1065 build_bhb_mitigation(ctx); 1066 1067 /* Restore FP/LR registers */ 1068 emit(A64_POP(A64_FP, A64_LR, A64_SP), ctx); 1069 1070 /* Move the return value from bpf:r0 (aka x8) to x0 */ 1071 emit(A64_MOV(1, A64_R(0), r0), ctx); 1072 1073 /* Authenticate lr */ 1074 if (IS_ENABLED(CONFIG_ARM64_PTR_AUTH_KERNEL)) 1075 emit(A64_AUTIASP, ctx); 1076 1077 emit(A64_RET(A64_LR), ctx); 1078 } 1079 1080 /* 1081 * Metadata encoding for exception handling in JITed code. 1082 * 1083 * Format of `fixup` field in `struct exception_table_entry`: 1084 * 1085 * Bit layout of `fixup` (32-bit): 1086 * 1087 * +-----------+--------+-------------+-----------+-----------+----------+ 1088 * | 31-27 | 26-23 | 22 | 21 | 20-16 | 15-0 | 1089 * | | | | | | | 1090 * | FIXUP_REG | Unused | ARENA_WRITE | ARENA_ACC | ARENA_REG | OFFSET | 1091 * +-----------+--------+-------------+-----------+-----------+----------+ 1092 * 1093 * - OFFSET (16 bits): Offset used to compute address for Load/Store instruction. 1094 * - ARENA_REG (5 bits): Register that is used to calculate the address for load/store when 1095 * accessing the arena region. 1096 * - ARENA_ACCESS (1 bit): This bit is set when the faulting instruction accessed the arena region. 1097 * - ARENA_WRITE (1 bit): This bit is set when the faulting instruction wrote to the arena region. 1098 * It is independent of FIXUP_REG, since a read-modify-write both writes to 1099 * memory and reads the old value into a register. 1100 * - FIXUP_REG (5 bits): Destination register for the load instruction (cleared on fault) or set to 1101 * DONT_CLEAR if the instruction does not read into a register. 1102 */ 1103 1104 #define BPF_FIXUP_OFFSET_MASK GENMASK(15, 0) 1105 #define BPF_FIXUP_ARENA_REG_MASK GENMASK(20, 16) 1106 #define BPF_ARENA_ACCESS BIT(21) 1107 #define BPF_ARENA_WRITE BIT(22) 1108 #define BPF_FIXUP_REG_MASK GENMASK(31, 27) 1109 #define DONT_CLEAR 5 /* Unused ARM64 register from BPF's POV */ 1110 1111 bool ex_handler_bpf(const struct exception_table_entry *ex, 1112 struct pt_regs *regs) 1113 { 1114 int dst_reg = FIELD_GET(BPF_FIXUP_REG_MASK, ex->fixup); 1115 s16 off = FIELD_GET(BPF_FIXUP_OFFSET_MASK, ex->fixup); 1116 int arena_reg = FIELD_GET(BPF_FIXUP_ARENA_REG_MASK, ex->fixup); 1117 bool is_arena = !!(ex->fixup & BPF_ARENA_ACCESS); 1118 bool is_write = !!(ex->fixup & BPF_ARENA_WRITE); 1119 unsigned long addr; 1120 1121 if (is_arena) { 1122 addr = regs->regs[arena_reg] + off; 1123 bpf_prog_report_arena_violation(is_write, addr, regs->pc); 1124 } 1125 1126 if (dst_reg != DONT_CLEAR) 1127 regs->regs[dst_reg] = 0; 1128 /* Skip the faulting instruction */ 1129 regs->pc += AARCH64_INSN_SIZE; 1130 1131 return true; 1132 } 1133 1134 /* For accesses to BTF pointers, add an entry to the exception table */ 1135 static int add_exception_handler(const struct bpf_insn *insn, 1136 struct jit_ctx *ctx, 1137 int dst_reg) 1138 { 1139 off_t ins_offset; 1140 s16 off = insn->off; 1141 bool is_arena, is_write; 1142 int arena_reg; 1143 unsigned long pc; 1144 struct exception_table_entry *ex; 1145 1146 if (!ctx->image) 1147 /* First pass */ 1148 return 0; 1149 1150 if (BPF_MODE(insn->code) != BPF_PROBE_MEM && 1151 BPF_MODE(insn->code) != BPF_PROBE_MEMSX && 1152 BPF_MODE(insn->code) != BPF_PROBE_MEM32 && 1153 BPF_MODE(insn->code) != BPF_PROBE_MEM32SX && 1154 BPF_MODE(insn->code) != BPF_PROBE_ATOMIC) 1155 return 0; 1156 1157 is_arena = (BPF_MODE(insn->code) == BPF_PROBE_MEM32) || 1158 (BPF_MODE(insn->code) == BPF_PROBE_MEM32SX) || 1159 (BPF_MODE(insn->code) == BPF_PROBE_ATOMIC); 1160 1161 if (!ctx->prog->aux->extable || 1162 WARN_ON_ONCE(ctx->exentry_idx >= ctx->prog->aux->num_exentries)) 1163 return -EINVAL; 1164 1165 ex = &ctx->prog->aux->extable[ctx->exentry_idx]; 1166 pc = (unsigned long)&ctx->ro_image[ctx->idx - 1]; 1167 1168 /* 1169 * This is the relative offset of the instruction that may fault from 1170 * the exception table itself. This will be written to the exception 1171 * table and if this instruction faults, the destination register will 1172 * be set to '0' and the execution will jump to the next instruction. 1173 */ 1174 ins_offset = pc - (long)&ex->insn; 1175 if (WARN_ON_ONCE(ins_offset >= 0 || ins_offset < INT_MIN)) 1176 return -ERANGE; 1177 1178 /* 1179 * The offsets above have been calculated using the RO buffer but we 1180 * need to use the R/W buffer for writes. 1181 * switch ex to rw buffer for writing. 1182 */ 1183 ex = (void *)ctx->image + ((void *)ex - (void *)ctx->ro_image); 1184 1185 ex->insn = ins_offset; 1186 1187 /* 1188 * A load-acquire is of BPF_STX class, but reads from src_reg into 1189 * dst_reg like a BPF_LDX does, hence it must not be treated as a store 1190 * here. A read-modify-write carrying BPF_FETCH is reported as a write 1191 * even though it does have a register to clear, see the callers. 1192 */ 1193 is_write = BPF_CLASS(insn->code) != BPF_LDX && 1194 !bpf_atomic_is_load_acq(insn); 1195 1196 ex->fixup = FIELD_PREP(BPF_FIXUP_REG_MASK, dst_reg); 1197 1198 if (is_arena) { 1199 ex->fixup |= BPF_ARENA_ACCESS; 1200 if (is_write) 1201 ex->fixup |= BPF_ARENA_WRITE; 1202 /* 1203 * insn->src_reg/dst_reg holds the address in the arena region with upper 32-bits 1204 * being zero because of a preceding addr_space_cast(r<n>, 0x0, 0x1) instruction. 1205 * This address is adjusted with the addition of arena_vm_start (see the 1206 * implementation of BPF_PROBE_MEM32 and BPF_PROBE_ATOMIC) before being used for the 1207 * memory access. Pass the reg holding the unmodified 32-bit address to 1208 * ex_handler_bpf. 1209 */ 1210 if (BPF_CLASS(insn->code) == BPF_LDX || bpf_atomic_is_load_acq(insn)) 1211 arena_reg = bpf2a64[insn->src_reg]; 1212 else 1213 arena_reg = bpf2a64[insn->dst_reg]; 1214 1215 ex->fixup |= FIELD_PREP(BPF_FIXUP_OFFSET_MASK, off) | 1216 FIELD_PREP(BPF_FIXUP_ARENA_REG_MASK, arena_reg); 1217 } 1218 1219 ex->type = EX_TYPE_BPF; 1220 1221 ctx->exentry_idx++; 1222 return 0; 1223 } 1224 1225 static const u8 stack_arg_reg[] = { A64_R(5), A64_R(6), A64_R(7) }; 1226 1227 #define NR_STACK_ARG_REGS ARRAY_SIZE(stack_arg_reg) 1228 1229 static void emit_stack_arg_load(u8 dst, s16 bpf_off, struct jit_ctx *ctx) 1230 { 1231 int idx = bpf_off / sizeof(u64) - 1; 1232 1233 if (idx < NR_STACK_ARG_REGS) 1234 emit(A64_MOV(1, dst, stack_arg_reg[idx]), ctx); 1235 else 1236 emit(A64_LDR64I(dst, A64_FP, (idx - NR_STACK_ARG_REGS) * sizeof(u64) + 16), ctx); 1237 } 1238 1239 static void emit_stack_arg_store(u8 src_a64, s16 bpf_off, struct jit_ctx *ctx) 1240 { 1241 int idx = -bpf_off / sizeof(u64) - 1; 1242 1243 if (idx < NR_STACK_ARG_REGS) 1244 emit(A64_MOV(1, stack_arg_reg[idx], src_a64), ctx); 1245 else 1246 emit(A64_STR64I(src_a64, A64_SP, (idx - NR_STACK_ARG_REGS) * sizeof(u64)), ctx); 1247 } 1248 1249 static void emit_stack_arg_store_imm(s32 imm, s16 bpf_off, const u8 tmp, struct jit_ctx *ctx) 1250 { 1251 int idx = -bpf_off / sizeof(u64) - 1; 1252 1253 if (idx < NR_STACK_ARG_REGS) { 1254 emit_a64_mov_i(1, stack_arg_reg[idx], imm, ctx); 1255 } else { 1256 emit_a64_mov_i(1, tmp, imm, ctx); 1257 emit(A64_STR64I(tmp, A64_SP, (idx - NR_STACK_ARG_REGS) * sizeof(u64)), ctx); 1258 } 1259 } 1260 1261 /* 1262 * Rebase the __arena args of a kfunc call to arena kernel addresses, 1263 * xN = kern_vm_start + (u32)xN, with the arena base register holding 1264 * kern_vm_start. A nullable arg preserves NULL by skipping the add, tested 1265 * on the truncated value as arena NULL is offset 0. 1266 */ 1267 static int emit_kfunc_arena_args(struct jit_ctx *ctx, const struct bpf_insn *insn) 1268 { 1269 const u8 arena_vm_base = bpf2a64[ARENA_VM_START]; 1270 const struct btf_func_model *fm; 1271 int i; 1272 1273 fm = bpf_jit_find_kfunc_model(ctx->prog, insn); 1274 if (!fm) 1275 return -EINVAL; 1276 1277 for (i = 0; i < min_t(int, fm->nr_args, MAX_BPF_FUNC_REG_ARGS); i++) { 1278 const u8 reg = bpf2a64[BPF_REG_1 + i]; 1279 u8 flags = fm->arg_flags[i]; 1280 1281 if (!(flags & BTF_FMODEL_ARENA_ARG)) 1282 continue; 1283 if (WARN_ON_ONCE(!ctx->arena_vm_start)) 1284 return -EINVAL; 1285 1286 if (flags & BTF_FMODEL_NULLABLE_ARG) { 1287 /* 32-bit mov clears the upper 32 bits */ 1288 emit(A64_MOV(0, reg, reg), ctx); 1289 /* skip the add so that NULL stays NULL */ 1290 emit(A64_CBZ(0, reg, 2), ctx); 1291 } 1292 emit(A64_ADD_UXTW(reg, arena_vm_base, reg), ctx); 1293 } 1294 1295 return 0; 1296 } 1297 1298 /* JITs an eBPF instruction. 1299 * Returns: 1300 * 0 - successfully JITed an 8-byte eBPF instruction. 1301 * >0 - successfully JITed a 16-byte eBPF instruction. 1302 * <0 - failed to JIT. 1303 */ 1304 static int build_insn(const struct bpf_verifier_env *env, const struct bpf_insn *insn, 1305 struct jit_ctx *ctx, bool extra_pass) 1306 { 1307 const u8 code = insn->code; 1308 u8 dst = bpf2a64[insn->dst_reg]; 1309 u8 src = bpf2a64[insn->src_reg]; 1310 const u8 tmp = bpf2a64[TMP_REG_1]; 1311 const u8 tmp2 = bpf2a64[TMP_REG_2]; 1312 const u8 tmp3 = bpf2a64[TMP_REG_3]; 1313 const u8 fp = bpf2a64[BPF_REG_FP]; 1314 const u8 arena_vm_base = bpf2a64[ARENA_VM_START]; 1315 const u8 priv_sp = bpf2a64[PRIVATE_SP]; 1316 const s16 off = insn->off; 1317 const s32 imm = insn->imm; 1318 const int i = insn - ctx->prog->insnsi; 1319 const bool is64 = BPF_CLASS(code) == BPF_ALU64 || 1320 BPF_CLASS(code) == BPF_JMP; 1321 u8 jmp_cond; 1322 s32 jmp_offset; 1323 u32 a64_insn; 1324 u8 src_adj; 1325 u8 dst_adj; 1326 int off_adj; 1327 int ret; 1328 bool sign_extend; 1329 1330 if (bpf_insn_is_indirect_target(env, ctx->prog, i)) 1331 emit_bti(A64_BTI_J, ctx); 1332 1333 switch (code) { 1334 /* dst = src */ 1335 case BPF_ALU | BPF_MOV | BPF_X: 1336 case BPF_ALU64 | BPF_MOV | BPF_X: 1337 if (insn_is_cast_user(insn)) { 1338 u32 upper = ctx->user_vm_start >> 32; 1339 u16 upper_low = upper & 0xffff; 1340 u16 upper_high = upper >> 16; 1341 int nr_movk = !!upper_low + !!upper_high; 1342 1343 /* 1344 * Build the user address: the low 32 bits are the arena 1345 * offset, the upper 32 bits come from user_vm_start. A 1346 * zero offset must stay NULL, so branch over the MOVKs 1347 * when it is zero. 1348 */ 1349 emit(A64_MOV(0, dst, src), ctx); /* 32-bit mov clears the upper 32 bits */ 1350 if (nr_movk) { 1351 emit(A64_CBZ(0, dst, nr_movk + 1), ctx); 1352 if (upper_low) 1353 emit(A64_MOVK(1, dst, upper_low, 32), ctx); 1354 if (upper_high) 1355 emit(A64_MOVK(1, dst, upper_high, 48), ctx); 1356 } 1357 break; 1358 } else if (insn_is_mov_percpu_addr(insn)) { 1359 if (dst != src) 1360 emit(A64_MOV(1, dst, src), ctx); 1361 if (cpus_have_cap(ARM64_HAS_VIRT_HOST_EXTN)) 1362 emit(A64_MRS_TPIDR_EL2(tmp), ctx); 1363 else 1364 emit(A64_MRS_TPIDR_EL1(tmp), ctx); 1365 emit(A64_ADD(1, dst, dst, tmp), ctx); 1366 break; 1367 } 1368 switch (insn->off) { 1369 case 0: 1370 emit(A64_MOV(is64, dst, src), ctx); 1371 break; 1372 case 8: 1373 emit(A64_SXTB(is64, dst, src), ctx); 1374 break; 1375 case 16: 1376 emit(A64_SXTH(is64, dst, src), ctx); 1377 break; 1378 case 32: 1379 emit(A64_SXTW(is64, dst, src), ctx); 1380 break; 1381 } 1382 break; 1383 /* dst = dst OP src */ 1384 case BPF_ALU | BPF_ADD | BPF_X: 1385 case BPF_ALU64 | BPF_ADD | BPF_X: 1386 emit(A64_ADD(is64, dst, dst, src), ctx); 1387 break; 1388 case BPF_ALU | BPF_SUB | BPF_X: 1389 case BPF_ALU64 | BPF_SUB | BPF_X: 1390 emit(A64_SUB(is64, dst, dst, src), ctx); 1391 break; 1392 case BPF_ALU | BPF_AND | BPF_X: 1393 case BPF_ALU64 | BPF_AND | BPF_X: 1394 emit(A64_AND(is64, dst, dst, src), ctx); 1395 break; 1396 case BPF_ALU | BPF_OR | BPF_X: 1397 case BPF_ALU64 | BPF_OR | BPF_X: 1398 emit(A64_ORR(is64, dst, dst, src), ctx); 1399 break; 1400 case BPF_ALU | BPF_XOR | BPF_X: 1401 case BPF_ALU64 | BPF_XOR | BPF_X: 1402 emit(A64_EOR(is64, dst, dst, src), ctx); 1403 break; 1404 case BPF_ALU | BPF_MUL | BPF_X: 1405 case BPF_ALU64 | BPF_MUL | BPF_X: 1406 emit(A64_MUL(is64, dst, dst, src), ctx); 1407 break; 1408 case BPF_ALU | BPF_DIV | BPF_X: 1409 case BPF_ALU64 | BPF_DIV | BPF_X: 1410 if (!off) 1411 emit(A64_UDIV(is64, dst, dst, src), ctx); 1412 else 1413 emit(A64_SDIV(is64, dst, dst, src), ctx); 1414 break; 1415 case BPF_ALU | BPF_MOD | BPF_X: 1416 case BPF_ALU64 | BPF_MOD | BPF_X: 1417 if (!off) 1418 emit(A64_UDIV(is64, tmp, dst, src), ctx); 1419 else 1420 emit(A64_SDIV(is64, tmp, dst, src), ctx); 1421 emit(A64_MSUB(is64, dst, dst, tmp, src), ctx); 1422 break; 1423 case BPF_ALU | BPF_LSH | BPF_X: 1424 case BPF_ALU64 | BPF_LSH | BPF_X: 1425 emit(A64_LSLV(is64, dst, dst, src), ctx); 1426 break; 1427 case BPF_ALU | BPF_RSH | BPF_X: 1428 case BPF_ALU64 | BPF_RSH | BPF_X: 1429 emit(A64_LSRV(is64, dst, dst, src), ctx); 1430 break; 1431 case BPF_ALU | BPF_ARSH | BPF_X: 1432 case BPF_ALU64 | BPF_ARSH | BPF_X: 1433 emit(A64_ASRV(is64, dst, dst, src), ctx); 1434 break; 1435 /* dst = -dst */ 1436 case BPF_ALU | BPF_NEG: 1437 case BPF_ALU64 | BPF_NEG: 1438 emit(A64_NEG(is64, dst, dst), ctx); 1439 break; 1440 /* dst = BSWAP##imm(dst) */ 1441 case BPF_ALU | BPF_END | BPF_FROM_LE: 1442 case BPF_ALU | BPF_END | BPF_FROM_BE: 1443 case BPF_ALU64 | BPF_END | BPF_FROM_LE: 1444 #ifdef CONFIG_CPU_BIG_ENDIAN 1445 if (BPF_CLASS(code) == BPF_ALU && BPF_SRC(code) == BPF_FROM_BE) 1446 goto emit_bswap_uxt; 1447 #else /* !CONFIG_CPU_BIG_ENDIAN */ 1448 if (BPF_CLASS(code) == BPF_ALU && BPF_SRC(code) == BPF_FROM_LE) 1449 goto emit_bswap_uxt; 1450 #endif 1451 switch (imm) { 1452 case 16: 1453 emit(A64_REV16(is64, dst, dst), ctx); 1454 /* zero-extend 16 bits into 64 bits */ 1455 emit(A64_UXTH(is64, dst, dst), ctx); 1456 break; 1457 case 32: 1458 emit(A64_REV32(0, dst, dst), ctx); 1459 /* upper 32 bits already cleared */ 1460 break; 1461 case 64: 1462 emit(A64_REV64(dst, dst), ctx); 1463 break; 1464 } 1465 break; 1466 emit_bswap_uxt: 1467 switch (imm) { 1468 case 16: 1469 /* zero-extend 16 bits into 64 bits */ 1470 emit(A64_UXTH(is64, dst, dst), ctx); 1471 break; 1472 case 32: 1473 /* zero-extend 32 bits into 64 bits */ 1474 emit(A64_UXTW(is64, dst, dst), ctx); 1475 break; 1476 case 64: 1477 /* nop */ 1478 break; 1479 } 1480 break; 1481 /* dst = imm */ 1482 case BPF_ALU | BPF_MOV | BPF_K: 1483 case BPF_ALU64 | BPF_MOV | BPF_K: 1484 emit_a64_mov_i(is64, dst, imm, ctx); 1485 break; 1486 /* dst = dst OP imm */ 1487 case BPF_ALU | BPF_ADD | BPF_K: 1488 case BPF_ALU64 | BPF_ADD | BPF_K: 1489 emit_a64_add_i(is64, dst, dst, tmp, imm, ctx); 1490 break; 1491 case BPF_ALU | BPF_SUB | BPF_K: 1492 case BPF_ALU64 | BPF_SUB | BPF_K: 1493 if (is_addsub_imm(imm)) { 1494 emit(A64_SUB_I(is64, dst, dst, imm), ctx); 1495 } else if (is_addsub_imm(-(u32)imm)) { 1496 emit(A64_ADD_I(is64, dst, dst, -imm), ctx); 1497 } else { 1498 emit_a64_mov_i(is64, tmp, imm, ctx); 1499 emit(A64_SUB(is64, dst, dst, tmp), ctx); 1500 } 1501 break; 1502 case BPF_ALU | BPF_AND | BPF_K: 1503 case BPF_ALU64 | BPF_AND | BPF_K: 1504 a64_insn = A64_AND_I(is64, dst, dst, imm); 1505 if (a64_insn != AARCH64_BREAK_FAULT) { 1506 emit(a64_insn, ctx); 1507 } else { 1508 emit_a64_mov_i(is64, tmp, imm, ctx); 1509 emit(A64_AND(is64, dst, dst, tmp), ctx); 1510 } 1511 break; 1512 case BPF_ALU | BPF_OR | BPF_K: 1513 case BPF_ALU64 | BPF_OR | BPF_K: 1514 a64_insn = A64_ORR_I(is64, dst, dst, imm); 1515 if (a64_insn != AARCH64_BREAK_FAULT) { 1516 emit(a64_insn, ctx); 1517 } else { 1518 emit_a64_mov_i(is64, tmp, imm, ctx); 1519 emit(A64_ORR(is64, dst, dst, tmp), ctx); 1520 } 1521 break; 1522 case BPF_ALU | BPF_XOR | BPF_K: 1523 case BPF_ALU64 | BPF_XOR | BPF_K: 1524 a64_insn = A64_EOR_I(is64, dst, dst, imm); 1525 if (a64_insn != AARCH64_BREAK_FAULT) { 1526 emit(a64_insn, ctx); 1527 } else { 1528 emit_a64_mov_i(is64, tmp, imm, ctx); 1529 emit(A64_EOR(is64, dst, dst, tmp), ctx); 1530 } 1531 break; 1532 case BPF_ALU | BPF_MUL | BPF_K: 1533 case BPF_ALU64 | BPF_MUL | BPF_K: 1534 emit_a64_mov_i(is64, tmp, imm, ctx); 1535 emit(A64_MUL(is64, dst, dst, tmp), ctx); 1536 break; 1537 case BPF_ALU | BPF_DIV | BPF_K: 1538 case BPF_ALU64 | BPF_DIV | BPF_K: 1539 emit_a64_mov_i(is64, tmp, imm, ctx); 1540 if (!off) 1541 emit(A64_UDIV(is64, dst, dst, tmp), ctx); 1542 else 1543 emit(A64_SDIV(is64, dst, dst, tmp), ctx); 1544 break; 1545 case BPF_ALU | BPF_MOD | BPF_K: 1546 case BPF_ALU64 | BPF_MOD | BPF_K: 1547 emit_a64_mov_i(is64, tmp2, imm, ctx); 1548 if (!off) 1549 emit(A64_UDIV(is64, tmp, dst, tmp2), ctx); 1550 else 1551 emit(A64_SDIV(is64, tmp, dst, tmp2), ctx); 1552 emit(A64_MSUB(is64, dst, dst, tmp, tmp2), ctx); 1553 break; 1554 case BPF_ALU | BPF_LSH | BPF_K: 1555 case BPF_ALU64 | BPF_LSH | BPF_K: 1556 emit(A64_LSL(is64, dst, dst, imm), ctx); 1557 break; 1558 case BPF_ALU | BPF_RSH | BPF_K: 1559 case BPF_ALU64 | BPF_RSH | BPF_K: 1560 emit(A64_LSR(is64, dst, dst, imm), ctx); 1561 break; 1562 case BPF_ALU | BPF_ARSH | BPF_K: 1563 case BPF_ALU64 | BPF_ARSH | BPF_K: 1564 emit(A64_ASR(is64, dst, dst, imm), ctx); 1565 break; 1566 1567 /* JUMP reg */ 1568 case BPF_JMP | BPF_JA | BPF_X: 1569 emit(A64_BR(dst), ctx); 1570 break; 1571 /* JUMP off */ 1572 case BPF_JMP | BPF_JA: 1573 case BPF_JMP32 | BPF_JA: 1574 if (BPF_CLASS(code) == BPF_JMP) 1575 jmp_offset = bpf2a64_offset(i, off, ctx); 1576 else 1577 jmp_offset = bpf2a64_offset(i, imm, ctx); 1578 check_imm26(jmp_offset); 1579 emit(A64_B(jmp_offset), ctx); 1580 break; 1581 /* IF (dst COND src) JUMP off */ 1582 case BPF_JMP | BPF_JEQ | BPF_X: 1583 case BPF_JMP | BPF_JGT | BPF_X: 1584 case BPF_JMP | BPF_JLT | BPF_X: 1585 case BPF_JMP | BPF_JGE | BPF_X: 1586 case BPF_JMP | BPF_JLE | BPF_X: 1587 case BPF_JMP | BPF_JNE | BPF_X: 1588 case BPF_JMP | BPF_JSGT | BPF_X: 1589 case BPF_JMP | BPF_JSLT | BPF_X: 1590 case BPF_JMP | BPF_JSGE | BPF_X: 1591 case BPF_JMP | BPF_JSLE | BPF_X: 1592 case BPF_JMP32 | BPF_JEQ | BPF_X: 1593 case BPF_JMP32 | BPF_JGT | BPF_X: 1594 case BPF_JMP32 | BPF_JLT | BPF_X: 1595 case BPF_JMP32 | BPF_JGE | BPF_X: 1596 case BPF_JMP32 | BPF_JLE | BPF_X: 1597 case BPF_JMP32 | BPF_JNE | BPF_X: 1598 case BPF_JMP32 | BPF_JSGT | BPF_X: 1599 case BPF_JMP32 | BPF_JSLT | BPF_X: 1600 case BPF_JMP32 | BPF_JSGE | BPF_X: 1601 case BPF_JMP32 | BPF_JSLE | BPF_X: 1602 emit(A64_CMP(is64, dst, src), ctx); 1603 emit_cond_jmp: 1604 jmp_offset = bpf2a64_offset(i, off, ctx); 1605 check_imm19(jmp_offset); 1606 switch (BPF_OP(code)) { 1607 case BPF_JEQ: 1608 jmp_cond = A64_COND_EQ; 1609 break; 1610 case BPF_JGT: 1611 jmp_cond = A64_COND_HI; 1612 break; 1613 case BPF_JLT: 1614 jmp_cond = A64_COND_CC; 1615 break; 1616 case BPF_JGE: 1617 jmp_cond = A64_COND_CS; 1618 break; 1619 case BPF_JLE: 1620 jmp_cond = A64_COND_LS; 1621 break; 1622 case BPF_JSET: 1623 case BPF_JNE: 1624 jmp_cond = A64_COND_NE; 1625 break; 1626 case BPF_JSGT: 1627 jmp_cond = A64_COND_GT; 1628 break; 1629 case BPF_JSLT: 1630 jmp_cond = A64_COND_LT; 1631 break; 1632 case BPF_JSGE: 1633 jmp_cond = A64_COND_GE; 1634 break; 1635 case BPF_JSLE: 1636 jmp_cond = A64_COND_LE; 1637 break; 1638 default: 1639 return -EFAULT; 1640 } 1641 emit(A64_B_(jmp_cond, jmp_offset), ctx); 1642 break; 1643 case BPF_JMP | BPF_JSET | BPF_X: 1644 case BPF_JMP32 | BPF_JSET | BPF_X: 1645 emit(A64_TST(is64, dst, src), ctx); 1646 goto emit_cond_jmp; 1647 /* IF (dst COND imm) JUMP off */ 1648 case BPF_JMP | BPF_JEQ | BPF_K: 1649 case BPF_JMP | BPF_JGT | BPF_K: 1650 case BPF_JMP | BPF_JLT | BPF_K: 1651 case BPF_JMP | BPF_JGE | BPF_K: 1652 case BPF_JMP | BPF_JLE | BPF_K: 1653 case BPF_JMP | BPF_JNE | BPF_K: 1654 case BPF_JMP | BPF_JSGT | BPF_K: 1655 case BPF_JMP | BPF_JSLT | BPF_K: 1656 case BPF_JMP | BPF_JSGE | BPF_K: 1657 case BPF_JMP | BPF_JSLE | BPF_K: 1658 case BPF_JMP32 | BPF_JEQ | BPF_K: 1659 case BPF_JMP32 | BPF_JGT | BPF_K: 1660 case BPF_JMP32 | BPF_JLT | BPF_K: 1661 case BPF_JMP32 | BPF_JGE | BPF_K: 1662 case BPF_JMP32 | BPF_JLE | BPF_K: 1663 case BPF_JMP32 | BPF_JNE | BPF_K: 1664 case BPF_JMP32 | BPF_JSGT | BPF_K: 1665 case BPF_JMP32 | BPF_JSLT | BPF_K: 1666 case BPF_JMP32 | BPF_JSGE | BPF_K: 1667 case BPF_JMP32 | BPF_JSLE | BPF_K: 1668 if (is_addsub_imm(imm)) { 1669 emit(A64_CMP_I(is64, dst, imm), ctx); 1670 } else if (is_addsub_imm(-(u32)imm)) { 1671 emit(A64_CMN_I(is64, dst, -imm), ctx); 1672 } else { 1673 emit_a64_mov_i(is64, tmp, imm, ctx); 1674 emit(A64_CMP(is64, dst, tmp), ctx); 1675 } 1676 goto emit_cond_jmp; 1677 case BPF_JMP | BPF_JSET | BPF_K: 1678 case BPF_JMP32 | BPF_JSET | BPF_K: 1679 a64_insn = A64_TST_I(is64, dst, imm); 1680 if (a64_insn != AARCH64_BREAK_FAULT) { 1681 emit(a64_insn, ctx); 1682 } else { 1683 emit_a64_mov_i(is64, tmp, imm, ctx); 1684 emit(A64_TST(is64, dst, tmp), ctx); 1685 } 1686 goto emit_cond_jmp; 1687 /* function call */ 1688 case BPF_JMP | BPF_CALL: 1689 { 1690 const u8 r0 = bpf2a64[BPF_REG_0]; 1691 bool func_addr_fixed; 1692 u64 func_addr; 1693 u32 cpu_offset; 1694 1695 /* Implement helper call to bpf_get_smp_processor_id() inline */ 1696 if (insn->src_reg == 0 && insn->imm == BPF_FUNC_get_smp_processor_id) { 1697 cpu_offset = offsetof(struct thread_info, cpu); 1698 1699 emit(A64_MRS_SP_EL0(tmp), ctx); 1700 if (is_lsi_offset(cpu_offset, 2)) { 1701 emit(A64_LDR32I(r0, tmp, cpu_offset), ctx); 1702 } else { 1703 emit_a64_mov_i(1, tmp2, cpu_offset, ctx); 1704 emit(A64_LDR32(r0, tmp, tmp2), ctx); 1705 } 1706 break; 1707 } 1708 1709 /* Implement helper call to bpf_get_current_task/_btf() inline */ 1710 if (insn->src_reg == 0 && (insn->imm == BPF_FUNC_get_current_task || 1711 insn->imm == BPF_FUNC_get_current_task_btf)) { 1712 emit(A64_MRS_SP_EL0(r0), ctx); 1713 break; 1714 } 1715 1716 ret = bpf_jit_get_func_addr(ctx->prog, insn, extra_pass, 1717 &func_addr, &func_addr_fixed); 1718 if (ret < 0) 1719 return ret; 1720 if (insn->src_reg == BPF_PSEUDO_KFUNC_CALL) { 1721 ret = emit_kfunc_arena_args(ctx, insn); 1722 if (ret < 0) 1723 return ret; 1724 } 1725 emit_call(func_addr, ctx); 1726 /* 1727 * Call to arch_bpf_timed_may_goto() is emitted by the 1728 * verifier and called with custom calling convention with 1729 * first argument and return value in BPF_REG_AX (x9). 1730 */ 1731 if (func_addr != (u64)arch_bpf_timed_may_goto) 1732 emit(A64_MOV(1, r0, A64_R(0)), ctx); 1733 break; 1734 } 1735 /* tail call */ 1736 case BPF_JMP | BPF_TAIL_CALL: 1737 if (emit_bpf_tail_call(ctx)) 1738 return -EFAULT; 1739 break; 1740 /* function return */ 1741 case BPF_JMP | BPF_EXIT: 1742 /* Optimization: when last instruction is EXIT, 1743 simply fallthrough to epilogue. */ 1744 if (i == ctx->prog->len - 1) 1745 break; 1746 jmp_offset = epilogue_offset(ctx); 1747 check_imm26(jmp_offset); 1748 emit(A64_B(jmp_offset), ctx); 1749 break; 1750 1751 /* dst = imm64 */ 1752 case BPF_LD | BPF_IMM | BPF_DW: 1753 { 1754 const struct bpf_insn insn1 = insn[1]; 1755 u64 imm64; 1756 1757 imm64 = (u64)insn1.imm << 32 | (u32)imm; 1758 if (bpf_pseudo_func(insn)) 1759 emit_addr_mov_i64(dst, imm64, ctx); 1760 else 1761 emit_a64_mov_i64(dst, imm64, ctx); 1762 1763 return 1; 1764 } 1765 1766 /* LDX: dst = (u64)*(unsigned size *)(src + off) */ 1767 case BPF_LDX | BPF_MEM | BPF_W: 1768 case BPF_LDX | BPF_MEM | BPF_H: 1769 case BPF_LDX | BPF_MEM | BPF_B: 1770 case BPF_LDX | BPF_MEM | BPF_DW: 1771 if (insn->src_reg == BPF_REG_PARAMS) { 1772 emit_stack_arg_load(dst, off, ctx); 1773 break; 1774 } 1775 fallthrough; 1776 case BPF_LDX | BPF_PROBE_MEM | BPF_DW: 1777 case BPF_LDX | BPF_PROBE_MEM | BPF_W: 1778 case BPF_LDX | BPF_PROBE_MEM | BPF_H: 1779 case BPF_LDX | BPF_PROBE_MEM | BPF_B: 1780 /* LDXS: dst_reg = (s64)*(signed size *)(src_reg + off) */ 1781 case BPF_LDX | BPF_MEMSX | BPF_B: 1782 case BPF_LDX | BPF_MEMSX | BPF_H: 1783 case BPF_LDX | BPF_MEMSX | BPF_W: 1784 case BPF_LDX | BPF_PROBE_MEMSX | BPF_B: 1785 case BPF_LDX | BPF_PROBE_MEMSX | BPF_H: 1786 case BPF_LDX | BPF_PROBE_MEMSX | BPF_W: 1787 case BPF_LDX | BPF_PROBE_MEM32 | BPF_B: 1788 case BPF_LDX | BPF_PROBE_MEM32 | BPF_H: 1789 case BPF_LDX | BPF_PROBE_MEM32 | BPF_W: 1790 case BPF_LDX | BPF_PROBE_MEM32 | BPF_DW: 1791 case BPF_LDX | BPF_PROBE_MEM32SX | BPF_B: 1792 case BPF_LDX | BPF_PROBE_MEM32SX | BPF_H: 1793 case BPF_LDX | BPF_PROBE_MEM32SX | BPF_W: 1794 if (BPF_MODE(insn->code) == BPF_PROBE_MEM32 || 1795 BPF_MODE(insn->code) == BPF_PROBE_MEM32SX) { 1796 emit(A64_ADD(1, tmp2, src, arena_vm_base), ctx); 1797 src = tmp2; 1798 } 1799 if (src == fp) { 1800 src_adj = ctx->priv_sp_used ? priv_sp : A64_SP; 1801 off_adj = off + ctx->stack_size; 1802 if (!ctx->priv_sp_used) 1803 off_adj += ctx->stack_arg_size; 1804 } else { 1805 src_adj = src; 1806 off_adj = off; 1807 } 1808 sign_extend = (BPF_MODE(insn->code) == BPF_MEMSX || 1809 BPF_MODE(insn->code) == BPF_PROBE_MEMSX || 1810 BPF_MODE(insn->code) == BPF_PROBE_MEM32SX); 1811 switch (BPF_SIZE(code)) { 1812 case BPF_W: 1813 if (is_lsi_offset(off_adj, 2)) { 1814 if (sign_extend) 1815 emit(A64_LDRSWI(dst, src_adj, off_adj), ctx); 1816 else 1817 emit(A64_LDR32I(dst, src_adj, off_adj), ctx); 1818 } else { 1819 emit_a64_mov_i(1, tmp, off, ctx); 1820 if (sign_extend) 1821 emit(A64_LDRSW(dst, src, tmp), ctx); 1822 else 1823 emit(A64_LDR32(dst, src, tmp), ctx); 1824 } 1825 break; 1826 case BPF_H: 1827 if (is_lsi_offset(off_adj, 1)) { 1828 if (sign_extend) 1829 emit(A64_LDRSHI(dst, src_adj, off_adj), ctx); 1830 else 1831 emit(A64_LDRHI(dst, src_adj, off_adj), ctx); 1832 } else { 1833 emit_a64_mov_i(1, tmp, off, ctx); 1834 if (sign_extend) 1835 emit(A64_LDRSH(dst, src, tmp), ctx); 1836 else 1837 emit(A64_LDRH(dst, src, tmp), ctx); 1838 } 1839 break; 1840 case BPF_B: 1841 if (is_lsi_offset(off_adj, 0)) { 1842 if (sign_extend) 1843 emit(A64_LDRSBI(dst, src_adj, off_adj), ctx); 1844 else 1845 emit(A64_LDRBI(dst, src_adj, off_adj), ctx); 1846 } else { 1847 emit_a64_mov_i(1, tmp, off, ctx); 1848 if (sign_extend) 1849 emit(A64_LDRSB(dst, src, tmp), ctx); 1850 else 1851 emit(A64_LDRB(dst, src, tmp), ctx); 1852 } 1853 break; 1854 case BPF_DW: 1855 if (is_lsi_offset(off_adj, 3)) { 1856 emit(A64_LDR64I(dst, src_adj, off_adj), ctx); 1857 } else { 1858 emit_a64_mov_i(1, tmp, off, ctx); 1859 emit(A64_LDR64(dst, src, tmp), ctx); 1860 } 1861 break; 1862 } 1863 1864 ret = add_exception_handler(insn, ctx, dst); 1865 if (ret) 1866 return ret; 1867 break; 1868 1869 /* speculation barrier against v1 and v4 */ 1870 case BPF_ST | BPF_NOSPEC: 1871 if (alternative_has_cap_likely(ARM64_HAS_SB)) { 1872 emit(A64_SB, ctx); 1873 } else { 1874 emit(A64_DSB_NSH, ctx); 1875 emit(A64_ISB, ctx); 1876 } 1877 break; 1878 1879 /* ST: *(size *)(dst + off) = imm */ 1880 case BPF_ST | BPF_MEM | BPF_W: 1881 case BPF_ST | BPF_MEM | BPF_H: 1882 case BPF_ST | BPF_MEM | BPF_B: 1883 case BPF_ST | BPF_MEM | BPF_DW: 1884 if (insn->dst_reg == BPF_REG_PARAMS) { 1885 emit_stack_arg_store_imm(imm, off, tmp, ctx); 1886 break; 1887 } 1888 fallthrough; 1889 case BPF_ST | BPF_PROBE_MEM32 | BPF_B: 1890 case BPF_ST | BPF_PROBE_MEM32 | BPF_H: 1891 case BPF_ST | BPF_PROBE_MEM32 | BPF_W: 1892 case BPF_ST | BPF_PROBE_MEM32 | BPF_DW: 1893 if (BPF_MODE(insn->code) == BPF_PROBE_MEM32) { 1894 emit(A64_ADD(1, tmp3, dst, arena_vm_base), ctx); 1895 dst = tmp3; 1896 } 1897 if (dst == fp) { 1898 dst_adj = ctx->priv_sp_used ? priv_sp : A64_SP; 1899 off_adj = off + ctx->stack_size; 1900 if (!ctx->priv_sp_used) 1901 off_adj += ctx->stack_arg_size; 1902 } else { 1903 dst_adj = dst; 1904 off_adj = off; 1905 } 1906 /* Load imm to a register then store it */ 1907 emit_a64_mov_i(1, tmp, imm, ctx); 1908 switch (BPF_SIZE(code)) { 1909 case BPF_W: 1910 if (is_lsi_offset(off_adj, 2)) { 1911 emit(A64_STR32I(tmp, dst_adj, off_adj), ctx); 1912 } else { 1913 emit_a64_mov_i(1, tmp2, off, ctx); 1914 emit(A64_STR32(tmp, dst, tmp2), ctx); 1915 } 1916 break; 1917 case BPF_H: 1918 if (is_lsi_offset(off_adj, 1)) { 1919 emit(A64_STRHI(tmp, dst_adj, off_adj), ctx); 1920 } else { 1921 emit_a64_mov_i(1, tmp2, off, ctx); 1922 emit(A64_STRH(tmp, dst, tmp2), ctx); 1923 } 1924 break; 1925 case BPF_B: 1926 if (is_lsi_offset(off_adj, 0)) { 1927 emit(A64_STRBI(tmp, dst_adj, off_adj), ctx); 1928 } else { 1929 emit_a64_mov_i(1, tmp2, off, ctx); 1930 emit(A64_STRB(tmp, dst, tmp2), ctx); 1931 } 1932 break; 1933 case BPF_DW: 1934 if (is_lsi_offset(off_adj, 3)) { 1935 emit(A64_STR64I(tmp, dst_adj, off_adj), ctx); 1936 } else { 1937 emit_a64_mov_i(1, tmp2, off, ctx); 1938 emit(A64_STR64(tmp, dst, tmp2), ctx); 1939 } 1940 break; 1941 } 1942 1943 ret = add_exception_handler(insn, ctx, DONT_CLEAR); 1944 if (ret) 1945 return ret; 1946 break; 1947 1948 /* STX: *(size *)(dst + off) = src */ 1949 case BPF_STX | BPF_MEM | BPF_W: 1950 case BPF_STX | BPF_MEM | BPF_H: 1951 case BPF_STX | BPF_MEM | BPF_B: 1952 case BPF_STX | BPF_MEM | BPF_DW: 1953 if (insn->dst_reg == BPF_REG_PARAMS) { 1954 emit_stack_arg_store(src, off, ctx); 1955 break; 1956 } 1957 fallthrough; 1958 case BPF_STX | BPF_PROBE_MEM32 | BPF_B: 1959 case BPF_STX | BPF_PROBE_MEM32 | BPF_H: 1960 case BPF_STX | BPF_PROBE_MEM32 | BPF_W: 1961 case BPF_STX | BPF_PROBE_MEM32 | BPF_DW: 1962 if (BPF_MODE(insn->code) == BPF_PROBE_MEM32) { 1963 emit(A64_ADD(1, tmp2, dst, arena_vm_base), ctx); 1964 dst = tmp2; 1965 } 1966 if (dst == fp) { 1967 dst_adj = ctx->priv_sp_used ? priv_sp : A64_SP; 1968 off_adj = off + ctx->stack_size; 1969 if (!ctx->priv_sp_used) 1970 off_adj += ctx->stack_arg_size; 1971 } else { 1972 dst_adj = dst; 1973 off_adj = off; 1974 } 1975 switch (BPF_SIZE(code)) { 1976 case BPF_W: 1977 if (is_lsi_offset(off_adj, 2)) { 1978 emit(A64_STR32I(src, dst_adj, off_adj), ctx); 1979 } else { 1980 emit_a64_mov_i(1, tmp, off, ctx); 1981 emit(A64_STR32(src, dst, tmp), ctx); 1982 } 1983 break; 1984 case BPF_H: 1985 if (is_lsi_offset(off_adj, 1)) { 1986 emit(A64_STRHI(src, dst_adj, off_adj), ctx); 1987 } else { 1988 emit_a64_mov_i(1, tmp, off, ctx); 1989 emit(A64_STRH(src, dst, tmp), ctx); 1990 } 1991 break; 1992 case BPF_B: 1993 if (is_lsi_offset(off_adj, 0)) { 1994 emit(A64_STRBI(src, dst_adj, off_adj), ctx); 1995 } else { 1996 emit_a64_mov_i(1, tmp, off, ctx); 1997 emit(A64_STRB(src, dst, tmp), ctx); 1998 } 1999 break; 2000 case BPF_DW: 2001 if (is_lsi_offset(off_adj, 3)) { 2002 emit(A64_STR64I(src, dst_adj, off_adj), ctx); 2003 } else { 2004 emit_a64_mov_i(1, tmp, off, ctx); 2005 emit(A64_STR64(src, dst, tmp), ctx); 2006 } 2007 break; 2008 } 2009 2010 ret = add_exception_handler(insn, ctx, DONT_CLEAR); 2011 if (ret) 2012 return ret; 2013 break; 2014 2015 case BPF_STX | BPF_ATOMIC | BPF_B: 2016 case BPF_STX | BPF_ATOMIC | BPF_H: 2017 case BPF_STX | BPF_ATOMIC | BPF_W: 2018 case BPF_STX | BPF_ATOMIC | BPF_DW: 2019 case BPF_STX | BPF_PROBE_ATOMIC | BPF_B: 2020 case BPF_STX | BPF_PROBE_ATOMIC | BPF_H: 2021 case BPF_STX | BPF_PROBE_ATOMIC | BPF_W: 2022 case BPF_STX | BPF_PROBE_ATOMIC | BPF_DW: 2023 if (bpf_atomic_is_load_store(insn)) 2024 ret = emit_atomic_ld_st(insn, ctx); 2025 else if (cpus_have_cap(ARM64_HAS_LSE_ATOMICS)) 2026 ret = emit_lse_atomic(insn, ctx); 2027 else 2028 ret = emit_ll_sc_atomic(insn, ctx); 2029 if (ret) 2030 return ret; 2031 2032 if (BPF_MODE(insn->code) == BPF_PROBE_ATOMIC) { 2033 /* 2034 * A load-acquire reads into dst_reg, and a read-modify-write 2035 * carrying BPF_FETCH reads the old value into src_reg, or into 2036 * r0 for a BPF_CMPXCHG. Clear that register on fault, the 2037 * remaining atomics have no destination register. 2038 */ 2039 int load_reg = bpf_atomic_load_reg(insn); 2040 2041 ret = add_exception_handler(insn, ctx, load_reg < 0 ? 2042 DONT_CLEAR : bpf2a64[load_reg]); 2043 if (ret) 2044 return ret; 2045 } 2046 break; 2047 2048 default: 2049 pr_err_once("unknown opcode %02x\n", code); 2050 return -EINVAL; 2051 } 2052 2053 return 0; 2054 } 2055 2056 static int build_body(struct bpf_verifier_env *env, struct jit_ctx *ctx, bool extra_pass) 2057 { 2058 const struct bpf_prog *prog = ctx->prog; 2059 int i; 2060 2061 /* 2062 * - offset[0] offset of the end of prologue, 2063 * start of the 1st instruction. 2064 * - offset[1] - offset of the end of 1st instruction, 2065 * start of the 2nd instruction 2066 * [....] 2067 * - offset[3] - offset of the end of 3rd instruction, 2068 * start of 4th instruction 2069 */ 2070 for (i = 0; i < prog->len; i++) { 2071 const struct bpf_insn *insn = &prog->insnsi[i]; 2072 int ret; 2073 2074 ctx->offset[i] = ctx->idx; 2075 ret = build_insn(env, insn, ctx, extra_pass); 2076 if (ret > 0) { 2077 i++; 2078 ctx->offset[i] = ctx->idx; 2079 continue; 2080 } 2081 if (ret) 2082 return ret; 2083 } 2084 /* 2085 * offset is allocated with prog->len + 1 so fill in 2086 * the last element with the offset after the last 2087 * instruction (end of program) 2088 */ 2089 ctx->offset[i] = ctx->idx; 2090 2091 return 0; 2092 } 2093 2094 static int validate_code(struct jit_ctx *ctx) 2095 { 2096 int i; 2097 2098 for (i = 0; i < ctx->idx; i++) { 2099 u32 a64_insn = le32_to_cpu(ctx->image[i]); 2100 2101 if (a64_insn == AARCH64_BREAK_FAULT) 2102 return -1; 2103 } 2104 return 0; 2105 } 2106 2107 static int validate_ctx(struct jit_ctx *ctx) 2108 { 2109 if (validate_code(ctx)) 2110 return -1; 2111 2112 if (WARN_ON_ONCE(ctx->exentry_idx != ctx->prog->aux->num_exentries)) 2113 return -1; 2114 2115 return 0; 2116 } 2117 2118 static void priv_stack_init_guard(void __percpu *priv_stack_ptr, int alloc_size) 2119 { 2120 int cpu, underflow_idx = (alloc_size - PRIV_STACK_GUARD_SZ) >> 3; 2121 u64 *stack_ptr; 2122 2123 for_each_possible_cpu(cpu) { 2124 stack_ptr = per_cpu_ptr(priv_stack_ptr, cpu); 2125 stack_ptr[0] = PRIV_STACK_GUARD_VAL; 2126 stack_ptr[1] = PRIV_STACK_GUARD_VAL; 2127 stack_ptr[underflow_idx] = PRIV_STACK_GUARD_VAL; 2128 stack_ptr[underflow_idx + 1] = PRIV_STACK_GUARD_VAL; 2129 } 2130 } 2131 2132 static void priv_stack_check_guard(void __percpu *priv_stack_ptr, int alloc_size, 2133 struct bpf_prog *prog) 2134 { 2135 int cpu, underflow_idx = (alloc_size - PRIV_STACK_GUARD_SZ) >> 3; 2136 u64 *stack_ptr; 2137 2138 for_each_possible_cpu(cpu) { 2139 stack_ptr = per_cpu_ptr(priv_stack_ptr, cpu); 2140 if (stack_ptr[0] != PRIV_STACK_GUARD_VAL || 2141 stack_ptr[1] != PRIV_STACK_GUARD_VAL || 2142 stack_ptr[underflow_idx] != PRIV_STACK_GUARD_VAL || 2143 stack_ptr[underflow_idx + 1] != PRIV_STACK_GUARD_VAL) { 2144 pr_err("BPF private stack overflow/underflow detected for prog %sx\n", 2145 bpf_jit_get_prog_name(prog)); 2146 break; 2147 } 2148 } 2149 } 2150 2151 struct arm64_jit_data { 2152 struct bpf_binary_header *header; 2153 u8 *ro_image; 2154 struct bpf_binary_header *ro_header; 2155 struct jit_ctx ctx; 2156 }; 2157 2158 struct bpf_prog *bpf_int_jit_compile(struct bpf_verifier_env *env, struct bpf_prog *prog) 2159 { 2160 int image_size, prog_size, extable_size, extable_align, extable_offset; 2161 struct bpf_binary_header *header; 2162 struct bpf_binary_header *ro_header = NULL; 2163 struct arm64_jit_data *jit_data; 2164 void __percpu *priv_stack_ptr = NULL; 2165 bool was_classic = bpf_prog_was_classic(prog); 2166 int priv_stack_alloc_sz; 2167 bool extra_pass = false; 2168 struct jit_ctx ctx; 2169 u8 *image_ptr; 2170 u8 *ro_image_ptr; 2171 int body_idx; 2172 int exentry_idx; 2173 int out_cnt; 2174 2175 if (!prog->jit_requested) 2176 return prog; 2177 2178 jit_data = prog->aux->jit_data; 2179 if (!jit_data) { 2180 jit_data = kzalloc_obj(*jit_data); 2181 if (!jit_data) 2182 return prog; 2183 prog->aux->jit_data = jit_data; 2184 } 2185 priv_stack_ptr = prog->aux->priv_stack_ptr; 2186 if (!priv_stack_ptr && prog->aux->jits_use_priv_stack) { 2187 /* Allocate actual private stack size with verifier-calculated 2188 * stack size plus two memory guards to protect overflow and 2189 * underflow. 2190 */ 2191 priv_stack_alloc_sz = round_up(prog->aux->stack_depth, 16) + 2192 2 * PRIV_STACK_GUARD_SZ; 2193 priv_stack_ptr = __alloc_percpu_gfp(priv_stack_alloc_sz, 16, GFP_KERNEL); 2194 if (!priv_stack_ptr) 2195 goto out_priv_stack; 2196 2197 priv_stack_init_guard(priv_stack_ptr, priv_stack_alloc_sz); 2198 prog->aux->priv_stack_ptr = priv_stack_ptr; 2199 } 2200 if (jit_data->ctx.offset) { 2201 ctx = jit_data->ctx; 2202 ro_image_ptr = jit_data->ro_image; 2203 ro_header = jit_data->ro_header; 2204 header = jit_data->header; 2205 image_ptr = (void *)header + ((void *)ro_image_ptr 2206 - (void *)ro_header); 2207 extra_pass = true; 2208 prog_size = sizeof(u32) * ctx.idx; 2209 goto skip_init_ctx; 2210 } 2211 memset(&ctx, 0, sizeof(ctx)); 2212 ctx.prog = prog; 2213 2214 ctx.offset = kvzalloc_objs(int, prog->len + 1); 2215 if (ctx.offset == NULL) 2216 goto out_off; 2217 2218 ctx.user_vm_start = bpf_arena_get_user_vm_start(prog->aux->arena); 2219 ctx.arena_vm_start = bpf_arena_get_kern_vm_start(prog->aux->arena); 2220 2221 out_cnt = bpf_out_stack_arg_cnt(env, prog); 2222 if (out_cnt) { 2223 int nr_on_stack = out_cnt - NR_STACK_ARG_REGS; 2224 2225 if (nr_on_stack > 0) 2226 ctx.stack_arg_size = round_up(nr_on_stack * sizeof(u64), 16); 2227 } 2228 2229 if (priv_stack_ptr) 2230 ctx.priv_sp_used = true; 2231 2232 /* Pass 1: Estimate the maximum image size. 2233 * 2234 * BPF line info needs ctx->offset[i] to be the offset of 2235 * instruction[i] in jited image, so build prologue first. 2236 */ 2237 if (build_prologue(&ctx, was_classic)) 2238 goto out_off; 2239 2240 if (build_body(env, &ctx, extra_pass)) 2241 goto out_off; 2242 2243 ctx.epilogue_offset = ctx.idx; 2244 build_epilogue(&ctx, was_classic); 2245 build_plt(&ctx); 2246 2247 extable_align = __alignof__(struct exception_table_entry); 2248 extable_size = prog->aux->num_exentries * 2249 sizeof(struct exception_table_entry); 2250 2251 /* Now we know the maximum image size. */ 2252 prog_size = sizeof(u32) * ctx.idx; 2253 /* also allocate space for plt target */ 2254 extable_offset = round_up(prog_size + PLT_TARGET_SIZE, extable_align); 2255 image_size = extable_offset + extable_size; 2256 ro_header = bpf_jit_binary_pack_alloc(image_size, &ro_image_ptr, 2257 sizeof(u64), &header, &image_ptr, 2258 jit_fill_hole, was_classic); 2259 if (!ro_header) 2260 goto out_off; 2261 2262 /* Pass 2: Determine jited position and result for each instruction */ 2263 2264 /* 2265 * Use the image(RW) for writing the JITed instructions. But also save 2266 * the ro_image(RX) for calculating the offsets in the image. The RW 2267 * image will be later copied to the RX image from where the program 2268 * will run. The bpf_jit_binary_pack_finalize() will do this copy in the 2269 * final step. 2270 */ 2271 ctx.image = (__le32 *)image_ptr; 2272 ctx.ro_image = (__le32 *)ro_image_ptr; 2273 if (extable_size) 2274 prog->aux->extable = (void *)ro_image_ptr + extable_offset; 2275 skip_init_ctx: 2276 ctx.idx = 0; 2277 ctx.exentry_idx = 0; 2278 ctx.write = true; 2279 2280 build_prologue(&ctx, was_classic); 2281 2282 /* Record exentry_idx and body_idx before first build_body */ 2283 exentry_idx = ctx.exentry_idx; 2284 body_idx = ctx.idx; 2285 /* Dont write body instructions to memory for now */ 2286 ctx.write = false; 2287 2288 if (build_body(env, &ctx, extra_pass)) 2289 goto out_free_hdr; 2290 2291 ctx.epilogue_offset = ctx.idx; 2292 ctx.exentry_idx = exentry_idx; 2293 ctx.idx = body_idx; 2294 ctx.write = true; 2295 2296 /* Pass 3: Adjust jump offset and write final image */ 2297 if (build_body(env, &ctx, extra_pass) || 2298 WARN_ON_ONCE(ctx.idx != ctx.epilogue_offset)) 2299 goto out_free_hdr; 2300 2301 build_epilogue(&ctx, was_classic); 2302 build_plt(&ctx); 2303 2304 /* Extra pass to validate JITed code. */ 2305 if (validate_ctx(&ctx)) 2306 goto out_free_hdr; 2307 2308 /* update the real prog size */ 2309 prog_size = sizeof(u32) * ctx.idx; 2310 2311 /* And we're done. */ 2312 if (bpf_jit_enable > 1) 2313 bpf_jit_dump(prog->len, prog_size, 2, ctx.image); 2314 2315 if (!prog->is_func || extra_pass) { 2316 /* The jited image may shrink since the jited result for 2317 * BPF_CALL to subprog may be changed from indirect call 2318 * to direct call. 2319 */ 2320 if (extra_pass && ctx.idx > jit_data->ctx.idx) { 2321 pr_err_once("multi-func JIT bug %d > %d\n", 2322 ctx.idx, jit_data->ctx.idx); 2323 goto out_free_hdr; 2324 } 2325 if (WARN_ON(bpf_jit_binary_pack_finalize(ro_header, header))) { 2326 /* ro_header and header has been freed */ 2327 ro_header = NULL; 2328 header = NULL; 2329 goto out_free_hdr; 2330 } 2331 } else { 2332 jit_data->ctx = ctx; 2333 jit_data->ro_image = ro_image_ptr; 2334 jit_data->header = header; 2335 jit_data->ro_header = ro_header; 2336 } 2337 2338 prog->bpf_func = (void *)ctx.ro_image + cfi_get_offset(); 2339 prog->jited = 1; 2340 prog->jited_len = prog_size - cfi_get_offset(); 2341 2342 if (!prog->is_func || extra_pass) { 2343 int i; 2344 2345 /* offset[prog->len] is the size of program */ 2346 for (i = 0; i <= prog->len; i++) 2347 ctx.offset[i] *= AARCH64_INSN_SIZE; 2348 bpf_prog_fill_jited_linfo(prog, ctx.offset + 1); 2349 /* 2350 * The bpf_prog_update_insn_ptrs function expects offsets to 2351 * point to the first byte of the jitted instruction (unlike 2352 * the bpf_prog_fill_jited_linfo above, which, for historical 2353 * reasons, expects to point to the next instruction) 2354 */ 2355 bpf_prog_update_insn_ptrs(prog, ctx.offset, ctx.ro_image); 2356 out_off: 2357 if (!ro_header && priv_stack_ptr) { 2358 free_percpu(priv_stack_ptr); 2359 prog->aux->priv_stack_ptr = NULL; 2360 } 2361 kvfree(ctx.offset); 2362 out_priv_stack: 2363 kfree(jit_data); 2364 prog->aux->jit_data = NULL; 2365 } 2366 2367 return prog; 2368 2369 out_free_hdr: 2370 if (extra_pass) { 2371 prog->bpf_func = NULL; 2372 prog->jited = 0; 2373 prog->jited_len = 0; 2374 } 2375 if (header) { 2376 bpf_arch_text_copy(&ro_header->size, &header->size, 2377 sizeof(header->size)); 2378 bpf_jit_binary_pack_free(ro_header, header); 2379 } 2380 goto out_off; 2381 } 2382 2383 bool bpf_jit_supports_private_stack(void) 2384 { 2385 return true; 2386 } 2387 2388 bool bpf_jit_supports_kfunc_call(void) 2389 { 2390 return true; 2391 } 2392 2393 bool bpf_jit_supports_stack_args(void) 2394 { 2395 return true; 2396 } 2397 2398 bool bpf_jit_supports_arena_args(void) 2399 { 2400 return true; 2401 } 2402 2403 void *bpf_arch_text_copy(void *dst, void *src, size_t len) 2404 { 2405 if (!aarch64_insn_copy(dst, src, len)) 2406 return ERR_PTR(-EINVAL); 2407 return dst; 2408 } 2409 2410 u64 bpf_jit_alloc_exec_limit(void) 2411 { 2412 return VMALLOC_END - VMALLOC_START; 2413 } 2414 2415 /* Indicate the JIT backend supports mixing bpf2bpf and tailcalls. */ 2416 bool bpf_jit_supports_subprog_tailcalls(void) 2417 { 2418 return true; 2419 } 2420 2421 static void invoke_bpf_prog(struct jit_ctx *ctx, struct bpf_tramp_node *node, 2422 int bargs_off, int retval_off, int run_ctx_off, 2423 bool save_ret) 2424 { 2425 __le32 *branch; 2426 u64 enter_prog; 2427 u64 exit_prog; 2428 struct bpf_prog *p = node->link->prog; 2429 int cookie_off = offsetof(struct bpf_tramp_run_ctx, bpf_cookie); 2430 2431 enter_prog = (u64)bpf_trampoline_enter(p); 2432 exit_prog = (u64)bpf_trampoline_exit(p); 2433 2434 if (node->cookie == 0) { 2435 /* if cookie is zero, one instruction is enough to store it */ 2436 emit(A64_STR64I(A64_ZR, A64_SP, run_ctx_off + cookie_off), ctx); 2437 } else { 2438 emit_a64_mov_i64(A64_R(10), node->cookie, ctx); 2439 emit(A64_STR64I(A64_R(10), A64_SP, run_ctx_off + cookie_off), 2440 ctx); 2441 } 2442 2443 /* save p to callee saved register x19 to avoid loading p with mov_i64 2444 * each time. 2445 */ 2446 emit_addr_mov_i64(A64_R(19), (const u64)p, ctx); 2447 2448 /* arg1: prog */ 2449 emit(A64_MOV(1, A64_R(0), A64_R(19)), ctx); 2450 /* arg2: &run_ctx */ 2451 emit(A64_ADD_I(1, A64_R(1), A64_SP, run_ctx_off), ctx); 2452 2453 emit_call(enter_prog, ctx); 2454 2455 /* save return value to callee saved register x20 */ 2456 emit(A64_MOV(1, A64_R(20), A64_R(0)), ctx); 2457 2458 /* if (__bpf_prog_enter(prog) == 0) 2459 * goto skip_exec_of_prog; 2460 */ 2461 branch = ctx->image + ctx->idx; 2462 emit(A64_NOP, ctx); 2463 2464 emit(A64_ADD_I(1, A64_R(0), A64_SP, bargs_off), ctx); 2465 if (!p->jited) 2466 emit_addr_mov_i64(A64_R(1), (const u64)p->insnsi, ctx); 2467 2468 emit_call((const u64)p->bpf_func, ctx); 2469 2470 if (save_ret) 2471 emit(A64_STR64I(A64_R(0), A64_SP, retval_off), ctx); 2472 2473 if (ctx->image) { 2474 int offset = &ctx->image[ctx->idx] - branch; 2475 *branch = cpu_to_le32(A64_CBZ(1, A64_R(0), offset)); 2476 } 2477 2478 /* arg1: prog */ 2479 emit(A64_MOV(1, A64_R(0), A64_R(19)), ctx); 2480 /* arg2: start time */ 2481 emit(A64_MOV(1, A64_R(1), A64_R(20)), ctx); 2482 /* arg3: &run_ctx */ 2483 emit(A64_ADD_I(1, A64_R(2), A64_SP, run_ctx_off), ctx); 2484 2485 emit_call(exit_prog, ctx); 2486 } 2487 2488 static void invoke_bpf_mod_ret(struct jit_ctx *ctx, struct bpf_tramp_nodes *tn, 2489 int bargs_off, int retval_off, int run_ctx_off, 2490 __le32 **branches) 2491 { 2492 int i; 2493 2494 /* The first fmod_ret program will receive a garbage return value. 2495 * Set this to 0 to avoid confusing the program. 2496 */ 2497 emit(A64_STR64I(A64_ZR, A64_SP, retval_off), ctx); 2498 for (i = 0; i < tn->nr_nodes; i++) { 2499 invoke_bpf_prog(ctx, tn->nodes[i], bargs_off, retval_off, 2500 run_ctx_off, true); 2501 /* if (*(u64 *)(sp + retval_off) != 0) 2502 * goto do_fexit; 2503 */ 2504 emit(A64_LDR64I(A64_R(10), A64_SP, retval_off), ctx); 2505 /* Save the location of branch, and generate a nop. 2506 * This nop will be replaced with a cbnz later. 2507 */ 2508 branches[i] = ctx->image + ctx->idx; 2509 emit(A64_NOP, ctx); 2510 } 2511 } 2512 2513 struct arg_aux { 2514 /* how many args are passed through registers, the rest of the args are 2515 * passed through stack 2516 */ 2517 int args_in_regs; 2518 /* how many registers are used to pass arguments */ 2519 int regs_for_args; 2520 /* how much stack is used for additional args passed to bpf program 2521 * that did not fit in original function registers 2522 */ 2523 int bstack_for_args; 2524 /* home much stack is used for additional args passed to the 2525 * original function when called from trampoline (this one needs 2526 * arguments to be properly aligned) 2527 */ 2528 int ostack_for_args; 2529 }; 2530 2531 static int calc_arg_aux(const struct btf_func_model *m, 2532 struct arg_aux *a) 2533 { 2534 int stack_slots, nregs, slots, i; 2535 2536 /* verifier ensures m->nr_args <= MAX_BPF_FUNC_ARGS */ 2537 for (i = 0, nregs = 0; i < m->nr_args; i++) { 2538 slots = (m->arg_size[i] + 7) / 8; 2539 if (nregs + slots <= 8) /* passed through register ? */ 2540 nregs += slots; 2541 else 2542 break; 2543 } 2544 2545 a->args_in_regs = i; 2546 a->regs_for_args = nregs; 2547 a->ostack_for_args = 0; 2548 a->bstack_for_args = 0; 2549 2550 /* the rest arguments are passed through stack */ 2551 for (; i < m->nr_args; i++) { 2552 stack_slots = (m->arg_size[i] + 7) / 8; 2553 a->bstack_for_args += stack_slots * 8; 2554 a->ostack_for_args = a->ostack_for_args + stack_slots * 8; 2555 } 2556 2557 return 0; 2558 } 2559 2560 static void clear_garbage(struct jit_ctx *ctx, int reg, int effective_bytes) 2561 { 2562 if (effective_bytes) { 2563 int garbage_bits = 64 - 8 * effective_bytes; 2564 #ifdef CONFIG_CPU_BIG_ENDIAN 2565 /* garbage bits are at the right end */ 2566 emit(A64_LSR(1, reg, reg, garbage_bits), ctx); 2567 emit(A64_LSL(1, reg, reg, garbage_bits), ctx); 2568 #else 2569 /* garbage bits are at the left end */ 2570 emit(A64_LSL(1, reg, reg, garbage_bits), ctx); 2571 emit(A64_LSR(1, reg, reg, garbage_bits), ctx); 2572 #endif 2573 } 2574 } 2575 2576 /* 2577 * Convert an arena kernel address into the arena pointer form on its way into 2578 * the BPF ctx, dst = (u32)(src - kern_vm_start), with @base_lo holding the low 2579 * 32 bits of kern_vm_start. A nullable arg preserves NULL, tested on the full 2580 * 64-bit kernel pointer. The 32-bit subtraction both truncates and clears the 2581 * upper half, so the stored value satisfies the JIT invariant for arena 2582 * pointer registers. 2583 */ 2584 static void emit_arena_arg_conv(struct jit_ctx *ctx, u8 dst, u8 src, bool nullable, u8 base_lo) 2585 { 2586 if (nullable) { 2587 if (dst != src) 2588 emit(A64_MOV(1, dst, src), ctx); 2589 /* skip the subtraction so that NULL stays NULL */ 2590 emit(A64_CBZ(1, dst, 2), ctx); 2591 src = dst; 2592 } 2593 emit(A64_SUB(0, dst, src, base_lo), ctx); 2594 } 2595 2596 static void save_args(struct jit_ctx *ctx, int bargs_off, int oargs_off, 2597 const struct btf_func_model *m, const struct arg_aux *a, 2598 bool for_call_origin, bool is_struct_ops, u64 arena_base) 2599 { 2600 u8 tmp = bpf2a64[TMP_REG_1]; 2601 u8 base_lo = bpf2a64[TMP_REG_2]; 2602 int i, reg, doff, soff, slots; 2603 2604 /* only the low 32 bits of the base take part in the subtraction */ 2605 if (arena_base) 2606 emit_a64_mov_i(0, base_lo, (s32)(u32)arena_base, ctx); 2607 2608 /* store arguments to the stack for the bpf program, or restore 2609 * arguments from stack for the original function 2610 */ 2611 for (i = 0, reg = 0; i < a->args_in_regs; i++) { 2612 bool arena_arg = arena_base && (m->arg_flags[i] & BTF_FMODEL_ARENA_ARG); 2613 bool nullable = m->arg_flags[i] & BTF_FMODEL_NULLABLE_ARG; 2614 2615 slots = (m->arg_size[i] + 7) / 8; 2616 while (slots-- > 0) { 2617 if (for_call_origin) { 2618 emit(A64_LDR64I(reg, A64_SP, bargs_off), ctx); 2619 } else if (arena_arg) { 2620 emit_arena_arg_conv(ctx, tmp, reg, nullable, base_lo); 2621 emit(A64_STR64I(tmp, A64_SP, bargs_off), ctx); 2622 } else { 2623 emit(A64_STR64I(reg, A64_SP, bargs_off), ctx); 2624 } 2625 reg++; 2626 bargs_off += 8; 2627 } 2628 } 2629 2630 /* 2631 * On-stack arguments start above the frame(s) pushed by the trampoline 2632 * prologue. Entered through the fentry call from a traced function, the 2633 * prologue saves both the parent (FP/x9) and the traced function 2634 * (FP/LR) frames, so the arguments start at FP + 32. A struct_ops 2635 * callback is called indirectly and only the FP/LR frame is saved, so 2636 * they start at FP + 16. 2637 */ 2638 soff = is_struct_ops ? 16 : 32; 2639 doff = (for_call_origin ? oargs_off : bargs_off); 2640 2641 /* save on stack arguments */ 2642 for (i = a->args_in_regs; i < m->nr_args; i++) { 2643 bool arena_arg = arena_base && (m->arg_flags[i] & BTF_FMODEL_ARENA_ARG); 2644 bool nullable = m->arg_flags[i] & BTF_FMODEL_NULLABLE_ARG; 2645 2646 slots = (m->arg_size[i] + 7) / 8; 2647 /* verifier ensures arg_size <= 16, so slots equals 1 or 2 */ 2648 while (slots-- > 0) { 2649 emit(A64_LDR64I(tmp, A64_FP, soff), ctx); 2650 /* if there is unused space in the last slot, clear 2651 * the garbage contained in the space. 2652 */ 2653 if (slots == 0 && !for_call_origin) 2654 clear_garbage(ctx, tmp, m->arg_size[i] % 8); 2655 /* 2656 * No guard on for_call_origin here: only the indirect 2657 * trampoline is given a base, and it never calls the 2658 * original function, so arguments are never converted 2659 * on their way back out to it. See the WARN_ON_ONCE() 2660 * in prepare_trampoline(). 2661 */ 2662 if (arena_arg) 2663 emit_arena_arg_conv(ctx, tmp, tmp, nullable, base_lo); 2664 emit(A64_STR64I(tmp, A64_SP, doff), ctx); 2665 soff += 8; 2666 doff += 8; 2667 } 2668 } 2669 } 2670 2671 static void restore_args(struct jit_ctx *ctx, int bargs_off, int nregs) 2672 { 2673 int reg; 2674 2675 for (reg = 0; reg < nregs; reg++) { 2676 emit(A64_LDR64I(reg, A64_SP, bargs_off), ctx); 2677 bargs_off += 8; 2678 } 2679 } 2680 2681 static void store_func_meta(struct jit_ctx *ctx, u64 func_meta, int func_meta_off) 2682 { 2683 emit_a64_mov_i64(A64_R(10), func_meta, ctx); 2684 emit(A64_STR64I(A64_R(10), A64_SP, func_meta_off), ctx); 2685 } 2686 2687 /* Based on the x86's implementation of arch_prepare_bpf_trampoline(). 2688 * 2689 * bpf prog and function entry before bpf trampoline hooked: 2690 * mov x9, lr 2691 * nop 2692 * 2693 * bpf prog and function entry after bpf trampoline hooked: 2694 * mov x9, lr 2695 * bl <bpf_trampoline or plt> 2696 * 2697 */ 2698 static int prepare_trampoline(struct jit_ctx *ctx, struct bpf_tramp_image *im, 2699 struct bpf_tramp_nodes *tnodes, void *func_addr, 2700 const struct btf_func_model *m, 2701 const struct arg_aux *a, 2702 u32 flags) 2703 { 2704 int i; 2705 int stack_size; 2706 int retaddr_off; 2707 int regs_off; 2708 int retval_off; 2709 int bargs_off; 2710 int func_meta_off; 2711 int ip_off; 2712 int run_ctx_off; 2713 int oargs_off; 2714 int nfuncargs; 2715 struct bpf_tramp_nodes *fentry = &tnodes[BPF_TRAMP_FENTRY]; 2716 struct bpf_tramp_nodes *fexit = &tnodes[BPF_TRAMP_FEXIT]; 2717 struct bpf_tramp_nodes *fmod_ret = &tnodes[BPF_TRAMP_MODIFY_RETURN]; 2718 bool save_ret; 2719 __le32 **branches = NULL; 2720 bool is_struct_ops = is_struct_ops_tramp(fentry); 2721 int cookie_off, cookie_cnt, cookie_bargs_off; 2722 int fsession_cnt = bpf_fsession_cnt(tnodes); 2723 u64 arena_base; 2724 u64 func_meta; 2725 2726 /* 2727 * F_INDIRECT is only compatible with F_RET_FENTRY_RET, it is explicitly 2728 * incompatible with F_CALL_ORIG | F_SKIP_FRAME | F_IP_ARG because 2729 * @func_addr. Arena conversion relies on this: bpf_tramp_arena_base() 2730 * only returns a base for the indirect trampoline, which therefore 2731 * never calls the original function with converted arguments. 2732 */ 2733 WARN_ON_ONCE((flags & BPF_TRAMP_F_INDIRECT) && 2734 (flags & ~(BPF_TRAMP_F_INDIRECT | BPF_TRAMP_F_RET_FENTRY_RET))); 2735 2736 arena_base = bpf_tramp_arena_base(m, tnodes, flags); 2737 2738 /* trampoline stack layout: 2739 * [ parent ip ] 2740 * [ FP ] 2741 * SP + retaddr_off [ self ip ] 2742 * [ FP ] 2743 * 2744 * [ padding ] align SP to multiples of 16 2745 * 2746 * [ x20 ] callee saved reg x20 2747 * SP + regs_off [ x19 ] callee saved reg x19 2748 * 2749 * SP + retval_off [ return value ] BPF_TRAMP_F_CALL_ORIG or 2750 * BPF_TRAMP_F_RET_FENTRY_RET 2751 * [ arg reg N ] 2752 * [ ... ] 2753 * SP + bargs_off [ arg reg 1 ] for bpf 2754 * 2755 * SP + func_meta_off [ regs count, etc ] 2756 * 2757 * SP + ip_off [ traced function ] BPF_TRAMP_F_IP_ARG flag 2758 * 2759 * [ stack cookie N ] 2760 * [ ... ] 2761 * SP + cookie_off [ stack cookie 1 ] 2762 * 2763 * SP + run_ctx_off [ bpf_tramp_run_ctx ] 2764 * 2765 * [ stack arg N ] 2766 * [ ... ] 2767 * SP + oargs_off [ stack arg 1 ] for original func 2768 */ 2769 2770 stack_size = 0; 2771 oargs_off = stack_size; 2772 if (flags & BPF_TRAMP_F_CALL_ORIG) 2773 stack_size += a->ostack_for_args; 2774 2775 run_ctx_off = stack_size; 2776 /* room for bpf_tramp_run_ctx */ 2777 stack_size += round_up(sizeof(struct bpf_tramp_run_ctx), 8); 2778 2779 cookie_off = stack_size; 2780 /* room for session cookies */ 2781 cookie_cnt = bpf_fsession_cookie_cnt(tnodes); 2782 stack_size += cookie_cnt * 8; 2783 2784 ip_off = stack_size; 2785 /* room for IP address argument */ 2786 if (flags & BPF_TRAMP_F_IP_ARG) 2787 stack_size += 8; 2788 2789 func_meta_off = stack_size; 2790 /* room for function metadata, such as regs count */ 2791 stack_size += 8; 2792 2793 bargs_off = stack_size; 2794 /* room for args */ 2795 nfuncargs = a->regs_for_args + a->bstack_for_args / 8; 2796 stack_size += 8 * nfuncargs; 2797 2798 /* room for return value */ 2799 retval_off = stack_size; 2800 save_ret = flags & (BPF_TRAMP_F_CALL_ORIG | BPF_TRAMP_F_RET_FENTRY_RET); 2801 if (save_ret) 2802 stack_size += 8; 2803 2804 /* room for callee saved registers, currently x19 and x20 are used */ 2805 regs_off = stack_size; 2806 stack_size += 16; 2807 2808 /* round up to multiples of 16 to avoid SPAlignmentFault */ 2809 stack_size = round_up(stack_size, 16); 2810 2811 /* return address locates above FP */ 2812 retaddr_off = stack_size + 8; 2813 2814 if (flags & BPF_TRAMP_F_INDIRECT) { 2815 /* 2816 * Indirect call for bpf_struct_ops 2817 */ 2818 emit_kcfi(cfi_get_func_hash(func_addr), ctx); 2819 } 2820 /* bpf trampoline may be invoked by 3 instruction types: 2821 * 1. bl, attached to bpf prog or kernel function via short jump 2822 * 2. br, attached to bpf prog or kernel function via long jump 2823 * 3. blr, working as a function pointer, used by struct_ops. 2824 * So BTI_JC should used here to support both br and blr. 2825 */ 2826 emit_bti(A64_BTI_JC, ctx); 2827 2828 /* x9 is not set for struct_ops */ 2829 if (!is_struct_ops) { 2830 /* frame for parent function */ 2831 emit(A64_PUSH(A64_FP, A64_R(9), A64_SP), ctx); 2832 emit(A64_MOV(1, A64_FP, A64_SP), ctx); 2833 } 2834 2835 /* frame for patched function for tracing, or caller for struct_ops */ 2836 emit(A64_PUSH(A64_FP, A64_LR, A64_SP), ctx); 2837 emit(A64_MOV(1, A64_FP, A64_SP), ctx); 2838 2839 /* allocate stack space */ 2840 emit(A64_SUB_I(1, A64_SP, A64_SP, stack_size), ctx); 2841 2842 if (flags & BPF_TRAMP_F_IP_ARG) { 2843 /* save ip address of the traced function */ 2844 emit_addr_mov_i64(A64_R(10), (const u64)func_addr, ctx); 2845 emit(A64_STR64I(A64_R(10), A64_SP, ip_off), ctx); 2846 } 2847 2848 /* save function metadata */ 2849 func_meta = nfuncargs; 2850 store_func_meta(ctx, func_meta, func_meta_off); 2851 2852 /* save args for bpf */ 2853 save_args(ctx, bargs_off, oargs_off, m, a, false, is_struct_ops, arena_base); 2854 2855 /* save callee saved registers */ 2856 emit(A64_STR64I(A64_R(19), A64_SP, regs_off), ctx); 2857 emit(A64_STR64I(A64_R(20), A64_SP, regs_off + 8), ctx); 2858 2859 if (flags & BPF_TRAMP_F_CALL_ORIG) { 2860 /* for the first pass, assume the worst case */ 2861 if (!ctx->image) 2862 ctx->idx += 4; 2863 else 2864 emit_a64_mov_i64(A64_R(0), (const u64)im, ctx); 2865 emit_call((const u64)__bpf_tramp_enter, ctx); 2866 } 2867 2868 if (fsession_cnt) { 2869 /* clear all the session cookies' value */ 2870 emit(A64_MOVZ(1, A64_R(10), 0, 0), ctx); 2871 for (int i = 0; i < cookie_cnt; i++) 2872 emit(A64_STR64I(A64_R(10), A64_SP, cookie_off + 8 * i), ctx); 2873 /* clear the return value to make sure fentry always gets 0 */ 2874 emit(A64_STR64I(A64_R(10), A64_SP, retval_off), ctx); 2875 } 2876 2877 cookie_bargs_off = (bargs_off - cookie_off) / 8; 2878 for (i = 0; i < fentry->nr_nodes; i++) { 2879 if (bpf_prog_calls_session_cookie(fentry->nodes[i])) { 2880 u64 meta = func_meta | (cookie_bargs_off << BPF_TRAMP_COOKIE_INDEX_SHIFT); 2881 2882 store_func_meta(ctx, meta, func_meta_off); 2883 cookie_bargs_off--; 2884 } 2885 invoke_bpf_prog(ctx, fentry->nodes[i], bargs_off, 2886 retval_off, run_ctx_off, 2887 flags & BPF_TRAMP_F_RET_FENTRY_RET); 2888 } 2889 2890 if (fmod_ret->nr_nodes) { 2891 branches = kcalloc(fmod_ret->nr_nodes, sizeof(__le32 *), 2892 GFP_KERNEL); 2893 if (!branches) 2894 return -ENOMEM; 2895 2896 invoke_bpf_mod_ret(ctx, fmod_ret, bargs_off, retval_off, 2897 run_ctx_off, branches); 2898 } 2899 2900 if (flags & BPF_TRAMP_F_CALL_ORIG) { 2901 /* the original func takes kernel addresses, never converted ones */ 2902 save_args(ctx, bargs_off, oargs_off, m, a, true, is_struct_ops, 0); 2903 /* call original func */ 2904 emit(A64_LDR64I(A64_R(10), A64_SP, retaddr_off), ctx); 2905 emit(A64_ADR(A64_LR, AARCH64_INSN_SIZE * 2), ctx); 2906 emit(A64_RET(A64_R(10)), ctx); 2907 /* store return value */ 2908 emit(A64_STR64I(A64_R(0), A64_SP, retval_off), ctx); 2909 /* reserve a nop for bpf_tramp_image_put */ 2910 im->ip_after_call = ctx->ro_image + ctx->idx; 2911 emit(A64_NOP, ctx); 2912 } 2913 2914 /* update the branches saved in invoke_bpf_mod_ret with cbnz */ 2915 for (i = 0; i < fmod_ret->nr_nodes && ctx->image != NULL; i++) { 2916 int offset = &ctx->image[ctx->idx] - branches[i]; 2917 *branches[i] = cpu_to_le32(A64_CBNZ(1, A64_R(10), offset)); 2918 } 2919 2920 /* set the "is_return" flag for fsession */ 2921 func_meta |= (1ULL << BPF_TRAMP_IS_RETURN_SHIFT); 2922 if (fsession_cnt) 2923 store_func_meta(ctx, func_meta, func_meta_off); 2924 2925 cookie_bargs_off = (bargs_off - cookie_off) / 8; 2926 for (i = 0; i < fexit->nr_nodes; i++) { 2927 if (bpf_prog_calls_session_cookie(fexit->nodes[i])) { 2928 u64 meta = func_meta | (cookie_bargs_off << BPF_TRAMP_COOKIE_INDEX_SHIFT); 2929 2930 store_func_meta(ctx, meta, func_meta_off); 2931 cookie_bargs_off--; 2932 } 2933 invoke_bpf_prog(ctx, fexit->nodes[i], bargs_off, retval_off, 2934 run_ctx_off, false); 2935 } 2936 2937 if (flags & BPF_TRAMP_F_CALL_ORIG) { 2938 im->ip_epilogue = ctx->ro_image + ctx->idx; 2939 /* for the first pass, assume the worst case */ 2940 if (!ctx->image) 2941 ctx->idx += 4; 2942 else 2943 emit_a64_mov_i64(A64_R(0), (const u64)im, ctx); 2944 emit_call((const u64)__bpf_tramp_exit, ctx); 2945 } 2946 2947 if (flags & BPF_TRAMP_F_RESTORE_REGS) 2948 restore_args(ctx, bargs_off, a->regs_for_args); 2949 2950 /* restore callee saved register x19 and x20 */ 2951 emit(A64_LDR64I(A64_R(19), A64_SP, regs_off), ctx); 2952 emit(A64_LDR64I(A64_R(20), A64_SP, regs_off + 8), ctx); 2953 2954 if (save_ret) 2955 emit(A64_LDR64I(A64_R(0), A64_SP, retval_off), ctx); 2956 2957 /* reset SP */ 2958 emit(A64_MOV(1, A64_SP, A64_FP), ctx); 2959 2960 if (is_struct_ops) { 2961 emit(A64_POP(A64_FP, A64_LR, A64_SP), ctx); 2962 emit(A64_RET(A64_LR), ctx); 2963 } else { 2964 /* pop frames */ 2965 emit(A64_POP(A64_FP, A64_LR, A64_SP), ctx); 2966 emit(A64_POP(A64_FP, A64_R(9), A64_SP), ctx); 2967 2968 if (flags & BPF_TRAMP_F_SKIP_FRAME) { 2969 /* skip patched function, return to parent */ 2970 emit(A64_MOV(1, A64_LR, A64_R(9)), ctx); 2971 emit(A64_RET(A64_R(9)), ctx); 2972 } else { 2973 /* return to patched function */ 2974 emit(A64_MOV(1, A64_R(10), A64_LR), ctx); 2975 emit(A64_MOV(1, A64_LR, A64_R(9)), ctx); 2976 emit(A64_RET(A64_R(10)), ctx); 2977 } 2978 } 2979 2980 kfree(branches); 2981 2982 return ctx->idx; 2983 } 2984 2985 bool bpf_jit_supports_fsession(void) 2986 { 2987 return true; 2988 } 2989 2990 int arch_bpf_trampoline_size(const struct btf_func_model *m, u32 flags, 2991 struct bpf_tramp_nodes *tnodes, void *func_addr) 2992 { 2993 struct jit_ctx ctx = { 2994 .image = NULL, 2995 .idx = 0, 2996 }; 2997 struct bpf_tramp_image im; 2998 struct arg_aux aaux; 2999 int ret; 3000 3001 ret = calc_arg_aux(m, &aaux); 3002 if (ret < 0) 3003 return ret; 3004 3005 ret = prepare_trampoline(&ctx, &im, tnodes, func_addr, m, &aaux, flags); 3006 if (ret < 0) 3007 return ret; 3008 3009 return ret < 0 ? ret : ret * AARCH64_INSN_SIZE; 3010 } 3011 3012 void *arch_alloc_bpf_trampoline(unsigned int size) 3013 { 3014 return bpf_prog_pack_alloc(size, jit_fill_hole, false); 3015 } 3016 3017 void arch_free_bpf_trampoline(void *image, unsigned int size) 3018 { 3019 bpf_prog_pack_free(image, size); 3020 } 3021 3022 int arch_protect_bpf_trampoline(void *image, unsigned int size) 3023 { 3024 return 0; 3025 } 3026 3027 int arch_prepare_bpf_trampoline(struct bpf_tramp_image *im, void *ro_image, 3028 void *ro_image_end, const struct btf_func_model *m, 3029 u32 flags, struct bpf_tramp_nodes *tnodes, 3030 void *func_addr) 3031 { 3032 u32 size = ro_image_end - ro_image; 3033 struct arg_aux aaux; 3034 void *image, *tmp; 3035 int ret; 3036 3037 /* image doesn't need to be in module memory range, so we can 3038 * use kvmalloc. 3039 */ 3040 image = kvmalloc(size, GFP_KERNEL); 3041 if (!image) 3042 return -ENOMEM; 3043 3044 struct jit_ctx ctx = { 3045 .image = image, 3046 .ro_image = ro_image, 3047 .idx = 0, 3048 .write = true, 3049 }; 3050 3051 3052 jit_fill_hole(image, (unsigned int)(ro_image_end - ro_image)); 3053 ret = calc_arg_aux(m, &aaux); 3054 if (ret) 3055 goto out; 3056 ret = prepare_trampoline(&ctx, im, tnodes, func_addr, m, &aaux, flags); 3057 3058 if (ret > 0 && validate_code(&ctx) < 0) { 3059 ret = -EINVAL; 3060 goto out; 3061 } 3062 3063 if (ret > 0) 3064 ret *= AARCH64_INSN_SIZE; 3065 3066 tmp = bpf_arch_text_copy(ro_image, image, size); 3067 if (IS_ERR(tmp)) { 3068 ret = PTR_ERR(tmp); 3069 goto out; 3070 } 3071 3072 out: 3073 kvfree(image); 3074 return ret; 3075 } 3076 3077 static bool is_long_jump(void *ip, void *target) 3078 { 3079 long offset; 3080 3081 /* NULL target means this is a NOP */ 3082 if (!target) 3083 return false; 3084 3085 offset = (long)target - (long)ip; 3086 return offset < -SZ_128M || offset >= SZ_128M; 3087 } 3088 3089 static int gen_branch_or_nop(enum aarch64_insn_branch_type type, void *ip, 3090 void *addr, void *plt, u32 *insn) 3091 { 3092 void *target; 3093 3094 if (!addr) { 3095 *insn = aarch64_insn_gen_nop(); 3096 return 0; 3097 } 3098 3099 if (is_long_jump(ip, addr)) 3100 target = plt; 3101 else 3102 target = addr; 3103 3104 *insn = aarch64_insn_gen_branch_imm((unsigned long)ip, 3105 (unsigned long)target, 3106 type); 3107 3108 return *insn != AARCH64_BREAK_FAULT ? 0 : -EFAULT; 3109 } 3110 3111 /* Replace the branch instruction from @ip to @old_addr in a bpf prog or a bpf 3112 * trampoline with the branch instruction from @ip to @new_addr. If @old_addr 3113 * or @new_addr is NULL, the old or new instruction is NOP. 3114 * 3115 * When @ip is the bpf prog entry, a bpf trampoline is being attached or 3116 * detached. Since bpf trampoline and bpf prog are allocated separately with 3117 * vmalloc, the address distance may exceed 128MB, the maximum branch range. 3118 * So long jump should be handled. 3119 * 3120 * When a bpf prog is constructed, a plt pointing to empty trampoline 3121 * dummy_tramp is placed at the end: 3122 * 3123 * bpf_prog: 3124 * mov x9, lr 3125 * nop // patchsite 3126 * ... 3127 * ret 3128 * 3129 * plt: 3130 * ldr x10, target 3131 * br x10 3132 * target: 3133 * .quad dummy_tramp // plt target 3134 * 3135 * This is also the state when no trampoline is attached. 3136 * 3137 * When a short-jump bpf trampoline is attached, the patchsite is patched 3138 * to a bl instruction to the trampoline directly: 3139 * 3140 * bpf_prog: 3141 * mov x9, lr 3142 * bl <short-jump bpf trampoline address> // patchsite 3143 * ... 3144 * ret 3145 * 3146 * plt: 3147 * ldr x10, target 3148 * br x10 3149 * target: 3150 * .quad dummy_tramp // plt target 3151 * 3152 * When a long-jump bpf trampoline is attached, the plt target is filled with 3153 * the trampoline address and the patchsite is patched to a bl instruction to 3154 * the plt: 3155 * 3156 * bpf_prog: 3157 * mov x9, lr 3158 * bl plt // patchsite 3159 * ... 3160 * ret 3161 * 3162 * plt: 3163 * ldr x10, target 3164 * br x10 3165 * target: 3166 * .quad <long-jump bpf trampoline address> // plt target 3167 * 3168 * The dummy_tramp is used to prevent another CPU from jumping to unknown 3169 * locations during the patching process, making the patching process easier. 3170 */ 3171 int bpf_arch_text_poke(void *ip, enum bpf_text_poke_type old_t, 3172 enum bpf_text_poke_type new_t, void *old_addr, 3173 void *new_addr) 3174 { 3175 int ret; 3176 u32 old_insn; 3177 u32 new_insn; 3178 u32 replaced; 3179 struct bpf_plt *plt = NULL; 3180 unsigned long size = 0UL; 3181 unsigned long offset = ~0UL; 3182 enum aarch64_insn_branch_type branch_type; 3183 char namebuf[KSYM_NAME_LEN]; 3184 void *image = NULL; 3185 u64 plt_target = 0ULL; 3186 bool poking_bpf_entry; 3187 3188 if (!bpf_address_lookup((unsigned long)ip, &size, &offset, namebuf)) 3189 /* Only poking bpf text is supported. Since kernel function 3190 * entry is set up by ftrace, we reply on ftrace to poke kernel 3191 * functions. 3192 */ 3193 return -ENOTSUPP; 3194 3195 image = ip - offset; 3196 /* zero offset means we're poking bpf prog entry */ 3197 poking_bpf_entry = (offset == 0UL); 3198 3199 /* bpf prog entry, find plt and the real patchsite */ 3200 if (poking_bpf_entry) { 3201 /* plt locates at the end of bpf prog */ 3202 plt = image + size - PLT_TARGET_OFFSET; 3203 3204 /* skip to the nop instruction in bpf prog entry: 3205 * bti c // if BTI enabled 3206 * mov x9, x30 3207 * nop 3208 */ 3209 ip = image + POKE_OFFSET * AARCH64_INSN_SIZE; 3210 } 3211 3212 /* long jump is only possible at bpf prog entry */ 3213 if (WARN_ON((is_long_jump(ip, new_addr) || is_long_jump(ip, old_addr)) && 3214 !poking_bpf_entry)) 3215 return -EINVAL; 3216 3217 branch_type = old_t == BPF_MOD_CALL ? AARCH64_INSN_BRANCH_LINK : 3218 AARCH64_INSN_BRANCH_NOLINK; 3219 if (gen_branch_or_nop(branch_type, ip, old_addr, plt, &old_insn) < 0) 3220 return -EFAULT; 3221 3222 branch_type = new_t == BPF_MOD_CALL ? AARCH64_INSN_BRANCH_LINK : 3223 AARCH64_INSN_BRANCH_NOLINK; 3224 if (gen_branch_or_nop(branch_type, ip, new_addr, plt, &new_insn) < 0) 3225 return -EFAULT; 3226 3227 if (is_long_jump(ip, new_addr)) 3228 plt_target = (u64)new_addr; 3229 else if (is_long_jump(ip, old_addr)) 3230 /* if the old target is a long jump and the new target is not, 3231 * restore the plt target to dummy_tramp, so there is always a 3232 * legal and harmless address stored in plt target, and we'll 3233 * never jump from plt to an unknown place. 3234 */ 3235 plt_target = (u64)&dummy_tramp; 3236 3237 if (plt_target) { 3238 /* non-zero plt_target indicates we're patching a bpf prog, 3239 * which is read only. 3240 */ 3241 if (set_memory_rw(PAGE_MASK & ((uintptr_t)&plt->target), 1)) 3242 return -EFAULT; 3243 WRITE_ONCE(plt->target, plt_target); 3244 set_memory_ro(PAGE_MASK & ((uintptr_t)&plt->target), 1); 3245 /* since plt target points to either the new trampoline 3246 * or dummy_tramp, even if another CPU reads the old plt 3247 * target value before fetching the bl instruction to plt, 3248 * it will be brought back by dummy_tramp, so no barrier is 3249 * required here. 3250 */ 3251 } 3252 3253 /* if the old target and the new target are both long jumps, no 3254 * patching is required 3255 */ 3256 if (old_insn == new_insn) 3257 return 0; 3258 3259 mutex_lock(&text_mutex); 3260 if (aarch64_insn_read(ip, &replaced)) { 3261 ret = -EFAULT; 3262 goto out; 3263 } 3264 3265 if (replaced != old_insn) { 3266 ret = -EFAULT; 3267 goto out; 3268 } 3269 3270 /* We call aarch64_insn_patch_text_nosync() to replace instruction 3271 * atomically, so no other CPUs will fetch a half-new and half-old 3272 * instruction. But there is chance that another CPU executes the 3273 * old instruction after the patching operation finishes (e.g., 3274 * pipeline not flushed, or icache not synchronized yet). 3275 * 3276 * 1. when a new trampoline is attached, it is not a problem for 3277 * different CPUs to jump to different trampolines temporarily. 3278 * 3279 * 2. when an old trampoline is freed, we should wait for all other 3280 * CPUs to exit the trampoline and make sure the trampoline is no 3281 * longer reachable, since bpf_tramp_image_put() function already 3282 * uses percpu_ref and task-based rcu to do the sync, no need to call 3283 * the sync version here, see bpf_tramp_image_put() for details. 3284 */ 3285 ret = aarch64_insn_patch_text_nosync(ip, new_insn); 3286 out: 3287 mutex_unlock(&text_mutex); 3288 3289 return ret; 3290 } 3291 3292 bool bpf_jit_supports_ptr_xchg(void) 3293 { 3294 return true; 3295 } 3296 3297 bool bpf_jit_supports_exceptions(void) 3298 { 3299 /* We unwind through both kernel frames starting from within bpf_throw 3300 * call and BPF frames. Therefore we require FP unwinder to be enabled 3301 * to walk kernel frames and reach BPF frames in the stack trace. 3302 * ARM64 kernel is always compiled with CONFIG_FRAME_POINTER=y 3303 */ 3304 return true; 3305 } 3306 3307 bool bpf_jit_supports_arena(void) 3308 { 3309 return true; 3310 } 3311 3312 bool bpf_jit_supports_insn(struct bpf_insn *insn, bool in_arena) 3313 { 3314 if (!in_arena) 3315 return true; 3316 switch (insn->code) { 3317 case BPF_STX | BPF_ATOMIC | BPF_W: 3318 case BPF_STX | BPF_ATOMIC | BPF_DW: 3319 if (!bpf_atomic_is_load_store(insn) && 3320 !cpus_have_cap(ARM64_HAS_LSE_ATOMICS)) 3321 return false; 3322 } 3323 return true; 3324 } 3325 3326 bool bpf_jit_supports_percpu_insn(void) 3327 { 3328 return true; 3329 } 3330 3331 bool bpf_jit_bypass_spec_v4(void) 3332 { 3333 /* In case of arm64, we rely on the firmware mitigation of Speculative 3334 * Store Bypass as controlled via the ssbd kernel parameter. Whenever 3335 * the mitigation is enabled, it works for all of the kernel code with 3336 * no need to provide any additional instructions. Therefore, skip 3337 * inserting nospec insns against Spectre v4. 3338 */ 3339 return true; 3340 } 3341 3342 bool bpf_jit_supports_timed_may_goto(void) 3343 { 3344 return true; 3345 } 3346 3347 bool bpf_jit_inlines_helper_call(s32 imm) 3348 { 3349 switch (imm) { 3350 case BPF_FUNC_get_smp_processor_id: 3351 case BPF_FUNC_get_current_task: 3352 case BPF_FUNC_get_current_task_btf: 3353 return true; 3354 default: 3355 return false; 3356 } 3357 } 3358 3359 void bpf_jit_free(struct bpf_prog *prog) 3360 { 3361 if (prog->jited) { 3362 struct arm64_jit_data *jit_data = prog->aux->jit_data; 3363 struct bpf_binary_header *hdr; 3364 void __percpu *priv_stack_ptr; 3365 int priv_stack_alloc_sz; 3366 3367 /* 3368 * If we fail the final pass of JIT (from jit_subprogs), 3369 * the program may not be finalized yet. Call finalize here 3370 * before freeing it. 3371 */ 3372 if (jit_data) { 3373 bpf_jit_binary_pack_finalize(jit_data->ro_header, jit_data->header); 3374 kfree(jit_data); 3375 } 3376 prog->bpf_func = (void *)prog->bpf_func - cfi_get_offset(); 3377 hdr = bpf_jit_binary_pack_hdr(prog); 3378 bpf_jit_binary_pack_free(hdr, NULL); 3379 priv_stack_ptr = prog->aux->priv_stack_ptr; 3380 if (priv_stack_ptr) { 3381 priv_stack_alloc_sz = round_up(prog->aux->stack_depth, 16) + 3382 2 * PRIV_STACK_GUARD_SZ; 3383 priv_stack_check_guard(priv_stack_ptr, priv_stack_alloc_sz, prog); 3384 free_percpu(prog->aux->priv_stack_ptr); 3385 } 3386 WARN_ON_ONCE(!bpf_prog_kallsyms_verify_off(prog)); 3387 } 3388 3389 bpf_prog_unlock_free(prog); 3390 } 3391