1 // SPDX-License-Identifier: ISC
2 /*
3 * Copyright (c) 2014 Broadcom Corporation
4 */
5
6 #include <linux/kernel.h>
7 #include <linux/module.h>
8 #include <linux/firmware.h>
9 #include <linux/pci.h>
10 #include <linux/vmalloc.h>
11 #include <linux/delay.h>
12 #include <linux/interrupt.h>
13 #include <linux/bcma/bcma.h>
14 #include <linux/sched.h>
15 #include <linux/sched/signal.h>
16 #include <linux/kthread.h>
17 #include <linux/io.h>
18 #include <linux/random.h>
19 #include <linux/unaligned.h>
20
21 #include <soc.h>
22 #include <chipcommon.h>
23 #include <brcmu_utils.h>
24 #include <brcmu_wifi.h>
25 #include <brcm_hw_ids.h>
26
27 /* Custom brcmf_err() that takes bus arg and passes it further */
28 #define brcmf_err(bus, fmt, ...) \
29 do { \
30 if (IS_ENABLED(CONFIG_BRCMDBG) || \
31 IS_ENABLED(CONFIG_BRCM_TRACING) || \
32 net_ratelimit()) \
33 __brcmf_err(bus, __func__, fmt, ##__VA_ARGS__); \
34 } while (0)
35
36 #include "debug.h"
37 #include "bus.h"
38 #include "commonring.h"
39 #include "msgbuf.h"
40 #include "pcie.h"
41 #include "firmware.h"
42 #include "chip.h"
43 #include "core.h"
44 #include "common.h"
45
46
47 enum brcmf_pcie_state {
48 BRCMFMAC_PCIE_STATE_DOWN,
49 BRCMFMAC_PCIE_STATE_UP
50 };
51
52 BRCMF_FW_DEF(43602, "brcmfmac43602-pcie");
53 BRCMF_FW_DEF(4350, "brcmfmac4350-pcie");
54 BRCMF_FW_DEF(4350C, "brcmfmac4350c2-pcie");
55 BRCMF_FW_CLM_DEF(4355, "brcmfmac4355-pcie");
56 BRCMF_FW_CLM_DEF(4355C1, "brcmfmac4355c1-pcie");
57 BRCMF_FW_CLM_DEF(4356, "brcmfmac4356-pcie");
58 BRCMF_FW_CLM_DEF(43570, "brcmfmac43570-pcie");
59 BRCMF_FW_DEF(4358, "brcmfmac4358-pcie");
60 BRCMF_FW_DEF(4359, "brcmfmac4359-pcie");
61 BRCMF_FW_DEF(4359C, "brcmfmac4359c-pcie");
62 BRCMF_FW_CLM_DEF(4364B2, "brcmfmac4364b2-pcie");
63 BRCMF_FW_CLM_DEF(4364B3, "brcmfmac4364b3-pcie");
64 BRCMF_FW_DEF(4365B, "brcmfmac4365b-pcie");
65 BRCMF_FW_DEF(4365C, "brcmfmac4365c-pcie");
66 BRCMF_FW_DEF(4366B, "brcmfmac4366b-pcie");
67 BRCMF_FW_DEF(4366C, "brcmfmac4366c-pcie");
68 BRCMF_FW_DEF(4371, "brcmfmac4371-pcie");
69 BRCMF_FW_CLM_DEF(4377B3, "brcmfmac4377b3-pcie");
70 BRCMF_FW_CLM_DEF(4378B1, "brcmfmac4378b1-pcie");
71 BRCMF_FW_CLM_DEF(4378B3, "brcmfmac4378b3-pcie");
72 BRCMF_FW_CLM_DEF(4387C2, "brcmfmac4387c2-pcie");
73
74 /* firmware config files */
75 MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.txt");
76 MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.*.txt");
77
78 /* per-board firmware binaries */
79 MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.*.bin");
80 MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.*.clm_blob");
81 MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.*.txcap_blob");
82
83 static const struct brcmf_firmware_mapping brcmf_pcie_fwnames[] = {
84 BRCMF_FW_ENTRY(BRCM_CC_43602_CHIP_ID, 0xFFFFFFFF, 43602),
85 BRCMF_FW_ENTRY(BRCM_CC_43465_CHIP_ID, 0xFFFFFFF0, 4366C),
86 BRCMF_FW_ENTRY(BRCM_CC_4350_CHIP_ID, 0x000000FF, 4350C),
87 BRCMF_FW_ENTRY(BRCM_CC_4350_CHIP_ID, 0xFFFFFF00, 4350),
88 BRCMF_FW_ENTRY(BRCM_CC_43525_CHIP_ID, 0xFFFFFFF0, 4365C),
89 BRCMF_FW_ENTRY(BRCM_CC_4355_CHIP_ID, 0x000007FF, 4355),
90 BRCMF_FW_ENTRY(BRCM_CC_4355_CHIP_ID, 0xFFFFF800, 4355C1), /* rev ID 12/C2 seen */
91 BRCMF_FW_ENTRY(BRCM_CC_4356_CHIP_ID, 0xFFFFFFFF, 4356),
92 BRCMF_FW_ENTRY(BRCM_CC_43567_CHIP_ID, 0xFFFFFFFF, 43570),
93 BRCMF_FW_ENTRY(BRCM_CC_43569_CHIP_ID, 0xFFFFFFFF, 43570),
94 BRCMF_FW_ENTRY(BRCM_CC_43570_CHIP_ID, 0xFFFFFFFF, 43570),
95 BRCMF_FW_ENTRY(BRCM_CC_4358_CHIP_ID, 0xFFFFFFFF, 4358),
96 BRCMF_FW_ENTRY(BRCM_CC_4359_CHIP_ID, 0x000001FF, 4359),
97 BRCMF_FW_ENTRY(BRCM_CC_4359_CHIP_ID, 0xFFFFFE00, 4359C),
98 BRCMF_FW_ENTRY(BRCM_CC_4364_CHIP_ID, 0x0000000F, 4364B2), /* 3 */
99 BRCMF_FW_ENTRY(BRCM_CC_4364_CHIP_ID, 0xFFFFFFF0, 4364B3), /* 4 */
100 BRCMF_FW_ENTRY(BRCM_CC_4365_CHIP_ID, 0x0000000F, 4365B),
101 BRCMF_FW_ENTRY(BRCM_CC_4365_CHIP_ID, 0xFFFFFFF0, 4365C),
102 BRCMF_FW_ENTRY(BRCM_CC_4366_CHIP_ID, 0x0000000F, 4366B),
103 BRCMF_FW_ENTRY(BRCM_CC_4366_CHIP_ID, 0xFFFFFFF0, 4366C),
104 BRCMF_FW_ENTRY(BRCM_CC_43664_CHIP_ID, 0xFFFFFFF0, 4366C),
105 BRCMF_FW_ENTRY(BRCM_CC_43666_CHIP_ID, 0xFFFFFFF0, 4366C),
106 BRCMF_FW_ENTRY(BRCM_CC_4371_CHIP_ID, 0xFFFFFFFF, 4371),
107 BRCMF_FW_ENTRY(BRCM_CC_4377_CHIP_ID, 0xFFFFFFFF, 4377B3), /* revision ID 4 */
108 BRCMF_FW_ENTRY(BRCM_CC_4378_CHIP_ID, 0x0000000F, 4378B1), /* revision ID 3 */
109 BRCMF_FW_ENTRY(BRCM_CC_4378_CHIP_ID, 0xFFFFFFE0, 4378B3), /* revision ID 5 */
110 BRCMF_FW_ENTRY(BRCM_CC_4387_CHIP_ID, 0xFFFFFFFF, 4387C2), /* revision ID 7 */
111 };
112
113 #define BRCMF_PCIE_FW_UP_TIMEOUT 5000 /* msec */
114
115 #define BRCMF_PCIE_REG_MAP_SIZE (32 * 1024)
116
117 /* backplane addres space accessed by BAR0 */
118 #define BRCMF_PCIE_BAR0_WINDOW 0x80
119 #define BRCMF_PCIE_BAR0_REG_SIZE 0x1000
120 #define BRCMF_PCIE_BAR0_WRAPPERBASE 0x70
121
122 #define BRCMF_PCIE_BAR0_WRAPBASE_DMP_OFFSET 0x1000
123 #define BRCMF_PCIE_BARO_PCIE_ENUM_OFFSET 0x2000
124
125 #define BRCMF_PCIE_ARMCR4REG_BANKIDX 0x40
126 #define BRCMF_PCIE_ARMCR4REG_BANKPDA 0x4C
127
128 #define BRCMF_PCIE_REG_INTSTATUS 0x90
129 #define BRCMF_PCIE_REG_INTMASK 0x94
130 #define BRCMF_PCIE_REG_SBMBX 0x98
131
132 #define BRCMF_PCIE_REG_LINK_STATUS_CTRL 0xBC
133
134 #define BRCMF_PCIE_PCIE2REG_INTMASK 0x24
135 #define BRCMF_PCIE_PCIE2REG_MAILBOXINT 0x48
136 #define BRCMF_PCIE_PCIE2REG_MAILBOXMASK 0x4C
137 #define BRCMF_PCIE_PCIE2REG_CONFIGADDR 0x120
138 #define BRCMF_PCIE_PCIE2REG_CONFIGDATA 0x124
139 #define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_0 0x140
140 #define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_1 0x144
141
142 #define BRCMF_PCIE_64_PCIE2REG_INTMASK 0xC14
143 #define BRCMF_PCIE_64_PCIE2REG_MAILBOXINT 0xC30
144 #define BRCMF_PCIE_64_PCIE2REG_MAILBOXMASK 0xC34
145 #define BRCMF_PCIE_64_PCIE2REG_H2D_MAILBOX_0 0xA20
146 #define BRCMF_PCIE_64_PCIE2REG_H2D_MAILBOX_1 0xA24
147
148 #define BRCMF_PCIE2_INTA 0x01
149 #define BRCMF_PCIE2_INTB 0x02
150
151 #define BRCMF_PCIE_INT_0 0x01
152 #define BRCMF_PCIE_INT_1 0x02
153 #define BRCMF_PCIE_INT_DEF (BRCMF_PCIE_INT_0 | \
154 BRCMF_PCIE_INT_1)
155
156 #define BRCMF_PCIE_MB_INT_FN0_0 0x0100
157 #define BRCMF_PCIE_MB_INT_FN0_1 0x0200
158 #define BRCMF_PCIE_MB_INT_D2H0_DB0 0x10000
159 #define BRCMF_PCIE_MB_INT_D2H0_DB1 0x20000
160 #define BRCMF_PCIE_MB_INT_D2H1_DB0 0x40000
161 #define BRCMF_PCIE_MB_INT_D2H1_DB1 0x80000
162 #define BRCMF_PCIE_MB_INT_D2H2_DB0 0x100000
163 #define BRCMF_PCIE_MB_INT_D2H2_DB1 0x200000
164 #define BRCMF_PCIE_MB_INT_D2H3_DB0 0x400000
165 #define BRCMF_PCIE_MB_INT_D2H3_DB1 0x800000
166
167 #define BRCMF_PCIE_MB_INT_FN0 (BRCMF_PCIE_MB_INT_FN0_0 | \
168 BRCMF_PCIE_MB_INT_FN0_1)
169 #define BRCMF_PCIE_MB_INT_D2H_DB (BRCMF_PCIE_MB_INT_D2H0_DB0 | \
170 BRCMF_PCIE_MB_INT_D2H0_DB1 | \
171 BRCMF_PCIE_MB_INT_D2H1_DB0 | \
172 BRCMF_PCIE_MB_INT_D2H1_DB1 | \
173 BRCMF_PCIE_MB_INT_D2H2_DB0 | \
174 BRCMF_PCIE_MB_INT_D2H2_DB1 | \
175 BRCMF_PCIE_MB_INT_D2H3_DB0 | \
176 BRCMF_PCIE_MB_INT_D2H3_DB1)
177
178 #define BRCMF_PCIE_64_MB_INT_D2H0_DB0 0x1
179 #define BRCMF_PCIE_64_MB_INT_D2H0_DB1 0x2
180 #define BRCMF_PCIE_64_MB_INT_D2H1_DB0 0x4
181 #define BRCMF_PCIE_64_MB_INT_D2H1_DB1 0x8
182 #define BRCMF_PCIE_64_MB_INT_D2H2_DB0 0x10
183 #define BRCMF_PCIE_64_MB_INT_D2H2_DB1 0x20
184 #define BRCMF_PCIE_64_MB_INT_D2H3_DB0 0x40
185 #define BRCMF_PCIE_64_MB_INT_D2H3_DB1 0x80
186 #define BRCMF_PCIE_64_MB_INT_D2H4_DB0 0x100
187 #define BRCMF_PCIE_64_MB_INT_D2H4_DB1 0x200
188 #define BRCMF_PCIE_64_MB_INT_D2H5_DB0 0x400
189 #define BRCMF_PCIE_64_MB_INT_D2H5_DB1 0x800
190 #define BRCMF_PCIE_64_MB_INT_D2H6_DB0 0x1000
191 #define BRCMF_PCIE_64_MB_INT_D2H6_DB1 0x2000
192 #define BRCMF_PCIE_64_MB_INT_D2H7_DB0 0x4000
193 #define BRCMF_PCIE_64_MB_INT_D2H7_DB1 0x8000
194
195 #define BRCMF_PCIE_64_MB_INT_D2H_DB (BRCMF_PCIE_64_MB_INT_D2H0_DB0 | \
196 BRCMF_PCIE_64_MB_INT_D2H0_DB1 | \
197 BRCMF_PCIE_64_MB_INT_D2H1_DB0 | \
198 BRCMF_PCIE_64_MB_INT_D2H1_DB1 | \
199 BRCMF_PCIE_64_MB_INT_D2H2_DB0 | \
200 BRCMF_PCIE_64_MB_INT_D2H2_DB1 | \
201 BRCMF_PCIE_64_MB_INT_D2H3_DB0 | \
202 BRCMF_PCIE_64_MB_INT_D2H3_DB1 | \
203 BRCMF_PCIE_64_MB_INT_D2H4_DB0 | \
204 BRCMF_PCIE_64_MB_INT_D2H4_DB1 | \
205 BRCMF_PCIE_64_MB_INT_D2H5_DB0 | \
206 BRCMF_PCIE_64_MB_INT_D2H5_DB1 | \
207 BRCMF_PCIE_64_MB_INT_D2H6_DB0 | \
208 BRCMF_PCIE_64_MB_INT_D2H6_DB1 | \
209 BRCMF_PCIE_64_MB_INT_D2H7_DB0 | \
210 BRCMF_PCIE_64_MB_INT_D2H7_DB1)
211
212 #define BRCMF_PCIE_SHARED_VERSION_7 7
213 #define BRCMF_PCIE_MIN_SHARED_VERSION 5
214 #define BRCMF_PCIE_MAX_SHARED_VERSION BRCMF_PCIE_SHARED_VERSION_7
215 #define BRCMF_PCIE_SHARED_VERSION_MASK 0x00FF
216 #define BRCMF_PCIE_SHARED_DMA_INDEX 0x10000
217 #define BRCMF_PCIE_SHARED_DMA_2B_IDX 0x100000
218 #define BRCMF_PCIE_SHARED_HOSTRDY_DB1 0x10000000
219
220 #define BRCMF_PCIE_FLAGS_HTOD_SPLIT 0x4000
221 #define BRCMF_PCIE_FLAGS_DTOH_SPLIT 0x8000
222
223 #define BRCMF_SHARED_MAX_RXBUFPOST_OFFSET 34
224 #define BRCMF_SHARED_RING_BASE_OFFSET 52
225 #define BRCMF_SHARED_RX_DATAOFFSET_OFFSET 36
226 #define BRCMF_SHARED_CONSOLE_ADDR_OFFSET 20
227 #define BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET 40
228 #define BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET 44
229 #define BRCMF_SHARED_RING_INFO_ADDR_OFFSET 48
230 #define BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET 52
231 #define BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET 56
232 #define BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET 64
233 #define BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET 68
234
235 #define BRCMF_RING_H2D_RING_COUNT_OFFSET 0
236 #define BRCMF_RING_D2H_RING_COUNT_OFFSET 1
237 #define BRCMF_RING_H2D_RING_MEM_OFFSET 4
238 #define BRCMF_RING_H2D_RING_STATE_OFFSET 8
239
240 #define BRCMF_RING_MEM_BASE_ADDR_OFFSET 8
241 #define BRCMF_RING_MAX_ITEM_OFFSET 4
242 #define BRCMF_RING_LEN_ITEMS_OFFSET 6
243 #define BRCMF_RING_MEM_SZ 16
244 #define BRCMF_RING_STATE_SZ 8
245
246 #define BRCMF_DEF_MAX_RXBUFPOST 255
247
248 #define BRCMF_CONSOLE_BUFADDR_OFFSET 8
249 #define BRCMF_CONSOLE_BUFSIZE_OFFSET 12
250 #define BRCMF_CONSOLE_WRITEIDX_OFFSET 16
251
252 #define BRCMF_DMA_D2H_SCRATCH_BUF_LEN 8
253 #define BRCMF_DMA_D2H_RINGUPD_BUF_LEN 1024
254
255 #define BRCMF_D2H_DEV_D3_ACK 0x00000001
256 #define BRCMF_D2H_DEV_DS_ENTER_REQ 0x00000002
257 #define BRCMF_D2H_DEV_DS_EXIT_NOTE 0x00000004
258 #define BRCMF_D2H_DEV_FWHALT 0x10000000
259
260 #define BRCMF_H2D_HOST_D3_INFORM 0x00000001
261 #define BRCMF_H2D_HOST_DS_ACK 0x00000002
262 #define BRCMF_H2D_HOST_D0_INFORM_IN_USE 0x00000008
263 #define BRCMF_H2D_HOST_D0_INFORM 0x00000010
264
265 #define BRCMF_PCIE_MBDATA_TIMEOUT msecs_to_jiffies(2000)
266
267 #define BRCMF_PCIE_CFGREG_STATUS_CMD 0x4
268 #define BRCMF_PCIE_CFGREG_PM_CSR 0x4C
269 #define BRCMF_PCIE_CFGREG_MSI_CAP 0x58
270 #define BRCMF_PCIE_CFGREG_MSI_ADDR_L 0x5C
271 #define BRCMF_PCIE_CFGREG_MSI_ADDR_H 0x60
272 #define BRCMF_PCIE_CFGREG_MSI_DATA 0x64
273 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL 0xBC
274 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2 0xDC
275 #define BRCMF_PCIE_CFGREG_RBAR_CTRL 0x228
276 #define BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1 0x248
277 #define BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG 0x4E0
278 #define BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG 0x4F4
279 #define BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB 3
280
281 /* Magic number at a magic location to find RAM size */
282 #define BRCMF_RAMSIZE_MAGIC 0x534d4152 /* SMAR */
283 #define BRCMF_RAMSIZE_OFFSET 0x6c
284
285
286 struct brcmf_pcie_console {
287 u32 base_addr;
288 u32 buf_addr;
289 u32 bufsize;
290 u32 read_idx;
291 u8 log_str[256];
292 u8 log_idx;
293 };
294
295 struct brcmf_pcie_shared_info {
296 u32 tcm_base_address;
297 u32 flags;
298 struct brcmf_pcie_ringbuf *commonrings[BRCMF_NROF_COMMON_MSGRINGS];
299 struct brcmf_pcie_ringbuf *flowrings;
300 u16 max_rxbufpost;
301 u16 max_flowrings;
302 u16 max_submissionrings;
303 u16 max_completionrings;
304 u32 rx_dataoffset;
305 u32 htod_mb_data_addr;
306 u32 dtoh_mb_data_addr;
307 u32 ring_info_addr;
308 struct brcmf_pcie_console console;
309 void *scratch;
310 dma_addr_t scratch_dmahandle;
311 void *ringupd;
312 dma_addr_t ringupd_dmahandle;
313 u8 version;
314 };
315
316 #define BRCMF_OTP_MAX_PARAM_LEN 16
317
318 struct brcmf_otp_params {
319 char module[BRCMF_OTP_MAX_PARAM_LEN];
320 char vendor[BRCMF_OTP_MAX_PARAM_LEN];
321 char version[BRCMF_OTP_MAX_PARAM_LEN];
322 bool valid;
323 };
324
325 struct brcmf_pciedev_info {
326 enum brcmf_pcie_state state;
327 bool in_irq;
328 struct pci_dev *pdev;
329 char fw_name[BRCMF_FW_NAME_LEN];
330 char nvram_name[BRCMF_FW_NAME_LEN];
331 char clm_name[BRCMF_FW_NAME_LEN];
332 char txcap_name[BRCMF_FW_NAME_LEN];
333 const struct firmware *clm_fw;
334 const struct firmware *txcap_fw;
335 const struct brcmf_pcie_reginfo *reginfo;
336 void __iomem *regs;
337 void __iomem *tcm;
338 u32 ram_base;
339 u32 ram_size;
340 struct brcmf_chip *ci;
341 u32 coreid;
342 struct brcmf_pcie_shared_info shared;
343 wait_queue_head_t mbdata_resp_wait;
344 bool mbdata_completed;
345 bool irq_allocated;
346 bool wowl_enabled;
347 u8 dma_idx_sz;
348 void *idxbuf;
349 u32 idxbuf_sz;
350 dma_addr_t idxbuf_dmahandle;
351 u16 (*read_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset);
352 void (*write_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
353 u16 value);
354 struct brcmf_mp_device *settings;
355 struct brcmf_otp_params otp;
356 #ifdef DEBUG
357 u32 console_interval;
358 bool console_active;
359 struct timer_list timer;
360 #endif
361 };
362
363 struct brcmf_pcie_ringbuf {
364 struct brcmf_commonring commonring;
365 dma_addr_t dma_handle;
366 u32 w_idx_addr;
367 u32 r_idx_addr;
368 struct brcmf_pciedev_info *devinfo;
369 u8 id;
370 };
371
372 /**
373 * struct brcmf_pcie_dhi_ringinfo - dongle/host interface shared ring info
374 *
375 * @ringmem: dongle memory pointer to ring memory location
376 * @h2d_w_idx_ptr: h2d ring write indices dongle memory pointers
377 * @h2d_r_idx_ptr: h2d ring read indices dongle memory pointers
378 * @d2h_w_idx_ptr: d2h ring write indices dongle memory pointers
379 * @d2h_r_idx_ptr: d2h ring read indices dongle memory pointers
380 * @h2d_w_idx_hostaddr: h2d ring write indices host memory pointers
381 * @h2d_r_idx_hostaddr: h2d ring read indices host memory pointers
382 * @d2h_w_idx_hostaddr: d2h ring write indices host memory pointers
383 * @d2h_r_idx_hostaddr: d2h ring reaD indices host memory pointers
384 * @max_flowrings: maximum number of tx flow rings supported.
385 * @max_submissionrings: maximum number of submission rings(h2d) supported.
386 * @max_completionrings: maximum number of completion rings(d2h) supported.
387 */
388 struct brcmf_pcie_dhi_ringinfo {
389 __le32 ringmem;
390 __le32 h2d_w_idx_ptr;
391 __le32 h2d_r_idx_ptr;
392 __le32 d2h_w_idx_ptr;
393 __le32 d2h_r_idx_ptr;
394 struct msgbuf_buf_addr h2d_w_idx_hostaddr;
395 struct msgbuf_buf_addr h2d_r_idx_hostaddr;
396 struct msgbuf_buf_addr d2h_w_idx_hostaddr;
397 struct msgbuf_buf_addr d2h_r_idx_hostaddr;
398 __le16 max_flowrings;
399 __le16 max_submissionrings;
400 __le16 max_completionrings;
401 };
402
403 static const u32 brcmf_ring_max_item[BRCMF_NROF_COMMON_MSGRINGS] = {
404 BRCMF_H2D_MSGRING_CONTROL_SUBMIT_MAX_ITEM,
405 BRCMF_H2D_MSGRING_RXPOST_SUBMIT_MAX_ITEM,
406 BRCMF_D2H_MSGRING_CONTROL_COMPLETE_MAX_ITEM,
407 BRCMF_D2H_MSGRING_TX_COMPLETE_MAX_ITEM,
408 BRCMF_D2H_MSGRING_RX_COMPLETE_MAX_ITEM
409 };
410
411 static const u32 brcmf_ring_itemsize_pre_v7[BRCMF_NROF_COMMON_MSGRINGS] = {
412 BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE,
413 BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE,
414 BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE,
415 BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE_PRE_V7,
416 BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE_PRE_V7
417 };
418
419 static const u32 brcmf_ring_itemsize[BRCMF_NROF_COMMON_MSGRINGS] = {
420 BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE,
421 BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE,
422 BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE,
423 BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE,
424 BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE
425 };
426
427 struct brcmf_pcie_reginfo {
428 u32 intmask;
429 u32 mailboxint;
430 u32 mailboxmask;
431 u32 h2d_mailbox_0;
432 u32 h2d_mailbox_1;
433 u32 int_d2h_db;
434 u32 int_fn0;
435 };
436
437 static const struct brcmf_pcie_reginfo brcmf_reginfo_default = {
438 .intmask = BRCMF_PCIE_PCIE2REG_INTMASK,
439 .mailboxint = BRCMF_PCIE_PCIE2REG_MAILBOXINT,
440 .mailboxmask = BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
441 .h2d_mailbox_0 = BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_0,
442 .h2d_mailbox_1 = BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_1,
443 .int_d2h_db = BRCMF_PCIE_MB_INT_D2H_DB,
444 .int_fn0 = BRCMF_PCIE_MB_INT_FN0,
445 };
446
447 static const struct brcmf_pcie_reginfo brcmf_reginfo_64 = {
448 .intmask = BRCMF_PCIE_64_PCIE2REG_INTMASK,
449 .mailboxint = BRCMF_PCIE_64_PCIE2REG_MAILBOXINT,
450 .mailboxmask = BRCMF_PCIE_64_PCIE2REG_MAILBOXMASK,
451 .h2d_mailbox_0 = BRCMF_PCIE_64_PCIE2REG_H2D_MAILBOX_0,
452 .h2d_mailbox_1 = BRCMF_PCIE_64_PCIE2REG_H2D_MAILBOX_1,
453 .int_d2h_db = BRCMF_PCIE_64_MB_INT_D2H_DB,
454 .int_fn0 = 0,
455 };
456
457 static void brcmf_pcie_setup(struct device *dev, int ret,
458 struct brcmf_fw_request *fwreq);
459 static struct brcmf_fw_request *
460 brcmf_pcie_prepare_fw_request(struct brcmf_pciedev_info *devinfo);
461 static void
462 brcmf_pcie_fwcon_timer(struct brcmf_pciedev_info *devinfo, bool active);
463 static void brcmf_pcie_debugfs_create(struct device *dev);
464
465 static u16
brcmf_pcie_read_reg16(struct brcmf_pciedev_info * devinfo,u32 reg_offset)466 brcmf_pcie_read_reg16(struct brcmf_pciedev_info *devinfo, u32 reg_offset)
467 {
468 void __iomem *address = devinfo->regs + reg_offset;
469
470 return ioread16(address);
471 }
472
473 static u32
brcmf_pcie_read_reg32(struct brcmf_pciedev_info * devinfo,u32 reg_offset)474 brcmf_pcie_read_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset)
475 {
476 void __iomem *address = devinfo->regs + reg_offset;
477
478 return (ioread32(address));
479 }
480
481
482 static void
brcmf_pcie_write_reg32(struct brcmf_pciedev_info * devinfo,u32 reg_offset,u32 value)483 brcmf_pcie_write_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset,
484 u32 value)
485 {
486 void __iomem *address = devinfo->regs + reg_offset;
487
488 iowrite32(value, address);
489 }
490
491
492 static u8
brcmf_pcie_read_tcm8(struct brcmf_pciedev_info * devinfo,u32 mem_offset)493 brcmf_pcie_read_tcm8(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
494 {
495 void __iomem *address = devinfo->tcm + mem_offset;
496
497 return (ioread8(address));
498 }
499
500
501 static u16
brcmf_pcie_read_tcm16(struct brcmf_pciedev_info * devinfo,u32 mem_offset)502 brcmf_pcie_read_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
503 {
504 void __iomem *address = devinfo->tcm + mem_offset;
505
506 return (ioread16(address));
507 }
508
509
510 static void
brcmf_pcie_write_tcm16(struct brcmf_pciedev_info * devinfo,u32 mem_offset,u16 value)511 brcmf_pcie_write_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
512 u16 value)
513 {
514 void __iomem *address = devinfo->tcm + mem_offset;
515
516 iowrite16(value, address);
517 }
518
519
520 static u16
brcmf_pcie_read_idx(struct brcmf_pciedev_info * devinfo,u32 mem_offset)521 brcmf_pcie_read_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
522 {
523 u16 *address = devinfo->idxbuf + mem_offset;
524
525 return (*(address));
526 }
527
528
529 static void
brcmf_pcie_write_idx(struct brcmf_pciedev_info * devinfo,u32 mem_offset,u16 value)530 brcmf_pcie_write_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
531 u16 value)
532 {
533 u16 *address = devinfo->idxbuf + mem_offset;
534
535 *(address) = value;
536 }
537
538
539 static u32
brcmf_pcie_read_tcm32(struct brcmf_pciedev_info * devinfo,u32 mem_offset)540 brcmf_pcie_read_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
541 {
542 void __iomem *address = devinfo->tcm + mem_offset;
543
544 return (ioread32(address));
545 }
546
547
548 static void
brcmf_pcie_write_tcm32(struct brcmf_pciedev_info * devinfo,u32 mem_offset,u32 value)549 brcmf_pcie_write_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
550 u32 value)
551 {
552 void __iomem *address = devinfo->tcm + mem_offset;
553
554 iowrite32(value, address);
555 }
556
557
558 static u32
brcmf_pcie_read_ram32(struct brcmf_pciedev_info * devinfo,u32 mem_offset)559 brcmf_pcie_read_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
560 {
561 void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset;
562
563 return (ioread32(addr));
564 }
565
566
567 static void
brcmf_pcie_write_ram32(struct brcmf_pciedev_info * devinfo,u32 mem_offset,u32 value)568 brcmf_pcie_write_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
569 u32 value)
570 {
571 void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset;
572
573 iowrite32(value, addr);
574 }
575
576
577 static void
brcmf_pcie_copy_dev_tomem(struct brcmf_pciedev_info * devinfo,u32 mem_offset,void * dstaddr,u32 len)578 brcmf_pcie_copy_dev_tomem(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
579 void *dstaddr, u32 len)
580 {
581 void __iomem *address = devinfo->tcm + mem_offset;
582 __le32 *dst32;
583 __le16 *dst16;
584 u8 *dst8;
585
586 if (((ulong)address & 4) || ((ulong)dstaddr & 4) || (len & 4)) {
587 if (((ulong)address & 2) || ((ulong)dstaddr & 2) || (len & 2)) {
588 dst8 = (u8 *)dstaddr;
589 while (len) {
590 *dst8 = ioread8(address);
591 address++;
592 dst8++;
593 len--;
594 }
595 } else {
596 len = len / 2;
597 dst16 = (__le16 *)dstaddr;
598 while (len) {
599 *dst16 = cpu_to_le16(ioread16(address));
600 address += 2;
601 dst16++;
602 len--;
603 }
604 }
605 } else {
606 len = len / 4;
607 dst32 = (__le32 *)dstaddr;
608 while (len) {
609 *dst32 = cpu_to_le32(ioread32(address));
610 address += 4;
611 dst32++;
612 len--;
613 }
614 }
615 }
616
617
618 #define READCC32(devinfo, reg) brcmf_pcie_read_reg32(devinfo, \
619 CHIPCREGOFFS(reg))
620 #define WRITECC32(devinfo, reg, value) brcmf_pcie_write_reg32(devinfo, \
621 CHIPCREGOFFS(reg), value)
622
623
624 static void
brcmf_pcie_select_core(struct brcmf_pciedev_info * devinfo,u16 coreid)625 brcmf_pcie_select_core(struct brcmf_pciedev_info *devinfo, u16 coreid)
626 {
627 const struct pci_dev *pdev = devinfo->pdev;
628 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev);
629 struct brcmf_core *core;
630 u32 bar0_win;
631
632 core = brcmf_chip_get_core(devinfo->ci, coreid);
633 if (core) {
634 bar0_win = core->base;
635 pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, bar0_win);
636 if (pci_read_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW,
637 &bar0_win) == 0) {
638 if (bar0_win != core->base) {
639 bar0_win = core->base;
640 pci_write_config_dword(pdev,
641 BRCMF_PCIE_BAR0_WINDOW,
642 bar0_win);
643 }
644 }
645 } else {
646 brcmf_err(bus, "Unsupported core selected %x\n", coreid);
647 }
648 }
649
650
brcmf_pcie_reset_device(struct brcmf_pciedev_info * devinfo)651 static void brcmf_pcie_reset_device(struct brcmf_pciedev_info *devinfo)
652 {
653 struct brcmf_core *core;
654 u16 cfg_offset[] = { BRCMF_PCIE_CFGREG_STATUS_CMD,
655 BRCMF_PCIE_CFGREG_PM_CSR,
656 BRCMF_PCIE_CFGREG_MSI_CAP,
657 BRCMF_PCIE_CFGREG_MSI_ADDR_L,
658 BRCMF_PCIE_CFGREG_MSI_ADDR_H,
659 BRCMF_PCIE_CFGREG_MSI_DATA,
660 BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2,
661 BRCMF_PCIE_CFGREG_RBAR_CTRL,
662 BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1,
663 BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG,
664 BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG };
665 u32 i;
666 u32 val;
667 u32 lsc;
668
669 if (!devinfo->ci)
670 return;
671
672 /* Disable ASPM */
673 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
674 pci_read_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
675 &lsc);
676 val = lsc & (~BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB);
677 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
678 val);
679
680 /* Watchdog reset */
681 brcmf_pcie_select_core(devinfo, BCMA_CORE_CHIPCOMMON);
682 WRITECC32(devinfo, watchdog, 4);
683 msleep(100);
684
685 /* Restore ASPM */
686 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
687 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
688 lsc);
689
690 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_PCIE2);
691 if (core->rev <= 13) {
692 for (i = 0; i < ARRAY_SIZE(cfg_offset); i++) {
693 brcmf_pcie_write_reg32(devinfo,
694 BRCMF_PCIE_PCIE2REG_CONFIGADDR,
695 cfg_offset[i]);
696 val = brcmf_pcie_read_reg32(devinfo,
697 BRCMF_PCIE_PCIE2REG_CONFIGDATA);
698 brcmf_dbg(PCIE, "config offset 0x%04x, value 0x%04x\n",
699 cfg_offset[i], val);
700 brcmf_pcie_write_reg32(devinfo,
701 BRCMF_PCIE_PCIE2REG_CONFIGDATA,
702 val);
703 }
704 }
705 }
706
707
brcmf_pcie_attach(struct brcmf_pciedev_info * devinfo)708 static void brcmf_pcie_attach(struct brcmf_pciedev_info *devinfo)
709 {
710 u32 config;
711
712 /* BAR1 window may not be sized properly */
713 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
714 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR, 0x4e0);
715 config = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA);
716 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, config);
717
718 device_wakeup_enable(&devinfo->pdev->dev);
719 }
720
721
brcmf_pcie_enter_download_state(struct brcmf_pciedev_info * devinfo)722 static int brcmf_pcie_enter_download_state(struct brcmf_pciedev_info *devinfo)
723 {
724 if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) {
725 brcmf_pcie_select_core(devinfo, BCMA_CORE_ARM_CR4);
726 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX,
727 5);
728 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA,
729 0);
730 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX,
731 7);
732 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA,
733 0);
734 }
735 return 0;
736 }
737
738
brcmf_pcie_exit_download_state(struct brcmf_pciedev_info * devinfo,u32 resetintr)739 static int brcmf_pcie_exit_download_state(struct brcmf_pciedev_info *devinfo,
740 u32 resetintr)
741 {
742 struct brcmf_core *core;
743
744 if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) {
745 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_INTERNAL_MEM);
746 brcmf_chip_resetcore(core, 0, 0, 0);
747 }
748
749 if (!brcmf_chip_set_active(devinfo->ci, resetintr))
750 return -EIO;
751 return 0;
752 }
753
754
755 static int
brcmf_pcie_send_mb_data(struct brcmf_pciedev_info * devinfo,u32 htod_mb_data)756 brcmf_pcie_send_mb_data(struct brcmf_pciedev_info *devinfo, u32 htod_mb_data)
757 {
758 struct brcmf_pcie_shared_info *shared;
759 struct brcmf_core *core;
760 u32 addr;
761 u32 cur_htod_mb_data;
762 u32 i;
763
764 shared = &devinfo->shared;
765 addr = shared->htod_mb_data_addr;
766 cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
767
768 if (cur_htod_mb_data != 0)
769 brcmf_dbg(PCIE, "MB transaction is already pending 0x%04x\n",
770 cur_htod_mb_data);
771
772 i = 0;
773 while (cur_htod_mb_data != 0) {
774 msleep(10);
775 i++;
776 if (i > 100)
777 return -EIO;
778 cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
779 }
780
781 brcmf_pcie_write_tcm32(devinfo, addr, htod_mb_data);
782 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1);
783
784 /* Send mailbox interrupt twice as a hardware workaround */
785 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_PCIE2);
786 if (core->rev <= 13)
787 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1);
788
789 return 0;
790 }
791
792
brcmf_pcie_handle_mb_data(struct brcmf_pciedev_info * devinfo)793 static void brcmf_pcie_handle_mb_data(struct brcmf_pciedev_info *devinfo)
794 {
795 struct brcmf_pcie_shared_info *shared;
796 u32 addr;
797 u32 dtoh_mb_data;
798
799 shared = &devinfo->shared;
800 addr = shared->dtoh_mb_data_addr;
801 dtoh_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
802
803 if (!dtoh_mb_data)
804 return;
805
806 brcmf_pcie_write_tcm32(devinfo, addr, 0);
807
808 brcmf_dbg(PCIE, "D2H_MB_DATA: 0x%04x\n", dtoh_mb_data);
809 if (dtoh_mb_data & BRCMF_D2H_DEV_DS_ENTER_REQ) {
810 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP REQ\n");
811 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_DS_ACK);
812 brcmf_dbg(PCIE, "D2H_MB_DATA: sent DEEP SLEEP ACK\n");
813 }
814 if (dtoh_mb_data & BRCMF_D2H_DEV_DS_EXIT_NOTE)
815 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP EXIT\n");
816 if (dtoh_mb_data & BRCMF_D2H_DEV_D3_ACK) {
817 brcmf_dbg(PCIE, "D2H_MB_DATA: D3 ACK\n");
818 devinfo->mbdata_completed = true;
819 wake_up(&devinfo->mbdata_resp_wait);
820 }
821 if (dtoh_mb_data & BRCMF_D2H_DEV_FWHALT) {
822 brcmf_dbg(PCIE, "D2H_MB_DATA: FW HALT\n");
823 brcmf_fw_crashed(&devinfo->pdev->dev);
824 }
825 }
826
827
brcmf_pcie_bus_console_init(struct brcmf_pciedev_info * devinfo)828 static void brcmf_pcie_bus_console_init(struct brcmf_pciedev_info *devinfo)
829 {
830 struct brcmf_pcie_shared_info *shared;
831 struct brcmf_pcie_console *console;
832 u32 addr;
833
834 shared = &devinfo->shared;
835 console = &shared->console;
836 addr = shared->tcm_base_address + BRCMF_SHARED_CONSOLE_ADDR_OFFSET;
837 console->base_addr = brcmf_pcie_read_tcm32(devinfo, addr);
838
839 addr = console->base_addr + BRCMF_CONSOLE_BUFADDR_OFFSET;
840 console->buf_addr = brcmf_pcie_read_tcm32(devinfo, addr);
841 addr = console->base_addr + BRCMF_CONSOLE_BUFSIZE_OFFSET;
842 console->bufsize = brcmf_pcie_read_tcm32(devinfo, addr);
843
844 brcmf_dbg(FWCON, "Console: base %x, buf %x, size %d\n",
845 console->base_addr, console->buf_addr, console->bufsize);
846 }
847
848 /**
849 * brcmf_pcie_bus_console_read - reads firmware messages
850 *
851 * @devinfo: pointer to the device data structure
852 * @error: specifies if error has occurred (prints messages unconditionally)
853 */
brcmf_pcie_bus_console_read(struct brcmf_pciedev_info * devinfo,bool error)854 static void brcmf_pcie_bus_console_read(struct brcmf_pciedev_info *devinfo,
855 bool error)
856 {
857 struct pci_dev *pdev = devinfo->pdev;
858 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev);
859 struct brcmf_pcie_console *console;
860 u32 addr;
861 u8 ch;
862 u32 newidx;
863
864 if (!error && !BRCMF_FWCON_ON())
865 return;
866
867 console = &devinfo->shared.console;
868 if (!console->base_addr)
869 return;
870 addr = console->base_addr + BRCMF_CONSOLE_WRITEIDX_OFFSET;
871 newidx = brcmf_pcie_read_tcm32(devinfo, addr);
872 while (newidx != console->read_idx) {
873 addr = console->buf_addr + console->read_idx;
874 ch = brcmf_pcie_read_tcm8(devinfo, addr);
875 console->read_idx++;
876 if (console->read_idx == console->bufsize)
877 console->read_idx = 0;
878 if (ch == '\r')
879 continue;
880 console->log_str[console->log_idx] = ch;
881 console->log_idx++;
882 if ((ch != '\n') &&
883 (console->log_idx == (sizeof(console->log_str) - 2))) {
884 ch = '\n';
885 console->log_str[console->log_idx] = ch;
886 console->log_idx++;
887 }
888 if (ch == '\n') {
889 console->log_str[console->log_idx] = 0;
890 if (error)
891 __brcmf_err(bus, __func__, "CONSOLE: %s",
892 console->log_str);
893 else
894 pr_debug("CONSOLE: %s", console->log_str);
895 console->log_idx = 0;
896 }
897 }
898 }
899
900
brcmf_pcie_intr_disable(struct brcmf_pciedev_info * devinfo)901 static void brcmf_pcie_intr_disable(struct brcmf_pciedev_info *devinfo)
902 {
903 brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->mailboxmask, 0);
904 }
905
906
brcmf_pcie_intr_enable(struct brcmf_pciedev_info * devinfo)907 static void brcmf_pcie_intr_enable(struct brcmf_pciedev_info *devinfo)
908 {
909 brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->mailboxmask,
910 devinfo->reginfo->int_d2h_db |
911 devinfo->reginfo->int_fn0);
912 }
913
brcmf_pcie_hostready(struct brcmf_pciedev_info * devinfo)914 static void brcmf_pcie_hostready(struct brcmf_pciedev_info *devinfo)
915 {
916 if (devinfo->shared.flags & BRCMF_PCIE_SHARED_HOSTRDY_DB1)
917 brcmf_pcie_write_reg32(devinfo,
918 devinfo->reginfo->h2d_mailbox_1, 1);
919 }
920
brcmf_pcie_quick_check_isr(int irq,void * arg)921 static irqreturn_t brcmf_pcie_quick_check_isr(int irq, void *arg)
922 {
923 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
924
925 if (brcmf_pcie_read_reg32(devinfo, devinfo->reginfo->mailboxint)) {
926 brcmf_pcie_intr_disable(devinfo);
927 brcmf_dbg(PCIE, "Enter\n");
928 return IRQ_WAKE_THREAD;
929 }
930 return IRQ_NONE;
931 }
932
933
brcmf_pcie_isr_thread(int irq,void * arg)934 static irqreturn_t brcmf_pcie_isr_thread(int irq, void *arg)
935 {
936 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
937 u32 status;
938
939 devinfo->in_irq = true;
940 status = brcmf_pcie_read_reg32(devinfo, devinfo->reginfo->mailboxint);
941 brcmf_dbg(PCIE, "Enter %x\n", status);
942 if (status) {
943 brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->mailboxint,
944 status);
945 if (status & devinfo->reginfo->int_fn0)
946 brcmf_pcie_handle_mb_data(devinfo);
947 if (status & devinfo->reginfo->int_d2h_db) {
948 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
949 brcmf_proto_msgbuf_rx_trigger(
950 &devinfo->pdev->dev);
951 }
952 }
953 brcmf_pcie_bus_console_read(devinfo, false);
954 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
955 brcmf_pcie_intr_enable(devinfo);
956 devinfo->in_irq = false;
957 return IRQ_HANDLED;
958 }
959
960
brcmf_pcie_request_irq(struct brcmf_pciedev_info * devinfo)961 static int brcmf_pcie_request_irq(struct brcmf_pciedev_info *devinfo)
962 {
963 struct pci_dev *pdev = devinfo->pdev;
964 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev);
965
966 brcmf_pcie_intr_disable(devinfo);
967
968 brcmf_dbg(PCIE, "Enter\n");
969
970 pci_enable_msi(pdev);
971 if (request_threaded_irq(pdev->irq, brcmf_pcie_quick_check_isr,
972 brcmf_pcie_isr_thread, IRQF_SHARED,
973 "brcmf_pcie_intr", devinfo)) {
974 pci_disable_msi(pdev);
975 brcmf_err(bus, "Failed to request IRQ %d\n", pdev->irq);
976 return -EIO;
977 }
978 devinfo->irq_allocated = true;
979 return 0;
980 }
981
982
brcmf_pcie_release_irq(struct brcmf_pciedev_info * devinfo)983 static void brcmf_pcie_release_irq(struct brcmf_pciedev_info *devinfo)
984 {
985 struct pci_dev *pdev = devinfo->pdev;
986 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev);
987 u32 status;
988 u32 count;
989
990 if (!devinfo->irq_allocated)
991 return;
992
993 brcmf_pcie_intr_disable(devinfo);
994 free_irq(pdev->irq, devinfo);
995 pci_disable_msi(pdev);
996
997 msleep(50);
998 count = 0;
999 while ((devinfo->in_irq) && (count < 20)) {
1000 msleep(50);
1001 count++;
1002 }
1003 if (devinfo->in_irq)
1004 brcmf_err(bus, "Still in IRQ (processing) !!!\n");
1005
1006 status = brcmf_pcie_read_reg32(devinfo, devinfo->reginfo->mailboxint);
1007 brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->mailboxint, status);
1008
1009 devinfo->irq_allocated = false;
1010 }
1011
1012
brcmf_pcie_ring_mb_write_rptr(void * ctx)1013 static int brcmf_pcie_ring_mb_write_rptr(void *ctx)
1014 {
1015 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
1016 struct brcmf_pciedev_info *devinfo = ring->devinfo;
1017 struct brcmf_commonring *commonring = &ring->commonring;
1018
1019 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
1020 return -EIO;
1021
1022 brcmf_dbg(PCIE, "W r_ptr %d (%d), ring %d\n", commonring->r_ptr,
1023 commonring->w_ptr, ring->id);
1024
1025 devinfo->write_ptr(devinfo, ring->r_idx_addr, commonring->r_ptr);
1026
1027 return 0;
1028 }
1029
1030
brcmf_pcie_ring_mb_write_wptr(void * ctx)1031 static int brcmf_pcie_ring_mb_write_wptr(void *ctx)
1032 {
1033 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
1034 struct brcmf_pciedev_info *devinfo = ring->devinfo;
1035 struct brcmf_commonring *commonring = &ring->commonring;
1036
1037 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
1038 return -EIO;
1039
1040 brcmf_dbg(PCIE, "W w_ptr %d (%d), ring %d\n", commonring->w_ptr,
1041 commonring->r_ptr, ring->id);
1042
1043 devinfo->write_ptr(devinfo, ring->w_idx_addr, commonring->w_ptr);
1044
1045 return 0;
1046 }
1047
1048
brcmf_pcie_ring_mb_ring_bell(void * ctx)1049 static int brcmf_pcie_ring_mb_ring_bell(void *ctx)
1050 {
1051 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
1052 struct brcmf_pciedev_info *devinfo = ring->devinfo;
1053
1054 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
1055 return -EIO;
1056
1057 brcmf_dbg(PCIE, "RING !\n");
1058 /* Any arbitrary value will do, lets use 1 */
1059 brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->h2d_mailbox_0, 1);
1060
1061 return 0;
1062 }
1063
1064
brcmf_pcie_ring_mb_update_rptr(void * ctx)1065 static int brcmf_pcie_ring_mb_update_rptr(void *ctx)
1066 {
1067 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
1068 struct brcmf_pciedev_info *devinfo = ring->devinfo;
1069 struct brcmf_commonring *commonring = &ring->commonring;
1070
1071 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
1072 return -EIO;
1073
1074 commonring->r_ptr = devinfo->read_ptr(devinfo, ring->r_idx_addr);
1075
1076 brcmf_dbg(PCIE, "R r_ptr %d (%d), ring %d\n", commonring->r_ptr,
1077 commonring->w_ptr, ring->id);
1078
1079 return 0;
1080 }
1081
1082
brcmf_pcie_ring_mb_update_wptr(void * ctx)1083 static int brcmf_pcie_ring_mb_update_wptr(void *ctx)
1084 {
1085 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
1086 struct brcmf_pciedev_info *devinfo = ring->devinfo;
1087 struct brcmf_commonring *commonring = &ring->commonring;
1088
1089 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
1090 return -EIO;
1091
1092 commonring->w_ptr = devinfo->read_ptr(devinfo, ring->w_idx_addr);
1093
1094 brcmf_dbg(PCIE, "R w_ptr %d (%d), ring %d\n", commonring->w_ptr,
1095 commonring->r_ptr, ring->id);
1096
1097 return 0;
1098 }
1099
1100
1101 static void *
brcmf_pcie_init_dmabuffer_for_device(struct brcmf_pciedev_info * devinfo,u32 size,u32 tcm_dma_phys_addr,dma_addr_t * dma_handle)1102 brcmf_pcie_init_dmabuffer_for_device(struct brcmf_pciedev_info *devinfo,
1103 u32 size, u32 tcm_dma_phys_addr,
1104 dma_addr_t *dma_handle)
1105 {
1106 void *ring;
1107 u64 address;
1108
1109 ring = dma_alloc_coherent(&devinfo->pdev->dev, size, dma_handle,
1110 GFP_KERNEL);
1111 if (!ring)
1112 return NULL;
1113
1114 address = (u64)*dma_handle;
1115 brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr,
1116 address & 0xffffffff);
1117 brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr + 4, address >> 32);
1118
1119 return (ring);
1120 }
1121
1122
1123 static struct brcmf_pcie_ringbuf *
brcmf_pcie_alloc_dma_and_ring(struct brcmf_pciedev_info * devinfo,u32 ring_id,u32 tcm_ring_phys_addr)1124 brcmf_pcie_alloc_dma_and_ring(struct brcmf_pciedev_info *devinfo, u32 ring_id,
1125 u32 tcm_ring_phys_addr)
1126 {
1127 void *dma_buf;
1128 dma_addr_t dma_handle;
1129 struct brcmf_pcie_ringbuf *ring;
1130 u32 size;
1131 u32 addr;
1132 const u32 *ring_itemsize_array;
1133
1134 if (devinfo->shared.version < BRCMF_PCIE_SHARED_VERSION_7)
1135 ring_itemsize_array = brcmf_ring_itemsize_pre_v7;
1136 else
1137 ring_itemsize_array = brcmf_ring_itemsize;
1138
1139 size = brcmf_ring_max_item[ring_id] * ring_itemsize_array[ring_id];
1140 dma_buf = brcmf_pcie_init_dmabuffer_for_device(devinfo, size,
1141 tcm_ring_phys_addr + BRCMF_RING_MEM_BASE_ADDR_OFFSET,
1142 &dma_handle);
1143 if (!dma_buf)
1144 return NULL;
1145
1146 addr = tcm_ring_phys_addr + BRCMF_RING_MAX_ITEM_OFFSET;
1147 brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_max_item[ring_id]);
1148 addr = tcm_ring_phys_addr + BRCMF_RING_LEN_ITEMS_OFFSET;
1149 brcmf_pcie_write_tcm16(devinfo, addr, ring_itemsize_array[ring_id]);
1150
1151 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
1152 if (!ring) {
1153 dma_free_coherent(&devinfo->pdev->dev, size, dma_buf,
1154 dma_handle);
1155 return NULL;
1156 }
1157 brcmf_commonring_config(&ring->commonring, brcmf_ring_max_item[ring_id],
1158 ring_itemsize_array[ring_id], dma_buf);
1159 ring->dma_handle = dma_handle;
1160 ring->devinfo = devinfo;
1161 brcmf_commonring_register_cb(&ring->commonring,
1162 brcmf_pcie_ring_mb_ring_bell,
1163 brcmf_pcie_ring_mb_update_rptr,
1164 brcmf_pcie_ring_mb_update_wptr,
1165 brcmf_pcie_ring_mb_write_rptr,
1166 brcmf_pcie_ring_mb_write_wptr, ring);
1167
1168 return (ring);
1169 }
1170
1171
brcmf_pcie_release_ringbuffer(struct device * dev,struct brcmf_pcie_ringbuf * ring)1172 static void brcmf_pcie_release_ringbuffer(struct device *dev,
1173 struct brcmf_pcie_ringbuf *ring)
1174 {
1175 void *dma_buf;
1176 u32 size;
1177
1178 if (!ring)
1179 return;
1180
1181 dma_buf = ring->commonring.buf_addr;
1182 if (dma_buf) {
1183 size = ring->commonring.depth * ring->commonring.item_len;
1184 dma_free_coherent(dev, size, dma_buf, ring->dma_handle);
1185 }
1186 kfree(ring);
1187 }
1188
1189
brcmf_pcie_release_ringbuffers(struct brcmf_pciedev_info * devinfo)1190 static void brcmf_pcie_release_ringbuffers(struct brcmf_pciedev_info *devinfo)
1191 {
1192 u32 i;
1193
1194 for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++) {
1195 brcmf_pcie_release_ringbuffer(&devinfo->pdev->dev,
1196 devinfo->shared.commonrings[i]);
1197 devinfo->shared.commonrings[i] = NULL;
1198 }
1199 kfree(devinfo->shared.flowrings);
1200 devinfo->shared.flowrings = NULL;
1201 if (devinfo->idxbuf) {
1202 dma_free_coherent(&devinfo->pdev->dev,
1203 devinfo->idxbuf_sz,
1204 devinfo->idxbuf,
1205 devinfo->idxbuf_dmahandle);
1206 devinfo->idxbuf = NULL;
1207 }
1208 }
1209
1210
brcmf_pcie_init_ringbuffers(struct brcmf_pciedev_info * devinfo)1211 static int brcmf_pcie_init_ringbuffers(struct brcmf_pciedev_info *devinfo)
1212 {
1213 struct brcmf_bus *bus = dev_get_drvdata(&devinfo->pdev->dev);
1214 struct brcmf_pcie_ringbuf *ring;
1215 struct brcmf_pcie_ringbuf *rings;
1216 u32 d2h_w_idx_ptr;
1217 u32 d2h_r_idx_ptr;
1218 u32 h2d_w_idx_ptr;
1219 u32 h2d_r_idx_ptr;
1220 u32 ring_mem_ptr;
1221 u32 i;
1222 u64 address;
1223 u32 bufsz;
1224 u8 idx_offset;
1225 struct brcmf_pcie_dhi_ringinfo ringinfo;
1226 u16 max_flowrings;
1227 u16 max_submissionrings;
1228 u16 max_completionrings;
1229
1230 memcpy_fromio(&ringinfo, devinfo->tcm + devinfo->shared.ring_info_addr,
1231 sizeof(ringinfo));
1232 if (devinfo->shared.version >= 6) {
1233 max_submissionrings = le16_to_cpu(ringinfo.max_submissionrings);
1234 max_flowrings = le16_to_cpu(ringinfo.max_flowrings);
1235 max_completionrings = le16_to_cpu(ringinfo.max_completionrings);
1236 } else {
1237 max_submissionrings = le16_to_cpu(ringinfo.max_flowrings);
1238 max_flowrings = max_submissionrings -
1239 BRCMF_NROF_H2D_COMMON_MSGRINGS;
1240 max_completionrings = BRCMF_NROF_D2H_COMMON_MSGRINGS;
1241 }
1242 if (max_flowrings > 512) {
1243 brcmf_err(bus, "invalid max_flowrings(%d)\n", max_flowrings);
1244 return -EIO;
1245 }
1246
1247 if (devinfo->dma_idx_sz != 0) {
1248 bufsz = (max_submissionrings + max_completionrings) *
1249 devinfo->dma_idx_sz * 2;
1250 devinfo->idxbuf = dma_alloc_coherent(&devinfo->pdev->dev, bufsz,
1251 &devinfo->idxbuf_dmahandle,
1252 GFP_KERNEL);
1253 if (!devinfo->idxbuf)
1254 devinfo->dma_idx_sz = 0;
1255 }
1256
1257 if (devinfo->dma_idx_sz == 0) {
1258 d2h_w_idx_ptr = le32_to_cpu(ringinfo.d2h_w_idx_ptr);
1259 d2h_r_idx_ptr = le32_to_cpu(ringinfo.d2h_r_idx_ptr);
1260 h2d_w_idx_ptr = le32_to_cpu(ringinfo.h2d_w_idx_ptr);
1261 h2d_r_idx_ptr = le32_to_cpu(ringinfo.h2d_r_idx_ptr);
1262 idx_offset = sizeof(u32);
1263 devinfo->write_ptr = brcmf_pcie_write_tcm16;
1264 devinfo->read_ptr = brcmf_pcie_read_tcm16;
1265 brcmf_dbg(PCIE, "Using TCM indices\n");
1266 } else {
1267 memset(devinfo->idxbuf, 0, bufsz);
1268 devinfo->idxbuf_sz = bufsz;
1269 idx_offset = devinfo->dma_idx_sz;
1270 devinfo->write_ptr = brcmf_pcie_write_idx;
1271 devinfo->read_ptr = brcmf_pcie_read_idx;
1272
1273 h2d_w_idx_ptr = 0;
1274 address = (u64)devinfo->idxbuf_dmahandle;
1275 ringinfo.h2d_w_idx_hostaddr.low_addr =
1276 cpu_to_le32(address & 0xffffffff);
1277 ringinfo.h2d_w_idx_hostaddr.high_addr =
1278 cpu_to_le32(address >> 32);
1279
1280 h2d_r_idx_ptr = h2d_w_idx_ptr +
1281 max_submissionrings * idx_offset;
1282 address += max_submissionrings * idx_offset;
1283 ringinfo.h2d_r_idx_hostaddr.low_addr =
1284 cpu_to_le32(address & 0xffffffff);
1285 ringinfo.h2d_r_idx_hostaddr.high_addr =
1286 cpu_to_le32(address >> 32);
1287
1288 d2h_w_idx_ptr = h2d_r_idx_ptr +
1289 max_submissionrings * idx_offset;
1290 address += max_submissionrings * idx_offset;
1291 ringinfo.d2h_w_idx_hostaddr.low_addr =
1292 cpu_to_le32(address & 0xffffffff);
1293 ringinfo.d2h_w_idx_hostaddr.high_addr =
1294 cpu_to_le32(address >> 32);
1295
1296 d2h_r_idx_ptr = d2h_w_idx_ptr +
1297 max_completionrings * idx_offset;
1298 address += max_completionrings * idx_offset;
1299 ringinfo.d2h_r_idx_hostaddr.low_addr =
1300 cpu_to_le32(address & 0xffffffff);
1301 ringinfo.d2h_r_idx_hostaddr.high_addr =
1302 cpu_to_le32(address >> 32);
1303
1304 memcpy_toio(devinfo->tcm + devinfo->shared.ring_info_addr,
1305 &ringinfo, sizeof(ringinfo));
1306 brcmf_dbg(PCIE, "Using host memory indices\n");
1307 }
1308
1309 ring_mem_ptr = le32_to_cpu(ringinfo.ringmem);
1310
1311 for (i = 0; i < BRCMF_NROF_H2D_COMMON_MSGRINGS; i++) {
1312 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr);
1313 if (!ring)
1314 goto fail;
1315 ring->w_idx_addr = h2d_w_idx_ptr;
1316 ring->r_idx_addr = h2d_r_idx_ptr;
1317 ring->id = i;
1318 devinfo->shared.commonrings[i] = ring;
1319
1320 h2d_w_idx_ptr += idx_offset;
1321 h2d_r_idx_ptr += idx_offset;
1322 ring_mem_ptr += BRCMF_RING_MEM_SZ;
1323 }
1324
1325 for (i = BRCMF_NROF_H2D_COMMON_MSGRINGS;
1326 i < BRCMF_NROF_COMMON_MSGRINGS; i++) {
1327 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr);
1328 if (!ring)
1329 goto fail;
1330 ring->w_idx_addr = d2h_w_idx_ptr;
1331 ring->r_idx_addr = d2h_r_idx_ptr;
1332 ring->id = i;
1333 devinfo->shared.commonrings[i] = ring;
1334
1335 d2h_w_idx_ptr += idx_offset;
1336 d2h_r_idx_ptr += idx_offset;
1337 ring_mem_ptr += BRCMF_RING_MEM_SZ;
1338 }
1339
1340 devinfo->shared.max_flowrings = max_flowrings;
1341 devinfo->shared.max_submissionrings = max_submissionrings;
1342 devinfo->shared.max_completionrings = max_completionrings;
1343 rings = kcalloc(max_flowrings, sizeof(*ring), GFP_KERNEL);
1344 if (!rings)
1345 goto fail;
1346
1347 brcmf_dbg(PCIE, "Nr of flowrings is %d\n", max_flowrings);
1348
1349 for (i = 0; i < max_flowrings; i++) {
1350 ring = &rings[i];
1351 ring->devinfo = devinfo;
1352 ring->id = i + BRCMF_H2D_MSGRING_FLOWRING_IDSTART;
1353 brcmf_commonring_register_cb(&ring->commonring,
1354 brcmf_pcie_ring_mb_ring_bell,
1355 brcmf_pcie_ring_mb_update_rptr,
1356 brcmf_pcie_ring_mb_update_wptr,
1357 brcmf_pcie_ring_mb_write_rptr,
1358 brcmf_pcie_ring_mb_write_wptr,
1359 ring);
1360 ring->w_idx_addr = h2d_w_idx_ptr;
1361 ring->r_idx_addr = h2d_r_idx_ptr;
1362 h2d_w_idx_ptr += idx_offset;
1363 h2d_r_idx_ptr += idx_offset;
1364 }
1365 devinfo->shared.flowrings = rings;
1366
1367 return 0;
1368
1369 fail:
1370 brcmf_err(bus, "Allocating ring buffers failed\n");
1371 brcmf_pcie_release_ringbuffers(devinfo);
1372 return -ENOMEM;
1373 }
1374
1375
1376 static void
brcmf_pcie_release_scratchbuffers(struct brcmf_pciedev_info * devinfo)1377 brcmf_pcie_release_scratchbuffers(struct brcmf_pciedev_info *devinfo)
1378 {
1379 if (devinfo->shared.scratch)
1380 dma_free_coherent(&devinfo->pdev->dev,
1381 BRCMF_DMA_D2H_SCRATCH_BUF_LEN,
1382 devinfo->shared.scratch,
1383 devinfo->shared.scratch_dmahandle);
1384 if (devinfo->shared.ringupd)
1385 dma_free_coherent(&devinfo->pdev->dev,
1386 BRCMF_DMA_D2H_RINGUPD_BUF_LEN,
1387 devinfo->shared.ringupd,
1388 devinfo->shared.ringupd_dmahandle);
1389 }
1390
brcmf_pcie_init_scratchbuffers(struct brcmf_pciedev_info * devinfo)1391 static int brcmf_pcie_init_scratchbuffers(struct brcmf_pciedev_info *devinfo)
1392 {
1393 struct brcmf_bus *bus = dev_get_drvdata(&devinfo->pdev->dev);
1394 u64 address;
1395 u32 addr;
1396
1397 devinfo->shared.scratch =
1398 dma_alloc_coherent(&devinfo->pdev->dev,
1399 BRCMF_DMA_D2H_SCRATCH_BUF_LEN,
1400 &devinfo->shared.scratch_dmahandle,
1401 GFP_KERNEL);
1402 if (!devinfo->shared.scratch)
1403 goto fail;
1404
1405 addr = devinfo->shared.tcm_base_address +
1406 BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET;
1407 address = (u64)devinfo->shared.scratch_dmahandle;
1408 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1409 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1410 addr = devinfo->shared.tcm_base_address +
1411 BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET;
1412 brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_SCRATCH_BUF_LEN);
1413
1414 devinfo->shared.ringupd =
1415 dma_alloc_coherent(&devinfo->pdev->dev,
1416 BRCMF_DMA_D2H_RINGUPD_BUF_LEN,
1417 &devinfo->shared.ringupd_dmahandle,
1418 GFP_KERNEL);
1419 if (!devinfo->shared.ringupd)
1420 goto fail;
1421
1422 addr = devinfo->shared.tcm_base_address +
1423 BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET;
1424 address = (u64)devinfo->shared.ringupd_dmahandle;
1425 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1426 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1427 addr = devinfo->shared.tcm_base_address +
1428 BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET;
1429 brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_RINGUPD_BUF_LEN);
1430 return 0;
1431
1432 fail:
1433 brcmf_err(bus, "Allocating scratch buffers failed\n");
1434 brcmf_pcie_release_scratchbuffers(devinfo);
1435 return -ENOMEM;
1436 }
1437
1438
brcmf_pcie_down(struct device * dev)1439 static void brcmf_pcie_down(struct device *dev)
1440 {
1441 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1442 struct brcmf_pciedev *pcie_bus_dev = bus_if->bus_priv.pcie;
1443 struct brcmf_pciedev_info *devinfo = pcie_bus_dev->devinfo;
1444
1445 brcmf_pcie_fwcon_timer(devinfo, false);
1446 }
1447
brcmf_pcie_preinit(struct device * dev)1448 static int brcmf_pcie_preinit(struct device *dev)
1449 {
1450 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1451 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1452
1453 brcmf_dbg(PCIE, "Enter\n");
1454
1455 brcmf_pcie_intr_enable(buspub->devinfo);
1456 brcmf_pcie_hostready(buspub->devinfo);
1457
1458 return 0;
1459 }
1460
brcmf_pcie_tx(struct device * dev,struct sk_buff * skb)1461 static int brcmf_pcie_tx(struct device *dev, struct sk_buff *skb)
1462 {
1463 return 0;
1464 }
1465
1466
brcmf_pcie_tx_ctlpkt(struct device * dev,unsigned char * msg,uint len)1467 static int brcmf_pcie_tx_ctlpkt(struct device *dev, unsigned char *msg,
1468 uint len)
1469 {
1470 return 0;
1471 }
1472
1473
brcmf_pcie_rx_ctlpkt(struct device * dev,unsigned char * msg,uint len)1474 static int brcmf_pcie_rx_ctlpkt(struct device *dev, unsigned char *msg,
1475 uint len)
1476 {
1477 return 0;
1478 }
1479
1480
brcmf_pcie_wowl_config(struct device * dev,bool enabled)1481 static void brcmf_pcie_wowl_config(struct device *dev, bool enabled)
1482 {
1483 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1484 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1485 struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1486
1487 brcmf_dbg(PCIE, "Configuring WOWL, enabled=%d\n", enabled);
1488 devinfo->wowl_enabled = enabled;
1489 }
1490
1491
brcmf_pcie_get_ramsize(struct device * dev)1492 static size_t brcmf_pcie_get_ramsize(struct device *dev)
1493 {
1494 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1495 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1496 struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1497
1498 return devinfo->ci->ramsize - devinfo->ci->srsize;
1499 }
1500
1501
brcmf_pcie_get_memdump(struct device * dev,void * data,size_t len)1502 static int brcmf_pcie_get_memdump(struct device *dev, void *data, size_t len)
1503 {
1504 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1505 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1506 struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1507
1508 brcmf_dbg(PCIE, "dump at 0x%08X: len=%zu\n", devinfo->ci->rambase, len);
1509 brcmf_pcie_copy_dev_tomem(devinfo, devinfo->ci->rambase, data, len);
1510 return 0;
1511 }
1512
brcmf_pcie_get_blob(struct device * dev,const struct firmware ** fw,enum brcmf_blob_type type)1513 static int brcmf_pcie_get_blob(struct device *dev, const struct firmware **fw,
1514 enum brcmf_blob_type type)
1515 {
1516 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1517 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1518 struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1519
1520 switch (type) {
1521 case BRCMF_BLOB_CLM:
1522 *fw = devinfo->clm_fw;
1523 devinfo->clm_fw = NULL;
1524 break;
1525 case BRCMF_BLOB_TXCAP:
1526 *fw = devinfo->txcap_fw;
1527 devinfo->txcap_fw = NULL;
1528 break;
1529 default:
1530 return -ENOENT;
1531 }
1532
1533 if (!*fw)
1534 return -ENOENT;
1535
1536 return 0;
1537 }
1538
brcmf_pcie_reset(struct device * dev)1539 static int brcmf_pcie_reset(struct device *dev)
1540 {
1541 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1542 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1543 struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1544 struct brcmf_fw_request *fwreq;
1545 int err;
1546
1547 brcmf_pcie_intr_disable(devinfo);
1548
1549 brcmf_pcie_bus_console_read(devinfo, true);
1550
1551 brcmf_detach(dev);
1552
1553 brcmf_pcie_release_irq(devinfo);
1554 brcmf_pcie_release_scratchbuffers(devinfo);
1555 brcmf_pcie_release_ringbuffers(devinfo);
1556 brcmf_pcie_reset_device(devinfo);
1557
1558 fwreq = brcmf_pcie_prepare_fw_request(devinfo);
1559 if (!fwreq) {
1560 dev_err(dev, "Failed to prepare FW request\n");
1561 return -ENOMEM;
1562 }
1563
1564 err = brcmf_fw_get_firmwares(dev, fwreq, brcmf_pcie_setup);
1565 if (err) {
1566 dev_err(dev, "Failed to prepare FW request\n");
1567 kfree(fwreq);
1568 }
1569
1570 return err;
1571 }
1572
1573 static const struct brcmf_bus_ops brcmf_pcie_bus_ops = {
1574 .preinit = brcmf_pcie_preinit,
1575 .txdata = brcmf_pcie_tx,
1576 .stop = brcmf_pcie_down,
1577 .txctl = brcmf_pcie_tx_ctlpkt,
1578 .rxctl = brcmf_pcie_rx_ctlpkt,
1579 .wowl_config = brcmf_pcie_wowl_config,
1580 .get_ramsize = brcmf_pcie_get_ramsize,
1581 .get_memdump = brcmf_pcie_get_memdump,
1582 .get_blob = brcmf_pcie_get_blob,
1583 .reset = brcmf_pcie_reset,
1584 .debugfs_create = brcmf_pcie_debugfs_create,
1585 };
1586
1587
1588 static void
brcmf_pcie_adjust_ramsize(struct brcmf_pciedev_info * devinfo,u8 * data,u32 data_len)1589 brcmf_pcie_adjust_ramsize(struct brcmf_pciedev_info *devinfo, u8 *data,
1590 u32 data_len)
1591 {
1592 __le32 *field;
1593 u32 newsize;
1594
1595 if (data_len < BRCMF_RAMSIZE_OFFSET + 8)
1596 return;
1597
1598 field = (__le32 *)&data[BRCMF_RAMSIZE_OFFSET];
1599 if (le32_to_cpup(field) != BRCMF_RAMSIZE_MAGIC)
1600 return;
1601 field++;
1602 newsize = le32_to_cpup(field);
1603
1604 brcmf_dbg(PCIE, "Found ramsize info in FW, adjusting to 0x%x\n",
1605 newsize);
1606 devinfo->ci->ramsize = newsize;
1607 }
1608
1609
1610 static int
brcmf_pcie_init_share_ram_info(struct brcmf_pciedev_info * devinfo,u32 sharedram_addr)1611 brcmf_pcie_init_share_ram_info(struct brcmf_pciedev_info *devinfo,
1612 u32 sharedram_addr)
1613 {
1614 struct brcmf_bus *bus = dev_get_drvdata(&devinfo->pdev->dev);
1615 struct brcmf_pcie_shared_info *shared;
1616 u32 addr;
1617
1618 shared = &devinfo->shared;
1619 shared->tcm_base_address = sharedram_addr;
1620
1621 shared->flags = brcmf_pcie_read_tcm32(devinfo, sharedram_addr);
1622 shared->version = (u8)(shared->flags & BRCMF_PCIE_SHARED_VERSION_MASK);
1623 brcmf_dbg(PCIE, "PCIe protocol version %d\n", shared->version);
1624 if ((shared->version > BRCMF_PCIE_MAX_SHARED_VERSION) ||
1625 (shared->version < BRCMF_PCIE_MIN_SHARED_VERSION)) {
1626 brcmf_err(bus, "Unsupported PCIE version %d\n",
1627 shared->version);
1628 return -EINVAL;
1629 }
1630
1631 /* check firmware support dma indicies */
1632 if (shared->flags & BRCMF_PCIE_SHARED_DMA_INDEX) {
1633 if (shared->flags & BRCMF_PCIE_SHARED_DMA_2B_IDX)
1634 devinfo->dma_idx_sz = sizeof(u16);
1635 else
1636 devinfo->dma_idx_sz = sizeof(u32);
1637 }
1638
1639 addr = sharedram_addr + BRCMF_SHARED_MAX_RXBUFPOST_OFFSET;
1640 shared->max_rxbufpost = brcmf_pcie_read_tcm16(devinfo, addr);
1641 if (shared->max_rxbufpost == 0)
1642 shared->max_rxbufpost = BRCMF_DEF_MAX_RXBUFPOST;
1643
1644 addr = sharedram_addr + BRCMF_SHARED_RX_DATAOFFSET_OFFSET;
1645 shared->rx_dataoffset = brcmf_pcie_read_tcm32(devinfo, addr);
1646
1647 addr = sharedram_addr + BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET;
1648 shared->htod_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1649
1650 addr = sharedram_addr + BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET;
1651 shared->dtoh_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1652
1653 addr = sharedram_addr + BRCMF_SHARED_RING_INFO_ADDR_OFFSET;
1654 shared->ring_info_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1655
1656 brcmf_dbg(PCIE, "max rx buf post %d, rx dataoffset %d\n",
1657 shared->max_rxbufpost, shared->rx_dataoffset);
1658
1659 brcmf_pcie_bus_console_init(devinfo);
1660 brcmf_pcie_bus_console_read(devinfo, false);
1661
1662 return 0;
1663 }
1664
1665 struct brcmf_random_seed_footer {
1666 __le32 length;
1667 __le32 magic;
1668 };
1669
1670 #define BRCMF_RANDOM_SEED_MAGIC 0xfeedc0de
1671 #define BRCMF_RANDOM_SEED_LENGTH 0x100
1672
1673 static noinline_for_stack void
brcmf_pcie_provide_random_bytes(struct brcmf_pciedev_info * devinfo,u32 address)1674 brcmf_pcie_provide_random_bytes(struct brcmf_pciedev_info *devinfo, u32 address)
1675 {
1676 u8 randbuf[BRCMF_RANDOM_SEED_LENGTH];
1677
1678 get_random_bytes(randbuf, BRCMF_RANDOM_SEED_LENGTH);
1679 memcpy_toio(devinfo->tcm + address, randbuf, BRCMF_RANDOM_SEED_LENGTH);
1680 }
1681
brcmf_pcie_download_fw_nvram(struct brcmf_pciedev_info * devinfo,const struct firmware * fw,void * nvram,u32 nvram_len)1682 static int brcmf_pcie_download_fw_nvram(struct brcmf_pciedev_info *devinfo,
1683 const struct firmware *fw, void *nvram,
1684 u32 nvram_len)
1685 {
1686 struct brcmf_bus *bus = dev_get_drvdata(&devinfo->pdev->dev);
1687 u32 sharedram_addr;
1688 u32 sharedram_addr_written;
1689 u32 loop_counter;
1690 int err;
1691 u32 address;
1692 u32 resetintr;
1693
1694 brcmf_dbg(PCIE, "Halt ARM.\n");
1695 err = brcmf_pcie_enter_download_state(devinfo);
1696 if (err)
1697 return err;
1698
1699 brcmf_dbg(PCIE, "Download FW %s\n", devinfo->fw_name);
1700 memcpy_toio(devinfo->tcm + devinfo->ci->rambase,
1701 (void *)fw->data, fw->size);
1702
1703 resetintr = get_unaligned_le32(fw->data);
1704 release_firmware(fw);
1705
1706 /* reset last 4 bytes of RAM address. to be used for shared
1707 * area. This identifies when FW is running
1708 */
1709 brcmf_pcie_write_ram32(devinfo, devinfo->ci->ramsize - 4, 0);
1710
1711 if (nvram) {
1712 brcmf_dbg(PCIE, "Download NVRAM %s\n", devinfo->nvram_name);
1713 address = devinfo->ci->rambase + devinfo->ci->ramsize -
1714 nvram_len;
1715 memcpy_toio(devinfo->tcm + address, nvram, nvram_len);
1716 brcmf_fw_nvram_free(nvram);
1717
1718 if (devinfo->otp.valid) {
1719 size_t rand_len = BRCMF_RANDOM_SEED_LENGTH;
1720 struct brcmf_random_seed_footer footer = {
1721 .length = cpu_to_le32(rand_len),
1722 .magic = cpu_to_le32(BRCMF_RANDOM_SEED_MAGIC),
1723 };
1724
1725 /* Some Apple chips/firmwares expect a buffer of random
1726 * data to be present before NVRAM
1727 */
1728 brcmf_dbg(PCIE, "Download random seed\n");
1729
1730 address -= sizeof(footer);
1731 memcpy_toio(devinfo->tcm + address, &footer,
1732 sizeof(footer));
1733
1734 address -= rand_len;
1735 brcmf_pcie_provide_random_bytes(devinfo, address);
1736 }
1737 } else {
1738 brcmf_dbg(PCIE, "No matching NVRAM file found %s\n",
1739 devinfo->nvram_name);
1740 }
1741
1742 sharedram_addr_written = brcmf_pcie_read_ram32(devinfo,
1743 devinfo->ci->ramsize -
1744 4);
1745 brcmf_dbg(PCIE, "Bring ARM in running state\n");
1746 err = brcmf_pcie_exit_download_state(devinfo, resetintr);
1747 if (err)
1748 return err;
1749
1750 brcmf_dbg(PCIE, "Wait for FW init\n");
1751 sharedram_addr = sharedram_addr_written;
1752 loop_counter = BRCMF_PCIE_FW_UP_TIMEOUT / 50;
1753 while ((sharedram_addr == sharedram_addr_written) && (loop_counter)) {
1754 msleep(50);
1755 sharedram_addr = brcmf_pcie_read_ram32(devinfo,
1756 devinfo->ci->ramsize -
1757 4);
1758 loop_counter--;
1759 }
1760 if (sharedram_addr == sharedram_addr_written) {
1761 brcmf_err(bus, "FW failed to initialize\n");
1762 return -ENODEV;
1763 }
1764 if (sharedram_addr < devinfo->ci->rambase ||
1765 sharedram_addr >= devinfo->ci->rambase + devinfo->ci->ramsize) {
1766 brcmf_err(bus, "Invalid shared RAM address 0x%08x\n",
1767 sharedram_addr);
1768 return -ENODEV;
1769 }
1770 brcmf_dbg(PCIE, "Shared RAM addr: 0x%08x\n", sharedram_addr);
1771
1772 return (brcmf_pcie_init_share_ram_info(devinfo, sharedram_addr));
1773 }
1774
1775
brcmf_pcie_get_resource(struct brcmf_pciedev_info * devinfo)1776 static int brcmf_pcie_get_resource(struct brcmf_pciedev_info *devinfo)
1777 {
1778 struct pci_dev *pdev = devinfo->pdev;
1779 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev);
1780 int err;
1781 phys_addr_t bar0_addr, bar1_addr;
1782 ulong bar1_size;
1783
1784 err = pci_enable_device(pdev);
1785 if (err) {
1786 brcmf_err(bus, "pci_enable_device failed err=%d\n", err);
1787 return err;
1788 }
1789
1790 pci_set_master(pdev);
1791
1792 /* Bar-0 mapped address */
1793 bar0_addr = pci_resource_start(pdev, 0);
1794 /* Bar-1 mapped address */
1795 bar1_addr = pci_resource_start(pdev, 2);
1796 /* read Bar-1 mapped memory range */
1797 bar1_size = pci_resource_len(pdev, 2);
1798 if ((bar1_size == 0) || (bar1_addr == 0)) {
1799 brcmf_err(bus, "BAR1 Not enabled, device size=%ld, addr=%#016llx\n",
1800 bar1_size, (unsigned long long)bar1_addr);
1801 return -EINVAL;
1802 }
1803
1804 devinfo->regs = ioremap(bar0_addr, BRCMF_PCIE_REG_MAP_SIZE);
1805 devinfo->tcm = ioremap(bar1_addr, bar1_size);
1806
1807 if (!devinfo->regs || !devinfo->tcm) {
1808 brcmf_err(bus, "ioremap() failed (%p,%p)\n", devinfo->regs,
1809 devinfo->tcm);
1810 return -EINVAL;
1811 }
1812 brcmf_dbg(PCIE, "Phys addr : reg space = %p base addr %#016llx\n",
1813 devinfo->regs, (unsigned long long)bar0_addr);
1814 brcmf_dbg(PCIE, "Phys addr : mem space = %p base addr %#016llx size 0x%x\n",
1815 devinfo->tcm, (unsigned long long)bar1_addr,
1816 (unsigned int)bar1_size);
1817
1818 return 0;
1819 }
1820
1821
brcmf_pcie_release_resource(struct brcmf_pciedev_info * devinfo)1822 static void brcmf_pcie_release_resource(struct brcmf_pciedev_info *devinfo)
1823 {
1824 if (devinfo->tcm)
1825 iounmap(devinfo->tcm);
1826 if (devinfo->regs)
1827 iounmap(devinfo->regs);
1828
1829 pci_disable_device(devinfo->pdev);
1830 }
1831
1832
brcmf_pcie_buscore_prep_addr(const struct pci_dev * pdev,u32 addr)1833 static u32 brcmf_pcie_buscore_prep_addr(const struct pci_dev *pdev, u32 addr)
1834 {
1835 u32 ret_addr;
1836
1837 ret_addr = addr & (BRCMF_PCIE_BAR0_REG_SIZE - 1);
1838 addr &= ~(BRCMF_PCIE_BAR0_REG_SIZE - 1);
1839 pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, addr);
1840
1841 return ret_addr;
1842 }
1843
1844
brcmf_pcie_buscore_read32(void * ctx,u32 addr)1845 static u32 brcmf_pcie_buscore_read32(void *ctx, u32 addr)
1846 {
1847 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1848
1849 addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr);
1850 return brcmf_pcie_read_reg32(devinfo, addr);
1851 }
1852
1853
brcmf_pcie_buscore_write32(void * ctx,u32 addr,u32 value)1854 static void brcmf_pcie_buscore_write32(void *ctx, u32 addr, u32 value)
1855 {
1856 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1857
1858 addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr);
1859 brcmf_pcie_write_reg32(devinfo, addr, value);
1860 }
1861
1862
brcmf_pcie_buscoreprep(void * ctx)1863 static int brcmf_pcie_buscoreprep(void *ctx)
1864 {
1865 return brcmf_pcie_get_resource(ctx);
1866 }
1867
1868
brcmf_pcie_buscore_reset(void * ctx,struct brcmf_chip * chip)1869 static int brcmf_pcie_buscore_reset(void *ctx, struct brcmf_chip *chip)
1870 {
1871 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1872 struct brcmf_core *core;
1873 u32 val, reg;
1874
1875 devinfo->ci = chip;
1876 brcmf_pcie_reset_device(devinfo);
1877
1878 /* reginfo is not ready yet */
1879 core = brcmf_chip_get_core(chip, BCMA_CORE_PCIE2);
1880 if (core->rev >= 64)
1881 reg = BRCMF_PCIE_64_PCIE2REG_MAILBOXINT;
1882 else
1883 reg = BRCMF_PCIE_PCIE2REG_MAILBOXINT;
1884
1885 val = brcmf_pcie_read_reg32(devinfo, reg);
1886 if (val != 0xffffffff)
1887 brcmf_pcie_write_reg32(devinfo, reg, val);
1888
1889 return 0;
1890 }
1891
1892
brcmf_pcie_buscore_activate(void * ctx,struct brcmf_chip * chip,u32 rstvec)1893 static void brcmf_pcie_buscore_activate(void *ctx, struct brcmf_chip *chip,
1894 u32 rstvec)
1895 {
1896 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1897
1898 brcmf_pcie_write_tcm32(devinfo, 0, rstvec);
1899 }
1900
1901
1902 static const struct brcmf_buscore_ops brcmf_pcie_buscore_ops = {
1903 .prepare = brcmf_pcie_buscoreprep,
1904 .reset = brcmf_pcie_buscore_reset,
1905 .activate = brcmf_pcie_buscore_activate,
1906 .read32 = brcmf_pcie_buscore_read32,
1907 .write32 = brcmf_pcie_buscore_write32,
1908 };
1909
1910 #define BRCMF_OTP_SYS_VENDOR 0x15
1911 #define BRCMF_OTP_BRCM_CIS 0x80
1912
1913 #define BRCMF_OTP_VENDOR_HDR 0x00000008
1914
1915 static int
brcmf_pcie_parse_otp_sys_vendor(struct brcmf_pciedev_info * devinfo,u8 * data,size_t size)1916 brcmf_pcie_parse_otp_sys_vendor(struct brcmf_pciedev_info *devinfo,
1917 u8 *data, size_t size)
1918 {
1919 int idx = 4;
1920 const char *chip_params;
1921 const char *board_params;
1922 const char *p;
1923
1924 /* 4-byte header and two empty strings */
1925 if (size < 6)
1926 return -EINVAL;
1927
1928 if (get_unaligned_le32(data) != BRCMF_OTP_VENDOR_HDR)
1929 return -EINVAL;
1930
1931 chip_params = &data[idx];
1932
1933 /* Skip first string, including terminator */
1934 idx += strnlen(chip_params, size - idx) + 1;
1935 if (idx >= size)
1936 return -EINVAL;
1937
1938 board_params = &data[idx];
1939
1940 /* Skip to terminator of second string */
1941 idx += strnlen(board_params, size - idx);
1942 if (idx >= size)
1943 return -EINVAL;
1944
1945 /* At this point both strings are guaranteed NUL-terminated */
1946 brcmf_dbg(PCIE, "OTP: chip_params='%s' board_params='%s'\n",
1947 chip_params, board_params);
1948
1949 p = skip_spaces(board_params);
1950 while (*p) {
1951 char tag = *p++;
1952 const char *end;
1953 size_t len;
1954
1955 if (*p++ != '=') /* implicit NUL check */
1956 return -EINVAL;
1957
1958 /* *p might be NUL here, if so end == p and len == 0 */
1959 end = strchrnul(p, ' ');
1960 len = end - p;
1961
1962 /* leave 1 byte for NUL in destination string */
1963 if (len > (BRCMF_OTP_MAX_PARAM_LEN - 1))
1964 return -EINVAL;
1965
1966 /* Copy len characters plus a NUL terminator */
1967 switch (tag) {
1968 case 'M':
1969 strscpy(devinfo->otp.module, p, len + 1);
1970 break;
1971 case 'V':
1972 strscpy(devinfo->otp.vendor, p, len + 1);
1973 break;
1974 case 'm':
1975 strscpy(devinfo->otp.version, p, len + 1);
1976 break;
1977 }
1978
1979 /* Skip to next arg, if any */
1980 p = skip_spaces(end);
1981 }
1982
1983 brcmf_dbg(PCIE, "OTP: module=%s vendor=%s version=%s\n",
1984 devinfo->otp.module, devinfo->otp.vendor,
1985 devinfo->otp.version);
1986
1987 if (!devinfo->otp.module[0] ||
1988 !devinfo->otp.vendor[0] ||
1989 !devinfo->otp.version[0])
1990 return -EINVAL;
1991
1992 devinfo->otp.valid = true;
1993 return 0;
1994 }
1995
1996 static int
brcmf_pcie_parse_otp(struct brcmf_pciedev_info * devinfo,u8 * otp,size_t size)1997 brcmf_pcie_parse_otp(struct brcmf_pciedev_info *devinfo, u8 *otp, size_t size)
1998 {
1999 int p = 0;
2000 int ret = -EINVAL;
2001
2002 brcmf_dbg(PCIE, "parse_otp size=%zd\n", size);
2003
2004 while (p < (size - 1)) {
2005 u8 type = otp[p];
2006 u8 length = otp[p + 1];
2007
2008 if (type == 0)
2009 break;
2010
2011 if ((p + 2 + length) > size)
2012 break;
2013
2014 switch (type) {
2015 case BRCMF_OTP_SYS_VENDOR:
2016 brcmf_dbg(PCIE, "OTP @ 0x%x (%d): SYS_VENDOR\n",
2017 p, length);
2018 ret = brcmf_pcie_parse_otp_sys_vendor(devinfo,
2019 &otp[p + 2],
2020 length);
2021 break;
2022 case BRCMF_OTP_BRCM_CIS:
2023 brcmf_dbg(PCIE, "OTP @ 0x%x (%d): BRCM_CIS\n",
2024 p, length);
2025 break;
2026 default:
2027 brcmf_dbg(PCIE, "OTP @ 0x%x (%d): Unknown type 0x%x\n",
2028 p, length, type);
2029 break;
2030 }
2031
2032 p += 2 + length;
2033 }
2034
2035 return ret;
2036 }
2037
brcmf_pcie_read_otp(struct brcmf_pciedev_info * devinfo)2038 static int brcmf_pcie_read_otp(struct brcmf_pciedev_info *devinfo)
2039 {
2040 const struct pci_dev *pdev = devinfo->pdev;
2041 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev);
2042 u32 coreid, base, words, idx, sromctl;
2043 u16 *otp;
2044 struct brcmf_core *core;
2045 int ret;
2046
2047 switch (devinfo->ci->chip) {
2048 case BRCM_CC_4355_CHIP_ID:
2049 coreid = BCMA_CORE_CHIPCOMMON;
2050 base = 0x8c0;
2051 words = 0xb2;
2052 break;
2053 case BRCM_CC_4364_CHIP_ID:
2054 coreid = BCMA_CORE_CHIPCOMMON;
2055 base = 0x8c0;
2056 words = 0x1a0;
2057 break;
2058 case BRCM_CC_4377_CHIP_ID:
2059 case BRCM_CC_4378_CHIP_ID:
2060 coreid = BCMA_CORE_GCI;
2061 base = 0x1120;
2062 words = 0x170;
2063 break;
2064 case BRCM_CC_4387_CHIP_ID:
2065 coreid = BCMA_CORE_GCI;
2066 base = 0x113c;
2067 words = 0x170;
2068 break;
2069 default:
2070 /* OTP not supported on this chip */
2071 return 0;
2072 }
2073
2074 core = brcmf_chip_get_core(devinfo->ci, coreid);
2075 if (!core) {
2076 brcmf_err(bus, "No OTP core\n");
2077 return -ENODEV;
2078 }
2079
2080 if (coreid == BCMA_CORE_CHIPCOMMON) {
2081 /* Chips with OTP accessed via ChipCommon need additional
2082 * handling to access the OTP
2083 */
2084 brcmf_pcie_select_core(devinfo, coreid);
2085 sromctl = READCC32(devinfo, sromcontrol);
2086
2087 if (!(sromctl & BCMA_CC_SROM_CONTROL_OTP_PRESENT)) {
2088 /* Chip lacks OTP, try without it... */
2089 brcmf_err(bus,
2090 "OTP unavailable, using default firmware\n");
2091 return 0;
2092 }
2093
2094 /* Map OTP to shadow area */
2095 WRITECC32(devinfo, sromcontrol,
2096 sromctl | BCMA_CC_SROM_CONTROL_OTPSEL);
2097 }
2098
2099 otp = kcalloc(words, sizeof(u16), GFP_KERNEL);
2100 if (!otp)
2101 return -ENOMEM;
2102
2103 /* Map bus window to SROM/OTP shadow area in core */
2104 base = brcmf_pcie_buscore_prep_addr(devinfo->pdev, base + core->base);
2105
2106 brcmf_dbg(PCIE, "OTP data:\n");
2107 for (idx = 0; idx < words; idx++) {
2108 otp[idx] = brcmf_pcie_read_reg16(devinfo, base + 2 * idx);
2109 brcmf_dbg(PCIE, "[%8x] 0x%04x\n", base + 2 * idx, otp[idx]);
2110 }
2111
2112 if (coreid == BCMA_CORE_CHIPCOMMON) {
2113 brcmf_pcie_select_core(devinfo, coreid);
2114 WRITECC32(devinfo, sromcontrol, sromctl);
2115 }
2116
2117 ret = brcmf_pcie_parse_otp(devinfo, (u8 *)otp, 2 * words);
2118 kfree(otp);
2119
2120 return ret;
2121 }
2122
2123 #define BRCMF_PCIE_FW_CODE 0
2124 #define BRCMF_PCIE_FW_NVRAM 1
2125 #define BRCMF_PCIE_FW_CLM 2
2126 #define BRCMF_PCIE_FW_TXCAP 3
2127
brcmf_pcie_setup(struct device * dev,int ret,struct brcmf_fw_request * fwreq)2128 static void brcmf_pcie_setup(struct device *dev, int ret,
2129 struct brcmf_fw_request *fwreq)
2130 {
2131 const struct firmware *fw;
2132 void *nvram;
2133 struct brcmf_bus *bus;
2134 struct brcmf_pciedev *pcie_bus_dev;
2135 struct brcmf_pciedev_info *devinfo;
2136 struct brcmf_commonring **flowrings;
2137 u32 i, nvram_len;
2138
2139 bus = dev_get_drvdata(dev);
2140 pcie_bus_dev = bus->bus_priv.pcie;
2141 devinfo = pcie_bus_dev->devinfo;
2142
2143 /* check firmware loading result */
2144 if (ret)
2145 goto fail;
2146
2147 brcmf_pcie_attach(devinfo);
2148
2149 fw = fwreq->items[BRCMF_PCIE_FW_CODE].binary;
2150 nvram = fwreq->items[BRCMF_PCIE_FW_NVRAM].nv_data.data;
2151 nvram_len = fwreq->items[BRCMF_PCIE_FW_NVRAM].nv_data.len;
2152 devinfo->clm_fw = fwreq->items[BRCMF_PCIE_FW_CLM].binary;
2153 devinfo->txcap_fw = fwreq->items[BRCMF_PCIE_FW_TXCAP].binary;
2154 kfree(fwreq);
2155
2156 ret = brcmf_chip_get_raminfo(devinfo->ci);
2157 if (ret) {
2158 brcmf_err(bus, "Failed to get RAM info\n");
2159 release_firmware(fw);
2160 brcmf_fw_nvram_free(nvram);
2161 goto fail;
2162 }
2163
2164 /* Some of the firmwares have the size of the memory of the device
2165 * defined inside the firmware. This is because part of the memory in
2166 * the device is shared and the devision is determined by FW. Parse
2167 * the firmware and adjust the chip memory size now.
2168 */
2169 brcmf_pcie_adjust_ramsize(devinfo, (u8 *)fw->data, fw->size);
2170
2171 ret = brcmf_pcie_download_fw_nvram(devinfo, fw, nvram, nvram_len);
2172 if (ret)
2173 goto fail;
2174
2175 devinfo->state = BRCMFMAC_PCIE_STATE_UP;
2176
2177 ret = brcmf_pcie_init_ringbuffers(devinfo);
2178 if (ret)
2179 goto fail;
2180
2181 ret = brcmf_pcie_init_scratchbuffers(devinfo);
2182 if (ret)
2183 goto fail;
2184
2185 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
2186 ret = brcmf_pcie_request_irq(devinfo);
2187 if (ret)
2188 goto fail;
2189
2190 /* hook the commonrings in the bus structure. */
2191 for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++)
2192 bus->msgbuf->commonrings[i] =
2193 &devinfo->shared.commonrings[i]->commonring;
2194
2195 flowrings = kcalloc(devinfo->shared.max_flowrings, sizeof(*flowrings),
2196 GFP_KERNEL);
2197 if (!flowrings)
2198 goto fail;
2199
2200 for (i = 0; i < devinfo->shared.max_flowrings; i++)
2201 flowrings[i] = &devinfo->shared.flowrings[i].commonring;
2202 bus->msgbuf->flowrings = flowrings;
2203
2204 bus->msgbuf->rx_dataoffset = devinfo->shared.rx_dataoffset;
2205 bus->msgbuf->max_rxbufpost = devinfo->shared.max_rxbufpost;
2206 bus->msgbuf->max_flowrings = devinfo->shared.max_flowrings;
2207
2208 init_waitqueue_head(&devinfo->mbdata_resp_wait);
2209
2210 ret = brcmf_attach(&devinfo->pdev->dev);
2211 if (ret)
2212 goto fail;
2213
2214 brcmf_pcie_bus_console_read(devinfo, false);
2215
2216 brcmf_pcie_fwcon_timer(devinfo, true);
2217
2218 return;
2219
2220 fail:
2221 brcmf_err(bus, "Dongle setup failed\n");
2222 brcmf_pcie_bus_console_read(devinfo, true);
2223 brcmf_fw_crashed(dev);
2224 device_release_driver(dev);
2225 }
2226
2227 static struct brcmf_fw_request *
brcmf_pcie_prepare_fw_request(struct brcmf_pciedev_info * devinfo)2228 brcmf_pcie_prepare_fw_request(struct brcmf_pciedev_info *devinfo)
2229 {
2230 struct brcmf_fw_request *fwreq;
2231 struct brcmf_fw_name fwnames[] = {
2232 { ".bin", devinfo->fw_name },
2233 { ".txt", devinfo->nvram_name },
2234 { ".clm_blob", devinfo->clm_name },
2235 { ".txcap_blob", devinfo->txcap_name },
2236 };
2237
2238 fwreq = brcmf_fw_alloc_request(devinfo->ci->chip, devinfo->ci->chiprev,
2239 brcmf_pcie_fwnames,
2240 ARRAY_SIZE(brcmf_pcie_fwnames),
2241 fwnames, ARRAY_SIZE(fwnames));
2242 if (!fwreq)
2243 return NULL;
2244
2245 fwreq->items[BRCMF_PCIE_FW_CODE].type = BRCMF_FW_TYPE_BINARY;
2246 fwreq->items[BRCMF_PCIE_FW_NVRAM].type = BRCMF_FW_TYPE_NVRAM;
2247 fwreq->items[BRCMF_PCIE_FW_NVRAM].flags = BRCMF_FW_REQF_OPTIONAL;
2248 fwreq->items[BRCMF_PCIE_FW_CLM].type = BRCMF_FW_TYPE_BINARY;
2249 fwreq->items[BRCMF_PCIE_FW_CLM].flags = BRCMF_FW_REQF_OPTIONAL;
2250 fwreq->items[BRCMF_PCIE_FW_TXCAP].type = BRCMF_FW_TYPE_BINARY;
2251 fwreq->items[BRCMF_PCIE_FW_TXCAP].flags = BRCMF_FW_REQF_OPTIONAL;
2252 /* NVRAM reserves PCI domain 0 for Broadcom's SDK faked bus */
2253 fwreq->domain_nr = pci_domain_nr(devinfo->pdev->bus) + 1;
2254 fwreq->bus_nr = devinfo->pdev->bus->number;
2255
2256 /* Apple platforms with fancy firmware/NVRAM selection */
2257 if (devinfo->settings->board_type &&
2258 devinfo->settings->antenna_sku &&
2259 devinfo->otp.valid) {
2260 const struct brcmf_otp_params *otp = &devinfo->otp;
2261 struct device *dev = &devinfo->pdev->dev;
2262 const char **bt = fwreq->board_types;
2263
2264 brcmf_dbg(PCIE, "Apple board: %s\n",
2265 devinfo->settings->board_type);
2266
2267 /* Example: apple,shikoku-RASP-m-6.11-X3 */
2268 bt[0] = devm_kasprintf(dev, GFP_KERNEL, "%s-%s-%s-%s-%s",
2269 devinfo->settings->board_type,
2270 otp->module, otp->vendor, otp->version,
2271 devinfo->settings->antenna_sku);
2272 bt[1] = devm_kasprintf(dev, GFP_KERNEL, "%s-%s-%s-%s",
2273 devinfo->settings->board_type,
2274 otp->module, otp->vendor, otp->version);
2275 bt[2] = devm_kasprintf(dev, GFP_KERNEL, "%s-%s-%s",
2276 devinfo->settings->board_type,
2277 otp->module, otp->vendor);
2278 bt[3] = devm_kasprintf(dev, GFP_KERNEL, "%s-%s",
2279 devinfo->settings->board_type,
2280 otp->module);
2281 bt[4] = devm_kasprintf(dev, GFP_KERNEL, "%s-%s",
2282 devinfo->settings->board_type,
2283 devinfo->settings->antenna_sku);
2284 bt[5] = devinfo->settings->board_type;
2285
2286 if (!bt[0] || !bt[1] || !bt[2] || !bt[3] || !bt[4]) {
2287 kfree(fwreq);
2288 return NULL;
2289 }
2290 } else {
2291 brcmf_dbg(PCIE, "Board: %s\n", devinfo->settings->board_type);
2292 fwreq->board_types[0] = devinfo->settings->board_type;
2293 }
2294
2295 return fwreq;
2296 }
2297
2298 #ifdef DEBUG
2299 static void
brcmf_pcie_fwcon_timer(struct brcmf_pciedev_info * devinfo,bool active)2300 brcmf_pcie_fwcon_timer(struct brcmf_pciedev_info *devinfo, bool active)
2301 {
2302 if (!active) {
2303 if (devinfo->console_active) {
2304 del_timer_sync(&devinfo->timer);
2305 devinfo->console_active = false;
2306 }
2307 return;
2308 }
2309
2310 /* don't start the timer */
2311 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP ||
2312 !devinfo->console_interval || !BRCMF_FWCON_ON())
2313 return;
2314
2315 if (!devinfo->console_active) {
2316 devinfo->timer.expires = jiffies + devinfo->console_interval;
2317 add_timer(&devinfo->timer);
2318 devinfo->console_active = true;
2319 } else {
2320 /* Reschedule the timer */
2321 mod_timer(&devinfo->timer, jiffies + devinfo->console_interval);
2322 }
2323 }
2324
2325 static void
brcmf_pcie_fwcon(struct timer_list * t)2326 brcmf_pcie_fwcon(struct timer_list *t)
2327 {
2328 struct brcmf_pciedev_info *devinfo = from_timer(devinfo, t, timer);
2329
2330 if (!devinfo->console_active)
2331 return;
2332
2333 brcmf_pcie_bus_console_read(devinfo, false);
2334
2335 /* Reschedule the timer if console interval is not zero */
2336 mod_timer(&devinfo->timer, jiffies + devinfo->console_interval);
2337 }
2338
brcmf_pcie_console_interval_get(void * data,u64 * val)2339 static int brcmf_pcie_console_interval_get(void *data, u64 *val)
2340 {
2341 struct brcmf_pciedev_info *devinfo = data;
2342
2343 *val = devinfo->console_interval;
2344
2345 return 0;
2346 }
2347
brcmf_pcie_console_interval_set(void * data,u64 val)2348 static int brcmf_pcie_console_interval_set(void *data, u64 val)
2349 {
2350 struct brcmf_pciedev_info *devinfo = data;
2351
2352 if (val > MAX_CONSOLE_INTERVAL)
2353 return -EINVAL;
2354
2355 devinfo->console_interval = val;
2356
2357 if (!val && devinfo->console_active)
2358 brcmf_pcie_fwcon_timer(devinfo, false);
2359 else if (val)
2360 brcmf_pcie_fwcon_timer(devinfo, true);
2361
2362 return 0;
2363 }
2364
2365 DEFINE_SIMPLE_ATTRIBUTE(brcmf_pcie_console_interval_fops,
2366 brcmf_pcie_console_interval_get,
2367 brcmf_pcie_console_interval_set,
2368 "%llu\n");
2369
brcmf_pcie_debugfs_create(struct device * dev)2370 static void brcmf_pcie_debugfs_create(struct device *dev)
2371 {
2372 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2373 struct brcmf_pub *drvr = bus_if->drvr;
2374 struct brcmf_pciedev *pcie_bus_dev = bus_if->bus_priv.pcie;
2375 struct brcmf_pciedev_info *devinfo = pcie_bus_dev->devinfo;
2376 struct dentry *dentry = brcmf_debugfs_get_devdir(drvr);
2377
2378 if (IS_ERR_OR_NULL(dentry))
2379 return;
2380
2381 devinfo->console_interval = BRCMF_CONSOLE;
2382
2383 debugfs_create_file("console_interval", 0644, dentry, devinfo,
2384 &brcmf_pcie_console_interval_fops);
2385 }
2386
2387 #else
brcmf_pcie_fwcon_timer(struct brcmf_pciedev_info * devinfo,bool active)2388 void brcmf_pcie_fwcon_timer(struct brcmf_pciedev_info *devinfo, bool active)
2389 {
2390 }
2391
brcmf_pcie_debugfs_create(struct device * dev)2392 static void brcmf_pcie_debugfs_create(struct device *dev)
2393 {
2394 }
2395 #endif
2396
2397 /* Forward declaration for pci_match_id() call */
2398 static const struct pci_device_id brcmf_pcie_devid_table[];
2399
2400 static int
brcmf_pcie_probe(struct pci_dev * pdev,const struct pci_device_id * id)2401 brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2402 {
2403 int ret;
2404 struct brcmf_fw_request *fwreq;
2405 struct brcmf_pciedev_info *devinfo;
2406 struct brcmf_pciedev *pcie_bus_dev;
2407 struct brcmf_core *core;
2408 struct brcmf_bus *bus;
2409
2410 if (!id) {
2411 id = pci_match_id(brcmf_pcie_devid_table, pdev);
2412 if (!id) {
2413 pci_err(pdev, "Error could not find pci_device_id for %x:%x\n", pdev->vendor, pdev->device);
2414 return -ENODEV;
2415 }
2416 }
2417
2418 brcmf_dbg(PCIE, "Enter %x:%x\n", pdev->vendor, pdev->device);
2419
2420 ret = -ENOMEM;
2421 devinfo = kzalloc(sizeof(*devinfo), GFP_KERNEL);
2422 if (devinfo == NULL)
2423 return ret;
2424
2425 devinfo->pdev = pdev;
2426 pcie_bus_dev = NULL;
2427 devinfo->ci = brcmf_chip_attach(devinfo, pdev->device,
2428 &brcmf_pcie_buscore_ops);
2429 if (IS_ERR(devinfo->ci)) {
2430 ret = PTR_ERR(devinfo->ci);
2431 devinfo->ci = NULL;
2432 goto fail;
2433 }
2434
2435 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_PCIE2);
2436 if (core->rev >= 64)
2437 devinfo->reginfo = &brcmf_reginfo_64;
2438 else
2439 devinfo->reginfo = &brcmf_reginfo_default;
2440
2441 pcie_bus_dev = kzalloc(sizeof(*pcie_bus_dev), GFP_KERNEL);
2442 if (pcie_bus_dev == NULL) {
2443 ret = -ENOMEM;
2444 goto fail;
2445 }
2446
2447 devinfo->settings = brcmf_get_module_param(&devinfo->pdev->dev,
2448 BRCMF_BUSTYPE_PCIE,
2449 devinfo->ci->chip,
2450 devinfo->ci->chiprev);
2451 if (!devinfo->settings) {
2452 ret = -ENOMEM;
2453 goto fail;
2454 }
2455
2456 bus = kzalloc(sizeof(*bus), GFP_KERNEL);
2457 if (!bus) {
2458 ret = -ENOMEM;
2459 goto fail;
2460 }
2461 bus->msgbuf = kzalloc(sizeof(*bus->msgbuf), GFP_KERNEL);
2462 if (!bus->msgbuf) {
2463 ret = -ENOMEM;
2464 kfree(bus);
2465 goto fail;
2466 }
2467
2468 /* hook it all together. */
2469 pcie_bus_dev->devinfo = devinfo;
2470 pcie_bus_dev->bus = bus;
2471 bus->dev = &pdev->dev;
2472 bus->bus_priv.pcie = pcie_bus_dev;
2473 bus->ops = &brcmf_pcie_bus_ops;
2474 bus->proto_type = BRCMF_PROTO_MSGBUF;
2475 bus->fwvid = id->driver_data;
2476 bus->chip = devinfo->coreid;
2477 bus->wowl_supported = pci_pme_capable(pdev, PCI_D3hot);
2478 dev_set_drvdata(&pdev->dev, bus);
2479
2480 ret = brcmf_alloc(&devinfo->pdev->dev, devinfo->settings);
2481 if (ret)
2482 goto fail_bus;
2483
2484 ret = brcmf_pcie_read_otp(devinfo);
2485 if (ret) {
2486 brcmf_err(bus, "failed to parse OTP\n");
2487 goto fail_brcmf;
2488 }
2489
2490 #ifdef DEBUG
2491 /* Set up the fwcon timer */
2492 timer_setup(&devinfo->timer, brcmf_pcie_fwcon, 0);
2493 #endif
2494
2495 fwreq = brcmf_pcie_prepare_fw_request(devinfo);
2496 if (!fwreq) {
2497 ret = -ENOMEM;
2498 goto fail_brcmf;
2499 }
2500
2501 ret = brcmf_fw_get_firmwares(bus->dev, fwreq, brcmf_pcie_setup);
2502 if (ret < 0) {
2503 kfree(fwreq);
2504 goto fail_brcmf;
2505 }
2506 return 0;
2507
2508 fail_brcmf:
2509 brcmf_free(&devinfo->pdev->dev);
2510 fail_bus:
2511 kfree(bus->msgbuf);
2512 kfree(bus);
2513 fail:
2514 brcmf_err(NULL, "failed %x:%x\n", pdev->vendor, pdev->device);
2515 brcmf_pcie_release_resource(devinfo);
2516 if (devinfo->ci)
2517 brcmf_chip_detach(devinfo->ci);
2518 if (devinfo->settings)
2519 brcmf_release_module_param(devinfo->settings);
2520 kfree(pcie_bus_dev);
2521 kfree(devinfo);
2522 return ret;
2523 }
2524
2525
2526 static void
brcmf_pcie_remove(struct pci_dev * pdev)2527 brcmf_pcie_remove(struct pci_dev *pdev)
2528 {
2529 struct brcmf_pciedev_info *devinfo;
2530 struct brcmf_bus *bus;
2531
2532 brcmf_dbg(PCIE, "Enter\n");
2533
2534 bus = dev_get_drvdata(&pdev->dev);
2535 if (bus == NULL)
2536 return;
2537
2538 devinfo = bus->bus_priv.pcie->devinfo;
2539 brcmf_pcie_bus_console_read(devinfo, false);
2540 brcmf_pcie_fwcon_timer(devinfo, false);
2541
2542 devinfo->state = BRCMFMAC_PCIE_STATE_DOWN;
2543 if (devinfo->ci)
2544 brcmf_pcie_intr_disable(devinfo);
2545
2546 brcmf_detach(&pdev->dev);
2547 brcmf_free(&pdev->dev);
2548
2549 kfree(bus->bus_priv.pcie);
2550 kfree(bus->msgbuf->flowrings);
2551 kfree(bus->msgbuf);
2552 kfree(bus);
2553
2554 brcmf_pcie_release_irq(devinfo);
2555 brcmf_pcie_release_scratchbuffers(devinfo);
2556 brcmf_pcie_release_ringbuffers(devinfo);
2557 brcmf_pcie_reset_device(devinfo);
2558 brcmf_pcie_release_resource(devinfo);
2559 release_firmware(devinfo->clm_fw);
2560 release_firmware(devinfo->txcap_fw);
2561
2562 if (devinfo->ci)
2563 brcmf_chip_detach(devinfo->ci);
2564 if (devinfo->settings)
2565 brcmf_release_module_param(devinfo->settings);
2566
2567 kfree(devinfo);
2568 dev_set_drvdata(&pdev->dev, NULL);
2569 }
2570
2571
2572 #ifdef CONFIG_PM
2573
2574
brcmf_pcie_pm_enter_D3(struct device * dev)2575 static int brcmf_pcie_pm_enter_D3(struct device *dev)
2576 {
2577 struct brcmf_pciedev_info *devinfo;
2578 struct brcmf_bus *bus;
2579
2580 brcmf_dbg(PCIE, "Enter\n");
2581
2582 bus = dev_get_drvdata(dev);
2583 devinfo = bus->bus_priv.pcie->devinfo;
2584
2585 brcmf_pcie_fwcon_timer(devinfo, false);
2586 brcmf_bus_change_state(bus, BRCMF_BUS_DOWN);
2587
2588 devinfo->mbdata_completed = false;
2589 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D3_INFORM);
2590
2591 wait_event_timeout(devinfo->mbdata_resp_wait, devinfo->mbdata_completed,
2592 BRCMF_PCIE_MBDATA_TIMEOUT);
2593 if (!devinfo->mbdata_completed) {
2594 brcmf_err(bus, "Timeout on response for entering D3 substate\n");
2595 brcmf_bus_change_state(bus, BRCMF_BUS_UP);
2596 return -EIO;
2597 }
2598
2599 devinfo->state = BRCMFMAC_PCIE_STATE_DOWN;
2600
2601 return 0;
2602 }
2603
2604
brcmf_pcie_pm_leave_D3(struct device * dev)2605 static int brcmf_pcie_pm_leave_D3(struct device *dev)
2606 {
2607 struct brcmf_pciedev_info *devinfo;
2608 struct brcmf_bus *bus;
2609 struct pci_dev *pdev;
2610 int err;
2611
2612 brcmf_dbg(PCIE, "Enter\n");
2613
2614 bus = dev_get_drvdata(dev);
2615 devinfo = bus->bus_priv.pcie->devinfo;
2616 brcmf_dbg(PCIE, "Enter, dev=%p, bus=%p\n", dev, bus);
2617
2618 /* Check if device is still up and running, if so we are ready */
2619 if (brcmf_pcie_read_reg32(devinfo, devinfo->reginfo->intmask) != 0) {
2620 brcmf_dbg(PCIE, "Try to wakeup device....\n");
2621 if (brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D0_INFORM))
2622 goto cleanup;
2623 brcmf_dbg(PCIE, "Hot resume, continue....\n");
2624 devinfo->state = BRCMFMAC_PCIE_STATE_UP;
2625 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
2626 brcmf_bus_change_state(bus, BRCMF_BUS_UP);
2627 brcmf_pcie_intr_enable(devinfo);
2628 brcmf_pcie_hostready(devinfo);
2629 brcmf_pcie_fwcon_timer(devinfo, true);
2630 return 0;
2631 }
2632
2633 cleanup:
2634 brcmf_chip_detach(devinfo->ci);
2635 devinfo->ci = NULL;
2636 pdev = devinfo->pdev;
2637 brcmf_pcie_remove(pdev);
2638
2639 err = brcmf_pcie_probe(pdev, NULL);
2640 if (err)
2641 __brcmf_err(NULL, __func__, "probe after resume failed, err=%d\n", err);
2642
2643 return err;
2644 }
2645
2646
2647 static const struct dev_pm_ops brcmf_pciedrvr_pm = {
2648 .suspend = brcmf_pcie_pm_enter_D3,
2649 .resume = brcmf_pcie_pm_leave_D3,
2650 .freeze = brcmf_pcie_pm_enter_D3,
2651 .restore = brcmf_pcie_pm_leave_D3,
2652 };
2653
2654
2655 #endif /* CONFIG_PM */
2656
2657
2658 #define BRCMF_PCIE_DEVICE(dev_id, fw_vend) \
2659 { \
2660 BRCM_PCIE_VENDOR_ID_BROADCOM, (dev_id), \
2661 PCI_ANY_ID, PCI_ANY_ID, \
2662 PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, \
2663 BRCMF_FWVENDOR_ ## fw_vend \
2664 }
2665 #define BRCMF_PCIE_DEVICE_SUB(dev_id, subvend, subdev, fw_vend) \
2666 { \
2667 BRCM_PCIE_VENDOR_ID_BROADCOM, (dev_id), \
2668 (subvend), (subdev), \
2669 PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, \
2670 BRCMF_FWVENDOR_ ## fw_vend \
2671 }
2672
2673 static const struct pci_device_id brcmf_pcie_devid_table[] = {
2674 BRCMF_PCIE_DEVICE(BRCM_PCIE_4350_DEVICE_ID, WCC),
2675 BRCMF_PCIE_DEVICE_SUB(0x4355, BRCM_PCIE_VENDOR_ID_BROADCOM, 0x4355, WCC),
2676 BRCMF_PCIE_DEVICE(BRCM_PCIE_4354_RAW_DEVICE_ID, WCC),
2677 BRCMF_PCIE_DEVICE(BRCM_PCIE_4355_DEVICE_ID, WCC),
2678 BRCMF_PCIE_DEVICE(BRCM_PCIE_4356_DEVICE_ID, WCC),
2679 BRCMF_PCIE_DEVICE(BRCM_PCIE_43567_DEVICE_ID, WCC),
2680 BRCMF_PCIE_DEVICE(BRCM_PCIE_43570_DEVICE_ID, WCC),
2681 BRCMF_PCIE_DEVICE(BRCM_PCIE_43570_RAW_DEVICE_ID, WCC),
2682 BRCMF_PCIE_DEVICE(BRCM_PCIE_4358_DEVICE_ID, WCC),
2683 BRCMF_PCIE_DEVICE(BRCM_PCIE_4359_DEVICE_ID, WCC),
2684 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_DEVICE_ID, WCC),
2685 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_2G_DEVICE_ID, WCC),
2686 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_5G_DEVICE_ID, WCC),
2687 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_RAW_DEVICE_ID, WCC),
2688 BRCMF_PCIE_DEVICE(BRCM_PCIE_4364_DEVICE_ID, WCC),
2689 BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_DEVICE_ID, BCA),
2690 BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_2G_DEVICE_ID, BCA),
2691 BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_5G_DEVICE_ID, BCA),
2692 BRCMF_PCIE_DEVICE_SUB(0x4365, BRCM_PCIE_VENDOR_ID_BROADCOM, 0x4365, BCA),
2693 BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_DEVICE_ID, BCA),
2694 BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_2G_DEVICE_ID, BCA),
2695 BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_5G_DEVICE_ID, BCA),
2696 BRCMF_PCIE_DEVICE(BRCM_PCIE_4371_DEVICE_ID, WCC),
2697 BRCMF_PCIE_DEVICE(BRCM_PCIE_43596_DEVICE_ID, CYW),
2698 BRCMF_PCIE_DEVICE(BRCM_PCIE_4377_DEVICE_ID, WCC),
2699 BRCMF_PCIE_DEVICE(BRCM_PCIE_4378_DEVICE_ID, WCC),
2700 BRCMF_PCIE_DEVICE(BRCM_PCIE_4387_DEVICE_ID, WCC),
2701
2702 { /* end: all zeroes */ }
2703 };
2704
2705
2706 MODULE_DEVICE_TABLE(pci, brcmf_pcie_devid_table);
2707
2708
2709 static struct pci_driver brcmf_pciedrvr = {
2710 .name = KBUILD_MODNAME,
2711 .id_table = brcmf_pcie_devid_table,
2712 .probe = brcmf_pcie_probe,
2713 .remove = brcmf_pcie_remove,
2714 #ifdef CONFIG_PM
2715 .driver.pm = &brcmf_pciedrvr_pm,
2716 #endif
2717 .driver.coredump = brcmf_dev_coredump,
2718 };
2719
2720
brcmf_pcie_register(void)2721 int brcmf_pcie_register(void)
2722 {
2723 brcmf_dbg(PCIE, "Enter\n");
2724 return pci_register_driver(&brcmf_pciedrvr);
2725 }
2726
2727
brcmf_pcie_exit(void)2728 void brcmf_pcie_exit(void)
2729 {
2730 brcmf_dbg(PCIE, "Enter\n");
2731 pci_unregister_driver(&brcmf_pciedrvr);
2732 }
2733