xref: /linux/drivers/clk/mxs/clk-imx23.c (revision 75bf465f0bc33e9b776a46d6a1b9b990f5fb7c37)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Copyright 2012 Freescale Semiconductor, Inc.
4  */
5 
6 #include <linux/clk/mxs.h>
7 #include <linux/clk.h>
8 #include <linux/clk-provider.h>
9 #include <linux/err.h>
10 #include <linux/init.h>
11 #include <linux/io.h>
12 #include <linux/of.h>
13 #include <linux/of_address.h>
14 #include "clk.h"
15 
16 static void __iomem *clkctrl;
17 static void __iomem *digctrl;
18 
19 #define CLKCTRL clkctrl
20 #define DIGCTRL digctrl
21 
22 #define PLLCTRL0		(CLKCTRL + 0x0000)
23 #define CPU			(CLKCTRL + 0x0020)
24 #define HBUS			(CLKCTRL + 0x0030)
25 #define XBUS			(CLKCTRL + 0x0040)
26 #define XTAL			(CLKCTRL + 0x0050)
27 #define PIX			(CLKCTRL + 0x0060)
28 #define SSP			(CLKCTRL + 0x0070)
29 #define GPMI			(CLKCTRL + 0x0080)
30 #define SPDIF			(CLKCTRL + 0x0090)
31 #define EMI			(CLKCTRL + 0x00a0)
32 #define SAIF			(CLKCTRL + 0x00c0)
33 #define TV			(CLKCTRL + 0x00d0)
34 #define ETM			(CLKCTRL + 0x00e0)
35 #define FRAC			(CLKCTRL + 0x00f0)
36 #define CLKSEQ			(CLKCTRL + 0x0110)
37 
38 #define BP_CPU_INTERRUPT_WAIT	12
39 #define BP_CLKSEQ_BYPASS_SAIF	0
40 #define BP_CLKSEQ_BYPASS_SSP	5
41 #define BP_SAIF_DIV_FRAC_EN	16
42 #define BP_FRAC_IOFRAC		24
43 
clk_misc_init(void)44 static void __init clk_misc_init(void)
45 {
46 	u32 val;
47 
48 	/* Gate off cpu clock in WFI for power saving */
49 	writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET);
50 
51 	/* Clear BYPASS for SAIF */
52 	writel_relaxed(1 << BP_CLKSEQ_BYPASS_SAIF, CLKSEQ + CLR);
53 
54 	/* SAIF has to use frac div for functional operation */
55 	val = readl_relaxed(SAIF);
56 	val |= 1 << BP_SAIF_DIV_FRAC_EN;
57 	writel_relaxed(val, SAIF);
58 
59 	/*
60 	 * Source ssp clock from ref_io than ref_xtal,
61 	 * as ref_xtal only provides 24 MHz as maximum.
62 	 */
63 	writel_relaxed(1 << BP_CLKSEQ_BYPASS_SSP, CLKSEQ + CLR);
64 
65 	/*
66 	 * 480 MHz seems too high to be ssp clock source directly,
67 	 * so set frac to get a 288 MHz ref_io.
68 	 */
69 	writel_relaxed(0x3f << BP_FRAC_IOFRAC, FRAC + CLR);
70 	writel_relaxed(30 << BP_FRAC_IOFRAC, FRAC + SET);
71 }
72 
73 static const char *const sel_pll[]  __initconst = { "pll", "ref_xtal", };
74 static const char *const sel_cpu[]  __initconst = { "ref_cpu", "ref_xtal", };
75 static const char *const sel_pix[]  __initconst = { "ref_pix", "ref_xtal", };
76 static const char *const sel_io[]   __initconst = { "ref_io", "ref_xtal", };
77 static const char *const cpu_sels[] __initconst = { "cpu_pll", "cpu_xtal", };
78 static const char *const emi_sels[] __initconst = { "emi_pll", "emi_xtal", };
79 
80 enum imx23_clk {
81 	ref_xtal, pll, ref_cpu, ref_emi, ref_pix, ref_io, saif_sel,
82 	lcdif_sel, gpmi_sel, ssp_sel, emi_sel, cpu, etm_sel, cpu_pll,
83 	cpu_xtal, hbus, xbus, lcdif_div, ssp_div, gpmi_div, emi_pll,
84 	emi_xtal, etm_div, saif_div, clk32k_div, rtc, adc, spdif_div,
85 	clk32k, dri, pwm, filt, uart, ssp, gpmi, spdif, emi, saif,
86 	lcdif, etm, usb, usb_phy,
87 	clk_max
88 };
89 
90 static struct clk *clks[clk_max];
91 static struct clk_onecell_data clk_data;
92 
93 static enum imx23_clk clks_init_on[] __initdata = {
94 	cpu, hbus, xbus, emi, uart,
95 };
96 
mx23_clocks_init(struct device_node * np)97 static void __init mx23_clocks_init(struct device_node *np)
98 {
99 	struct device_node *dcnp;
100 	u32 i;
101 
102 	dcnp = of_find_compatible_node(NULL, NULL, "fsl,imx23-digctl");
103 	digctrl = of_iomap(dcnp, 0);
104 	WARN_ON(!digctrl);
105 	of_node_put(dcnp);
106 
107 	clkctrl = of_iomap(np, 0);
108 	WARN_ON(!clkctrl);
109 
110 	clk_misc_init();
111 
112 	clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000);
113 	clks[pll] = mxs_clk_pll("pll", "ref_xtal", PLLCTRL0, 16, 480000000);
114 	clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll", FRAC, 0);
115 	clks[ref_emi] = mxs_clk_ref("ref_emi", "pll", FRAC, 1);
116 	clks[ref_pix] = mxs_clk_ref("ref_pix", "pll", FRAC, 2);
117 	clks[ref_io] = mxs_clk_ref("ref_io", "pll", FRAC, 3);
118 	clks[saif_sel] = mxs_clk_mux("saif_sel", CLKSEQ, 0, 1, sel_pll, ARRAY_SIZE(sel_pll));
119 	clks[lcdif_sel] = mxs_clk_mux("lcdif_sel", CLKSEQ, 1, 1, sel_pix, ARRAY_SIZE(sel_pix));
120 	clks[gpmi_sel] = mxs_clk_mux("gpmi_sel", CLKSEQ, 4, 1, sel_io, ARRAY_SIZE(sel_io));
121 	clks[ssp_sel] = mxs_clk_mux("ssp_sel", CLKSEQ, 5, 1, sel_io, ARRAY_SIZE(sel_io));
122 	clks[emi_sel] = mxs_clk_mux("emi_sel", CLKSEQ, 6, 1, emi_sels, ARRAY_SIZE(emi_sels));
123 	clks[cpu] = mxs_clk_mux("cpu", CLKSEQ, 7, 1, cpu_sels, ARRAY_SIZE(cpu_sels));
124 	clks[etm_sel] = mxs_clk_mux("etm_sel", CLKSEQ, 8, 1, sel_cpu, ARRAY_SIZE(sel_cpu));
125 	clks[cpu_pll] = mxs_clk_div("cpu_pll", "ref_cpu", CPU, 0, 6, 28);
126 	clks[cpu_xtal] = mxs_clk_div("cpu_xtal", "ref_xtal", CPU, 16, 10, 29);
127 	clks[hbus] = mxs_clk_div("hbus", "cpu", HBUS, 0, 5, 29);
128 	clks[xbus] = mxs_clk_div("xbus", "ref_xtal", XBUS, 0, 10, 31);
129 	clks[lcdif_div] = mxs_clk_div("lcdif_div", "lcdif_sel", PIX, 0, 12, 29);
130 	clks[ssp_div] = mxs_clk_div("ssp_div", "ssp_sel", SSP, 0, 9, 29);
131 	clks[gpmi_div] = mxs_clk_div("gpmi_div", "gpmi_sel", GPMI, 0, 10, 29);
132 	clks[emi_pll] = mxs_clk_div("emi_pll", "ref_emi", EMI, 0, 6, 28);
133 	clks[emi_xtal] = mxs_clk_div("emi_xtal", "ref_xtal", EMI, 8, 4, 29);
134 	clks[etm_div] = mxs_clk_div("etm_div", "etm_sel", ETM, 0, 6, 29);
135 	clks[saif_div] = mxs_clk_frac("saif_div", "saif_sel", SAIF, 0, 16, 29);
136 	clks[clk32k_div] = mxs_clk_fixed_factor("clk32k_div", "ref_xtal", 1, 750);
137 	clks[rtc] = mxs_clk_fixed_factor("rtc", "ref_xtal", 1, 768);
138 	clks[adc] = mxs_clk_fixed_factor("adc", "clk32k", 1, 16);
139 	clks[spdif_div] = mxs_clk_fixed_factor("spdif_div", "pll", 1, 4);
140 	clks[clk32k] = mxs_clk_gate("clk32k", "clk32k_div", XTAL, 26);
141 	clks[dri] = mxs_clk_gate("dri", "ref_xtal", XTAL, 28);
142 	clks[pwm] = mxs_clk_gate("pwm", "ref_xtal", XTAL, 29);
143 	clks[filt] = mxs_clk_gate("filt", "ref_xtal", XTAL, 30);
144 	clks[uart] = mxs_clk_gate("uart", "ref_xtal", XTAL, 31);
145 	clks[ssp] = mxs_clk_gate("ssp", "ssp_div", SSP, 31);
146 	clks[gpmi] = mxs_clk_gate("gpmi", "gpmi_div", GPMI, 31);
147 	clks[spdif] = mxs_clk_gate("spdif", "spdif_div", SPDIF, 31);
148 	clks[emi] = mxs_clk_gate("emi", "emi_sel", EMI, 31);
149 	clks[saif] = mxs_clk_gate("saif", "saif_div", SAIF, 31);
150 	clks[lcdif] = mxs_clk_gate("lcdif", "lcdif_div", PIX, 31);
151 	clks[etm] = mxs_clk_gate("etm", "etm_div", ETM, 31);
152 	clks[usb] = mxs_clk_gate("usb", "usb_phy", DIGCTRL, 2);
153 	clks[usb_phy] = clk_register_gate(NULL, "usb_phy", "pll", 0, PLLCTRL0, 18, 0, &mxs_lock);
154 
155 	for (i = 0; i < ARRAY_SIZE(clks); i++)
156 		if (IS_ERR(clks[i])) {
157 			pr_err("i.MX23 clk %d: register failed with %ld\n",
158 				i, PTR_ERR(clks[i]));
159 			return;
160 		}
161 
162 	clk_data.clks = clks;
163 	clk_data.clk_num = ARRAY_SIZE(clks);
164 	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
165 
166 	for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
167 		clk_prepare_enable(clks[clks_init_on[i]]);
168 
169 }
170 CLK_OF_DECLARE(imx23_clkctrl, "fsl,imx23-clkctrl", mx23_clocks_init);
171