1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Copyright (c) 2014 MundoReader S.L.
4 * Author: Heiko Stuebner <heiko@sntech.de>
5 *
6 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
7 * Author: Xing Zheng <zhengxing@rock-chips.com>
8 *
9 * based on
10 *
11 * samsung/clk.h
12 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
13 * Copyright (c) 2013 Linaro Ltd.
14 * Author: Thomas Abraham <thomas.ab@samsung.com>
15 */
16
17 #ifndef CLK_ROCKCHIP_CLK_H
18 #define CLK_ROCKCHIP_CLK_H
19
20 #include <linux/io.h>
21 #include <linux/clk-provider.h>
22 #include <linux/hashtable.h>
23
24 struct clk;
25
26 #define HIWORD_UPDATE(val, mask, shift) \
27 ((val) << (shift) | (mask) << ((shift) + 16))
28
29 /* register positions shared by PX30, RV1108, RK2928, RK3036, RK3066, RK3188 and RK3228 */
30 #define BOOST_PLL_H_CON(x) ((x) * 0x4)
31 #define BOOST_CLK_CON 0x0008
32 #define BOOST_BOOST_CON 0x000c
33 #define BOOST_SWITCH_CNT 0x0010
34 #define BOOST_HIGH_PERF_CNT0 0x0014
35 #define BOOST_HIGH_PERF_CNT1 0x0018
36 #define BOOST_STATIS_THRESHOLD 0x001c
37 #define BOOST_SHORT_SWITCH_CNT 0x0020
38 #define BOOST_SWITCH_THRESHOLD 0x0024
39 #define BOOST_FSM_STATUS 0x0028
40 #define BOOST_PLL_L_CON(x) ((x) * 0x4 + 0x2c)
41 #define BOOST_RECOVERY_MASK 0x1
42 #define BOOST_RECOVERY_SHIFT 1
43 #define BOOST_SW_CTRL_MASK 0x1
44 #define BOOST_SW_CTRL_SHIFT 2
45 #define BOOST_LOW_FREQ_EN_MASK 0x1
46 #define BOOST_LOW_FREQ_EN_SHIFT 3
47 #define BOOST_BUSY_STATE BIT(8)
48
49 #define PX30_PLL_CON(x) ((x) * 0x4)
50 #define PX30_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
51 #define PX30_CLKGATE_CON(x) ((x) * 0x4 + 0x200)
52 #define PX30_GLB_SRST_FST 0xb8
53 #define PX30_GLB_SRST_SND 0xbc
54 #define PX30_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
55 #define PX30_MODE_CON 0xa0
56 #define PX30_MISC_CON 0xa4
57 #define PX30_SDMMC_CON0 0x380
58 #define PX30_SDMMC_CON1 0x384
59 #define PX30_SDIO_CON0 0x388
60 #define PX30_SDIO_CON1 0x38c
61 #define PX30_EMMC_CON0 0x390
62 #define PX30_EMMC_CON1 0x394
63
64 #define PX30_PMU_PLL_CON(x) ((x) * 0x4)
65 #define PX30_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x40)
66 #define PX30_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x80)
67 #define PX30_PMU_MODE 0x0020
68
69 #define RV1108_PLL_CON(x) ((x) * 0x4)
70 #define RV1108_CLKSEL_CON(x) ((x) * 0x4 + 0x60)
71 #define RV1108_CLKGATE_CON(x) ((x) * 0x4 + 0x120)
72 #define RV1108_SOFTRST_CON(x) ((x) * 0x4 + 0x180)
73 #define RV1108_GLB_SRST_FST 0x1c0
74 #define RV1108_GLB_SRST_SND 0x1c4
75 #define RV1108_MISC_CON 0x1cc
76 #define RV1108_SDMMC_CON0 0x1d8
77 #define RV1108_SDMMC_CON1 0x1dc
78 #define RV1108_SDIO_CON0 0x1e0
79 #define RV1108_SDIO_CON1 0x1e4
80 #define RV1108_EMMC_CON0 0x1e8
81 #define RV1108_EMMC_CON1 0x1ec
82
83 #define RV1126_PMU_MODE 0x0
84 #define RV1126_PMU_PLL_CON(x) ((x) * 0x4 + 0x10)
85 #define RV1126_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
86 #define RV1126_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x180)
87 #define RV1126_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x200)
88 #define RV1126_PLL_CON(x) ((x) * 0x4)
89 #define RV1126_MODE_CON 0x90
90 #define RV1126_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
91 #define RV1126_CLKGATE_CON(x) ((x) * 0x4 + 0x280)
92 #define RV1126_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
93 #define RV1126_GLB_SRST_FST 0x408
94 #define RV1126_GLB_SRST_SND 0x40c
95 #define RV1126_SDMMC_CON0 0x440
96 #define RV1126_SDMMC_CON1 0x444
97 #define RV1126_SDIO_CON0 0x448
98 #define RV1126_SDIO_CON1 0x44c
99 #define RV1126_EMMC_CON0 0x450
100 #define RV1126_EMMC_CON1 0x454
101
102 #define RV1126B_TOPCRU_BASE 0x0
103 #define RV1126B_BUSCRU_BASE 0x10000
104 #define RV1126B_PERICRU_BASE 0x20000
105 #define RV1126B_CORECRU_BASE 0x30000
106 #define RV1126B_PMUCRU_BASE 0x40000
107 #define RV1126B_PMU1CRU_BASE 0x50000
108 #define RV1126B_DDRCRU_BASE 0x60000
109 #define RV1126B_SUBDDRCRU_BASE 0x68000
110 #define RV1126B_VICRU_BASE 0x70000
111 #define RV1126B_VEPUCRU_BASE 0x80000
112 #define RV1126B_NPUCRU_BASE 0x90000
113 #define RV1126B_VDOCRU_BASE 0xA0000
114 #define RV1126B_VCPCRU_BASE 0xB0000
115
116 #define RV1126B_PLL_CON(x) ((x) * 0x4 + RV1126B_TOPCRU_BASE)
117 #define RV1126B_MODE_CON (0x280 + RV1126B_TOPCRU_BASE)
118 #define RV1126B_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_TOPCRU_BASE)
119 #define RV1126B_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_TOPCRU_BASE)
120 #define RV1126B_SOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_TOPCRU_BASE)
121 #define RV1126B_GLB_SRST_FST (0xc08 + RV1126B_TOPCRU_BASE)
122 #define RV1126B_GLB_SRST_SND (0xc0c + RV1126B_TOPCRU_BASE)
123 #define RV1126B_CLK_CM_FRAC0_DIV_H (0xcc0 + RV1126B_TOPCRU_BASE)
124 #define RV1126B_CLK_CM_FRAC1_DIV_H (0xcc4 + RV1126B_TOPCRU_BASE)
125 #define RV1126B_CLK_CM_FRAC2_DIV_H (0xcc8 + RV1126B_TOPCRU_BASE)
126 #define RV1126B_CLK_UART_FRAC0_DIV_H (0xccc + RV1126B_TOPCRU_BASE)
127 #define RV1126B_CLK_UART_FRAC1_DIV_H (0xcd0 + RV1126B_TOPCRU_BASE)
128 #define RV1126B_CLK_AUDIO_FRAC0_DIV_H (0xcd4 + RV1126B_TOPCRU_BASE)
129 #define RV1126B_CLK_AUDIO_FRAC1_DIV_H (0xcd8 + RV1126B_TOPCRU_BASE)
130 #define RV1126B_BUSCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_BUSCRU_BASE)
131 #define RV1126B_BUSCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_BUSCRU_BASE)
132 #define RV1126B_BUSSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_BUSCRU_BASE)
133 #define RV1126B_PERIPLL_CON(x) ((x) * 0x4 + RV1126B_PERICRU_BASE)
134 #define RV1126B_PERICLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_PERICRU_BASE)
135 #define RV1126B_PERICLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_PERICRU_BASE)
136 #define RV1126B_PERISOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_PERICRU_BASE)
137 #define RV1126B_CORECLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_CORECRU_BASE)
138 #define RV1126B_CORECLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_CORECRU_BASE)
139 #define RV1126B_CORESOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_CORECRU_BASE)
140 #define RV1126B_PMUCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_PMUCRU_BASE)
141 #define RV1126B_PMUCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_PMUCRU_BASE)
142 #define RV1126B_PMUSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_PMUCRU_BASE)
143 #define RV1126B_PMU1CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_PMU1CRU_BASE)
144 #define RV1126B_PMU1CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_PMU1CRU_BASE)
145 #define RV1126B_PMU1SOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_PMU1CRU_BASE)
146 #define RV1126B_DDRCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_DDRCRU_BASE)
147 #define RV1126B_DDRCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_DDRCRU_BASE)
148 #define RV1126B_DDRSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_DDRCRU_BASE)
149 #define RV1126B_SUBDDRPLL_CON(x) ((x) * 0x4 + RV1126B_SUBDDRCRU_BASE)
150 #define RV1126B_SUBDDRCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_SUBDDRCRU_BASE)
151 #define RV1126B_SUBDDRCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_SUBDDRCRU_BASE)
152 #define RV1126B_SUBDDRSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_SUBDDRCRU_BASE)
153 #define RV1126B_VICLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_VICRU_BASE)
154 #define RV1126B_VICLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_VICRU_BASE)
155 #define RV1126B_VISOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_VICRU_BASE)
156 #define RV1126B_VEPUCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_VEPUCRU_BASE)
157 #define RV1126B_VEPUCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_VEPUCRU_BASE)
158 #define RV1126B_VEPUSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_VEPUCRU_BASE)
159 #define RV1126B_NPUCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_NPUCRU_BASE)
160 #define RV1126B_NPUCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_NPUCRU_BASE)
161 #define RV1126B_NPUSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_NPUCRU_BASE)
162 #define RV1126B_VDOCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_VDOCRU_BASE)
163 #define RV1126B_VDOCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_VDOCRU_BASE)
164 #define RV1126B_VDOSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_VDOCRU_BASE)
165 #define RV1126B_VCPCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_VCPCRU_BASE)
166 #define RV1126B_VCPCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_VCPCRU_BASE)
167 #define RV1126B_VCPSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_VCPCRU_BASE)
168
169 #define RK2928_PLL_CON(x) ((x) * 0x4)
170 #define RK2928_MODE_CON 0x40
171 #define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44)
172 #define RK2928_CLKGATE_CON(x) ((x) * 0x4 + 0xd0)
173 #define RK2928_GLB_SRST_FST 0x100
174 #define RK2928_GLB_SRST_SND 0x104
175 #define RK2928_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
176 #define RK2928_MISC_CON 0x134
177
178 #define RK3036_SDMMC_CON0 0x144
179 #define RK3036_SDMMC_CON1 0x148
180 #define RK3036_SDIO_CON0 0x14c
181 #define RK3036_SDIO_CON1 0x150
182 #define RK3036_EMMC_CON0 0x154
183 #define RK3036_EMMC_CON1 0x158
184
185 #define RK3228_GLB_SRST_FST 0x1f0
186 #define RK3228_GLB_SRST_SND 0x1f4
187 #define RK3228_SDMMC_CON0 0x1c0
188 #define RK3228_SDMMC_CON1 0x1c4
189 #define RK3228_SDIO_CON0 0x1c8
190 #define RK3228_SDIO_CON1 0x1cc
191 #define RK3228_EMMC_CON0 0x1d8
192 #define RK3228_EMMC_CON1 0x1dc
193
194 #define RK3288_PLL_CON(x) RK2928_PLL_CON(x)
195 #define RK3288_MODE_CON 0x50
196 #define RK3288_CLKSEL_CON(x) ((x) * 0x4 + 0x60)
197 #define RK3288_CLKGATE_CON(x) ((x) * 0x4 + 0x160)
198 #define RK3288_GLB_SRST_FST 0x1b0
199 #define RK3288_GLB_SRST_SND 0x1b4
200 #define RK3288_SOFTRST_CON(x) ((x) * 0x4 + 0x1b8)
201 #define RK3288_MISC_CON 0x1e8
202 #define RK3288_SDMMC_CON0 0x200
203 #define RK3288_SDMMC_CON1 0x204
204 #define RK3288_SDIO0_CON0 0x208
205 #define RK3288_SDIO0_CON1 0x20c
206 #define RK3288_SDIO1_CON0 0x210
207 #define RK3288_SDIO1_CON1 0x214
208 #define RK3288_EMMC_CON0 0x218
209 #define RK3288_EMMC_CON1 0x21c
210
211 #define RK3308_PLL_CON(x) RK2928_PLL_CON(x)
212 #define RK3308_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
213 #define RK3308_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
214 #define RK3308_GLB_SRST_FST 0xb8
215 #define RK3308_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
216 #define RK3308_MODE_CON 0xa0
217 #define RK3308_SDMMC_CON0 0x480
218 #define RK3308_SDMMC_CON1 0x484
219 #define RK3308_SDIO_CON0 0x488
220 #define RK3308_SDIO_CON1 0x48c
221 #define RK3308_EMMC_CON0 0x490
222 #define RK3308_EMMC_CON1 0x494
223
224 #define RK3328_PLL_CON(x) RK2928_PLL_CON(x)
225 #define RK3328_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
226 #define RK3328_CLKGATE_CON(x) ((x) * 0x4 + 0x200)
227 #define RK3328_GRFCLKSEL_CON(x) ((x) * 0x4 + 0x100)
228 #define RK3328_GLB_SRST_FST 0x9c
229 #define RK3328_GLB_SRST_SND 0x98
230 #define RK3328_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
231 #define RK3328_MODE_CON 0x80
232 #define RK3328_MISC_CON 0x84
233 #define RK3328_SDMMC_CON0 0x380
234 #define RK3328_SDMMC_CON1 0x384
235 #define RK3328_SDIO_CON0 0x388
236 #define RK3328_SDIO_CON1 0x38c
237 #define RK3328_EMMC_CON0 0x390
238 #define RK3328_EMMC_CON1 0x394
239 #define RK3328_SDMMC_EXT_CON0 0x398
240 #define RK3328_SDMMC_EXT_CON1 0x39C
241
242 #define RK3368_PLL_CON(x) RK2928_PLL_CON(x)
243 #define RK3368_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
244 #define RK3368_CLKGATE_CON(x) ((x) * 0x4 + 0x200)
245 #define RK3368_GLB_SRST_FST 0x280
246 #define RK3368_GLB_SRST_SND 0x284
247 #define RK3368_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
248 #define RK3368_MISC_CON 0x380
249 #define RK3368_SDMMC_CON0 0x400
250 #define RK3368_SDMMC_CON1 0x404
251 #define RK3368_SDIO0_CON0 0x408
252 #define RK3368_SDIO0_CON1 0x40c
253 #define RK3368_SDIO1_CON0 0x410
254 #define RK3368_SDIO1_CON1 0x414
255 #define RK3368_EMMC_CON0 0x418
256 #define RK3368_EMMC_CON1 0x41c
257
258 #define RK3399_PLL_CON(x) RK2928_PLL_CON(x)
259 #define RK3399_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
260 #define RK3399_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
261 #define RK3399_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
262 #define RK3399_GLB_SRST_FST 0x500
263 #define RK3399_GLB_SRST_SND 0x504
264 #define RK3399_GLB_CNT_TH 0x508
265 #define RK3399_MISC_CON 0x50c
266 #define RK3399_RST_CON 0x510
267 #define RK3399_RST_ST 0x514
268 #define RK3399_SDMMC_CON0 0x580
269 #define RK3399_SDMMC_CON1 0x584
270 #define RK3399_SDIO_CON0 0x588
271 #define RK3399_SDIO_CON1 0x58c
272
273 #define RK3399_PMU_PLL_CON(x) RK2928_PLL_CON(x)
274 #define RK3399_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x80)
275 #define RK3399_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x100)
276 #define RK3399_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
277
278 #define RK3506_PMU_CRU_BASE 0x10000
279 #define RK3506_PLL_CON(x) ((x) * 0x4 + RK3506_PMU_CRU_BASE)
280 #define RK3506_CLKSEL_CON(x) ((x) * 0x4 + 0x300)
281 #define RK3506_CLKGATE_CON(x) ((x) * 0x4 + 0x800)
282 #define RK3506_SOFTRST_CON(x) ((x) * 0x4 + 0xa00)
283 #define RK3506_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3506_PMU_CRU_BASE)
284 #define RK3506_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3506_PMU_CRU_BASE)
285 #define RK3506_MODE_CON 0x280
286 #define RK3506_GLB_CNT_TH 0xc00
287 #define RK3506_GLB_SRST_FST 0xc08
288 #define RK3506_GLB_SRST_SND 0xc0c
289
290 #define RK3528_PMU_CRU_BASE 0x10000
291 #define RK3528_PCIE_CRU_BASE 0x20000
292 #define RK3528_DDRPHY_CRU_BASE 0x28000
293 #define RK3528_PLL_CON(x) RK2928_PLL_CON(x)
294 #define RK3528_PCIE_PLL_CON(x) ((x) * 0x4 + RK3528_PCIE_CRU_BASE)
295 #define RK3528_DDRPHY_PLL_CON(x) ((x) * 0x4 + RK3528_DDRPHY_CRU_BASE)
296 #define RK3528_MODE_CON 0x280
297 #define RK3528_CLKSEL_CON(x) ((x) * 0x4 + 0x300)
298 #define RK3528_CLKGATE_CON(x) ((x) * 0x4 + 0x800)
299 #define RK3528_SOFTRST_CON(x) ((x) * 0x4 + 0xa00)
300 #define RK3528_SDMMC_CON(x) ((x) * 0x4 + 0x24)
301 #define RK3528_SDIO0_CON(x) ((x) * 0x4 + 0x4)
302 #define RK3528_SDIO1_CON(x) ((x) * 0x4 + 0xc)
303 #define RK3528_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PMU_CRU_BASE)
304 #define RK3528_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_PMU_CRU_BASE)
305 #define RK3528_PCIE_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PCIE_CRU_BASE)
306 #define RK3528_PCIE_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_PCIE_CRU_BASE)
307 #define RK3528_DDRPHY_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_DDRPHY_CRU_BASE)
308 #define RK3528_DDRPHY_MODE_CON (0x280 + RK3528_DDRPHY_CRU_BASE)
309 #define RK3528_GLB_CNT_TH 0xc00
310 #define RK3528_GLB_SRST_FST 0xc08
311 #define RK3528_GLB_SRST_SND 0xc0c
312
313 #define RK3562_PMU0_CRU_BASE 0x10000
314 #define RK3562_PMU1_CRU_BASE 0x18000
315 #define RK3562_DDR_CRU_BASE 0x20000
316 #define RK3562_SUBDDR_CRU_BASE 0x28000
317 #define RK3562_PERI_CRU_BASE 0x30000
318
319 #define RK3562_PLL_CON(x) RK2928_PLL_CON(x)
320 #define RK3562_PMU1_PLL_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x40)
321 #define RK3562_SUBDDR_PLL_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x20)
322 #define RK3562_MODE_CON 0x600
323 #define RK3562_PMU1_MODE_CON (RK3562_PMU1_CRU_BASE + 0x380)
324 #define RK3562_SUBDDR_MODE_CON (RK3562_SUBDDR_CRU_BASE + 0x380)
325 #define RK3562_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
326 #define RK3562_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
327 #define RK3562_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
328 #define RK3562_DDR_CLKSEL_CON(x) ((x) * 0x4 + RK3562_DDR_CRU_BASE + 0x100)
329 #define RK3562_DDR_CLKGATE_CON(x) ((x) * 0x4 + RK3562_DDR_CRU_BASE + 0x180)
330 #define RK3562_DDR_SOFTRST_CON(x) ((x) * 0x4 + RK3562_DDR_CRU_BASE + 0x200)
331 #define RK3562_SUBDDR_CLKSEL_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x100)
332 #define RK3562_SUBDDR_CLKGATE_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x180)
333 #define RK3562_SUBDDR_SOFTRST_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x200)
334 #define RK3562_PERI_CLKSEL_CON(x) ((x) * 0x4 + RK3562_PERI_CRU_BASE + 0x100)
335 #define RK3562_PERI_CLKGATE_CON(x) ((x) * 0x4 + RK3562_PERI_CRU_BASE + 0x300)
336 #define RK3562_PERI_SOFTRST_CON(x) ((x) * 0x4 + RK3562_PERI_CRU_BASE + 0x400)
337 #define RK3562_PMU0_CLKSEL_CON(x) ((x) * 0x4 + RK3562_PMU0_CRU_BASE + 0x100)
338 #define RK3562_PMU0_CLKGATE_CON(x) ((x) * 0x4 + RK3562_PMU0_CRU_BASE + 0x180)
339 #define RK3562_PMU0_SOFTRST_CON(x) ((x) * 0x4 + RK3562_PMU0_CRU_BASE + 0x200)
340 #define RK3562_PMU1_CLKSEL_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x100)
341 #define RK3562_PMU1_CLKGATE_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x180)
342 #define RK3562_PMU1_SOFTRST_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x200)
343 #define RK3562_GLB_SRST_FST 0x614
344 #define RK3562_GLB_SRST_SND 0x618
345 #define RK3562_GLB_RST_CON 0x61c
346 #define RK3562_GLB_RST_ST 0x620
347 #define RK3562_SDMMC0_CON0 0x624
348 #define RK3562_SDMMC0_CON1 0x628
349 #define RK3562_SDMMC1_CON0 0x62c
350 #define RK3562_SDMMC1_CON1 0x630
351
352 #define RK3568_PLL_CON(x) RK2928_PLL_CON(x)
353 #define RK3568_MODE_CON0 0xc0
354 #define RK3568_MISC_CON0 0xc4
355 #define RK3568_MISC_CON1 0xc8
356 #define RK3568_MISC_CON2 0xcc
357 #define RK3568_GLB_CNT_TH 0xd0
358 #define RK3568_GLB_SRST_FST 0xd4
359 #define RK3568_GLB_SRST_SND 0xd8
360 #define RK3568_GLB_RST_CON 0xdc
361 #define RK3568_GLB_RST_ST 0xe0
362 #define RK3568_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
363 #define RK3568_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
364 #define RK3568_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
365 #define RK3568_SDMMC0_CON0 0x580
366 #define RK3568_SDMMC0_CON1 0x584
367 #define RK3568_SDMMC1_CON0 0x588
368 #define RK3568_SDMMC1_CON1 0x58c
369 #define RK3568_SDMMC2_CON0 0x590
370 #define RK3568_SDMMC2_CON1 0x594
371 #define RK3568_EMMC_CON0 0x598
372 #define RK3568_EMMC_CON1 0x59c
373
374 #define RK3568_PMU_PLL_CON(x) RK2928_PLL_CON(x)
375 #define RK3568_PMU_MODE_CON0 0x80
376 #define RK3568_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
377 #define RK3568_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x180)
378 #define RK3568_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x200)
379
380 #define RK3576_PHP_CRU_BASE 0x8000
381 #define RK3576_SECURE_NS_CRU_BASE 0x10000
382 #define RK3576_PMU_CRU_BASE 0x20000
383 #define RK3576_BIGCORE_CRU_BASE 0x38000
384 #define RK3576_LITCORE_CRU_BASE 0x40000
385 #define RK3576_CCI_CRU_BASE 0x48000
386
387 #define RK3576_PLL_CON(x) RK2928_PLL_CON(x)
388 #define RK3576_MODE_CON0 0x280
389 #define RK3576_BPLL_MODE_CON0 (RK3576_BIGCORE_CRU_BASE + 0x280)
390 #define RK3576_LPLL_MODE_CON0 (RK3576_LITCORE_CRU_BASE + 0x280)
391 #define RK3576_PPLL_MODE_CON0 (RK3576_PHP_CRU_BASE + 0x280)
392 #define RK3576_CLKSEL_CON(x) ((x) * 0x4 + 0x300)
393 #define RK3576_CLKGATE_CON(x) ((x) * 0x4 + 0x800)
394 #define RK3576_SOFTRST_CON(x) ((x) * 0x4 + 0xa00)
395 #define RK3576_GLB_CNT_TH 0xc00
396 #define RK3576_GLB_SRST_FST 0xc08
397 #define RK3576_GLB_SRST_SND 0xc0c
398 #define RK3576_GLB_RST_CON 0xc10
399 #define RK3576_GLB_RST_ST 0xc04
400 #define RK3576_SDIO_CON0 0xC24
401 #define RK3576_SDIO_CON1 0xC28
402 #define RK3576_SDMMC_CON0 0xC30
403 #define RK3576_SDMMC_CON1 0xC34
404
405 #define RK3576_PHP_CLKSEL_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0x300)
406 #define RK3576_PHP_CLKGATE_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0x800)
407 #define RK3576_PHP_SOFTRST_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0xa00)
408
409 #define RK3576_PMU_PLL_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE)
410 #define RK3576_PMU_CLKSEL_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0x300)
411 #define RK3576_PMU_CLKGATE_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0x800)
412 #define RK3576_PMU_SOFTRST_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0xa00)
413
414 #define RK3576_SECURE_NS_CLKSEL_CON(x) ((x) * 0x4 + RK3576_SECURE_NS_CRU_BASE + 0x300)
415 #define RK3576_SECURE_NS_CLKGATE_CON(x) ((x) * 0x4 + RK3576_SECURE_NS_CRU_BASE + 0x800)
416 #define RK3576_SECURE_NS_SOFTRST_CON(x) ((x) * 0x4 + RK3576_SECURE_NS_CRU_BASE + 0xa00)
417
418 #define RK3576_CCI_CLKSEL_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0x300)
419 #define RK3576_CCI_CLKGATE_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0x800)
420 #define RK3576_CCI_SOFTRST_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0xa00)
421
422 #define RK3576_BPLL_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE)
423 #define RK3576_BIGCORE_CLKSEL_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0x300)
424 #define RK3576_BIGCORE_CLKGATE_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0x800)
425 #define RK3576_BIGCORE_SOFTRST_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0xa00)
426 #define RK3576_LPLL_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE)
427 #define RK3576_LITCORE_CLKSEL_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0x300)
428 #define RK3576_LITCORE_CLKGATE_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0x800)
429 #define RK3576_LITCORE_SOFTRST_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0xa00)
430 #define RK3576_NON_SECURE_GATING_CON00 0xc48
431
432 #define RK3588_PHP_CRU_BASE 0x8000
433 #define RK3588_PMU_CRU_BASE 0x30000
434 #define RK3588_BIGCORE0_CRU_BASE 0x50000
435 #define RK3588_BIGCORE1_CRU_BASE 0x52000
436 #define RK3588_DSU_CRU_BASE 0x58000
437
438 #define RK3588_PLL_CON(x) RK2928_PLL_CON(x)
439 #define RK3588_MODE_CON0 0x280
440 #define RK3588_B0_PLL_MODE_CON0 (RK3588_BIGCORE0_CRU_BASE + 0x280)
441 #define RK3588_B1_PLL_MODE_CON0 (RK3588_BIGCORE1_CRU_BASE + 0x280)
442 #define RK3588_LPLL_MODE_CON0 (RK3588_DSU_CRU_BASE + 0x280)
443 #define RK3588_CLKSEL_CON(x) ((x) * 0x4 + 0x300)
444 #define RK3588_CLKGATE_CON(x) ((x) * 0x4 + 0x800)
445 #define RK3588_SOFTRST_CON(x) ((x) * 0x4 + 0xa00)
446 #define RK3588_GLB_CNT_TH 0xc00
447 #define RK3588_GLB_SRST_FST 0xc08
448 #define RK3588_GLB_SRST_SND 0xc0c
449 #define RK3588_GLB_RST_CON 0xc10
450 #define RK3588_GLB_RST_ST 0xc04
451 #define RK3588_SDIO_CON0 0xC24
452 #define RK3588_SDIO_CON1 0xC28
453 #define RK3588_SDMMC_CON0 0xC30
454 #define RK3588_SDMMC_CON1 0xC34
455
456 #define RK3588_PHP_CLKGATE_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE + 0x800)
457 #define RK3588_PHP_SOFTRST_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE + 0xa00)
458
459 #define RK3588_PMU_PLL_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE)
460 #define RK3588_PMU_CLKSEL_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0x300)
461 #define RK3588_PMU_CLKGATE_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0x800)
462 #define RK3588_PMU_SOFTRST_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0xa00)
463
464 #define RK3588_B0_PLL_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE)
465 #define RK3588_BIGCORE0_CLKSEL_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0x300)
466 #define RK3588_BIGCORE0_CLKGATE_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0x800)
467 #define RK3588_BIGCORE0_SOFTRST_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0xa00)
468 #define RK3588_B1_PLL_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE)
469 #define RK3588_BIGCORE1_CLKSEL_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0x300)
470 #define RK3588_BIGCORE1_CLKGATE_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0x800)
471 #define RK3588_BIGCORE1_SOFTRST_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0xa00)
472 #define RK3588_LPLL_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE)
473 #define RK3588_DSU_CLKSEL_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x300)
474 #define RK3588_DSU_CLKGATE_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x800)
475 #define RK3588_DSU_SOFTRST_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0xa00)
476
477 enum rockchip_pll_type {
478 pll_rk3036,
479 pll_rk3066,
480 pll_rk3328,
481 pll_rk3399,
482 pll_rk3588,
483 pll_rk3588_core,
484 pll_rk3588_ddr,
485 };
486
487 #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \
488 _postdiv2, _dsmpd, _frac) \
489 { \
490 .rate = _rate##U, \
491 .fbdiv = _fbdiv, \
492 .postdiv1 = _postdiv1, \
493 .refdiv = _refdiv, \
494 .postdiv2 = _postdiv2, \
495 .dsmpd = _dsmpd, \
496 .frac = _frac, \
497 }
498
499 #define RK3066_PLL_RATE(_rate, _nr, _nf, _no) \
500 { \
501 .rate = _rate##U, \
502 .nr = _nr, \
503 .nf = _nf, \
504 .no = _no, \
505 .nb = ((_nf) < 2) ? 1 : (_nf) >> 1, \
506 }
507
508 #define RK3066_PLL_RATE_NB(_rate, _nr, _nf, _no, _nb) \
509 { \
510 .rate = _rate##U, \
511 .nr = _nr, \
512 .nf = _nf, \
513 .no = _no, \
514 .nb = _nb, \
515 }
516
517 #define RK3588_PLL_RATE(_rate, _p, _m, _s, _k) \
518 { \
519 .rate = _rate##U, \
520 .p = _p, \
521 .m = _m, \
522 .s = _s, \
523 .k = _k, \
524 }
525
526 enum rockchip_grf_type {
527 grf_type_sys = 0,
528 grf_type_pmu0,
529 grf_type_pmu1,
530 grf_type_ioc,
531 grf_type_vo,
532 grf_type_vpu,
533 };
534
535 /* ceil(sqrt(enums in rockchip_grf_type - 1)) */
536 #define GRF_HASH_ORDER 2
537
538 /**
539 * struct rockchip_aux_grf - entry for the aux_grf_table hashtable
540 * @grf: pointer to the grf this entry references
541 * @type: what type of GRF this is
542 * @node: hlist node
543 */
544 struct rockchip_aux_grf {
545 struct regmap *grf;
546 enum rockchip_grf_type type;
547 struct hlist_node node;
548 };
549
550 /**
551 * struct rockchip_clk_provider - information about clock provider
552 * @reg_base: virtual address for the register base.
553 * @clk_data: holds clock related data like clk* and number of clocks.
554 * @cru_node: device-node of the clock-provider
555 * @grf: regmap of the general-register-files syscon
556 * @aux_grf_table: hashtable of auxiliary GRF regmaps, indexed by grf_type
557 * @lock: maintains exclusion between callbacks for a given clock-provider.
558 */
559 struct rockchip_clk_provider {
560 void __iomem *reg_base;
561 struct clk_onecell_data clk_data;
562 struct device_node *cru_node;
563 struct regmap *grf;
564 DECLARE_HASHTABLE(aux_grf_table, GRF_HASH_ORDER);
565 spinlock_t lock;
566 };
567
568 struct rockchip_pll_rate_table {
569 unsigned long rate;
570 union {
571 struct {
572 /* for RK3066 */
573 unsigned int nr;
574 unsigned int nf;
575 unsigned int no;
576 unsigned int nb;
577 };
578 struct {
579 /* for RK3036/RK3399 */
580 unsigned int fbdiv;
581 unsigned int postdiv1;
582 unsigned int refdiv;
583 unsigned int postdiv2;
584 unsigned int dsmpd;
585 unsigned int frac;
586 };
587 struct {
588 /* for RK3588 */
589 unsigned int m;
590 unsigned int p;
591 unsigned int s;
592 unsigned int k;
593 };
594 };
595 };
596
597 /**
598 * struct rockchip_pll_clock - information about pll clock
599 * @id: platform specific id of the clock.
600 * @name: name of this pll clock.
601 * @parent_names: name of the parent clock.
602 * @num_parents: number of parents
603 * @flags: optional flags for basic clock.
604 * @con_offset: offset of the register for configuring the PLL.
605 * @mode_offset: offset of the register for configuring the PLL-mode.
606 * @mode_shift: offset inside the mode-register for the mode of this pll.
607 * @lock_shift: offset inside the lock register for the lock status.
608 * @type: Type of PLL to be registered.
609 * @pll_flags: hardware-specific flags
610 * @rate_table: Table of usable pll rates
611 *
612 * Flags:
613 * ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the
614 * rate_table parameters and adjust them if necessary.
615 * ROCKCHIP_PLL_FIXED_MODE - the pll operates in normal mode only
616 */
617 struct rockchip_pll_clock {
618 unsigned int id;
619 const char *name;
620 const char *const *parent_names;
621 u8 num_parents;
622 unsigned long flags;
623 int con_offset;
624 int mode_offset;
625 int mode_shift;
626 int lock_shift;
627 enum rockchip_pll_type type;
628 u8 pll_flags;
629 struct rockchip_pll_rate_table *rate_table;
630 };
631
632 #define ROCKCHIP_PLL_SYNC_RATE BIT(0)
633 #define ROCKCHIP_PLL_FIXED_MODE BIT(1)
634
635 #define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \
636 _lshift, _pflags, _rtable) \
637 { \
638 .id = _id, \
639 .type = _type, \
640 .name = _name, \
641 .parent_names = _pnames, \
642 .num_parents = ARRAY_SIZE(_pnames), \
643 .flags = CLK_GET_RATE_NOCACHE | _flags, \
644 .con_offset = _con, \
645 .mode_offset = _mode, \
646 .mode_shift = _mshift, \
647 .lock_shift = _lshift, \
648 .pll_flags = _pflags, \
649 .rate_table = _rtable, \
650 }
651
652 struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
653 enum rockchip_pll_type pll_type,
654 const char *name, const char *const *parent_names,
655 u8 num_parents, int con_offset, int grf_lock_offset,
656 int lock_shift, int mode_offset, int mode_shift,
657 struct rockchip_pll_rate_table *rate_table,
658 unsigned long flags, u8 clk_pll_flags);
659
660 struct rockchip_cpuclk_clksel {
661 int reg;
662 u32 val;
663 };
664
665 #define ROCKCHIP_CPUCLK_NUM_DIVIDERS 6
666 #define ROCKCHIP_CPUCLK_MAX_CORES 4
667 struct rockchip_cpuclk_rate_table {
668 unsigned long prate;
669 struct rockchip_cpuclk_clksel divs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
670 struct rockchip_cpuclk_clksel pre_muxs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
671 struct rockchip_cpuclk_clksel post_muxs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
672 };
673
674 /**
675 * struct rockchip_cpuclk_reg_data - register offsets and masks of the cpuclock
676 * @core_reg[]: register offset of the cores setting register
677 * @div_core_shift[]: cores divider offset used to divide the pll value
678 * @div_core_mask[]: cores divider mask
679 * @num_cores: number of cpu cores
680 * @mux_core_reg: register offset of the cores select parent
681 * @mux_core_alt: mux value to select alternate parent
682 * @mux_core_main: mux value to select main parent of core
683 * @mux_core_shift: offset of the core multiplexer
684 * @mux_core_mask: core multiplexer mask
685 */
686 struct rockchip_cpuclk_reg_data {
687 int core_reg[ROCKCHIP_CPUCLK_MAX_CORES];
688 u8 div_core_shift[ROCKCHIP_CPUCLK_MAX_CORES];
689 u32 div_core_mask[ROCKCHIP_CPUCLK_MAX_CORES];
690 int num_cores;
691 int mux_core_reg;
692 u8 mux_core_alt;
693 u8 mux_core_main;
694 u8 mux_core_shift;
695 u32 mux_core_mask;
696 };
697
698 struct clk *rockchip_clk_register_cpuclk(const char *name,
699 const char *const *parent_names, u8 num_parents,
700 const struct rockchip_cpuclk_reg_data *reg_data,
701 const struct rockchip_cpuclk_rate_table *rates,
702 int nrates, void __iomem *reg_base, spinlock_t *lock);
703
704 struct clk *rockchip_clk_register_cpuclk_multi_pll(const char *name,
705 const char *const *parent_names,
706 u8 num_parents, void __iomem *base,
707 int muxdiv_offset, u8 mux_shift,
708 u8 mux_width, u8 mux_flags,
709 int div_offset, u8 div_shift,
710 u8 div_width, u8 div_flags,
711 unsigned long flags, spinlock_t *lock,
712 const struct rockchip_cpuclk_rate_table *rates,
713 int nrates);
714
715 struct clk *rockchip_clk_register_mmc(const char *name,
716 const char *const *parent_names, u8 num_parents,
717 void __iomem *reg,
718 struct regmap *grf, int grf_reg,
719 int shift);
720
721 /*
722 * DDRCLK flags, including method of setting the rate
723 * ROCKCHIP_DDRCLK_SIP: use SIP call to bl31 to change ddrclk rate.
724 */
725 #define ROCKCHIP_DDRCLK_SIP BIT(0)
726
727 struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
728 const char *const *parent_names,
729 u8 num_parents, int mux_offset,
730 int mux_shift, int mux_width,
731 int div_shift, int div_width,
732 int ddr_flags, void __iomem *reg_base,
733 spinlock_t *lock);
734
735 #define ROCKCHIP_INVERTER_HIWORD_MASK BIT(0)
736
737 struct clk *rockchip_clk_register_inverter(const char *name,
738 const char *const *parent_names, u8 num_parents,
739 void __iomem *reg, int shift, int flags,
740 spinlock_t *lock);
741
742 struct clk *rockchip_clk_register_muxgrf(const char *name,
743 const char *const *parent_names, u8 num_parents,
744 int flags, struct regmap *grf, int reg,
745 int shift, int width, int mux_flags);
746
747 struct clk *rockchip_clk_register_gate_grf(const char *name,
748 const char *parent_name, unsigned long flags,
749 struct regmap *regmap, unsigned int reg,
750 unsigned int shift, u8 gate_flags);
751
752 #define PNAME(x) static const char *const x[] __initconst
753
754 enum rockchip_clk_branch_type {
755 branch_composite,
756 branch_mux,
757 branch_grf_mux,
758 branch_divider,
759 branch_fraction_divider,
760 branch_gate,
761 branch_grf_gate,
762 branch_linked_gate,
763 branch_mmc,
764 branch_grf_mmc,
765 branch_inverter,
766 branch_factor,
767 branch_ddrclk,
768 branch_half_divider,
769 };
770
771 struct rockchip_clk_branch {
772 unsigned int id;
773 enum rockchip_clk_branch_type branch_type;
774 const char *name;
775 const char *const *parent_names;
776 u8 num_parents;
777 unsigned long flags;
778 int muxdiv_offset;
779 u8 mux_shift;
780 u8 mux_width;
781 u8 mux_flags;
782 u32 *mux_table;
783 int div_offset;
784 u8 div_shift;
785 u8 div_width;
786 u8 div_flags;
787 struct clk_div_table *div_table;
788 int gate_offset;
789 u8 gate_shift;
790 u8 gate_flags;
791 unsigned int linked_clk_id;
792 enum rockchip_grf_type grf_type;
793 struct rockchip_clk_branch *child;
794 };
795
796 #define COMPOSITE(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\
797 df, go, gs, gf) \
798 { \
799 .id = _id, \
800 .branch_type = branch_composite, \
801 .name = cname, \
802 .parent_names = pnames, \
803 .num_parents = ARRAY_SIZE(pnames), \
804 .flags = f, \
805 .muxdiv_offset = mo, \
806 .mux_shift = ms, \
807 .mux_width = mw, \
808 .mux_flags = mf, \
809 .div_shift = ds, \
810 .div_width = dw, \
811 .div_flags = df, \
812 .gate_offset = go, \
813 .gate_shift = gs, \
814 .gate_flags = gf, \
815 }
816
817 #define COMPOSITE_DIV_OFFSET(_id, cname, pnames, f, mo, ms, mw, \
818 mf, do, ds, dw, df, go, gs, gf) \
819 { \
820 .id = _id, \
821 .branch_type = branch_composite, \
822 .name = cname, \
823 .parent_names = pnames, \
824 .num_parents = ARRAY_SIZE(pnames), \
825 .flags = f, \
826 .muxdiv_offset = mo, \
827 .mux_shift = ms, \
828 .mux_width = mw, \
829 .mux_flags = mf, \
830 .div_offset = do, \
831 .div_shift = ds, \
832 .div_width = dw, \
833 .div_flags = df, \
834 .gate_offset = go, \
835 .gate_shift = gs, \
836 .gate_flags = gf, \
837 }
838
839 #define COMPOSITE_NOMUX(_id, cname, pname, f, mo, ds, dw, df, \
840 go, gs, gf) \
841 { \
842 .id = _id, \
843 .branch_type = branch_composite, \
844 .name = cname, \
845 .parent_names = (const char *[]){ pname }, \
846 .num_parents = 1, \
847 .flags = f, \
848 .muxdiv_offset = mo, \
849 .div_shift = ds, \
850 .div_width = dw, \
851 .div_flags = df, \
852 .gate_offset = go, \
853 .gate_shift = gs, \
854 .gate_flags = gf, \
855 }
856
857 #define COMPOSITE_NOMUX_DIVTBL(_id, cname, pname, f, mo, ds, dw,\
858 df, dt, go, gs, gf) \
859 { \
860 .id = _id, \
861 .branch_type = branch_composite, \
862 .name = cname, \
863 .parent_names = (const char *[]){ pname }, \
864 .num_parents = 1, \
865 .flags = f, \
866 .muxdiv_offset = mo, \
867 .div_shift = ds, \
868 .div_width = dw, \
869 .div_flags = df, \
870 .div_table = dt, \
871 .gate_offset = go, \
872 .gate_shift = gs, \
873 .gate_flags = gf, \
874 }
875
876 #define COMPOSITE_NODIV(_id, cname, pnames, f, mo, ms, mw, mf, \
877 go, gs, gf) \
878 { \
879 .id = _id, \
880 .branch_type = branch_composite, \
881 .name = cname, \
882 .parent_names = pnames, \
883 .num_parents = ARRAY_SIZE(pnames), \
884 .flags = f, \
885 .muxdiv_offset = mo, \
886 .mux_shift = ms, \
887 .mux_width = mw, \
888 .mux_flags = mf, \
889 .gate_offset = go, \
890 .gate_shift = gs, \
891 .gate_flags = gf, \
892 }
893
894 #define COMPOSITE_NOGATE(_id, cname, pnames, f, mo, ms, mw, mf, \
895 ds, dw, df) \
896 { \
897 .id = _id, \
898 .branch_type = branch_composite, \
899 .name = cname, \
900 .parent_names = pnames, \
901 .num_parents = ARRAY_SIZE(pnames), \
902 .flags = f, \
903 .muxdiv_offset = mo, \
904 .mux_shift = ms, \
905 .mux_width = mw, \
906 .mux_flags = mf, \
907 .div_shift = ds, \
908 .div_width = dw, \
909 .div_flags = df, \
910 .gate_offset = -1, \
911 }
912
913 #define COMPOSITE_NOGATE_DIVTBL(_id, cname, pnames, f, mo, ms, \
914 mw, mf, ds, dw, df, dt) \
915 { \
916 .id = _id, \
917 .branch_type = branch_composite, \
918 .name = cname, \
919 .parent_names = pnames, \
920 .num_parents = ARRAY_SIZE(pnames), \
921 .flags = f, \
922 .muxdiv_offset = mo, \
923 .mux_shift = ms, \
924 .mux_width = mw, \
925 .mux_flags = mf, \
926 .div_shift = ds, \
927 .div_width = dw, \
928 .div_flags = df, \
929 .div_table = dt, \
930 .gate_offset = -1, \
931 }
932
933 #define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf)\
934 { \
935 .id = _id, \
936 .branch_type = branch_fraction_divider, \
937 .name = cname, \
938 .parent_names = (const char *[]){ pname }, \
939 .num_parents = 1, \
940 .flags = f, \
941 .muxdiv_offset = mo, \
942 .div_shift = 16, \
943 .div_width = 16, \
944 .div_flags = df, \
945 .gate_offset = go, \
946 .gate_shift = gs, \
947 .gate_flags = gf, \
948 }
949
950 #define COMPOSITE_FRACMUX(_id, cname, pname, f, mo, df, go, gs, gf, ch) \
951 { \
952 .id = _id, \
953 .branch_type = branch_fraction_divider, \
954 .name = cname, \
955 .parent_names = (const char *[]){ pname }, \
956 .num_parents = 1, \
957 .flags = f, \
958 .muxdiv_offset = mo, \
959 .div_shift = 16, \
960 .div_width = 16, \
961 .div_flags = df, \
962 .gate_offset = go, \
963 .gate_shift = gs, \
964 .gate_flags = gf, \
965 .child = ch, \
966 }
967
968 #define COMPOSITE_FRACMUX_NOGATE(_id, cname, pname, f, mo, df, ch) \
969 { \
970 .id = _id, \
971 .branch_type = branch_fraction_divider, \
972 .name = cname, \
973 .parent_names = (const char *[]){ pname }, \
974 .num_parents = 1, \
975 .flags = f, \
976 .muxdiv_offset = mo, \
977 .div_shift = 16, \
978 .div_width = 16, \
979 .div_flags = df, \
980 .gate_offset = -1, \
981 .child = ch, \
982 }
983
984 #define COMPOSITE_DDRCLK(_id, cname, pnames, f, mo, ms, mw, \
985 ds, dw, df) \
986 { \
987 .id = _id, \
988 .branch_type = branch_ddrclk, \
989 .name = cname, \
990 .parent_names = pnames, \
991 .num_parents = ARRAY_SIZE(pnames), \
992 .flags = f, \
993 .muxdiv_offset = mo, \
994 .mux_shift = ms, \
995 .mux_width = mw, \
996 .div_shift = ds, \
997 .div_width = dw, \
998 .div_flags = df, \
999 .gate_offset = -1, \
1000 }
1001
1002 #define MUX(_id, cname, pnames, f, o, s, w, mf) \
1003 { \
1004 .id = _id, \
1005 .branch_type = branch_mux, \
1006 .name = cname, \
1007 .parent_names = pnames, \
1008 .num_parents = ARRAY_SIZE(pnames), \
1009 .flags = f, \
1010 .muxdiv_offset = o, \
1011 .mux_shift = s, \
1012 .mux_width = w, \
1013 .mux_flags = mf, \
1014 .gate_offset = -1, \
1015 }
1016
1017 #define MUXTBL(_id, cname, pnames, f, o, s, w, mf, mt) \
1018 { \
1019 .id = _id, \
1020 .branch_type = branch_mux, \
1021 .name = cname, \
1022 .parent_names = pnames, \
1023 .num_parents = ARRAY_SIZE(pnames), \
1024 .flags = f, \
1025 .muxdiv_offset = o, \
1026 .mux_shift = s, \
1027 .mux_width = w, \
1028 .mux_flags = mf, \
1029 .gate_offset = -1, \
1030 .mux_table = mt, \
1031 }
1032
1033 #define MUXGRF(_id, cname, pnames, f, o, s, w, mf, gt) \
1034 { \
1035 .id = _id, \
1036 .branch_type = branch_grf_mux, \
1037 .name = cname, \
1038 .parent_names = pnames, \
1039 .num_parents = ARRAY_SIZE(pnames), \
1040 .flags = f, \
1041 .muxdiv_offset = o, \
1042 .mux_shift = s, \
1043 .mux_width = w, \
1044 .mux_flags = mf, \
1045 .gate_offset = -1, \
1046 .grf_type = gt, \
1047 }
1048
1049 #define DIV(_id, cname, pname, f, o, s, w, df) \
1050 { \
1051 .id = _id, \
1052 .branch_type = branch_divider, \
1053 .name = cname, \
1054 .parent_names = (const char *[]){ pname }, \
1055 .num_parents = 1, \
1056 .flags = f, \
1057 .muxdiv_offset = o, \
1058 .div_shift = s, \
1059 .div_width = w, \
1060 .div_flags = df, \
1061 .gate_offset = -1, \
1062 }
1063
1064 #define DIVTBL(_id, cname, pname, f, o, s, w, df, dt) \
1065 { \
1066 .id = _id, \
1067 .branch_type = branch_divider, \
1068 .name = cname, \
1069 .parent_names = (const char *[]){ pname }, \
1070 .num_parents = 1, \
1071 .flags = f, \
1072 .muxdiv_offset = o, \
1073 .div_shift = s, \
1074 .div_width = w, \
1075 .div_flags = df, \
1076 .div_table = dt, \
1077 }
1078
1079 #define GATE(_id, cname, pname, f, o, b, gf) \
1080 { \
1081 .id = _id, \
1082 .branch_type = branch_gate, \
1083 .name = cname, \
1084 .parent_names = (const char *[]){ pname }, \
1085 .num_parents = 1, \
1086 .flags = f, \
1087 .gate_offset = o, \
1088 .gate_shift = b, \
1089 .gate_flags = gf, \
1090 }
1091
1092 #define GATE_GRF(_id, cname, pname, f, o, b, gf, gt) \
1093 { \
1094 .id = _id, \
1095 .branch_type = branch_grf_gate, \
1096 .name = cname, \
1097 .parent_names = (const char *[]){ pname }, \
1098 .num_parents = 1, \
1099 .flags = f, \
1100 .gate_offset = o, \
1101 .gate_shift = b, \
1102 .gate_flags = gf, \
1103 .grf_type = gt, \
1104 }
1105
1106 #define GATE_LINK(_id, cname, pname, linkedclk, f, o, b, gf) \
1107 { \
1108 .id = _id, \
1109 .branch_type = branch_linked_gate, \
1110 .name = cname, \
1111 .parent_names = (const char *[]){ pname }, \
1112 .linked_clk_id = linkedclk, \
1113 .num_parents = 1, \
1114 .flags = f, \
1115 .gate_offset = o, \
1116 .gate_shift = b, \
1117 .gate_flags = gf, \
1118 }
1119
1120 #define MMC(_id, cname, pname, offset, shift) \
1121 { \
1122 .id = _id, \
1123 .branch_type = branch_mmc, \
1124 .name = cname, \
1125 .parent_names = (const char *[]){ pname }, \
1126 .num_parents = 1, \
1127 .muxdiv_offset = offset, \
1128 .div_shift = shift, \
1129 }
1130
1131 #define MMC_GRF(_id, cname, pname, offset, shift, grftype) \
1132 { \
1133 .id = _id, \
1134 .branch_type = branch_grf_mmc, \
1135 .name = cname, \
1136 .parent_names = (const char *[]){ pname }, \
1137 .num_parents = 1, \
1138 .muxdiv_offset = offset, \
1139 .div_shift = shift, \
1140 .grf_type = grftype, \
1141 }
1142
1143 #define INVERTER(_id, cname, pname, io, is, if) \
1144 { \
1145 .id = _id, \
1146 .branch_type = branch_inverter, \
1147 .name = cname, \
1148 .parent_names = (const char *[]){ pname }, \
1149 .num_parents = 1, \
1150 .muxdiv_offset = io, \
1151 .div_shift = is, \
1152 .div_flags = if, \
1153 }
1154
1155 #define FACTOR(_id, cname, pname, f, fm, fd) \
1156 { \
1157 .id = _id, \
1158 .branch_type = branch_factor, \
1159 .name = cname, \
1160 .parent_names = (const char *[]){ pname }, \
1161 .num_parents = 1, \
1162 .flags = f, \
1163 .div_shift = fm, \
1164 .div_width = fd, \
1165 }
1166
1167 #define FACTOR_GATE(_id, cname, pname, f, fm, fd, go, gb, gf) \
1168 { \
1169 .id = _id, \
1170 .branch_type = branch_factor, \
1171 .name = cname, \
1172 .parent_names = (const char *[]){ pname }, \
1173 .num_parents = 1, \
1174 .flags = f, \
1175 .div_shift = fm, \
1176 .div_width = fd, \
1177 .gate_offset = go, \
1178 .gate_shift = gb, \
1179 .gate_flags = gf, \
1180 }
1181
1182 #define COMPOSITE_HALFDIV(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\
1183 df, go, gs, gf) \
1184 { \
1185 .id = _id, \
1186 .branch_type = branch_half_divider, \
1187 .name = cname, \
1188 .parent_names = pnames, \
1189 .num_parents = ARRAY_SIZE(pnames), \
1190 .flags = f, \
1191 .muxdiv_offset = mo, \
1192 .mux_shift = ms, \
1193 .mux_width = mw, \
1194 .mux_flags = mf, \
1195 .div_shift = ds, \
1196 .div_width = dw, \
1197 .div_flags = df, \
1198 .gate_offset = go, \
1199 .gate_shift = gs, \
1200 .gate_flags = gf, \
1201 }
1202
1203 #define COMPOSITE_NOGATE_HALFDIV(_id, cname, pnames, f, mo, ms, mw, mf, \
1204 ds, dw, df) \
1205 { \
1206 .id = _id, \
1207 .branch_type = branch_half_divider, \
1208 .name = cname, \
1209 .parent_names = pnames, \
1210 .num_parents = ARRAY_SIZE(pnames), \
1211 .flags = f, \
1212 .muxdiv_offset = mo, \
1213 .mux_shift = ms, \
1214 .mux_width = mw, \
1215 .mux_flags = mf, \
1216 .div_shift = ds, \
1217 .div_width = dw, \
1218 .div_flags = df, \
1219 .gate_offset = -1, \
1220 }
1221
1222 #define COMPOSITE_NOMUX_HALFDIV(_id, cname, pname, f, mo, ds, dw, df, \
1223 go, gs, gf) \
1224 { \
1225 .id = _id, \
1226 .branch_type = branch_half_divider, \
1227 .name = cname, \
1228 .parent_names = (const char *[]){ pname }, \
1229 .num_parents = 1, \
1230 .flags = f, \
1231 .muxdiv_offset = mo, \
1232 .div_shift = ds, \
1233 .div_width = dw, \
1234 .div_flags = df, \
1235 .gate_offset = go, \
1236 .gate_shift = gs, \
1237 .gate_flags = gf, \
1238 }
1239
1240 #define DIV_HALF(_id, cname, pname, f, o, s, w, df) \
1241 { \
1242 .id = _id, \
1243 .branch_type = branch_half_divider, \
1244 .name = cname, \
1245 .parent_names = (const char *[]){ pname }, \
1246 .num_parents = 1, \
1247 .flags = f, \
1248 .muxdiv_offset = o, \
1249 .div_shift = s, \
1250 .div_width = w, \
1251 .div_flags = df, \
1252 .gate_offset = -1, \
1253 }
1254
1255 /* SGRF clocks are only accessible from secure mode, so not controllable */
1256 #define SGRF_GATE(_id, cname, pname) \
1257 FACTOR(_id, cname, pname, 0, 1, 1)
1258
rockchip_clk_get_lookup(struct rockchip_clk_provider * ctx,unsigned int id)1259 static inline struct clk *rockchip_clk_get_lookup(struct rockchip_clk_provider *ctx,
1260 unsigned int id)
1261 {
1262 return ctx->clk_data.clks[id];
1263 }
1264
rockchip_clk_set_lookup(struct rockchip_clk_provider * ctx,struct clk * clk,unsigned int id)1265 static inline void rockchip_clk_set_lookup(struct rockchip_clk_provider *ctx,
1266 struct clk *clk, unsigned int id)
1267 {
1268 ctx->clk_data.clks[id] = clk;
1269 }
1270
1271 struct rockchip_gate_link_platdata {
1272 struct rockchip_clk_provider *ctx;
1273 struct rockchip_clk_branch *clkbr;
1274 };
1275
1276 struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
1277 void __iomem *base, unsigned long nr_clks);
1278 struct rockchip_clk_provider *rockchip_clk_init_early(struct device_node *np,
1279 void __iomem *base, unsigned long nr_clks);
1280 void rockchip_clk_finalize(struct rockchip_clk_provider *ctx);
1281 void rockchip_clk_of_add_provider(struct device_node *np,
1282 struct rockchip_clk_provider *ctx);
1283 unsigned long rockchip_clk_find_max_clk_id(struct rockchip_clk_branch *list,
1284 unsigned int nr_clk);
1285 void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
1286 struct rockchip_clk_branch *list,
1287 unsigned int nr_clk);
1288 void rockchip_clk_register_late_branches(struct device *dev,
1289 struct rockchip_clk_provider *ctx,
1290 struct rockchip_clk_branch *list,
1291 unsigned int nr_clk);
1292 void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
1293 struct rockchip_pll_clock *pll_list,
1294 unsigned int nr_pll, int grf_lock_offset);
1295 void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
1296 unsigned int lookup_id, const char *name,
1297 const char *const *parent_names, u8 num_parents,
1298 const struct rockchip_cpuclk_reg_data *reg_data,
1299 const struct rockchip_cpuclk_rate_table *rates,
1300 int nrates);
1301 void rockchip_clk_register_armclk_multi_pll(struct rockchip_clk_provider *ctx,
1302 struct rockchip_clk_branch *list,
1303 const struct rockchip_cpuclk_rate_table *rates,
1304 int nrates);
1305 void rockchip_clk_protect_critical(const char *const clocks[], int nclocks);
1306 void rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx,
1307 unsigned int reg, void (*cb)(void));
1308
1309 #define ROCKCHIP_SOFTRST_HIWORD_MASK BIT(0)
1310
1311 struct clk *rockchip_clk_register_halfdiv(const char *name,
1312 const char *const *parent_names,
1313 u8 num_parents, void __iomem *base,
1314 int muxdiv_offset, u8 mux_shift,
1315 u8 mux_width, u8 mux_flags,
1316 u8 div_shift, u8 div_width,
1317 u8 div_flags, int gate_offset,
1318 u8 gate_shift, u8 gate_flags,
1319 unsigned long flags,
1320 spinlock_t *lock);
1321
1322 #ifdef CONFIG_RESET_CONTROLLER
1323 void rockchip_register_softrst_lut(struct device_node *np,
1324 const int *lookup_table,
1325 unsigned int num_regs,
1326 void __iomem *base, u8 flags);
1327 #else
rockchip_register_softrst_lut(struct device_node * np,const int * lookup_table,unsigned int num_regs,void __iomem * base,u8 flags)1328 static inline void rockchip_register_softrst_lut(struct device_node *np,
1329 const int *lookup_table,
1330 unsigned int num_regs,
1331 void __iomem *base, u8 flags)
1332 {
1333 }
1334 #endif
1335
rockchip_register_softrst(struct device_node * np,unsigned int num_regs,void __iomem * base,u8 flags)1336 static inline void rockchip_register_softrst(struct device_node *np,
1337 unsigned int num_regs,
1338 void __iomem *base, u8 flags)
1339 {
1340 return rockchip_register_softrst_lut(np, NULL, num_regs, base, flags);
1341 }
1342
1343 void rv1126b_rst_init(struct device_node *np, void __iomem *reg_base);
1344 void rk3506_rst_init(struct device_node *np, void __iomem *reg_base);
1345 void rk3528_rst_init(struct device_node *np, void __iomem *reg_base);
1346 void rk3562_rst_init(struct device_node *np, void __iomem *reg_base);
1347 void rk3576_rst_init(struct device_node *np, void __iomem *reg_base);
1348 void rk3588_rst_init(struct device_node *np, void __iomem *reg_base);
1349
1350 #endif
1351