1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright 2024 Fiona Klute
3 *
4 * Based on code originally in rtw8723d.[ch],
5 * Copyright(c) 2018-2019 Realtek Corporation
6 */
7
8 #ifndef __RTW8723X_H__
9 #define __RTW8723X_H__
10
11 #include "main.h"
12 #include "debug.h"
13 #include "phy.h"
14 #include "reg.h"
15
16 enum rtw8723x_path {
17 PATH_S1,
18 PATH_S0,
19 PATH_NR,
20 };
21
22 enum rtw8723x_iqk_round {
23 IQK_ROUND_0,
24 IQK_ROUND_1,
25 IQK_ROUND_2,
26 IQK_ROUND_HYBRID,
27 IQK_ROUND_SIZE,
28 IQK_ROUND_INVALID = 0xff,
29 };
30
31 enum rtw8723x_iqk_result {
32 IQK_S1_TX_X,
33 IQK_S1_TX_Y,
34 IQK_S1_RX_X,
35 IQK_S1_RX_Y,
36 IQK_S0_TX_X,
37 IQK_S0_TX_Y,
38 IQK_S0_RX_X,
39 IQK_S0_RX_Y,
40 IQK_NR,
41 IQK_SX_NR = IQK_NR / PATH_NR,
42 };
43
44 struct rtw8723xe_efuse {
45 u8 mac_addr[ETH_ALEN]; /* 0xd0 */
46 u8 vendor_id[2];
47 u8 device_id[2];
48 u8 sub_vendor_id[2];
49 u8 sub_device_id[2];
50 } __packed;
51
52 struct rtw8723xu_efuse {
53 u8 res4[48]; /* 0xd0 */
54 u8 vendor_id[2]; /* 0x100 */
55 u8 product_id[2]; /* 0x102 */
56 u8 usb_option; /* 0x104 */
57 u8 res5[2]; /* 0x105 */
58 u8 mac_addr[ETH_ALEN]; /* 0x107 */
59 } __packed;
60
61 struct rtw8723xs_efuse {
62 u8 res4[0x4a]; /* 0xd0 */
63 u8 mac_addr[ETH_ALEN]; /* 0x11a */
64 } __packed;
65
66 struct rtw8723x_efuse {
67 __le16 rtl_id;
68 u8 rsvd[2];
69 u8 afe;
70 u8 rsvd1[11];
71
72 /* power index for four RF paths */
73 struct rtw_txpwr_idx txpwr_idx_table[4];
74
75 u8 channel_plan; /* 0xb8 */
76 u8 xtal_k;
77 u8 thermal_meter;
78 u8 iqk_lck;
79 u8 pa_type; /* 0xbc */
80 u8 lna_type_2g[2]; /* 0xbd */
81 u8 lna_type_5g[2];
82 u8 rf_board_option;
83 u8 rf_feature_option;
84 u8 rf_bt_setting;
85 u8 eeprom_version;
86 u8 eeprom_customer_id;
87 u8 tx_bb_swing_setting_2g;
88 u8 res_c7;
89 u8 tx_pwr_calibrate_rate;
90 u8 rf_antenna_option; /* 0xc9 */
91 u8 rfe_option;
92 u8 country_code[2];
93 u8 res[3];
94 union {
95 struct rtw8723xe_efuse e;
96 struct rtw8723xu_efuse u;
97 struct rtw8723xs_efuse s;
98 };
99 } __packed;
100
101 #define RTW8723X_IQK_ADDA_REG_NUM 16
102 #define RTW8723X_IQK_MAC8_REG_NUM 3
103 #define RTW8723X_IQK_MAC32_REG_NUM 1
104 #define RTW8723X_IQK_BB_REG_NUM 9
105
106 struct rtw8723x_iqk_backup_regs {
107 u32 adda[RTW8723X_IQK_ADDA_REG_NUM];
108 u8 mac8[RTW8723X_IQK_MAC8_REG_NUM];
109 u32 mac32[RTW8723X_IQK_MAC32_REG_NUM];
110 u32 bb[RTW8723X_IQK_BB_REG_NUM];
111
112 u32 lte_path;
113 u32 lte_gnt;
114
115 u32 bb_sel_btg;
116 u8 btg_sel;
117
118 u8 igia;
119 u8 igib;
120 };
121
122 struct rtw8723x_common {
123 /* registers that must be backed up before IQK and restored after */
124 u32 iqk_adda_regs[RTW8723X_IQK_ADDA_REG_NUM];
125 u32 iqk_mac8_regs[RTW8723X_IQK_MAC8_REG_NUM];
126 u32 iqk_mac32_regs[RTW8723X_IQK_MAC32_REG_NUM];
127 u32 iqk_bb_regs[RTW8723X_IQK_BB_REG_NUM];
128
129 /* chip register definitions */
130 struct rtw_ltecoex_addr ltecoex_addr;
131 struct rtw_rf_sipi_addr rf_sipi_addr[2];
132 struct rtw_hw_reg dig[2];
133 struct rtw_hw_reg dig_cck[1];
134 struct rtw_prioq_addrs prioq_addrs;
135
136 /* common functions */
137 void (*lck)(struct rtw_dev *rtwdev);
138 int (*read_efuse)(struct rtw_dev *rtwdev, u8 *log_map);
139 int (*mac_init)(struct rtw_dev *rtwdev);
140 int (*mac_postinit)(struct rtw_dev *rtwdev);
141 void (*cfg_ldo25)(struct rtw_dev *rtwdev, bool enable);
142 void (*set_tx_power_index)(struct rtw_dev *rtwdev);
143 void (*efuse_grant)(struct rtw_dev *rtwdev, bool on);
144 void (*false_alarm_statistics)(struct rtw_dev *rtwdev);
145 void (*iqk_backup_regs)(struct rtw_dev *rtwdev,
146 struct rtw8723x_iqk_backup_regs *backup);
147 void (*iqk_restore_regs)(struct rtw_dev *rtwdev,
148 const struct rtw8723x_iqk_backup_regs *backup);
149 bool (*iqk_similarity_cmp)(struct rtw_dev *rtwdev, s32 result[][IQK_NR],
150 u8 c1, u8 c2);
151 u8 (*pwrtrack_get_limit_ofdm)(struct rtw_dev *rtwdev);
152 void (*pwrtrack_set_xtal)(struct rtw_dev *rtwdev, u8 therm_path,
153 u8 delta);
154 void (*coex_cfg_init)(struct rtw_dev *rtwdev);
155 void (*fill_txdesc_checksum)(struct rtw_dev *rtwdev,
156 struct rtw_tx_pkt_info *pkt_info,
157 u8 *txdesc);
158 void (*debug_txpwr_limit)(struct rtw_dev *rtwdev,
159 struct rtw_txpwr_idx *table,
160 int tx_path_count);
161 };
162
163 extern const struct rtw8723x_common rtw8723x_common;
164
165 #define PATH_IQK_RETRY 2
166 #define MAX_TOLERANCE 5
167 #define IQK_TX_X_ERR 0x142
168 #define IQK_TX_Y_ERR 0x42
169 #define IQK_RX_X_ERR 0x132
170 #define IQK_RX_Y_ERR 0x36
171 #define IQK_RX_X_UPPER 0x11a
172 #define IQK_RX_X_LOWER 0xe6
173 #define IQK_RX_Y_LMT 0x1a
174 #define IQK_TX_OK BIT(0)
175 #define IQK_RX_OK BIT(1)
176
177 #define WLAN_TXQ_RPT_EN 0x1F
178
179 #define SPUR_THRES 0x16
180 #define DIS_3WIRE 0xccf000c0
181 #define EN_3WIRE 0xccc000c0
182 #define START_PSD 0x400000
183 #define FREQ_CH5 0xfccd
184 #define FREQ_CH6 0xfc4d
185 #define FREQ_CH7 0xffcd
186 #define FREQ_CH8 0xff4d
187 #define FREQ_CH13 0xfccd
188 #define FREQ_CH14 0xff9a
189 #define RFCFGCH_CHANNEL_MASK GENMASK(7, 0)
190 #define RFCFGCH_BW_MASK (BIT(11) | BIT(10))
191 #define RFCFGCH_BW_20M (BIT(11) | BIT(10))
192 #define RFCFGCH_BW_40M BIT(10)
193 #define BIT_MASK_RFMOD BIT(0)
194 #define BIT_LCK BIT(15)
195
196 #define REG_GPIO_INTM 0x0048
197 #define REG_BTG_SEL 0x0067
198 #define BIT_MASK_BTG_WL BIT(7)
199 #define REG_LTECOEX_PATH_CONTROL 0x0070
200 #define REG_LTECOEX_CTRL 0x07c0
201 #define REG_LTECOEX_WRITE_DATA 0x07c4
202 #define REG_LTECOEX_READ_DATA 0x07c8
203 #define REG_PSDFN 0x0808
204 #define REG_BB_PWR_SAV1_11N 0x0874
205 #define REG_ANA_PARAM1 0x0880
206 #define REG_ANALOG_P4 0x088c
207 #define REG_PSDRPT 0x08b4
208 #define REG_FPGA1_RFMOD 0x0900
209 #define REG_BB_SEL_BTG 0x0948
210 #define REG_BBRX_DFIR 0x0954
211 #define BIT_MASK_RXBB_DFIR GENMASK(27, 24)
212 #define BIT_RXBB_DFIR_EN BIT(19)
213 #define REG_CCK0_SYS 0x0a00
214 #define BIT_CCK_SIDE_BAND BIT(4)
215 #define REG_CCK_ANT_SEL_11N 0x0a04
216 #define REG_PWRTH 0x0a08
217 #define REG_CCK_FA_RST_11N 0x0a2c
218 #define BIT_MASK_CCK_CNT_KEEP BIT(12)
219 #define BIT_MASK_CCK_CNT_EN BIT(13)
220 #define BIT_MASK_CCK_CNT_KPEN (BIT_MASK_CCK_CNT_KEEP | BIT_MASK_CCK_CNT_EN)
221 #define BIT_MASK_CCK_FA_KEEP BIT(14)
222 #define BIT_MASK_CCK_FA_EN BIT(15)
223 #define BIT_MASK_CCK_FA_KPEN (BIT_MASK_CCK_FA_KEEP | BIT_MASK_CCK_FA_EN)
224 #define REG_CCK_FA_LSB_11N 0x0a5c
225 #define REG_CCK_FA_MSB_11N 0x0a58
226 #define REG_CCK_CCA_CNT_11N 0x0a60
227 #define BIT_MASK_CCK_FA_MSB GENMASK(7, 0)
228 #define BIT_MASK_CCK_FA_LSB GENMASK(15, 8)
229 #define REG_PWRTH2 0x0aa8
230 #define REG_CSRATIO 0x0aaa
231 #define REG_OFDM_FA_HOLDC_11N 0x0c00
232 #define BIT_MASK_OFDM_FA_KEEP BIT(31)
233 #define REG_BB_RX_PATH_11N 0x0c04
234 #define REG_TRMUX_11N 0x0c08
235 #define REG_OFDM_FA_RSTC_11N 0x0c0c
236 #define BIT_MASK_OFDM_FA_RST BIT(31)
237 #define REG_A_RXIQI 0x0c14
238 #define BIT_MASK_RXIQ_S1_X 0x000003FF
239 #define BIT_MASK_RXIQ_S1_Y1 0x0000FC00
240 #define BIT_SET_RXIQ_S1_Y1(y) ((y) & 0x3F)
241 #define REG_OFDM0_RXDSP 0x0c40
242 #define BIT_MASK_RXDSP GENMASK(28, 24)
243 #define BIT_EN_RXDSP BIT(9)
244 #define REG_OFDM_0_ECCA_THRESHOLD 0x0c4c
245 #define BIT_MASK_OFDM0_EXT_A BIT(31)
246 #define BIT_MASK_OFDM0_EXT_C BIT(29)
247 #define BIT_MASK_OFDM0_EXTS (BIT(31) | BIT(29) | BIT(28))
248 #define BIT_SET_OFDM0_EXTS(a, c, d) (((a) << 31) | ((c) << 29) | ((d) << 28))
249 #define BIT_MASK_OFDM0_EXTS_B (BIT(27) | BIT(25) | BIT(24))
250 #define BIT_SET_OFDM0_EXTS_B(a, c, d) (((a) << 27) | ((c) << 25) | ((d) << 24))
251 #define REG_OFDM0_XAAGC1 0x0c50
252 #define REG_OFDM0_XBAGC1 0x0c58
253 #define REG_AGCRSSI 0x0c78
254 #define REG_OFDM_0_XA_TX_IQ_IMBALANCE 0x0c80
255 #define REG_OFDM_0_XB_TX_IQ_IMBALANCE 0x0c88
256 #define BIT_MASK_TXIQ_ELM_A 0x03ff
257 #define BIT_SET_TXIQ_ELM_ACD(a, c, d) (((d) << 22) | (((c) & 0x3F) << 16) | \
258 ((a) & 0x03ff))
259 #define BIT_MASK_TXIQ_ELM_C GENMASK(21, 16)
260 #define BIT_SET_TXIQ_ELM_C2(c) ((c) & 0x3F)
261 #define BIT_MASK_TXIQ_ELM_D GENMASK(31, 22)
262 #define REG_TXIQK_MATRIXA_LSB2_11N 0x0c94
263 #define BIT_SET_TXIQ_ELM_C1(c) (((c) & 0x000003C0) >> 6)
264 #define REG_RXIQK_MATRIX_LSB_11N 0x0ca0
265 #define BIT_MASK_RXIQ_S1_Y2 0xF0000000
266 #define BIT_SET_RXIQ_S1_Y2(y) (((y) >> 6) & 0xF)
267 #define REG_TXIQ_AB_S0 0x0cd0
268 #define BIT_MASK_TXIQ_A_S0 0x000007FE
269 #define BIT_MASK_TXIQ_A_EXT_S0 BIT(0)
270 #define BIT_MASK_TXIQ_B_S0 0x0007E000
271 #define REG_TXIQ_CD_S0 0x0cd4
272 #define BIT_MASK_TXIQ_C_S0 0x000007FE
273 #define BIT_MASK_TXIQ_C_EXT_S0 BIT(0)
274 #define BIT_MASK_TXIQ_D_S0 GENMASK(22, 13)
275 #define BIT_MASK_TXIQ_D_EXT_S0 BIT(12)
276 #define REG_RXIQ_AB_S0 0x0cd8
277 #define BIT_MASK_RXIQ_X_S0 0x000003FF
278 #define BIT_MASK_RXIQ_Y_S0 0x003FF000
279 #define REG_OFDM_FA_TYPE1_11N 0x0cf0
280 #define BIT_MASK_OFDM_FF_CNT GENMASK(15, 0)
281 #define BIT_MASK_OFDM_SF_CNT GENMASK(31, 16)
282 #define REG_OFDM_FA_RSTD_11N 0x0d00
283 #define BIT_MASK_OFDM_FA_RST1 BIT(27)
284 #define BIT_MASK_OFDM_FA_KEEP1 BIT(31)
285 #define REG_CTX 0x0d03
286 #define BIT_MASK_CTX_TYPE GENMASK(6, 4)
287 #define REG_OFDM1_CFOTRK 0x0d2c
288 #define BIT_EN_CFOTRK BIT(28)
289 #define REG_OFDM1_CSI1 0x0d40
290 #define REG_OFDM1_CSI2 0x0d44
291 #define REG_OFDM1_CSI3 0x0d48
292 #define REG_OFDM1_CSI4 0x0d4c
293 #define REG_OFDM_FA_TYPE2_11N 0x0da0
294 #define BIT_MASK_OFDM_CCA_CNT GENMASK(15, 0)
295 #define BIT_MASK_OFDM_PF_CNT GENMASK(31, 16)
296 #define REG_OFDM_FA_TYPE3_11N 0x0da4
297 #define BIT_MASK_OFDM_RI_CNT GENMASK(15, 0)
298 #define BIT_MASK_OFDM_CRC_CNT GENMASK(31, 16)
299 #define REG_OFDM_FA_TYPE4_11N 0x0da8
300 #define BIT_MASK_OFDM_MNS_CNT GENMASK(15, 0)
301 #define REG_FPGA0_IQK_11N 0x0e28
302 #define BIT_MASK_IQK_MOD 0xffffff00
303 #define EN_IQK 0x808000
304 #define RST_IQK 0x000000
305 #define REG_TXIQK_TONE_A_11N 0x0e30
306 #define REG_RXIQK_TONE_A_11N 0x0e34
307 #define REG_TXIQK_PI_A_11N 0x0e38
308 #define REG_RXIQK_PI_A_11N 0x0e3c
309 #define REG_TXIQK_11N 0x0e40
310 #define BIT_SET_TXIQK_11N(x, y) (0x80007C00 | ((x) << 16) | (y))
311 #define REG_RXIQK_11N 0x0e44
312 #define REG_IQK_AGC_PTS_11N 0x0e48
313 #define REG_IQK_AGC_RSP_11N 0x0e4c
314 #define REG_TX_IQK_TONE_B 0x0e50
315 #define REG_RX_IQK_TONE_B 0x0e54
316 #define REG_TXIQK_PI_B 0x0e58
317 #define REG_RXIQK_PI_B 0x0e5c
318 #define REG_IQK_RES_TX 0x0e94
319 #define BIT_MASK_RES_TX GENMASK(25, 16)
320 #define REG_IQK_RES_TY 0x0e9c
321 #define BIT_MASK_RES_TY GENMASK(25, 16)
322 #define REG_IQK_RES_RX 0x0ea4
323 #define BIT_MASK_RES_RX GENMASK(25, 16)
324 #define REG_IQK_RES_RY 0x0eac
325 #define BIT_IQK_TX_FAIL BIT(28)
326 #define BIT_IQK_RX_FAIL BIT(27)
327 #define BIT_IQK_DONE BIT(26)
328 #define BIT_MASK_RES_RY GENMASK(25, 16)
329 #define REG_PAGE_F_RST_11N 0x0f14
330 #define BIT_MASK_F_RST_ALL BIT(16)
331 #define REG_IGI_C_11N 0x0f84
332 #define REG_IGI_D_11N 0x0f88
333 #define REG_HT_CRC32_CNT_11N 0x0f90
334 #define BIT_MASK_HT_CRC_OK GENMASK(15, 0)
335 #define BIT_MASK_HT_CRC_ERR GENMASK(31, 16)
336 #define REG_OFDM_CRC32_CNT_11N 0x0f94
337 #define BIT_MASK_OFDM_LCRC_OK GENMASK(15, 0)
338 #define BIT_MASK_OFDM_LCRC_ERR GENMASK(31, 16)
339 #define REG_HT_CRC32_CNT_11N_AGG 0x0fb8
340
341 #define OFDM_SWING_A(swing) FIELD_GET(GENMASK(9, 0), swing)
342 #define OFDM_SWING_B(swing) FIELD_GET(GENMASK(15, 10), swing)
343 #define OFDM_SWING_C(swing) FIELD_GET(GENMASK(21, 16), swing)
344 #define OFDM_SWING_D(swing) FIELD_GET(GENMASK(31, 22), swing)
345
iqkxy_to_s32(s32 val)346 static inline s32 iqkxy_to_s32(s32 val)
347 {
348 /* val is Q10.8 */
349 return sign_extend32(val, 9);
350 }
351
iqk_mult(s32 x,s32 y,s32 * ext)352 static inline s32 iqk_mult(s32 x, s32 y, s32 *ext)
353 {
354 /* x, y and return value are Q10.8 */
355 s32 t;
356
357 t = x * y;
358 if (ext)
359 *ext = (t >> 7) & 0x1; /* Q.16 --> Q.9; get LSB of Q.9 */
360
361 return (t >> 8); /* Q.16 --> Q.8 */
362 }
363
364 static inline
rtw8723x_debug_txpwr_limit(struct rtw_dev * rtwdev,struct rtw_txpwr_idx * table,int tx_path_count)365 void rtw8723x_debug_txpwr_limit(struct rtw_dev *rtwdev,
366 struct rtw_txpwr_idx *table,
367 int tx_path_count)
368 {
369 rtw8723x_common.debug_txpwr_limit(rtwdev, table, tx_path_count);
370 }
371
rtw8723x_lck(struct rtw_dev * rtwdev)372 static inline void rtw8723x_lck(struct rtw_dev *rtwdev)
373 {
374 rtw8723x_common.lck(rtwdev);
375 }
376
rtw8723x_read_efuse(struct rtw_dev * rtwdev,u8 * log_map)377 static inline int rtw8723x_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)
378 {
379 return rtw8723x_common.read_efuse(rtwdev, log_map);
380 }
381
rtw8723x_mac_init(struct rtw_dev * rtwdev)382 static inline int rtw8723x_mac_init(struct rtw_dev *rtwdev)
383 {
384 return rtw8723x_common.mac_init(rtwdev);
385 }
386
rtw8723x_mac_postinit(struct rtw_dev * rtwdev)387 static inline int rtw8723x_mac_postinit(struct rtw_dev *rtwdev)
388 {
389 return rtw8723x_common.mac_postinit(rtwdev);
390 }
391
rtw8723x_cfg_ldo25(struct rtw_dev * rtwdev,bool enable)392 static inline void rtw8723x_cfg_ldo25(struct rtw_dev *rtwdev, bool enable)
393 {
394 rtw8723x_common.cfg_ldo25(rtwdev, enable);
395 }
396
rtw8723x_set_tx_power_index(struct rtw_dev * rtwdev)397 static inline void rtw8723x_set_tx_power_index(struct rtw_dev *rtwdev)
398 {
399 rtw8723x_common.set_tx_power_index(rtwdev);
400 }
401
rtw8723x_efuse_grant(struct rtw_dev * rtwdev,bool on)402 static inline void rtw8723x_efuse_grant(struct rtw_dev *rtwdev, bool on)
403 {
404 rtw8723x_common.efuse_grant(rtwdev, on);
405 }
406
rtw8723x_false_alarm_statistics(struct rtw_dev * rtwdev)407 static inline void rtw8723x_false_alarm_statistics(struct rtw_dev *rtwdev)
408 {
409 rtw8723x_common.false_alarm_statistics(rtwdev);
410 }
411
412 static inline
rtw8723x_iqk_backup_regs(struct rtw_dev * rtwdev,struct rtw8723x_iqk_backup_regs * backup)413 void rtw8723x_iqk_backup_regs(struct rtw_dev *rtwdev,
414 struct rtw8723x_iqk_backup_regs *backup)
415 {
416 rtw8723x_common.iqk_backup_regs(rtwdev, backup);
417 }
418
419 static inline
rtw8723x_iqk_restore_regs(struct rtw_dev * rtwdev,const struct rtw8723x_iqk_backup_regs * backup)420 void rtw8723x_iqk_restore_regs(struct rtw_dev *rtwdev,
421 const struct rtw8723x_iqk_backup_regs *backup)
422 {
423 rtw8723x_common.iqk_restore_regs(rtwdev, backup);
424 }
425
426 static inline
rtw8723x_iqk_similarity_cmp(struct rtw_dev * rtwdev,s32 result[][IQK_NR],u8 c1,u8 c2)427 bool rtw8723x_iqk_similarity_cmp(struct rtw_dev *rtwdev, s32 result[][IQK_NR],
428 u8 c1, u8 c2)
429 {
430 return rtw8723x_common.iqk_similarity_cmp(rtwdev, result, c1, c2);
431 }
432
rtw8723x_pwrtrack_get_limit_ofdm(struct rtw_dev * rtwdev)433 static inline u8 rtw8723x_pwrtrack_get_limit_ofdm(struct rtw_dev *rtwdev)
434 {
435 return rtw8723x_common.pwrtrack_get_limit_ofdm(rtwdev);
436 }
437
438 static inline
rtw8723x_pwrtrack_set_xtal(struct rtw_dev * rtwdev,u8 therm_path,u8 delta)439 void rtw8723x_pwrtrack_set_xtal(struct rtw_dev *rtwdev, u8 therm_path,
440 u8 delta)
441 {
442 rtw8723x_common.pwrtrack_set_xtal(rtwdev, therm_path, delta);
443 }
444
rtw8723x_coex_cfg_init(struct rtw_dev * rtwdev)445 static inline void rtw8723x_coex_cfg_init(struct rtw_dev *rtwdev)
446 {
447 rtw8723x_common.coex_cfg_init(rtwdev);
448 }
449
450 static inline
rtw8723x_fill_txdesc_checksum(struct rtw_dev * rtwdev,struct rtw_tx_pkt_info * pkt_info,u8 * txdesc)451 void rtw8723x_fill_txdesc_checksum(struct rtw_dev *rtwdev,
452 struct rtw_tx_pkt_info *pkt_info,
453 u8 *txdesc)
454 {
455 rtw8723x_common.fill_txdesc_checksum(rtwdev, pkt_info, txdesc);
456 }
457
458 /* IQK helper functions, defined as inline so they can be shared
459 * without needing an EXPORT_SYMBOL each.
460 */
461 static inline void
rtw8723x_iqk_backup_path_ctrl(struct rtw_dev * rtwdev,struct rtw8723x_iqk_backup_regs * backup)462 rtw8723x_iqk_backup_path_ctrl(struct rtw_dev *rtwdev,
463 struct rtw8723x_iqk_backup_regs *backup)
464 {
465 backup->btg_sel = rtw_read8(rtwdev, REG_BTG_SEL);
466 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] original 0x67 = 0x%x\n",
467 backup->btg_sel);
468 }
469
rtw8723x_iqk_config_path_ctrl(struct rtw_dev * rtwdev)470 static inline void rtw8723x_iqk_config_path_ctrl(struct rtw_dev *rtwdev)
471 {
472 rtw_write32_mask(rtwdev, REG_PAD_CTRL1, BIT_BT_BTG_SEL, 0x1);
473 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] set 0x67 = 0x%x\n",
474 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3));
475 }
476
477 static inline void
rtw8723x_iqk_restore_path_ctrl(struct rtw_dev * rtwdev,const struct rtw8723x_iqk_backup_regs * backup)478 rtw8723x_iqk_restore_path_ctrl(struct rtw_dev *rtwdev,
479 const struct rtw8723x_iqk_backup_regs *backup)
480 {
481 rtw_write8(rtwdev, REG_BTG_SEL, backup->btg_sel);
482 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] restore 0x67 = 0x%x\n",
483 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3));
484 }
485
486 static inline void
rtw8723x_iqk_backup_lte_path_gnt(struct rtw_dev * rtwdev,struct rtw8723x_iqk_backup_regs * backup)487 rtw8723x_iqk_backup_lte_path_gnt(struct rtw_dev *rtwdev,
488 struct rtw8723x_iqk_backup_regs *backup)
489 {
490 backup->lte_path = rtw_read32(rtwdev, REG_LTECOEX_PATH_CONTROL);
491 rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0x800f0038);
492 mdelay(1);
493 backup->lte_gnt = rtw_read32(rtwdev, REG_LTECOEX_READ_DATA);
494 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] OriginalGNT = 0x%x\n",
495 backup->lte_gnt);
496 }
497
498 static inline void
rtw8723x_iqk_config_lte_path_gnt(struct rtw_dev * rtwdev,u32 write_data)499 rtw8723x_iqk_config_lte_path_gnt(struct rtw_dev *rtwdev,
500 u32 write_data)
501 {
502 rtw_write32(rtwdev, REG_LTECOEX_WRITE_DATA, write_data);
503 rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0xc0020038);
504 rtw_write32_mask(rtwdev, REG_LTECOEX_PATH_CONTROL,
505 BIT_LTE_MUX_CTRL_PATH, 0x1);
506 }
507
508 static inline void
rtw8723x_iqk_restore_lte_path_gnt(struct rtw_dev * rtwdev,const struct rtw8723x_iqk_backup_regs * bak)509 rtw8723x_iqk_restore_lte_path_gnt(struct rtw_dev *rtwdev,
510 const struct rtw8723x_iqk_backup_regs *bak)
511 {
512 rtw_write32(rtwdev, REG_LTECOEX_WRITE_DATA, bak->lte_gnt);
513 rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0xc00f0038);
514 rtw_write32(rtwdev, REG_LTECOEX_PATH_CONTROL, bak->lte_path);
515 }
516
517 /* set all ADDA registers to the given value */
rtw8723x_iqk_path_adda_on(struct rtw_dev * rtwdev,u32 value)518 static inline void rtw8723x_iqk_path_adda_on(struct rtw_dev *rtwdev, u32 value)
519 {
520 for (int i = 0; i < RTW8723X_IQK_ADDA_REG_NUM; i++)
521 rtw_write32(rtwdev, rtw8723x_common.iqk_adda_regs[i], value);
522 }
523
524 #endif /* __RTW8723X_H__ */
525