1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Xilinx ASoC audio formatter support 4 // 5 // Copyright (C) 2018 Xilinx, Inc. 6 // 7 // Author: Maruthi Srinivas Bayyavarapu <maruthis@xilinx.com> 8 9 #include <linux/clk.h> 10 #include <linux/io.h> 11 #include <linux/module.h> 12 #include <linux/sizes.h> 13 14 #include <sound/asoundef.h> 15 #include <sound/soc.h> 16 #include <sound/pcm_params.h> 17 18 #define DRV_NAME "xlnx_formatter_pcm" 19 20 #define XLNX_S2MM_OFFSET 0 21 #define XLNX_MM2S_OFFSET 0x100 22 23 #define XLNX_AUD_CORE_CONFIG 0x4 24 #define XLNX_AUD_CTRL 0x10 25 #define XLNX_AUD_STS 0x14 26 27 #define AUD_CTRL_RESET_MASK BIT(1) 28 #define AUD_CFG_MM2S_MASK BIT(15) 29 #define AUD_CFG_S2MM_MASK BIT(31) 30 31 #define XLNX_AUD_FS_MULTIPLIER 0x18 32 #define XLNX_AUD_PERIOD_CONFIG 0x1C 33 #define XLNX_AUD_BUFF_ADDR_LSB 0x20 34 #define XLNX_AUD_BUFF_ADDR_MSB 0x24 35 #define XLNX_AUD_XFER_COUNT 0x28 36 #define XLNX_AUD_CH_STS_START 0x2C 37 #define XLNX_BYTES_PER_CH 0x44 38 #define XLNX_AUD_ALIGN_BYTES 64 39 40 #define AUD_STS_IOC_IRQ_MASK BIT(31) 41 #define AUD_STS_CH_STS_MASK BIT(29) 42 #define AUD_CTRL_IOC_IRQ_MASK BIT(13) 43 #define AUD_CTRL_TOUT_IRQ_MASK BIT(14) 44 #define AUD_CTRL_DMA_EN_MASK BIT(0) 45 46 #define CFG_MM2S_CH_MASK GENMASK(11, 8) 47 #define CFG_MM2S_CH_SHIFT 8 48 #define CFG_MM2S_XFER_MASK GENMASK(14, 13) 49 #define CFG_MM2S_XFER_SHIFT 13 50 #define CFG_MM2S_PKG_MASK BIT(12) 51 52 #define CFG_S2MM_CH_MASK GENMASK(27, 24) 53 #define CFG_S2MM_CH_SHIFT 24 54 #define CFG_S2MM_XFER_MASK GENMASK(30, 29) 55 #define CFG_S2MM_XFER_SHIFT 29 56 #define CFG_S2MM_PKG_MASK BIT(28) 57 58 #define AUD_CTRL_DATA_WIDTH_SHIFT 16 59 #define AUD_CTRL_ACTIVE_CH_SHIFT 19 60 #define PERIOD_CFG_PERIODS_SHIFT 16 61 62 #define PERIODS_MIN 2 63 #define PERIODS_MAX 6 64 #define PERIOD_BYTES_MIN 192 65 #define PERIOD_BYTES_MAX (50 * 1024) 66 #define XLNX_PARAM_UNKNOWN 0 67 68 enum bit_depth { 69 BIT_DEPTH_8, 70 BIT_DEPTH_16, 71 BIT_DEPTH_20, 72 BIT_DEPTH_24, 73 BIT_DEPTH_32, 74 }; 75 76 struct xlnx_pcm_drv_data { 77 void __iomem *mmio; 78 bool s2mm_presence; 79 bool mm2s_presence; 80 int s2mm_irq; 81 int mm2s_irq; 82 struct snd_pcm_substream *play_stream; 83 struct snd_pcm_substream *capture_stream; 84 struct clk *axi_clk; 85 unsigned int sysclk; 86 }; 87 88 /* 89 * struct xlnx_pcm_stream_param - stream configuration 90 * @mmio: base address offset 91 * @interleaved: audio channels arrangement in buffer 92 * @xfer_mode: data formatting mode during transfer 93 * @ch_limit: Maximum channels supported 94 * @buffer_size: stream ring buffer size 95 */ 96 struct xlnx_pcm_stream_param { 97 void __iomem *mmio; 98 bool interleaved; 99 u32 xfer_mode; 100 u32 ch_limit; 101 u64 buffer_size; 102 }; 103 104 static const struct snd_pcm_hardware xlnx_pcm_hardware = { 105 .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER | 106 SNDRV_PCM_INFO_BATCH | SNDRV_PCM_INFO_PAUSE | 107 SNDRV_PCM_INFO_RESUME, 108 .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | 109 SNDRV_PCM_FMTBIT_S24_LE, 110 .channels_min = 2, 111 .channels_max = 2, 112 .rates = SNDRV_PCM_RATE_8000_192000, 113 .rate_min = 8000, 114 .rate_max = 192000, 115 .buffer_bytes_max = PERIODS_MAX * PERIOD_BYTES_MAX, 116 .period_bytes_min = PERIOD_BYTES_MIN, 117 .period_bytes_max = PERIOD_BYTES_MAX, 118 .periods_min = PERIODS_MIN, 119 .periods_max = PERIODS_MAX, 120 }; 121 122 enum { 123 AES_TO_AES, 124 AES_TO_PCM, 125 PCM_TO_PCM, 126 PCM_TO_AES 127 }; 128 129 static void xlnx_parse_aes_params(u32 chsts_reg1_val, u32 chsts_reg2_val, 130 struct device *dev) 131 { 132 u32 padded, srate, bit_depth, status[2]; 133 134 if (chsts_reg1_val & IEC958_AES0_PROFESSIONAL) { 135 status[0] = chsts_reg1_val & 0xff; 136 status[1] = (chsts_reg1_val >> 16) & 0xff; 137 138 switch (status[0] & IEC958_AES0_PRO_FS) { 139 case IEC958_AES0_PRO_FS_44100: 140 srate = 44100; 141 break; 142 case IEC958_AES0_PRO_FS_48000: 143 srate = 48000; 144 break; 145 case IEC958_AES0_PRO_FS_32000: 146 srate = 32000; 147 break; 148 case IEC958_AES0_PRO_FS_NOTID: 149 default: 150 srate = XLNX_PARAM_UNKNOWN; 151 break; 152 } 153 154 switch (status[1] & IEC958_AES2_PRO_SBITS) { 155 case IEC958_AES2_PRO_WORDLEN_NOTID: 156 case IEC958_AES2_PRO_SBITS_20: 157 padded = 0; 158 break; 159 case IEC958_AES2_PRO_SBITS_24: 160 padded = 4; 161 break; 162 default: 163 bit_depth = XLNX_PARAM_UNKNOWN; 164 goto log_params; 165 } 166 167 switch (status[1] & IEC958_AES2_PRO_WORDLEN) { 168 case IEC958_AES2_PRO_WORDLEN_20_16: 169 bit_depth = 16 + padded; 170 break; 171 case IEC958_AES2_PRO_WORDLEN_22_18: 172 bit_depth = 18 + padded; 173 break; 174 case IEC958_AES2_PRO_WORDLEN_23_19: 175 bit_depth = 19 + padded; 176 break; 177 case IEC958_AES2_PRO_WORDLEN_24_20: 178 bit_depth = 20 + padded; 179 break; 180 case IEC958_AES2_PRO_WORDLEN_NOTID: 181 default: 182 bit_depth = XLNX_PARAM_UNKNOWN; 183 break; 184 } 185 186 } else { 187 status[0] = (chsts_reg1_val >> 24) & 0xff; 188 status[1] = chsts_reg2_val & 0xff; 189 190 switch (status[0] & IEC958_AES3_CON_FS) { 191 case IEC958_AES3_CON_FS_44100: 192 srate = 44100; 193 break; 194 case IEC958_AES3_CON_FS_48000: 195 srate = 48000; 196 break; 197 case IEC958_AES3_CON_FS_32000: 198 srate = 32000; 199 break; 200 default: 201 srate = XLNX_PARAM_UNKNOWN; 202 break; 203 } 204 205 if (status[1] & IEC958_AES4_CON_MAX_WORDLEN_24) 206 padded = 4; 207 else 208 padded = 0; 209 210 switch (status[1] & IEC958_AES4_CON_WORDLEN) { 211 case IEC958_AES4_CON_WORDLEN_20_16: 212 bit_depth = 16 + padded; 213 break; 214 case IEC958_AES4_CON_WORDLEN_22_18: 215 bit_depth = 18 + padded; 216 break; 217 case IEC958_AES4_CON_WORDLEN_23_19: 218 bit_depth = 19 + padded; 219 break; 220 case IEC958_AES4_CON_WORDLEN_24_20: 221 bit_depth = 20 + padded; 222 break; 223 case IEC958_AES4_CON_WORDLEN_21_17: 224 bit_depth = 17 + padded; 225 break; 226 case IEC958_AES4_CON_WORDLEN_NOTID: 227 default: 228 bit_depth = XLNX_PARAM_UNKNOWN; 229 break; 230 } 231 } 232 233 log_params: 234 if (srate != XLNX_PARAM_UNKNOWN) 235 dev_info(dev, "sample rate = %d\n", srate); 236 else 237 dev_info(dev, "sample rate = unknown\n"); 238 239 if (bit_depth != XLNX_PARAM_UNKNOWN) 240 dev_info(dev, "bit_depth = %d\n", bit_depth); 241 else 242 dev_info(dev, "bit_depth = unknown\n"); 243 } 244 245 static int xlnx_formatter_pcm_reset(void __iomem *mmio_base) 246 { 247 u32 val, retries = 0; 248 249 val = readl(mmio_base + XLNX_AUD_CTRL); 250 val |= AUD_CTRL_RESET_MASK; 251 writel(val, mmio_base + XLNX_AUD_CTRL); 252 253 val = readl(mmio_base + XLNX_AUD_CTRL); 254 /* Poll for maximum timeout of approximately 100ms (1 * 100)*/ 255 while ((val & AUD_CTRL_RESET_MASK) && (retries < 100)) { 256 mdelay(1); 257 retries++; 258 val = readl(mmio_base + XLNX_AUD_CTRL); 259 } 260 if (val & AUD_CTRL_RESET_MASK) 261 return -ENODEV; 262 263 return 0; 264 } 265 266 static void xlnx_formatter_disable_irqs(void __iomem *mmio_base, int stream) 267 { 268 u32 val; 269 270 val = readl(mmio_base + XLNX_AUD_CTRL); 271 val &= ~AUD_CTRL_IOC_IRQ_MASK; 272 if (stream == SNDRV_PCM_STREAM_CAPTURE) 273 val &= ~AUD_CTRL_TOUT_IRQ_MASK; 274 275 writel(val, mmio_base + XLNX_AUD_CTRL); 276 } 277 278 static irqreturn_t xlnx_mm2s_irq_handler(int irq, void *arg) 279 { 280 u32 val; 281 void __iomem *reg; 282 struct xlnx_pcm_drv_data *adata = arg; 283 284 reg = adata->mmio + XLNX_MM2S_OFFSET + XLNX_AUD_STS; 285 val = readl(reg); 286 if (val & AUD_STS_IOC_IRQ_MASK) { 287 writel(val & AUD_STS_IOC_IRQ_MASK, reg); 288 if (adata->play_stream) 289 snd_pcm_period_elapsed(adata->play_stream); 290 return IRQ_HANDLED; 291 } 292 293 return IRQ_NONE; 294 } 295 296 static irqreturn_t xlnx_s2mm_irq_handler(int irq, void *arg) 297 { 298 u32 val; 299 void __iomem *reg; 300 struct xlnx_pcm_drv_data *adata = arg; 301 302 reg = adata->mmio + XLNX_S2MM_OFFSET + XLNX_AUD_STS; 303 val = readl(reg); 304 if (val & AUD_STS_IOC_IRQ_MASK) { 305 writel(val & AUD_STS_IOC_IRQ_MASK, reg); 306 if (adata->capture_stream) 307 snd_pcm_period_elapsed(adata->capture_stream); 308 return IRQ_HANDLED; 309 } 310 311 return IRQ_NONE; 312 } 313 314 static int xlnx_formatter_set_sysclk(struct snd_soc_component *component, 315 int clk_id, int source, unsigned int freq, int dir) 316 { 317 struct xlnx_pcm_drv_data *adata = dev_get_drvdata(component->dev); 318 319 adata->sysclk = freq; 320 return 0; 321 } 322 323 static int xlnx_formatter_pcm_open(struct snd_soc_component *component, 324 struct snd_pcm_substream *substream) 325 { 326 int err; 327 u32 val, data_format_mode; 328 u32 ch_count_mask, ch_count_shift, data_xfer_mode, data_xfer_shift; 329 struct xlnx_pcm_stream_param *stream_data; 330 struct snd_pcm_runtime *runtime = substream->runtime; 331 struct xlnx_pcm_drv_data *adata = dev_get_drvdata(component->dev); 332 333 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK && 334 !adata->mm2s_presence) 335 return -ENODEV; 336 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE && 337 !adata->s2mm_presence) 338 return -ENODEV; 339 340 stream_data = kzalloc_obj(*stream_data); 341 if (!stream_data) 342 return -ENOMEM; 343 344 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 345 ch_count_mask = CFG_MM2S_CH_MASK; 346 ch_count_shift = CFG_MM2S_CH_SHIFT; 347 data_xfer_mode = CFG_MM2S_XFER_MASK; 348 data_xfer_shift = CFG_MM2S_XFER_SHIFT; 349 data_format_mode = CFG_MM2S_PKG_MASK; 350 stream_data->mmio = adata->mmio + XLNX_MM2S_OFFSET; 351 adata->play_stream = substream; 352 353 } else { 354 ch_count_mask = CFG_S2MM_CH_MASK; 355 ch_count_shift = CFG_S2MM_CH_SHIFT; 356 data_xfer_mode = CFG_S2MM_XFER_MASK; 357 data_xfer_shift = CFG_S2MM_XFER_SHIFT; 358 data_format_mode = CFG_S2MM_PKG_MASK; 359 stream_data->mmio = adata->mmio + XLNX_S2MM_OFFSET; 360 adata->capture_stream = substream; 361 } 362 363 val = readl(adata->mmio + XLNX_AUD_CORE_CONFIG); 364 365 if (!(val & data_format_mode)) 366 stream_data->interleaved = true; 367 368 stream_data->xfer_mode = (val & data_xfer_mode) >> data_xfer_shift; 369 stream_data->ch_limit = (val & ch_count_mask) >> ch_count_shift; 370 dev_info(component->dev, 371 "stream %d : format = %d mode = %d ch_limit = %d\n", 372 substream->stream, stream_data->interleaved, 373 stream_data->xfer_mode, stream_data->ch_limit); 374 375 snd_soc_set_runtime_hwparams(substream, &xlnx_pcm_hardware); 376 runtime->private_data = stream_data; 377 378 /* Resize the period bytes as divisible by 64 */ 379 err = snd_pcm_hw_constraint_step(runtime, 0, 380 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 381 XLNX_AUD_ALIGN_BYTES); 382 if (err) { 383 dev_err(component->dev, 384 "Unable to set constraint on period bytes\n"); 385 goto error; 386 } 387 388 /* Resize the buffer bytes as divisible by 64 */ 389 err = snd_pcm_hw_constraint_step(runtime, 0, 390 SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 391 XLNX_AUD_ALIGN_BYTES); 392 if (err) { 393 dev_err(component->dev, 394 "Unable to set constraint on buffer bytes\n"); 395 goto error; 396 } 397 398 /* Set periods as integer multiple */ 399 err = snd_pcm_hw_constraint_integer(runtime, 400 SNDRV_PCM_HW_PARAM_PERIODS); 401 if (err < 0) { 402 dev_err(component->dev, 403 "Unable to set constraint on periods to be integer\n"); 404 goto error; 405 } 406 407 /* enable DMA IOC irq */ 408 val = readl(stream_data->mmio + XLNX_AUD_CTRL); 409 val |= AUD_CTRL_IOC_IRQ_MASK; 410 writel(val, stream_data->mmio + XLNX_AUD_CTRL); 411 412 return 0; 413 414 error: 415 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 416 adata->play_stream = NULL; 417 else 418 adata->capture_stream = NULL; 419 kfree(stream_data); 420 return err; 421 } 422 423 static int xlnx_formatter_pcm_close(struct snd_soc_component *component, 424 struct snd_pcm_substream *substream) 425 { 426 int ret; 427 struct xlnx_pcm_stream_param *stream_data = 428 substream->runtime->private_data; 429 430 ret = xlnx_formatter_pcm_reset(stream_data->mmio); 431 if (ret) { 432 dev_err(component->dev, "audio formatter reset failed\n"); 433 goto err_reset; 434 } 435 xlnx_formatter_disable_irqs(stream_data->mmio, substream->stream); 436 437 err_reset: 438 kfree(stream_data); 439 return 0; 440 } 441 442 static snd_pcm_uframes_t 443 xlnx_formatter_pcm_pointer(struct snd_soc_component *component, 444 struct snd_pcm_substream *substream) 445 { 446 u32 pos; 447 struct snd_pcm_runtime *runtime = substream->runtime; 448 struct xlnx_pcm_stream_param *stream_data = runtime->private_data; 449 450 pos = readl(stream_data->mmio + XLNX_AUD_XFER_COUNT); 451 452 if (pos >= stream_data->buffer_size) 453 pos = 0; 454 455 return bytes_to_frames(runtime, pos); 456 } 457 458 static int xlnx_formatter_pcm_hw_params(struct snd_soc_component *component, 459 struct snd_pcm_substream *substream, 460 struct snd_pcm_hw_params *params) 461 { 462 u32 low, high, active_ch, val, bytes_per_ch, bits_per_sample; 463 u32 aes_reg1_val, aes_reg2_val; 464 u64 size; 465 struct snd_pcm_runtime *runtime = substream->runtime; 466 struct xlnx_pcm_stream_param *stream_data = runtime->private_data; 467 struct xlnx_pcm_drv_data *adata = dev_get_drvdata(component->dev); 468 469 active_ch = params_channels(params); 470 if (active_ch > stream_data->ch_limit) 471 return -EINVAL; 472 473 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK && 474 adata->sysclk) { 475 unsigned int mclk_fs = adata->sysclk / params_rate(params); 476 477 if (adata->sysclk % params_rate(params) != 0) { 478 dev_warn(component->dev, "sysclk %u not divisible by rate %u\n", 479 adata->sysclk, params_rate(params)); 480 return -EINVAL; 481 } 482 483 writel(mclk_fs, stream_data->mmio + XLNX_AUD_FS_MULTIPLIER); 484 } 485 486 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE && 487 stream_data->xfer_mode == AES_TO_PCM) { 488 val = readl(stream_data->mmio + XLNX_AUD_STS); 489 if (val & AUD_STS_CH_STS_MASK) { 490 aes_reg1_val = readl(stream_data->mmio + 491 XLNX_AUD_CH_STS_START); 492 aes_reg2_val = readl(stream_data->mmio + 493 XLNX_AUD_CH_STS_START + 0x4); 494 495 xlnx_parse_aes_params(aes_reg1_val, aes_reg2_val, 496 component->dev); 497 } 498 } 499 500 size = params_buffer_bytes(params); 501 502 stream_data->buffer_size = size; 503 504 low = lower_32_bits(runtime->dma_addr); 505 high = upper_32_bits(runtime->dma_addr); 506 writel(low, stream_data->mmio + XLNX_AUD_BUFF_ADDR_LSB); 507 writel(high, stream_data->mmio + XLNX_AUD_BUFF_ADDR_MSB); 508 509 val = readl(stream_data->mmio + XLNX_AUD_CTRL); 510 bits_per_sample = params_width(params); 511 switch (bits_per_sample) { 512 case 8: 513 val |= (BIT_DEPTH_8 << AUD_CTRL_DATA_WIDTH_SHIFT); 514 break; 515 case 16: 516 val |= (BIT_DEPTH_16 << AUD_CTRL_DATA_WIDTH_SHIFT); 517 break; 518 case 20: 519 val |= (BIT_DEPTH_20 << AUD_CTRL_DATA_WIDTH_SHIFT); 520 break; 521 case 24: 522 val |= (BIT_DEPTH_24 << AUD_CTRL_DATA_WIDTH_SHIFT); 523 break; 524 case 32: 525 val |= (BIT_DEPTH_32 << AUD_CTRL_DATA_WIDTH_SHIFT); 526 break; 527 default: 528 return -EINVAL; 529 } 530 531 val |= active_ch << AUD_CTRL_ACTIVE_CH_SHIFT; 532 writel(val, stream_data->mmio + XLNX_AUD_CTRL); 533 534 val = (params_periods(params) << PERIOD_CFG_PERIODS_SHIFT) 535 | params_period_bytes(params); 536 writel(val, stream_data->mmio + XLNX_AUD_PERIOD_CONFIG); 537 bytes_per_ch = DIV_ROUND_UP(params_period_bytes(params), active_ch); 538 writel(bytes_per_ch, stream_data->mmio + XLNX_BYTES_PER_CH); 539 540 return 0; 541 } 542 543 static int xlnx_formatter_pcm_trigger(struct snd_soc_component *component, 544 struct snd_pcm_substream *substream, 545 int cmd) 546 { 547 u32 val; 548 struct xlnx_pcm_stream_param *stream_data = 549 substream->runtime->private_data; 550 551 switch (cmd) { 552 case SNDRV_PCM_TRIGGER_START: 553 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 554 case SNDRV_PCM_TRIGGER_RESUME: 555 val = readl(stream_data->mmio + XLNX_AUD_CTRL); 556 val |= AUD_CTRL_DMA_EN_MASK; 557 writel(val, stream_data->mmio + XLNX_AUD_CTRL); 558 break; 559 case SNDRV_PCM_TRIGGER_STOP: 560 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 561 case SNDRV_PCM_TRIGGER_SUSPEND: 562 val = readl(stream_data->mmio + XLNX_AUD_CTRL); 563 val &= ~AUD_CTRL_DMA_EN_MASK; 564 writel(val, stream_data->mmio + XLNX_AUD_CTRL); 565 break; 566 } 567 568 return 0; 569 } 570 571 static int xlnx_formatter_pcm_new(struct snd_soc_component *component, 572 struct snd_soc_pcm_runtime *rtd) 573 { 574 snd_pcm_set_managed_buffer_all(rtd->pcm, 575 SNDRV_DMA_TYPE_DEV, component->dev, 576 xlnx_pcm_hardware.buffer_bytes_max, 577 xlnx_pcm_hardware.buffer_bytes_max); 578 return 0; 579 } 580 581 static const struct snd_soc_component_driver xlnx_asoc_component = { 582 .name = DRV_NAME, 583 .set_sysclk = xlnx_formatter_set_sysclk, 584 .open = xlnx_formatter_pcm_open, 585 .close = xlnx_formatter_pcm_close, 586 .hw_params = xlnx_formatter_pcm_hw_params, 587 .trigger = xlnx_formatter_pcm_trigger, 588 .pointer = xlnx_formatter_pcm_pointer, 589 .pcm_new = xlnx_formatter_pcm_new, 590 }; 591 592 static int xlnx_formatter_pcm_probe(struct platform_device *pdev) 593 { 594 int ret; 595 u32 val; 596 struct xlnx_pcm_drv_data *aud_drv_data; 597 struct device *dev = &pdev->dev; 598 599 aud_drv_data = devm_kzalloc(dev, sizeof(*aud_drv_data), GFP_KERNEL); 600 if (!aud_drv_data) 601 return -ENOMEM; 602 603 aud_drv_data->axi_clk = devm_clk_get(dev, "s_axi_lite_aclk"); 604 if (IS_ERR(aud_drv_data->axi_clk)) { 605 ret = PTR_ERR(aud_drv_data->axi_clk); 606 dev_err(dev, "failed to get s_axi_lite_aclk(%d)\n", ret); 607 return ret; 608 } 609 ret = clk_prepare_enable(aud_drv_data->axi_clk); 610 if (ret) { 611 dev_err(dev, 612 "failed to enable s_axi_lite_aclk(%d)\n", ret); 613 return ret; 614 } 615 616 aud_drv_data->mmio = devm_platform_ioremap_resource(pdev, 0); 617 if (IS_ERR(aud_drv_data->mmio)) { 618 dev_err(dev, "audio formatter ioremap failed\n"); 619 ret = PTR_ERR(aud_drv_data->mmio); 620 goto clk_err; 621 } 622 623 val = readl(aud_drv_data->mmio + XLNX_AUD_CORE_CONFIG); 624 if (val & AUD_CFG_MM2S_MASK) { 625 aud_drv_data->mm2s_presence = true; 626 ret = xlnx_formatter_pcm_reset(aud_drv_data->mmio + 627 XLNX_MM2S_OFFSET); 628 if (ret) { 629 dev_err(dev, "audio formatter reset failed\n"); 630 goto clk_err; 631 } 632 xlnx_formatter_disable_irqs(aud_drv_data->mmio + 633 XLNX_MM2S_OFFSET, 634 SNDRV_PCM_STREAM_PLAYBACK); 635 636 aud_drv_data->mm2s_irq = platform_get_irq_byname(pdev, 637 "irq_mm2s"); 638 if (aud_drv_data->mm2s_irq < 0) { 639 ret = aud_drv_data->mm2s_irq; 640 goto clk_err; 641 } 642 ret = devm_request_irq(dev, aud_drv_data->mm2s_irq, 643 xlnx_mm2s_irq_handler, 0, 644 "xlnx_formatter_pcm_mm2s_irq", aud_drv_data); 645 if (ret) { 646 dev_err(dev, "xlnx audio mm2s irq request failed\n"); 647 goto clk_err; 648 } 649 } 650 if (val & AUD_CFG_S2MM_MASK) { 651 aud_drv_data->s2mm_presence = true; 652 ret = xlnx_formatter_pcm_reset(aud_drv_data->mmio + 653 XLNX_S2MM_OFFSET); 654 if (ret) { 655 dev_err(dev, "audio formatter reset failed\n"); 656 goto clk_err; 657 } 658 xlnx_formatter_disable_irqs(aud_drv_data->mmio + 659 XLNX_S2MM_OFFSET, 660 SNDRV_PCM_STREAM_CAPTURE); 661 662 aud_drv_data->s2mm_irq = platform_get_irq_byname(pdev, 663 "irq_s2mm"); 664 if (aud_drv_data->s2mm_irq < 0) { 665 ret = aud_drv_data->s2mm_irq; 666 goto clk_err; 667 } 668 ret = devm_request_irq(dev, aud_drv_data->s2mm_irq, 669 xlnx_s2mm_irq_handler, 0, 670 "xlnx_formatter_pcm_s2mm_irq", 671 aud_drv_data); 672 if (ret) { 673 dev_err(dev, "xlnx audio s2mm irq request failed\n"); 674 goto clk_err; 675 } 676 } 677 678 dev_set_drvdata(dev, aud_drv_data); 679 680 ret = devm_snd_soc_register_component(dev, &xlnx_asoc_component, 681 NULL, 0); 682 if (ret) { 683 dev_err(dev, "pcm platform device register failed\n"); 684 goto clk_err; 685 } 686 687 return 0; 688 689 clk_err: 690 clk_disable_unprepare(aud_drv_data->axi_clk); 691 return ret; 692 } 693 694 static void xlnx_formatter_pcm_remove(struct platform_device *pdev) 695 { 696 int ret = 0; 697 struct xlnx_pcm_drv_data *adata = dev_get_drvdata(&pdev->dev); 698 699 if (adata->s2mm_presence) 700 ret = xlnx_formatter_pcm_reset(adata->mmio + XLNX_S2MM_OFFSET); 701 702 /* Try MM2S reset, even if S2MM reset fails */ 703 if (adata->mm2s_presence) 704 ret = xlnx_formatter_pcm_reset(adata->mmio + XLNX_MM2S_OFFSET); 705 706 if (ret) 707 dev_err(&pdev->dev, "audio formatter reset failed\n"); 708 709 clk_disable_unprepare(adata->axi_clk); 710 } 711 712 static const struct of_device_id xlnx_formatter_pcm_of_match[] = { 713 { .compatible = "xlnx,audio-formatter-1.0"}, 714 {}, 715 }; 716 MODULE_DEVICE_TABLE(of, xlnx_formatter_pcm_of_match); 717 718 static struct platform_driver xlnx_formatter_pcm_driver = { 719 .probe = xlnx_formatter_pcm_probe, 720 .remove = xlnx_formatter_pcm_remove, 721 .driver = { 722 .name = DRV_NAME, 723 .of_match_table = xlnx_formatter_pcm_of_match, 724 }, 725 }; 726 727 module_platform_driver(xlnx_formatter_pcm_driver); 728 729 MODULE_DESCRIPTION("ASoC driver for Xilinx audio formatter"); 730 MODULE_AUTHOR("Maruthi Srinivas Bayyavarapu <maruthis@xilinx.com>"); 731 MODULE_LICENSE("GPL v2"); 732