1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* Copyright (C) 2024 ROHM Semiconductors */ 3 4 #ifndef __MFD_BD96801_H__ 5 #define __MFD_BD96801_H__ 6 7 #define BD96801_REG_SSCG_CTRL 0x09 8 #define BD96801_REG_SHD_INTB 0x20 9 #define BD96801_LDO5_VOL_LVL_REG 0x2c 10 #define BD96801_LDO6_VOL_LVL_REG 0x2d 11 #define BD96801_LDO7_VOL_LVL_REG 0x2e 12 #define BD96801_REG_BUCK_OVP 0x30 13 #define BD96801_REG_BUCK_OVD 0x35 14 #define BD96801_REG_LDO_OVP 0x31 15 #define BD96801_REG_LDO_OVD 0x36 16 #define BD96801_REG_BOOT_OVERTIME 0x3a 17 #define BD96801_REG_WD_TMO 0x40 18 #define BD96801_REG_WD_CONF 0x41 19 #define BD96801_REG_WD_FEED 0x42 20 #define BD96801_REG_WD_FAILCOUNT 0x43 21 #define BD96801_REG_WD_ASK 0x46 22 #define BD96801_REG_WD_STATUS 0x4a 23 #define BD96801_REG_PMIC_STATE 0x4f 24 #define BD96801_REG_EXT_STATE 0x50 25 26 #define BD96801_STATE_STBY 0x09 27 28 #define BD96801_LOCK_REG 0x04 29 #define BD96801_UNLOCK 0x9d 30 #define BD96801_LOCK 0x00 31 32 /* IRQ register area */ 33 #define BD96801_REG_INT_MAIN 0x51 34 35 /* 36 * The BD96801 has two physical IRQ lines, INTB and ERRB. 37 * 38 * The 'main status register' is located at 0x51. 39 * The ERRB status registers are located at 0x52 ... 0x5B 40 * INTB status registers are at range 0x5c ... 0x63 41 */ 42 #define BD96801_REG_INT_SYS_ERRB1 0x52 43 #define BD96801_REG_INT_BUCK2_ERRB 0x56 44 #define BD96801_REG_INT_SYS_INTB 0x5c 45 #define BD96801_REG_INT_BUCK2_INTB 0x5e 46 #define BD96801_REG_INT_LDO7_INTB 0x63 47 48 /* MASK registers */ 49 #define BD96801_REG_MASK_SYS_INTB 0x73 50 #define BD96801_REG_MASK_SYS_ERRB 0x69 51 52 #define BD96801_MAX_REGISTER 0x7a 53 54 #define BD96801_OTP_ERR_MASK BIT(0) 55 #define BD96801_DBIST_ERR_MASK BIT(1) 56 #define BD96801_EEP_ERR_MASK BIT(2) 57 #define BD96801_ABIST_ERR_MASK BIT(3) 58 #define BD96801_PRSTB_ERR_MASK BIT(4) 59 #define BD96801_DRMOS1_ERR_MASK BIT(5) 60 #define BD96801_DRMOS2_ERR_MASK BIT(6) 61 #define BD96801_SLAVE_ERR_MASK BIT(7) 62 #define BD96801_VREF_ERR_MASK BIT(0) 63 #define BD96801_TSD_ERR_MASK BIT(1) 64 #define BD96801_UVLO_ERR_MASK BIT(2) 65 #define BD96801_OVLO_ERR_MASK BIT(3) 66 #define BD96801_OSC_ERR_MASK BIT(4) 67 #define BD96801_PON_ERR_MASK BIT(5) 68 #define BD96801_POFF_ERR_MASK BIT(6) 69 #define BD96801_CMD_SHDN_ERR_MASK BIT(7) 70 #define BD96801_INT_PRSTB_WDT_ERR_MASK BIT(0) 71 #define BD96801_INT_CHIP_IF_ERR_MASK BIT(3) 72 #define BD96801_INT_SHDN_ERR_MASK BIT(7) 73 #define BD96801_OUT_PVIN_ERR_MASK BIT(0) 74 #define BD96801_OUT_OVP_ERR_MASK BIT(1) 75 #define BD96801_OUT_UVP_ERR_MASK BIT(2) 76 #define BD96801_OUT_SHDN_ERR_MASK BIT(7) 77 78 /* ERRB IRQs */ 79 enum { 80 /* Reg 0x52, 0x53, 0x54 - ERRB system IRQs */ 81 BD96801_OTP_ERR_STAT, 82 BD96801_DBIST_ERR_STAT, 83 BD96801_EEP_ERR_STAT, 84 BD96801_ABIST_ERR_STAT, 85 BD96801_PRSTB_ERR_STAT, 86 BD96801_DRMOS1_ERR_STAT, 87 BD96801_DRMOS2_ERR_STAT, 88 BD96801_SLAVE_ERR_STAT, 89 BD96801_VREF_ERR_STAT, 90 BD96801_TSD_ERR_STAT, 91 BD96801_UVLO_ERR_STAT, 92 BD96801_OVLO_ERR_STAT, 93 BD96801_OSC_ERR_STAT, 94 BD96801_PON_ERR_STAT, 95 BD96801_POFF_ERR_STAT, 96 BD96801_CMD_SHDN_ERR_STAT, 97 BD96801_INT_PRSTB_WDT_ERR, 98 BD96801_INT_CHIP_IF_ERR, 99 BD96801_INT_SHDN_ERR_STAT, 100 101 /* Reg 0x55 BUCK1 ERR IRQs */ 102 BD96801_BUCK1_PVIN_ERR_STAT, 103 BD96801_BUCK1_OVP_ERR_STAT, 104 BD96801_BUCK1_UVP_ERR_STAT, 105 BD96801_BUCK1_SHDN_ERR_STAT, 106 107 /* Reg 0x56 BUCK2 ERR IRQs */ 108 BD96801_BUCK2_PVIN_ERR_STAT, 109 BD96801_BUCK2_OVP_ERR_STAT, 110 BD96801_BUCK2_UVP_ERR_STAT, 111 BD96801_BUCK2_SHDN_ERR_STAT, 112 113 /* Reg 0x57 BUCK3 ERR IRQs */ 114 BD96801_BUCK3_PVIN_ERR_STAT, 115 BD96801_BUCK3_OVP_ERR_STAT, 116 BD96801_BUCK3_UVP_ERR_STAT, 117 BD96801_BUCK3_SHDN_ERR_STAT, 118 119 /* Reg 0x58 BUCK4 ERR IRQs */ 120 BD96801_BUCK4_PVIN_ERR_STAT, 121 BD96801_BUCK4_OVP_ERR_STAT, 122 BD96801_BUCK4_UVP_ERR_STAT, 123 BD96801_BUCK4_SHDN_ERR_STAT, 124 125 /* Reg 0x59 LDO5 ERR IRQs */ 126 BD96801_LDO5_PVIN_ERR_STAT, 127 BD96801_LDO5_OVP_ERR_STAT, 128 BD96801_LDO5_UVP_ERR_STAT, 129 BD96801_LDO5_SHDN_ERR_STAT, 130 131 /* Reg 0x5a LDO6 ERR IRQs */ 132 BD96801_LDO6_PVIN_ERR_STAT, 133 BD96801_LDO6_OVP_ERR_STAT, 134 BD96801_LDO6_UVP_ERR_STAT, 135 BD96801_LDO6_SHDN_ERR_STAT, 136 137 /* Reg 0x5b LDO7 ERR IRQs */ 138 BD96801_LDO7_PVIN_ERR_STAT, 139 BD96801_LDO7_OVP_ERR_STAT, 140 BD96801_LDO7_UVP_ERR_STAT, 141 BD96801_LDO7_SHDN_ERR_STAT, 142 }; 143 144 /* INTB IRQs */ 145 enum { 146 /* Reg 0x5c (System INTB) */ 147 BD96801_TW_STAT, 148 BD96801_WDT_ERR_STAT, 149 BD96801_I2C_ERR_STAT, 150 BD96801_CHIP_IF_ERR_STAT, 151 152 /* Reg 0x5d (BUCK1 INTB) */ 153 BD96801_BUCK1_OCPH_STAT, 154 BD96801_BUCK1_OCPL_STAT, 155 BD96801_BUCK1_OCPN_STAT, 156 BD96801_BUCK1_OVD_STAT, 157 BD96801_BUCK1_UVD_STAT, 158 BD96801_BUCK1_TW_CH_STAT, 159 160 /* Reg 0x5e (BUCK2 INTB) */ 161 BD96801_BUCK2_OCPH_STAT, 162 BD96801_BUCK2_OCPL_STAT, 163 BD96801_BUCK2_OCPN_STAT, 164 BD96801_BUCK2_OVD_STAT, 165 BD96801_BUCK2_UVD_STAT, 166 BD96801_BUCK2_TW_CH_STAT, 167 168 /* Reg 0x5f (BUCK3 INTB)*/ 169 BD96801_BUCK3_OCPH_STAT, 170 BD96801_BUCK3_OCPL_STAT, 171 BD96801_BUCK3_OCPN_STAT, 172 BD96801_BUCK3_OVD_STAT, 173 BD96801_BUCK3_UVD_STAT, 174 BD96801_BUCK3_TW_CH_STAT, 175 176 /* Reg 0x60 (BUCK4 INTB)*/ 177 BD96801_BUCK4_OCPH_STAT, 178 BD96801_BUCK4_OCPL_STAT, 179 BD96801_BUCK4_OCPN_STAT, 180 BD96801_BUCK4_OVD_STAT, 181 BD96801_BUCK4_UVD_STAT, 182 BD96801_BUCK4_TW_CH_STAT, 183 184 /* Reg 0x61 (LDO5 INTB) */ 185 BD96801_LDO5_OCPH_STAT, /* bit [0] */ 186 BD96801_LDO5_OVD_STAT, /* bit [3] */ 187 BD96801_LDO5_UVD_STAT, /* bit [4] */ 188 189 /* Reg 0x62 (LDO6 INTB) */ 190 BD96801_LDO6_OCPH_STAT, /* bit [0] */ 191 BD96801_LDO6_OVD_STAT, /* bit [3] */ 192 BD96801_LDO6_UVD_STAT, /* bit [4] */ 193 194 /* Reg 0x63 (LDO7 INTB) */ 195 BD96801_LDO7_OCPH_STAT, /* bit [0] */ 196 BD96801_LDO7_OVD_STAT, /* bit [3] */ 197 BD96801_LDO7_UVD_STAT, /* bit [4] */ 198 }; 199 200 /* IRQ MASKs */ 201 #define BD96801_TW_STAT_MASK BIT(0) 202 #define BD96801_WDT_ERR_STAT_MASK BIT(1) 203 #define BD96801_I2C_ERR_STAT_MASK BIT(2) 204 #define BD96801_CHIP_IF_ERR_STAT_MASK BIT(3) 205 206 #define BD96801_BUCK_OCPH_STAT_MASK BIT(0) 207 #define BD96801_BUCK_OCPL_STAT_MASK BIT(1) 208 #define BD96801_BUCK_OCPN_STAT_MASK BIT(2) 209 #define BD96801_BUCK_OVD_STAT_MASK BIT(3) 210 #define BD96801_BUCK_UVD_STAT_MASK BIT(4) 211 #define BD96801_BUCK_TW_CH_STAT_MASK BIT(5) 212 213 #define BD96801_LDO_OCPH_STAT_MASK BIT(0) 214 #define BD96801_LDO_OVD_STAT_MASK BIT(3) 215 #define BD96801_LDO_UVD_STAT_MASK BIT(4) 216 217 #endif 218