1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas I3C Controller driver 4 * Copyright (C) 2023-25 Renesas Electronics Corp. 5 * 6 * TODO: IBI support, HotJoin support, Target support 7 */ 8 9 #include <linux/bitfield.h> 10 #include <linux/bitops.h> 11 #include <linux/cleanup.h> 12 #include <linux/clk.h> 13 #include <linux/completion.h> 14 #include <linux/err.h> 15 #include <linux/errno.h> 16 #include <linux/i2c.h> 17 #include <linux/i3c/master.h> 18 #include <linux/interrupt.h> 19 #include <linux/ioport.h> 20 #include <linux/iopoll.h> 21 #include <linux/list.h> 22 #include <linux/module.h> 23 #include <linux/of.h> 24 #include <linux/platform_device.h> 25 #include <linux/reset.h> 26 #include <linux/slab.h> 27 #include "../internals.h" 28 29 #define PRTS 0x00 30 #define PRTS_PRTMD BIT(0) 31 32 #define BCTL 0x14 33 #define BCTL_INCBA BIT(0) 34 #define BCTL_HJACKCTL BIT(8) 35 #define BCTL_ABT BIT(29) 36 #define BCTL_BUSE BIT(31) 37 38 #define MSDVAD 0x18 39 #define MSDVAD_MDYAD(x) FIELD_PREP(GENMASK(21, 16), x) 40 #define MSDVAD_MDYADV BIT(31) 41 42 #define RSTCTL 0x20 43 #define RSTCTL_RI3CRST BIT(0) 44 #define RSTCTL_INTLRST BIT(16) 45 46 #define INST 0x30 47 48 #define IBINCTL 0x58 49 #define IBINCTL_NRHJCTL BIT(0) 50 #define IBINCTL_NRMRCTL BIT(1) 51 #define IBINCTL_NRSIRCTL BIT(3) 52 53 #define SVCTL 0x64 54 55 #define REFCKCTL 0x70 56 #define REFCKCTL_IREFCKS(x) FIELD_PREP(GENMASK(2, 0), x) 57 58 #define STDBR 0x74 59 #define STDBR_SBRLO(cond, x) FIELD_PREP(GENMASK(7, 0), (x) >> (cond)) 60 #define STDBR_SBRHO(cond, x) FIELD_PREP(GENMASK(15, 8), (x) >> (cond)) 61 #define STDBR_SBRLP(x) FIELD_PREP(GENMASK(21, 16), x) 62 #define STDBR_SBRHP(x) FIELD_PREP(GENMASK(29, 24), x) 63 #define STDBR_DSBRPO BIT(31) 64 65 #define EXTBR 0x78 66 #define EXTBR_EBRLO(x) FIELD_PREP(GENMASK(7, 0), x) 67 #define EXTBR_EBRHO(x) FIELD_PREP(GENMASK(15, 8), x) 68 #define EXTBR_EBRLP(x) FIELD_PREP(GENMASK(21, 16), x) 69 #define EXTBR_EBRHP(x) FIELD_PREP(GENMASK(29, 24), x) 70 71 #define BFRECDT 0x7c 72 #define BFRECDT_FRECYC(x) FIELD_PREP(GENMASK(8, 0), x) 73 74 #define BAVLCDT 0x80 75 #define BAVLCDT_AVLCYC(x) FIELD_PREP(GENMASK(8, 0), x) 76 77 #define BIDLCDT 0x84 78 #define BIDLCDT_IDLCYC(x) FIELD_PREP(GENMASK(17, 0), x) 79 80 #define ACKCTL 0xa0 81 #define ACKCTL_ACKT BIT(1) 82 #define ACKCTL_ACKTWP BIT(2) 83 84 #define SCSTRCTL 0xa4 85 #define SCSTRCTL_ACKTWE BIT(0) 86 #define SCSTRCTL_RWE BIT(1) 87 88 #define SCSTLCTL 0xb0 89 90 #define CNDCTL 0x140 91 #define CNDCTL_STCND BIT(0) 92 #define CNDCTL_SRCND BIT(1) 93 #define CNDCTL_SPCND BIT(2) 94 95 #define NCMDQP 0x150 /* Normal Command Queue */ 96 #define NCMDQP_CMD_ATTR(x) FIELD_PREP(GENMASK(2, 0), x) 97 #define NCMDQP_IMMED_XFER 0x01 98 #define NCMDQP_ADDR_ASSGN 0x02 99 #define NCMDQP_TID(x) FIELD_PREP(GENMASK(6, 3), x) 100 #define NCMDQP_CMD(x) FIELD_PREP(GENMASK(14, 7), x) 101 #define NCMDQP_CP BIT(15) 102 #define NCMDQP_DEV_INDEX(x) FIELD_PREP(GENMASK(20, 16), x) 103 #define NCMDQP_BYTE_CNT(x) FIELD_PREP(GENMASK(25, 23), x) 104 #define NCMDQP_DEV_COUNT(x) FIELD_PREP(GENMASK(29, 26), x) 105 #define NCMDQP_MODE(x) FIELD_PREP(GENMASK(28, 26), x) 106 #define NCMDQP_RNW(x) FIELD_PREP(GENMASK(29, 29), x) 107 #define NCMDQP_ROC BIT(30) 108 #define NCMDQP_TOC BIT(31) 109 #define NCMDQP_DATA_LENGTH(x) FIELD_PREP(GENMASK(31, 16), x) 110 111 #define NRSPQP 0x154 /* Normal Respone Queue */ 112 #define NRSPQP_NO_ERROR 0 113 #define NRSPQP_ERROR_CRC 1 114 #define NRSPQP_ERROR_PARITY 2 115 #define NRSPQP_ERROR_FRAME 3 116 #define NRSPQP_ERROR_IBA_NACK 4 117 #define NRSPQP_ERROR_ADDRESS_NACK 5 118 #define NRSPQP_ERROR_OVER_UNDER_FLOW 6 119 #define NRSPQP_ERROR_TRANSF_ABORT 8 120 #define NRSPQP_ERROR_I2C_W_NACK_ERR 9 121 #define NRSPQP_ERROR_UNSUPPORTED 10 122 #define NRSPQP_DATA_LEN(x) FIELD_GET(GENMASK(15, 0), x) 123 #define NRSPQP_ERR_STATUS(x) FIELD_GET(GENMASK(31, 28), x) 124 125 #define NTDTBP0 0x158 /* Normal Transfer Data Buffer */ 126 #define NTDTBP0_DEPTH 16 127 128 #define NQTHCTL 0x190 129 #define NQTHCTL_CMDQTH(x) FIELD_PREP(GENMASK(1, 0), x) 130 #define NQTHCTL_IBIDSSZ(x) FIELD_PREP(GENMASK(23, 16), x) 131 132 #define NTBTHCTL0 0x194 133 134 #define NRQTHCTL 0x1c0 135 136 #define BST 0x1d0 137 #define BST_STCNDDF BIT(0) 138 #define BST_SPCNDDF BIT(1) 139 #define BST_NACKDF BIT(4) 140 #define BST_TENDF BIT(8) 141 142 #define BSTE 0x1d4 143 #define BSTE_STCNDDE BIT(0) 144 #define BSTE_SPCNDDE BIT(1) 145 #define BSTE_NACKDE BIT(4) 146 #define BSTE_TENDE BIT(8) 147 #define BSTE_ALE BIT(16) 148 #define BSTE_TODE BIT(20) 149 #define BSTE_WUCNDDE BIT(24) 150 #define BSTE_ALL_FLAG (BSTE_STCNDDE | BSTE_SPCNDDE |\ 151 BSTE_NACKDE | BSTE_TENDE |\ 152 BSTE_ALE | BSTE_TODE | BSTE_WUCNDDE) 153 154 #define BIE 0x1d8 155 #define BIE_STCNDDIE BIT(0) 156 #define BIE_SPCNDDIE BIT(1) 157 #define BIE_NACKDIE BIT(4) 158 #define BIE_TENDIE BIT(8) 159 160 #define NTST 0x1e0 161 #define NTST_TDBEF0 BIT(0) 162 #define NTST_RDBFF0 BIT(1) 163 #define NTST_CMDQEF BIT(3) 164 #define NTST_RSPQFF BIT(4) 165 #define NTST_TABTF BIT(5) 166 #define NTST_TEF BIT(9) 167 168 #define NTSTE 0x1e4 169 #define NTSTE_TDBEE0 BIT(0) 170 #define NTSTE_RDBFE0 BIT(1) 171 #define NTSTE_IBIQEFE BIT(2) 172 #define NTSTE_CMDQEE BIT(3) 173 #define NTSTE_RSPQFE BIT(4) 174 #define NTSTE_TABTE BIT(5) 175 #define NTSTE_TEE BIT(9) 176 #define NTSTE_RSQFE BIT(20) 177 #define NTSTE_ALL_FLAG (NTSTE_TDBEE0 | NTSTE_RDBFE0 |\ 178 NTSTE_IBIQEFE | NTSTE_CMDQEE |\ 179 NTSTE_RSPQFE | NTSTE_TABTE |\ 180 NTSTE_TEE | NTSTE_RSQFE) 181 182 #define NTIE 0x1e8 183 #define NTIE_TDBEIE0 BIT(0) 184 #define NTIE_RDBFIE0 BIT(1) 185 #define NTIE_IBIQEFIE BIT(2) 186 #define NTIE_RSPQFIE BIT(4) 187 #define NTIE_RSQFIE BIT(20) 188 189 #define BCST 0x210 190 #define BCST_BFREF BIT(0) 191 192 #define DATBAS(x) (0x224 + 0x8 * (x)) 193 #define DATBAS_DVSTAD(x) FIELD_PREP(GENMASK(6, 0), x) 194 #define DATBAS_DVDYAD(x) FIELD_PREP(GENMASK(23, 16), x) 195 196 #define NDBSTLV0 0x398 197 #define NDBSTLV0_RDBLV(x) FIELD_GET(GENMASK(15, 8), x) 198 199 #define RENESAS_I3C_MAX_DEVS 8 200 #define I2C_INIT_MSG -1 201 202 #define RENESAS_I3C_TCLK_IDX 1 203 204 enum i3c_internal_state { 205 I3C_INTERNAL_STATE_DISABLED, 206 I3C_INTERNAL_STATE_CONTROLLER_IDLE, 207 I3C_INTERNAL_STATE_CONTROLLER_ENTDAA, 208 I3C_INTERNAL_STATE_CONTROLLER_SETDASA, 209 I3C_INTERNAL_STATE_CONTROLLER_WRITE, 210 I3C_INTERNAL_STATE_CONTROLLER_READ, 211 I3C_INTERNAL_STATE_CONTROLLER_COMMAND_WRITE, 212 I3C_INTERNAL_STATE_CONTROLLER_COMMAND_READ, 213 }; 214 215 enum renesas_i3c_event { 216 I3C_COMMAND_ADDRESS_ASSIGNMENT, 217 I3C_WRITE, 218 I3C_READ, 219 I3C_COMMAND_WRITE, 220 I3C_COMMAND_READ, 221 }; 222 223 struct renesas_i3c_cmd { 224 u32 cmd0; 225 u32 len; 226 const void *tx_buf; 227 u32 tx_count; 228 void *rx_buf; 229 u32 rx_count; 230 u32 err; 231 u8 rnw; 232 /* i2c xfer */ 233 int i2c_bytes_left; 234 int i2c_is_last; 235 u8 *i2c_buf; 236 const struct i2c_msg *msg; 237 }; 238 239 struct renesas_i3c_xfer { 240 struct list_head node; 241 struct completion comp; 242 int ret; 243 bool is_i2c_xfer; 244 unsigned int ncmds; 245 struct renesas_i3c_cmd cmds[] __counted_by(ncmds); 246 }; 247 248 struct renesas_i3c_xferqueue { 249 struct list_head list; 250 struct renesas_i3c_xfer *cur; 251 /* Lock for accessing the xfer queue */ 252 spinlock_t lock; 253 }; 254 255 struct renesas_i3c { 256 struct i3c_master_controller base; 257 enum i3c_internal_state internal_state; 258 u16 maxdevs; 259 u32 free_pos; 260 u32 dyn_addr; 261 u32 i2c_STDBR; 262 u32 i3c_STDBR; 263 unsigned long rate; 264 u8 addrs[RENESAS_I3C_MAX_DEVS]; 265 struct renesas_i3c_xferqueue xferqueue; 266 void __iomem *regs; 267 u32 *DATBASn; 268 struct clk_bulk_data *clks; 269 struct reset_control *presetn; 270 struct reset_control *tresetn; 271 u8 num_clks; 272 u8 refclk_div; 273 }; 274 275 struct renesas_i3c_i2c_dev_data { 276 u8 index; 277 }; 278 279 struct renesas_i3c_irq_desc { 280 const char *name; 281 irq_handler_t isr; 282 const char *desc; 283 }; 284 285 static inline void renesas_i3c_reg_update(void __iomem *reg, u32 mask, u32 val) 286 { 287 u32 data = readl(reg); 288 289 data &= ~mask; 290 data |= (val & mask); 291 writel(data, reg); 292 } 293 294 static inline u32 renesas_readl(void __iomem *base, u32 reg) 295 { 296 return readl(base + reg); 297 } 298 299 static inline void renesas_writel(void __iomem *base, u32 reg, u32 val) 300 { 301 writel(val, base + reg); 302 } 303 304 static void renesas_set_bit(void __iomem *base, u32 reg, u32 val) 305 { 306 renesas_i3c_reg_update(base + reg, val, val); 307 } 308 309 static void renesas_clear_bit(void __iomem *base, u32 reg, u32 val) 310 { 311 renesas_i3c_reg_update(base + reg, val, 0); 312 } 313 314 static inline struct renesas_i3c *to_renesas_i3c(struct i3c_master_controller *m) 315 { 316 return container_of(m, struct renesas_i3c, base); 317 } 318 319 static inline u32 datbas_dvdyad_with_parity(u8 addr) 320 { 321 return DATBAS_DVDYAD(addr | (parity8(addr) ? 0 : BIT(7))); 322 } 323 324 static int renesas_i3c_get_free_pos(struct renesas_i3c *i3c) 325 { 326 if (!(i3c->free_pos & GENMASK(i3c->maxdevs - 1, 0))) 327 return -ENOSPC; 328 329 return ffs(i3c->free_pos) - 1; 330 } 331 332 static int renesas_i3c_get_addr_pos(struct renesas_i3c *i3c, u8 addr) 333 { 334 int pos; 335 336 for (pos = 0; pos < i3c->maxdevs; pos++) { 337 if (addr == i3c->addrs[pos]) 338 return pos; 339 } 340 341 return -EINVAL; 342 } 343 344 static struct renesas_i3c_xfer *renesas_i3c_alloc_xfer(struct renesas_i3c *i3c, 345 unsigned int ncmds) 346 { 347 struct renesas_i3c_xfer *xfer; 348 349 xfer = kzalloc_flex(*xfer, cmds, ncmds); 350 if (!xfer) 351 return NULL; 352 353 INIT_LIST_HEAD(&xfer->node); 354 xfer->ncmds = ncmds; 355 xfer->ret = -ETIMEDOUT; 356 357 return xfer; 358 } 359 360 static void renesas_i3c_start_xfer_locked(struct renesas_i3c *i3c) 361 { 362 struct renesas_i3c_xfer *xfer = i3c->xferqueue.cur; 363 struct renesas_i3c_cmd *cmd; 364 u32 cmd1; 365 366 if (!xfer) 367 return; 368 369 cmd = xfer->cmds; 370 371 switch (i3c->internal_state) { 372 case I3C_INTERNAL_STATE_CONTROLLER_ENTDAA: 373 case I3C_INTERNAL_STATE_CONTROLLER_SETDASA: 374 renesas_set_bit(i3c->regs, NTIE, NTIE_RSPQFIE); 375 renesas_writel(i3c->regs, NCMDQP, cmd->cmd0); 376 renesas_writel(i3c->regs, NCMDQP, 0); 377 break; 378 case I3C_INTERNAL_STATE_CONTROLLER_WRITE: 379 case I3C_INTERNAL_STATE_CONTROLLER_COMMAND_WRITE: 380 renesas_set_bit(i3c->regs, NTIE, NTIE_RSPQFIE); 381 if (cmd->len <= 4) { 382 cmd->cmd0 |= NCMDQP_CMD_ATTR(NCMDQP_IMMED_XFER); 383 cmd->cmd0 |= NCMDQP_BYTE_CNT(cmd->len); 384 cmd->tx_count = cmd->len; 385 cmd1 = cmd->len == 0 ? 0 : *(u32 *)cmd->tx_buf; 386 } else { 387 cmd1 = NCMDQP_DATA_LENGTH(cmd->len); 388 } 389 renesas_writel(i3c->regs, NCMDQP, cmd->cmd0); 390 renesas_writel(i3c->regs, NCMDQP, cmd1); 391 break; 392 case I3C_INTERNAL_STATE_CONTROLLER_READ: 393 case I3C_INTERNAL_STATE_CONTROLLER_COMMAND_READ: 394 renesas_set_bit(i3c->regs, NTIE, NTIE_RDBFIE0); 395 cmd1 = NCMDQP_DATA_LENGTH(cmd->len); 396 renesas_writel(i3c->regs, NCMDQP, cmd->cmd0); 397 renesas_writel(i3c->regs, NCMDQP, cmd1); 398 break; 399 default: 400 break; 401 } 402 403 /* Clear the command queue empty flag */ 404 renesas_clear_bit(i3c->regs, NTST, NTST_CMDQEF); 405 } 406 407 static void renesas_i3c_dequeue_xfer_locked(struct renesas_i3c *i3c, 408 struct renesas_i3c_xfer *xfer) 409 { 410 if (i3c->xferqueue.cur == xfer) 411 i3c->xferqueue.cur = NULL; 412 else 413 list_del_init(&xfer->node); 414 } 415 416 static void renesas_i3c_dequeue_xfer(struct renesas_i3c *i3c, struct renesas_i3c_xfer *xfer) 417 { 418 scoped_guard(spinlock_irqsave, &i3c->xferqueue.lock) 419 renesas_i3c_dequeue_xfer_locked(i3c, xfer); 420 } 421 422 static void renesas_i3c_enqueue_xfer(struct renesas_i3c *i3c, struct renesas_i3c_xfer *xfer) 423 { 424 reinit_completion(&xfer->comp); 425 scoped_guard(spinlock_irqsave, &i3c->xferqueue.lock) { 426 if (i3c->xferqueue.cur) { 427 list_add_tail(&xfer->node, &i3c->xferqueue.list); 428 } else { 429 i3c->xferqueue.cur = xfer; 430 if (!xfer->is_i2c_xfer) 431 renesas_i3c_start_xfer_locked(i3c); 432 } 433 } 434 } 435 436 static void renesas_i3c_wait_xfer(struct renesas_i3c *i3c, struct renesas_i3c_xfer *xfer) 437 { 438 unsigned long time_left; 439 440 renesas_i3c_enqueue_xfer(i3c, xfer); 441 442 time_left = wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000)); 443 if (!time_left) 444 renesas_i3c_dequeue_xfer(i3c, xfer); 445 } 446 447 static void renesas_i3c_set_prts(struct renesas_i3c *i3c, u32 val) 448 { 449 /* Required sequence according to tnrza0140ae */ 450 renesas_set_bit(i3c->regs, RSTCTL, RSTCTL_INTLRST); 451 renesas_writel(i3c->regs, PRTS, val); 452 renesas_clear_bit(i3c->regs, RSTCTL, RSTCTL_INTLRST); 453 } 454 455 static void renesas_i3c_bus_enable(struct i3c_master_controller *m, bool i3c_mode) 456 { 457 struct renesas_i3c *i3c = to_renesas_i3c(m); 458 459 /* Setup either I3C or I2C protocol */ 460 if (i3c_mode) { 461 renesas_i3c_set_prts(i3c, 0); 462 /* Revisit: INCBA handling, especially after I2C transfers */ 463 renesas_set_bit(i3c->regs, BCTL, BCTL_HJACKCTL | BCTL_INCBA); 464 renesas_set_bit(i3c->regs, MSDVAD, MSDVAD_MDYADV); 465 renesas_writel(i3c->regs, STDBR, i3c->i3c_STDBR); 466 } else { 467 renesas_i3c_set_prts(i3c, PRTS_PRTMD); 468 renesas_writel(i3c->regs, STDBR, i3c->i2c_STDBR); 469 } 470 471 /* Enable I3C bus */ 472 renesas_set_bit(i3c->regs, BCTL, BCTL_BUSE); 473 } 474 475 static int renesas_i3c_reset(struct renesas_i3c *i3c) 476 { 477 u32 val; 478 479 renesas_writel(i3c->regs, BCTL, 0); 480 renesas_set_bit(i3c->regs, RSTCTL, RSTCTL_RI3CRST); 481 482 return read_poll_timeout(renesas_readl, val, !(val & RSTCTL_RI3CRST), 483 0, 1000, false, i3c->regs, RSTCTL); 484 } 485 486 static void renesas_i3c_hw_init(struct renesas_i3c *i3c) 487 { 488 u32 val; 489 490 /* Disable Slave Mode */ 491 renesas_writel(i3c->regs, SVCTL, 0); 492 493 /* Initialize Queue/Buffer threshold */ 494 renesas_writel(i3c->regs, NQTHCTL, NQTHCTL_IBIDSSZ(6) | 495 NQTHCTL_CMDQTH(1)); 496 497 /* The only supported configuration is two entries*/ 498 renesas_writel(i3c->regs, NTBTHCTL0, 0); 499 /* Interrupt when there is one entry in the queue */ 500 renesas_writel(i3c->regs, NRQTHCTL, 0); 501 502 /* Enable all Bus/Transfer Status Flags */ 503 renesas_writel(i3c->regs, BSTE, BSTE_ALL_FLAG); 504 renesas_writel(i3c->regs, NTSTE, NTSTE_ALL_FLAG); 505 506 /* Interrupt enable settings */ 507 renesas_writel(i3c->regs, BIE, BIE_NACKDIE | BIE_TENDIE); 508 renesas_writel(i3c->regs, NTIE, 0); 509 510 /* Clear Status register */ 511 renesas_writel(i3c->regs, NTST, 0); 512 renesas_writel(i3c->regs, INST, 0); 513 renesas_writel(i3c->regs, BST, 0); 514 515 /* Hot-Join Acknowlege setting. */ 516 renesas_set_bit(i3c->regs, BCTL, BCTL_HJACKCTL); 517 518 renesas_writel(i3c->regs, IBINCTL, IBINCTL_NRHJCTL | IBINCTL_NRMRCTL | 519 IBINCTL_NRSIRCTL); 520 521 renesas_writel(i3c->regs, SCSTLCTL, 0); 522 renesas_set_bit(i3c->regs, SCSTRCTL, SCSTRCTL_ACKTWE); 523 524 /* Bus condition timing */ 525 val = DIV_ROUND_UP(I3C_BUS_TBUF_MIXED_FM_MIN_NS, 526 NSEC_PER_SEC / i3c->rate); 527 renesas_writel(i3c->regs, BFRECDT, BFRECDT_FRECYC(val)); 528 529 val = DIV_ROUND_UP(I3C_BUS_TAVAL_MIN_NS, 530 NSEC_PER_SEC / i3c->rate); 531 renesas_writel(i3c->regs, BAVLCDT, BAVLCDT_AVLCYC(val)); 532 533 val = DIV_ROUND_UP(I3C_BUS_TIDLE_MIN_NS, 534 NSEC_PER_SEC / i3c->rate); 535 renesas_writel(i3c->regs, BIDLCDT, BIDLCDT_IDLCYC(val)); 536 } 537 538 static int renesas_i3c_bus_init(struct i3c_master_controller *m) 539 { 540 struct renesas_i3c *i3c = to_renesas_i3c(m); 541 struct i3c_bus *bus = i3c_master_get_bus(m); 542 struct i3c_device_info info = {}; 543 struct i2c_timings t; 544 u32 double_SBR; 545 int cks, pp_high_ticks, pp_low_ticks, i3c_total_ticks; 546 int od_high_ticks, od_low_ticks, i2c_total_ticks; 547 int ret; 548 549 i3c->rate = clk_get_rate(i3c->clks[RENESAS_I3C_TCLK_IDX].clk); 550 if (!i3c->rate) 551 return -EINVAL; 552 553 ret = renesas_i3c_reset(i3c); 554 if (ret) 555 return ret; 556 557 i2c_total_ticks = DIV_ROUND_UP(i3c->rate, bus->scl_rate.i2c); 558 i3c_total_ticks = DIV_ROUND_UP(i3c->rate, bus->scl_rate.i3c); 559 560 i2c_parse_fw_timings(&m->dev, &t, true); 561 562 for (cks = 0; cks < 7; cks++) { 563 /* SCL low-period calculation in Open-drain mode */ 564 od_low_ticks = ((i2c_total_ticks * 6) / 10); 565 566 /* SCL clock calculation in Push-Pull mode */ 567 if (bus->mode == I3C_BUS_MODE_PURE) 568 pp_high_ticks = ((i3c_total_ticks * 5) / 10); 569 else 570 pp_high_ticks = DIV_ROUND_UP(I3C_BUS_THIGH_MIXED_MAX_NS, 571 NSEC_PER_SEC / i3c->rate); 572 pp_low_ticks = i3c_total_ticks - pp_high_ticks; 573 574 if ((od_low_ticks / 2) <= 0xFF && pp_low_ticks < 0x3F) 575 break; 576 577 i2c_total_ticks /= 2; 578 i3c_total_ticks /= 2; 579 i3c->rate /= 2; 580 } 581 582 /* SCL clock period calculation in Open-drain mode */ 583 if ((od_low_ticks / 2) > 0xFF || pp_low_ticks > 0x3F) { 584 dev_err(&m->dev, "invalid speed (i2c-scl = %lu Hz, i3c-scl = %lu Hz). Too slow.\n", 585 (unsigned long)bus->scl_rate.i2c, (unsigned long)bus->scl_rate.i3c); 586 return -EINVAL; 587 } 588 589 /* SCL high-period calculation in Open-drain mode */ 590 od_high_ticks = i2c_total_ticks - od_low_ticks; 591 592 /* Standard Bit Rate setting */ 593 double_SBR = od_low_ticks > 0xFF ? 1 : 0; 594 i3c->i3c_STDBR = (double_SBR ? STDBR_DSBRPO : 0) | 595 STDBR_SBRLO(double_SBR, od_low_ticks) | 596 STDBR_SBRHO(double_SBR, od_high_ticks) | 597 STDBR_SBRLP(pp_low_ticks) | 598 STDBR_SBRHP(pp_high_ticks); 599 600 od_low_ticks -= t.scl_fall_ns / (NSEC_PER_SEC / i3c->rate) + 1; 601 od_high_ticks -= t.scl_rise_ns / (NSEC_PER_SEC / i3c->rate) + 1; 602 i3c->i2c_STDBR = (double_SBR ? STDBR_DSBRPO : 0) | 603 STDBR_SBRLO(double_SBR, od_low_ticks) | 604 STDBR_SBRHO(double_SBR, od_high_ticks) | 605 STDBR_SBRLP(pp_low_ticks) | 606 STDBR_SBRHP(pp_high_ticks); 607 renesas_writel(i3c->regs, STDBR, i3c->i3c_STDBR); 608 609 /* Extended Bit Rate setting */ 610 renesas_writel(i3c->regs, EXTBR, EXTBR_EBRLO(od_low_ticks) | 611 EXTBR_EBRHO(od_high_ticks) | 612 EXTBR_EBRLP(pp_low_ticks) | 613 EXTBR_EBRHP(pp_high_ticks)); 614 615 renesas_writel(i3c->regs, REFCKCTL, REFCKCTL_IREFCKS(cks)); 616 i3c->refclk_div = cks; 617 618 /* I3C hw init*/ 619 renesas_i3c_hw_init(i3c); 620 621 ret = i3c_master_get_free_addr(m, 0); 622 if (ret < 0) 623 return ret; 624 625 i3c->dyn_addr = ret; 626 renesas_writel(i3c->regs, MSDVAD, MSDVAD_MDYAD(ret) | MSDVAD_MDYADV); 627 628 memset(&info, 0, sizeof(info)); 629 info.dyn_addr = ret; 630 return i3c_master_set_info(&i3c->base, &info); 631 } 632 633 static void renesas_i3c_bus_cleanup(struct i3c_master_controller *m) 634 { 635 struct renesas_i3c *i3c = to_renesas_i3c(m); 636 637 renesas_i3c_reset(i3c); 638 } 639 640 static int renesas_i3c_daa(struct i3c_master_controller *m) 641 { 642 struct renesas_i3c *i3c = to_renesas_i3c(m); 643 struct renesas_i3c_cmd *cmd; 644 u32 olddevs, newdevs; 645 u8 last_addr = 0, pos; 646 int ret; 647 648 struct renesas_i3c_xfer *xfer __free(kfree) = renesas_i3c_alloc_xfer(i3c, 1); 649 if (!xfer) 650 return -ENOMEM; 651 652 /* Enable I3C bus. */ 653 renesas_i3c_bus_enable(m, true); 654 655 olddevs = ~(i3c->free_pos); 656 i3c->internal_state = I3C_INTERNAL_STATE_CONTROLLER_ENTDAA; 657 658 /* Setting DATBASn registers for target devices. */ 659 for (pos = 0; pos < i3c->maxdevs; pos++) { 660 if (olddevs & BIT(pos)) 661 continue; 662 663 ret = i3c_master_get_free_addr(m, last_addr + 1); 664 if (ret < 0) 665 return -ENOSPC; 666 667 i3c->addrs[pos] = ret; 668 last_addr = ret; 669 670 renesas_writel(i3c->regs, DATBAS(pos), datbas_dvdyad_with_parity(ret)); 671 } 672 673 init_completion(&xfer->comp); 674 cmd = xfer->cmds; 675 cmd->rx_count = 0; 676 677 ret = renesas_i3c_get_free_pos(i3c); 678 if (ret < 0) 679 return ret; 680 681 /* 682 * Setup the command descriptor to start the ENTDAA command 683 * and starting at the selected device index. 684 */ 685 cmd->cmd0 = NCMDQP_CMD_ATTR(NCMDQP_ADDR_ASSGN) | NCMDQP_ROC | 686 NCMDQP_TID(I3C_COMMAND_ADDRESS_ASSIGNMENT) | 687 NCMDQP_CMD(I3C_CCC_ENTDAA) | NCMDQP_DEV_INDEX(ret) | 688 NCMDQP_DEV_COUNT(i3c->maxdevs - ret) | NCMDQP_TOC; 689 690 renesas_i3c_wait_xfer(i3c, xfer); 691 692 newdevs = GENMASK(i3c->maxdevs - cmd->rx_count - 1, 0); 693 newdevs &= ~olddevs; 694 695 for (pos = 0; pos < i3c->maxdevs; pos++) { 696 if (newdevs & BIT(pos)) 697 i3c_master_add_i3c_dev_locked(m, i3c->addrs[pos]); 698 } 699 700 return 0; 701 } 702 703 static bool renesas_i3c_supports_ccc_cmd(struct i3c_master_controller *m, 704 const struct i3c_ccc_cmd *cmd) 705 { 706 if (cmd->ndests > 1) 707 return false; 708 709 switch (cmd->id) { 710 case I3C_CCC_ENEC(true): 711 case I3C_CCC_ENEC(false): 712 case I3C_CCC_DISEC(true): 713 case I3C_CCC_DISEC(false): 714 case I3C_CCC_ENTAS(0, true): 715 case I3C_CCC_ENTAS(1, true): 716 case I3C_CCC_ENTAS(2, true): 717 case I3C_CCC_ENTAS(3, true): 718 case I3C_CCC_ENTAS(0, false): 719 case I3C_CCC_ENTAS(1, false): 720 case I3C_CCC_ENTAS(2, false): 721 case I3C_CCC_ENTAS(3, false): 722 case I3C_CCC_RSTDAA(true): 723 case I3C_CCC_RSTDAA(false): 724 case I3C_CCC_ENTDAA: 725 case I3C_CCC_DEFSLVS: 726 case I3C_CCC_SETMWL(true): 727 case I3C_CCC_SETMWL(false): 728 case I3C_CCC_SETMRL(true): 729 case I3C_CCC_SETMRL(false): 730 case I3C_CCC_ENTTM: 731 case I3C_CCC_SETDASA: 732 case I3C_CCC_SETNEWDA: 733 case I3C_CCC_GETMWL: 734 case I3C_CCC_GETMRL: 735 case I3C_CCC_GETPID: 736 case I3C_CCC_GETBCR: 737 case I3C_CCC_GETDCR: 738 case I3C_CCC_GETSTATUS: 739 case I3C_CCC_GETACCMST: 740 case I3C_CCC_GETMXDS: 741 return true; 742 default: 743 return false; 744 } 745 } 746 747 static int renesas_i3c_send_ccc_cmd(struct i3c_master_controller *m, 748 struct i3c_ccc_cmd *ccc) 749 { 750 struct renesas_i3c *i3c = to_renesas_i3c(m); 751 struct renesas_i3c_cmd *cmd; 752 int ret, pos = 0; 753 754 if (ccc->id & I3C_CCC_DIRECT) { 755 pos = renesas_i3c_get_addr_pos(i3c, ccc->dests[0].addr); 756 if (pos < 0) 757 return pos; 758 } 759 760 struct renesas_i3c_xfer *xfer __free(kfree) = renesas_i3c_alloc_xfer(i3c, 1); 761 if (!xfer) 762 return -ENOMEM; 763 764 renesas_i3c_bus_enable(m, true); 765 766 init_completion(&xfer->comp); 767 cmd = xfer->cmds; 768 cmd->rnw = ccc->rnw; 769 cmd->cmd0 = 0; 770 771 /* Calculate the command descriptor. */ 772 switch (ccc->id) { 773 case I3C_CCC_SETDASA: 774 renesas_writel(i3c->regs, DATBAS(pos), 775 DATBAS_DVSTAD(ccc->dests[0].addr) | 776 DATBAS_DVDYAD(*(u8 *)ccc->dests[0].payload.data >> 1)); 777 cmd->cmd0 = NCMDQP_CMD_ATTR(NCMDQP_ADDR_ASSGN) | NCMDQP_ROC | 778 NCMDQP_TID(I3C_COMMAND_ADDRESS_ASSIGNMENT) | 779 NCMDQP_CMD(I3C_CCC_SETDASA) | NCMDQP_DEV_INDEX(pos) | 780 NCMDQP_DEV_COUNT(0) | NCMDQP_TOC; 781 i3c->internal_state = I3C_INTERNAL_STATE_CONTROLLER_SETDASA; 782 break; 783 default: 784 /* Calculate the command descriptor. */ 785 cmd->cmd0 = NCMDQP_TID(I3C_COMMAND_WRITE) | NCMDQP_MODE(0) | 786 NCMDQP_RNW(ccc->rnw) | NCMDQP_CMD(ccc->id) | 787 NCMDQP_ROC | NCMDQP_TOC | NCMDQP_CP | 788 NCMDQP_DEV_INDEX(pos); 789 790 if (ccc->rnw) { 791 cmd->rx_buf = ccc->dests[0].payload.data; 792 cmd->len = ccc->dests[0].payload.len; 793 cmd->rx_count = 0; 794 i3c->internal_state = I3C_INTERNAL_STATE_CONTROLLER_COMMAND_READ; 795 } else { 796 cmd->tx_buf = ccc->dests[0].payload.data; 797 cmd->len = ccc->dests[0].payload.len; 798 cmd->tx_count = 0; 799 i3c->internal_state = I3C_INTERNAL_STATE_CONTROLLER_COMMAND_WRITE; 800 } 801 } 802 803 renesas_i3c_wait_xfer(i3c, xfer); 804 805 ret = xfer->ret; 806 if (ret) 807 ccc->err = I3C_ERROR_M2; 808 809 return ret; 810 } 811 812 static int renesas_i3c_i3c_xfers(struct i3c_dev_desc *dev, struct i3c_xfer *i3c_xfers, 813 int i3c_nxfers, enum i3c_xfer_mode mode) 814 { 815 struct i3c_master_controller *m = i3c_dev_get_master(dev); 816 struct renesas_i3c *i3c = to_renesas_i3c(m); 817 struct renesas_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 818 int i; 819 820 /* Enable I3C bus. */ 821 renesas_i3c_bus_enable(m, true); 822 823 struct renesas_i3c_xfer *xfer __free(kfree) = renesas_i3c_alloc_xfer(i3c, 1); 824 if (!xfer) 825 return -ENOMEM; 826 827 init_completion(&xfer->comp); 828 829 for (i = 0; i < i3c_nxfers; i++) { 830 struct renesas_i3c_cmd *cmd = xfer->cmds; 831 832 /* Calculate the Transfer Command Descriptor */ 833 cmd->rnw = i3c_xfers[i].rnw; 834 cmd->cmd0 = NCMDQP_DEV_INDEX(data->index) | NCMDQP_MODE(0) | 835 NCMDQP_RNW(cmd->rnw) | NCMDQP_ROC | NCMDQP_TOC; 836 837 if (i3c_xfers[i].rnw) { 838 cmd->rx_count = 0; 839 cmd->cmd0 |= NCMDQP_TID(I3C_READ); 840 cmd->rx_buf = i3c_xfers[i].data.in; 841 cmd->len = i3c_xfers[i].len; 842 i3c->internal_state = I3C_INTERNAL_STATE_CONTROLLER_READ; 843 } else { 844 cmd->tx_count = 0; 845 cmd->cmd0 |= NCMDQP_TID(I3C_WRITE); 846 cmd->tx_buf = i3c_xfers[i].data.out; 847 cmd->len = i3c_xfers[i].len; 848 i3c->internal_state = I3C_INTERNAL_STATE_CONTROLLER_WRITE; 849 } 850 851 if (!i3c_xfers[i].rnw && i3c_xfers[i].len > 4) { 852 i3c_writel_fifo(i3c->regs + NTDTBP0, cmd->tx_buf, cmd->len); 853 if (cmd->len > NTDTBP0_DEPTH * sizeof(u32)) 854 renesas_set_bit(i3c->regs, NTIE, NTIE_TDBEIE0); 855 } 856 857 renesas_i3c_wait_xfer(i3c, xfer); 858 } 859 860 return 0; 861 } 862 863 static int renesas_i3c_attach_i3c_dev(struct i3c_dev_desc *dev) 864 { 865 struct i3c_master_controller *m = i3c_dev_get_master(dev); 866 struct renesas_i3c *i3c = to_renesas_i3c(m); 867 struct renesas_i3c_i2c_dev_data *data; 868 int pos; 869 870 pos = renesas_i3c_get_free_pos(i3c); 871 if (pos < 0) 872 return pos; 873 874 data = kzalloc_obj(*data); 875 if (!data) 876 return -ENOMEM; 877 878 data->index = pos; 879 i3c->addrs[pos] = dev->info.dyn_addr ? : dev->info.static_addr; 880 i3c->free_pos &= ~BIT(pos); 881 882 renesas_writel(i3c->regs, DATBAS(pos), DATBAS_DVSTAD(dev->info.static_addr) | 883 datbas_dvdyad_with_parity(i3c->addrs[pos])); 884 i3c_dev_set_master_data(dev, data); 885 886 return 0; 887 } 888 889 static int renesas_i3c_reattach_i3c_dev(struct i3c_dev_desc *dev, 890 u8 old_dyn_addr) 891 { 892 struct i3c_master_controller *m = i3c_dev_get_master(dev); 893 struct renesas_i3c *i3c = to_renesas_i3c(m); 894 struct renesas_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 895 896 i3c->addrs[data->index] = dev->info.dyn_addr ? dev->info.dyn_addr : 897 dev->info.static_addr; 898 899 return 0; 900 } 901 902 static void renesas_i3c_detach_i3c_dev(struct i3c_dev_desc *dev) 903 { 904 struct renesas_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 905 struct i3c_master_controller *m = i3c_dev_get_master(dev); 906 struct renesas_i3c *i3c = to_renesas_i3c(m); 907 908 i3c_dev_set_master_data(dev, NULL); 909 i3c->addrs[data->index] = 0; 910 i3c->free_pos |= BIT(data->index); 911 kfree(data); 912 } 913 914 static int renesas_i3c_i2c_xfers(struct i2c_dev_desc *dev, 915 struct i2c_msg *i2c_xfers, 916 int i2c_nxfers) 917 { 918 struct i3c_master_controller *m = i2c_dev_get_master(dev); 919 struct renesas_i3c *i3c = to_renesas_i3c(m); 920 struct renesas_i3c_cmd *cmd; 921 u8 start_bit = CNDCTL_STCND; 922 int i; 923 924 struct renesas_i3c_xfer *xfer __free(kfree) = renesas_i3c_alloc_xfer(i3c, 1); 925 if (!xfer) 926 return -ENOMEM; 927 928 if (!i2c_nxfers) 929 return 0; 930 931 renesas_i3c_bus_enable(m, false); 932 933 init_completion(&xfer->comp); 934 xfer->is_i2c_xfer = true; 935 cmd = xfer->cmds; 936 937 if (!(renesas_readl(i3c->regs, BCST) & BCST_BFREF)) { 938 cmd->err = -EBUSY; 939 return cmd->err; 940 } 941 942 renesas_writel(i3c->regs, BST, 0); 943 944 renesas_i3c_enqueue_xfer(i3c, xfer); 945 946 for (i = 0; i < i2c_nxfers; i++) { 947 cmd->i2c_bytes_left = I2C_INIT_MSG; 948 cmd->i2c_buf = i2c_xfers[i].buf; 949 cmd->msg = &i2c_xfers[i]; 950 cmd->i2c_is_last = (i == i2c_nxfers - 1); 951 952 renesas_set_bit(i3c->regs, BIE, BIE_NACKDIE); 953 renesas_set_bit(i3c->regs, NTIE, NTIE_TDBEIE0); 954 renesas_set_bit(i3c->regs, BIE, BIE_STCNDDIE); 955 956 /* Issue Start condition */ 957 renesas_set_bit(i3c->regs, CNDCTL, start_bit); 958 959 renesas_set_bit(i3c->regs, NTSTE, NTSTE_TDBEE0); 960 961 wait_for_completion_timeout(&xfer->comp, m->i2c.timeout); 962 963 if (cmd->err) 964 break; 965 966 start_bit = CNDCTL_SRCND; 967 } 968 969 renesas_i3c_dequeue_xfer(i3c, xfer); 970 return cmd->err; 971 } 972 973 static int renesas_i3c_attach_i2c_dev(struct i2c_dev_desc *dev) 974 { 975 struct i3c_master_controller *m = i2c_dev_get_master(dev); 976 struct renesas_i3c *i3c = to_renesas_i3c(m); 977 struct renesas_i3c_i2c_dev_data *data; 978 int pos; 979 980 pos = renesas_i3c_get_free_pos(i3c); 981 if (pos < 0) 982 return pos; 983 984 data = kzalloc_obj(*data); 985 if (!data) 986 return -ENOMEM; 987 988 data->index = pos; 989 i3c->addrs[pos] = dev->addr; 990 i3c->free_pos &= ~BIT(pos); 991 i2c_dev_set_master_data(dev, data); 992 993 return 0; 994 } 995 996 static void renesas_i3c_detach_i2c_dev(struct i2c_dev_desc *dev) 997 { 998 struct renesas_i3c_i2c_dev_data *data = i2c_dev_get_master_data(dev); 999 struct i3c_master_controller *m = i2c_dev_get_master(dev); 1000 struct renesas_i3c *i3c = to_renesas_i3c(m); 1001 1002 i2c_dev_set_master_data(dev, NULL); 1003 i3c->addrs[data->index] = 0; 1004 i3c->free_pos |= BIT(data->index); 1005 kfree(data); 1006 } 1007 1008 static irqreturn_t renesas_i3c_tx_isr(int irq, void *data) 1009 { 1010 struct renesas_i3c *i3c = data; 1011 struct renesas_i3c_xfer *xfer; 1012 struct renesas_i3c_cmd *cmd; 1013 u8 val; 1014 1015 scoped_guard(spinlock, &i3c->xferqueue.lock) { 1016 xfer = i3c->xferqueue.cur; 1017 cmd = xfer->cmds; 1018 1019 if (xfer->is_i2c_xfer) { 1020 if (!cmd->i2c_bytes_left) 1021 return IRQ_NONE; 1022 1023 if (cmd->i2c_bytes_left != I2C_INIT_MSG) { 1024 val = *cmd->i2c_buf; 1025 cmd->i2c_buf++; 1026 cmd->i2c_bytes_left--; 1027 renesas_writel(i3c->regs, NTDTBP0, val); 1028 } 1029 1030 if (cmd->i2c_bytes_left == 0) { 1031 renesas_clear_bit(i3c->regs, NTIE, NTIE_TDBEIE0); 1032 renesas_set_bit(i3c->regs, BIE, BIE_TENDIE); 1033 } 1034 1035 /* Clear the Transmit Buffer Empty status flag. */ 1036 renesas_clear_bit(i3c->regs, NTST, NTST_TDBEF0); 1037 } else { 1038 i3c_writel_fifo(i3c->regs + NTDTBP0, cmd->tx_buf, cmd->len); 1039 } 1040 } 1041 1042 return IRQ_HANDLED; 1043 } 1044 1045 static irqreturn_t renesas_i3c_resp_isr(int irq, void *data) 1046 { 1047 struct renesas_i3c *i3c = data; 1048 struct renesas_i3c_xfer *xfer; 1049 struct renesas_i3c_cmd *cmd; 1050 u32 resp_descriptor = renesas_readl(i3c->regs, NRSPQP); 1051 u32 bytes_remaining = 0; 1052 u32 ntst, data_len; 1053 int ret = 0; 1054 1055 scoped_guard(spinlock, &i3c->xferqueue.lock) { 1056 xfer = i3c->xferqueue.cur; 1057 cmd = xfer->cmds; 1058 1059 /* Clear the Respone Queue Full status flag*/ 1060 renesas_clear_bit(i3c->regs, NTST, NTST_RSPQFF); 1061 1062 data_len = NRSPQP_DATA_LEN(resp_descriptor); 1063 1064 switch (i3c->internal_state) { 1065 case I3C_INTERNAL_STATE_CONTROLLER_ENTDAA: 1066 cmd->rx_count = data_len; 1067 break; 1068 case I3C_INTERNAL_STATE_CONTROLLER_WRITE: 1069 case I3C_INTERNAL_STATE_CONTROLLER_COMMAND_WRITE: 1070 /* Disable the transmit IRQ if it hasn't been disabled already. */ 1071 renesas_clear_bit(i3c->regs, NTIE, NTIE_TDBEIE0); 1072 break; 1073 case I3C_INTERNAL_STATE_CONTROLLER_READ: 1074 case I3C_INTERNAL_STATE_CONTROLLER_COMMAND_READ: 1075 if (NDBSTLV0_RDBLV(renesas_readl(i3c->regs, NDBSTLV0)) && !cmd->err) 1076 bytes_remaining = data_len - cmd->rx_count; 1077 1078 i3c_readl_fifo(i3c->regs + NTDTBP0, cmd->rx_buf, bytes_remaining); 1079 renesas_clear_bit(i3c->regs, NTIE, NTIE_RDBFIE0); 1080 break; 1081 default: 1082 break; 1083 } 1084 1085 switch (NRSPQP_ERR_STATUS(resp_descriptor)) { 1086 case NRSPQP_NO_ERROR: 1087 break; 1088 case NRSPQP_ERROR_PARITY: 1089 case NRSPQP_ERROR_IBA_NACK: 1090 case NRSPQP_ERROR_TRANSF_ABORT: 1091 case NRSPQP_ERROR_CRC: 1092 case NRSPQP_ERROR_FRAME: 1093 ret = -EIO; 1094 break; 1095 case NRSPQP_ERROR_OVER_UNDER_FLOW: 1096 ret = -ENOSPC; 1097 break; 1098 case NRSPQP_ERROR_UNSUPPORTED: 1099 ret = -EOPNOTSUPP; 1100 break; 1101 case NRSPQP_ERROR_I2C_W_NACK_ERR: 1102 case NRSPQP_ERROR_ADDRESS_NACK: 1103 default: 1104 ret = -EINVAL; 1105 break; 1106 } 1107 1108 /* 1109 * If the transfer was aborted, then the abort flag must be cleared 1110 * before notifying the application that a transfer has completed. 1111 */ 1112 ntst = renesas_readl(i3c->regs, NTST); 1113 if (ntst & NTST_TABTF) 1114 renesas_clear_bit(i3c->regs, BCTL, BCTL_ABT); 1115 1116 /* Clear error status flags. */ 1117 renesas_clear_bit(i3c->regs, NTST, NTST_TEF | NTST_TABTF); 1118 1119 xfer->ret = ret; 1120 complete(&xfer->comp); 1121 1122 xfer = list_first_entry_or_null(&i3c->xferqueue.list, 1123 struct renesas_i3c_xfer, node); 1124 if (xfer) 1125 list_del_init(&xfer->node); 1126 1127 i3c->xferqueue.cur = xfer; 1128 } 1129 1130 return IRQ_HANDLED; 1131 } 1132 1133 static irqreturn_t renesas_i3c_tend_isr(int irq, void *data) 1134 { 1135 struct renesas_i3c *i3c = data; 1136 struct renesas_i3c_xfer *xfer; 1137 struct renesas_i3c_cmd *cmd; 1138 1139 scoped_guard(spinlock, &i3c->xferqueue.lock) { 1140 xfer = i3c->xferqueue.cur; 1141 cmd = xfer->cmds; 1142 1143 if (xfer->is_i2c_xfer) { 1144 if (renesas_readl(i3c->regs, BST) & BST_NACKDF) { 1145 /* We got a NACKIE */ 1146 renesas_readl(i3c->regs, NTDTBP0); /* dummy read */ 1147 renesas_clear_bit(i3c->regs, BST, BST_NACKDF); 1148 cmd->err = -ENXIO; 1149 } else if (cmd->i2c_bytes_left) { 1150 renesas_set_bit(i3c->regs, NTIE, NTIE_TDBEIE0); 1151 return IRQ_NONE; 1152 } 1153 1154 if (cmd->i2c_is_last || cmd->err) { 1155 renesas_clear_bit(i3c->regs, BIE, BIE_TENDIE); 1156 renesas_set_bit(i3c->regs, BIE, BIE_SPCNDDIE); 1157 renesas_set_bit(i3c->regs, CNDCTL, CNDCTL_SPCND); 1158 } else { 1159 /* Transfer is complete, but do not send STOP */ 1160 renesas_clear_bit(i3c->regs, NTSTE, NTSTE_TDBEE0); 1161 renesas_clear_bit(i3c->regs, BIE, BIE_TENDIE); 1162 xfer->ret = 0; 1163 complete(&xfer->comp); 1164 } 1165 } 1166 1167 /* Clear the Transmit Buffer Empty status flag. */ 1168 renesas_clear_bit(i3c->regs, BST, BST_TENDF); 1169 } 1170 1171 return IRQ_HANDLED; 1172 } 1173 1174 static irqreturn_t renesas_i3c_rx_isr(int irq, void *data) 1175 { 1176 struct renesas_i3c *i3c = data; 1177 struct renesas_i3c_xfer *xfer; 1178 struct renesas_i3c_cmd *cmd; 1179 int read_bytes; 1180 1181 /* If resp_isr already read the data and updated 'xfer', we can just leave */ 1182 if (!(renesas_readl(i3c->regs, NTIE) & NTIE_RDBFIE0)) 1183 return IRQ_NONE; 1184 1185 scoped_guard(spinlock, &i3c->xferqueue.lock) { 1186 xfer = i3c->xferqueue.cur; 1187 cmd = xfer->cmds; 1188 1189 if (xfer->is_i2c_xfer) { 1190 if (!cmd->i2c_bytes_left) 1191 return IRQ_NONE; 1192 1193 if (cmd->i2c_bytes_left == I2C_INIT_MSG) { 1194 cmd->i2c_bytes_left = cmd->msg->len; 1195 renesas_set_bit(i3c->regs, SCSTRCTL, SCSTRCTL_RWE); 1196 renesas_readl(i3c->regs, NTDTBP0); /* dummy read */ 1197 if (cmd->i2c_bytes_left == 1) 1198 renesas_writel(i3c->regs, ACKCTL, ACKCTL_ACKT | ACKCTL_ACKTWP); 1199 return IRQ_HANDLED; 1200 } 1201 1202 if (cmd->i2c_bytes_left == 1) { 1203 /* STOP must come before we set ACKCTL! */ 1204 if (cmd->i2c_is_last) { 1205 renesas_set_bit(i3c->regs, BIE, BIE_SPCNDDIE); 1206 renesas_clear_bit(i3c->regs, BST, BST_SPCNDDF); 1207 renesas_set_bit(i3c->regs, CNDCTL, CNDCTL_SPCND); 1208 } 1209 renesas_writel(i3c->regs, ACKCTL, ACKCTL_ACKT | ACKCTL_ACKTWP); 1210 } else { 1211 renesas_writel(i3c->regs, ACKCTL, ACKCTL_ACKTWP); 1212 } 1213 1214 /* Reading acks the RIE interrupt */ 1215 *cmd->i2c_buf = renesas_readl(i3c->regs, NTDTBP0); 1216 cmd->i2c_buf++; 1217 cmd->i2c_bytes_left--; 1218 } else { 1219 read_bytes = NDBSTLV0_RDBLV(renesas_readl(i3c->regs, NDBSTLV0)) * sizeof(u32); 1220 i3c_readl_fifo(i3c->regs + NTDTBP0, cmd->rx_buf, read_bytes); 1221 cmd->rx_count = read_bytes; 1222 } 1223 1224 /* Clear the Read Buffer Full status flag. */ 1225 renesas_clear_bit(i3c->regs, NTST, NTST_RDBFF0); 1226 } 1227 1228 return IRQ_HANDLED; 1229 } 1230 1231 static irqreturn_t renesas_i3c_stop_isr(int irq, void *data) 1232 { 1233 struct renesas_i3c *i3c = data; 1234 struct renesas_i3c_xfer *xfer; 1235 1236 scoped_guard(spinlock, &i3c->xferqueue.lock) { 1237 xfer = i3c->xferqueue.cur; 1238 1239 /* read back registers to confirm writes have fully propagated */ 1240 renesas_writel(i3c->regs, BST, 0); 1241 renesas_readl(i3c->regs, BST); 1242 renesas_writel(i3c->regs, BIE, 0); 1243 renesas_clear_bit(i3c->regs, NTST, NTST_TDBEF0 | NTST_RDBFF0); 1244 renesas_clear_bit(i3c->regs, SCSTRCTL, SCSTRCTL_RWE); 1245 1246 xfer->ret = 0; 1247 complete(&xfer->comp); 1248 } 1249 1250 return IRQ_HANDLED; 1251 } 1252 1253 static irqreturn_t renesas_i3c_start_isr(int irq, void *data) 1254 { 1255 struct renesas_i3c *i3c = data; 1256 struct renesas_i3c_xfer *xfer; 1257 struct renesas_i3c_cmd *cmd; 1258 u8 val; 1259 1260 scoped_guard(spinlock, &i3c->xferqueue.lock) { 1261 xfer = i3c->xferqueue.cur; 1262 cmd = xfer->cmds; 1263 1264 if (xfer->is_i2c_xfer) { 1265 if (!cmd->i2c_bytes_left) 1266 return IRQ_NONE; 1267 1268 if (cmd->i2c_bytes_left == I2C_INIT_MSG) { 1269 if (cmd->msg->flags & I2C_M_RD) { 1270 /* On read, switch over to receive interrupt */ 1271 renesas_clear_bit(i3c->regs, NTIE, NTIE_TDBEIE0); 1272 renesas_set_bit(i3c->regs, NTIE, NTIE_RDBFIE0); 1273 } else { 1274 /* On write, initialize length */ 1275 cmd->i2c_bytes_left = cmd->msg->len; 1276 } 1277 1278 val = i2c_8bit_addr_from_msg(cmd->msg); 1279 renesas_writel(i3c->regs, NTDTBP0, val); 1280 } 1281 } 1282 1283 renesas_clear_bit(i3c->regs, BIE, BIE_STCNDDIE); 1284 renesas_clear_bit(i3c->regs, BST, BST_STCNDDF); 1285 } 1286 1287 return IRQ_HANDLED; 1288 } 1289 1290 static const struct i3c_master_controller_ops renesas_i3c_ops = { 1291 .bus_init = renesas_i3c_bus_init, 1292 .bus_cleanup = renesas_i3c_bus_cleanup, 1293 .attach_i3c_dev = renesas_i3c_attach_i3c_dev, 1294 .reattach_i3c_dev = renesas_i3c_reattach_i3c_dev, 1295 .detach_i3c_dev = renesas_i3c_detach_i3c_dev, 1296 .do_daa = renesas_i3c_daa, 1297 .supports_ccc_cmd = renesas_i3c_supports_ccc_cmd, 1298 .send_ccc_cmd = renesas_i3c_send_ccc_cmd, 1299 .i3c_xfers = renesas_i3c_i3c_xfers, 1300 .attach_i2c_dev = renesas_i3c_attach_i2c_dev, 1301 .detach_i2c_dev = renesas_i3c_detach_i2c_dev, 1302 .i2c_xfers = renesas_i3c_i2c_xfers, 1303 }; 1304 1305 static const struct renesas_i3c_irq_desc renesas_i3c_irqs[] = { 1306 { .name = "resp", .isr = renesas_i3c_resp_isr, .desc = "i3c-resp" }, 1307 { .name = "rx", .isr = renesas_i3c_rx_isr, .desc = "i3c-rx" }, 1308 { .name = "tx", .isr = renesas_i3c_tx_isr, .desc = "i3c-tx" }, 1309 { .name = "st", .isr = renesas_i3c_start_isr, .desc = "i3c-start" }, 1310 { .name = "sp", .isr = renesas_i3c_stop_isr, .desc = "i3c-stop" }, 1311 { .name = "tend", .isr = renesas_i3c_tend_isr, .desc = "i3c-tend" }, 1312 { .name = "nack", .isr = renesas_i3c_tend_isr, .desc = "i3c-nack" }, 1313 }; 1314 1315 static int renesas_i3c_probe(struct platform_device *pdev) 1316 { 1317 struct renesas_i3c *i3c; 1318 int ret, i; 1319 1320 i3c = devm_kzalloc(&pdev->dev, sizeof(*i3c), GFP_KERNEL); 1321 if (!i3c) 1322 return -ENOMEM; 1323 1324 i3c->regs = devm_platform_ioremap_resource(pdev, 0); 1325 if (IS_ERR(i3c->regs)) 1326 return PTR_ERR(i3c->regs); 1327 1328 ret = devm_clk_bulk_get_all_enabled(&pdev->dev, &i3c->clks); 1329 if (ret <= RENESAS_I3C_TCLK_IDX) 1330 return dev_err_probe(&pdev->dev, ret < 0 ? ret : -EINVAL, 1331 "Failed to get clocks (need > %d, got %d)\n", 1332 RENESAS_I3C_TCLK_IDX, ret); 1333 i3c->num_clks = ret; 1334 1335 i3c->tresetn = devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev, "tresetn"); 1336 if (IS_ERR(i3c->tresetn)) 1337 return dev_err_probe(&pdev->dev, PTR_ERR(i3c->tresetn), 1338 "Error: missing tresetn ctrl\n"); 1339 1340 i3c->presetn = devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev, "presetn"); 1341 if (IS_ERR(i3c->presetn)) 1342 return dev_err_probe(&pdev->dev, PTR_ERR(i3c->presetn), 1343 "Error: missing presetn ctrl\n"); 1344 1345 spin_lock_init(&i3c->xferqueue.lock); 1346 INIT_LIST_HEAD(&i3c->xferqueue.list); 1347 1348 ret = renesas_i3c_reset(i3c); 1349 if (ret) 1350 return ret; 1351 1352 for (i = 0; i < ARRAY_SIZE(renesas_i3c_irqs); i++) { 1353 ret = platform_get_irq_byname(pdev, renesas_i3c_irqs[i].name); 1354 if (ret < 0) 1355 return ret; 1356 1357 ret = devm_request_irq(&pdev->dev, ret, renesas_i3c_irqs[i].isr, 1358 0, renesas_i3c_irqs[i].desc, i3c); 1359 if (ret) 1360 return ret; 1361 } 1362 1363 platform_set_drvdata(pdev, i3c); 1364 1365 i3c->maxdevs = RENESAS_I3C_MAX_DEVS; 1366 i3c->free_pos = GENMASK(i3c->maxdevs - 1, 0); 1367 1368 /* Allocate dynamic Device Address Table backup. */ 1369 i3c->DATBASn = devm_kzalloc(&pdev->dev, sizeof(u32) * i3c->maxdevs, 1370 GFP_KERNEL); 1371 if (!i3c->DATBASn) 1372 return -ENOMEM; 1373 1374 return i3c_master_register(&i3c->base, &pdev->dev, &renesas_i3c_ops, false); 1375 } 1376 1377 static void renesas_i3c_remove(struct platform_device *pdev) 1378 { 1379 struct renesas_i3c *i3c = platform_get_drvdata(pdev); 1380 1381 i3c_master_unregister(&i3c->base); 1382 } 1383 1384 static int renesas_i3c_suspend_noirq(struct device *dev) 1385 { 1386 struct renesas_i3c *i3c = dev_get_drvdata(dev); 1387 int i, ret; 1388 1389 i2c_mark_adapter_suspended(&i3c->base.i2c); 1390 1391 /* Store Device Address Table values. */ 1392 for (i = 0; i < i3c->maxdevs; i++) 1393 i3c->DATBASn[i] = renesas_readl(i3c->regs, DATBAS(i)); 1394 1395 ret = reset_control_assert(i3c->presetn); 1396 if (ret) 1397 goto err_mark_resumed; 1398 1399 ret = reset_control_assert(i3c->tresetn); 1400 if (ret) 1401 goto err_presetn; 1402 1403 clk_bulk_disable(i3c->num_clks, i3c->clks); 1404 1405 return 0; 1406 1407 err_presetn: 1408 reset_control_deassert(i3c->presetn); 1409 err_mark_resumed: 1410 i2c_mark_adapter_resumed(&i3c->base.i2c); 1411 1412 return ret; 1413 } 1414 1415 static int renesas_i3c_resume_noirq(struct device *dev) 1416 { 1417 struct renesas_i3c *i3c = dev_get_drvdata(dev); 1418 int i, ret; 1419 1420 ret = reset_control_deassert(i3c->presetn); 1421 if (ret) 1422 return ret; 1423 1424 ret = reset_control_deassert(i3c->tresetn); 1425 if (ret) 1426 goto err_presetn; 1427 1428 ret = clk_bulk_enable(i3c->num_clks, i3c->clks); 1429 if (ret) 1430 goto err_tresetn; 1431 1432 /* Re-store I3C registers value. */ 1433 renesas_writel(i3c->regs, REFCKCTL, 1434 REFCKCTL_IREFCKS(i3c->refclk_div)); 1435 renesas_writel(i3c->regs, MSDVAD, MSDVAD_MDYADV | 1436 MSDVAD_MDYAD(i3c->dyn_addr)); 1437 1438 /* Restore Device Address Table values. */ 1439 for (i = 0; i < i3c->maxdevs; i++) 1440 renesas_writel(i3c->regs, DATBAS(i), i3c->DATBASn[i]); 1441 1442 /* I3C hw init. */ 1443 renesas_i3c_hw_init(i3c); 1444 1445 i2c_mark_adapter_resumed(&i3c->base.i2c); 1446 1447 return 0; 1448 1449 err_tresetn: 1450 reset_control_assert(i3c->tresetn); 1451 err_presetn: 1452 reset_control_assert(i3c->presetn); 1453 return ret; 1454 } 1455 1456 static const struct dev_pm_ops renesas_i3c_pm_ops = { 1457 NOIRQ_SYSTEM_SLEEP_PM_OPS(renesas_i3c_suspend_noirq, 1458 renesas_i3c_resume_noirq) 1459 }; 1460 1461 static const struct of_device_id renesas_i3c_of_ids[] = { 1462 { .compatible = "renesas,r9a08g045-i3c" }, 1463 { .compatible = "renesas,r9a09g047-i3c" }, 1464 { /* sentinel */ }, 1465 }; 1466 MODULE_DEVICE_TABLE(of, renesas_i3c_of_ids); 1467 1468 static struct platform_driver renesas_i3c = { 1469 .probe = renesas_i3c_probe, 1470 .remove = renesas_i3c_remove, 1471 .driver = { 1472 .name = "renesas-i3c", 1473 .of_match_table = renesas_i3c_of_ids, 1474 .pm = pm_sleep_ptr(&renesas_i3c_pm_ops), 1475 }, 1476 }; 1477 module_platform_driver(renesas_i3c); 1478 1479 MODULE_AUTHOR("Wolfram Sang <wsa+renesas@sang-engineering.com>"); 1480 MODULE_AUTHOR("Renesas BSP teams"); 1481 MODULE_DESCRIPTION("Renesas I3C controller driver"); 1482 MODULE_LICENSE("GPL"); 1483