1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * DBAu1200/PBAu1200 board platform device registration 4 * 5 * Copyright (C) 2008-2011 Manuel Lauss 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/dma-mapping.h> 10 #include <linux/gpio.h> 11 #include <linux/i2c.h> 12 #include <linux/init.h> 13 #include <linux/interrupt.h> 14 #include <linux/io.h> 15 #include <linux/leds.h> 16 #include <linux/mmc/host.h> 17 #include <linux/mtd/mtd.h> 18 #include <linux/mtd/platnand.h> 19 #include <linux/platform_device.h> 20 #include <linux/serial_8250.h> 21 #include <linux/spi/spi.h> 22 #include <linux/spi/flash.h> 23 #include <linux/smc91x.h> 24 #include <linux/ata_platform.h> 25 #include <asm/mach-au1x00/au1000.h> 26 #include <asm/mach-au1x00/au1100_mmc.h> 27 #include <asm/mach-au1x00/au1xxx_dbdma.h> 28 #include <asm/mach-au1x00/au1xxx_psc.h> 29 #include <asm/mach-au1x00/au1200fb.h> 30 #include <asm/mach-au1x00/au1550_spi.h> 31 #include <asm/mach-db1x00/bcsr.h> 32 33 #include "db1xxx.h" 34 #include "platform.h" 35 36 #define BCSR_INT_IDE 0x0001 37 #define BCSR_INT_ETH 0x0002 38 #define BCSR_INT_PC0 0x0004 39 #define BCSR_INT_PC0STSCHG 0x0008 40 #define BCSR_INT_PC1 0x0010 41 #define BCSR_INT_PC1STSCHG 0x0020 42 #define BCSR_INT_DC 0x0040 43 #define BCSR_INT_FLASHBUSY 0x0080 44 #define BCSR_INT_PC0INSERT 0x0100 45 #define BCSR_INT_PC0EJECT 0x0200 46 #define BCSR_INT_PC1INSERT 0x0400 47 #define BCSR_INT_PC1EJECT 0x0800 48 #define BCSR_INT_SD0INSERT 0x1000 49 #define BCSR_INT_SD0EJECT 0x2000 50 #define BCSR_INT_SD1INSERT 0x4000 51 #define BCSR_INT_SD1EJECT 0x8000 52 53 #define DB1200_IDE_PHYS_ADDR 0x18800000 54 #define DB1200_IDE_REG_SHIFT 5 55 #define DB1200_IDE_PHYS_LEN (16 << DB1200_IDE_REG_SHIFT) 56 #define DB1200_ETH_PHYS_ADDR 0x19000300 57 #define DB1200_NAND_PHYS_ADDR 0x20000000 58 59 #define PB1200_IDE_PHYS_ADDR 0x0C800000 60 #define PB1200_ETH_PHYS_ADDR 0x0D000300 61 #define PB1200_NAND_PHYS_ADDR 0x1C000000 62 63 #define DB1200_INT_BEGIN (AU1000_MAX_INTR + 1) 64 #define DB1200_IDE_INT (DB1200_INT_BEGIN + 0) 65 #define DB1200_ETH_INT (DB1200_INT_BEGIN + 1) 66 #define DB1200_PC0_INT (DB1200_INT_BEGIN + 2) 67 #define DB1200_PC0_STSCHG_INT (DB1200_INT_BEGIN + 3) 68 #define DB1200_PC1_INT (DB1200_INT_BEGIN + 4) 69 #define DB1200_PC1_STSCHG_INT (DB1200_INT_BEGIN + 5) 70 #define DB1200_DC_INT (DB1200_INT_BEGIN + 6) 71 #define DB1200_FLASHBUSY_INT (DB1200_INT_BEGIN + 7) 72 #define DB1200_PC0_INSERT_INT (DB1200_INT_BEGIN + 8) 73 #define DB1200_PC0_EJECT_INT (DB1200_INT_BEGIN + 9) 74 #define DB1200_PC1_INSERT_INT (DB1200_INT_BEGIN + 10) 75 #define DB1200_PC1_EJECT_INT (DB1200_INT_BEGIN + 11) 76 #define DB1200_SD0_INSERT_INT (DB1200_INT_BEGIN + 12) 77 #define DB1200_SD0_EJECT_INT (DB1200_INT_BEGIN + 13) 78 #define PB1200_SD1_INSERT_INT (DB1200_INT_BEGIN + 14) 79 #define PB1200_SD1_EJECT_INT (DB1200_INT_BEGIN + 15) 80 #define DB1200_INT_END (DB1200_INT_BEGIN + 15) 81 82 const char *get_system_type(void); 83 84 static int __init db1200_detect_board(void) 85 { 86 int bid; 87 88 /* try the DB1200 first */ 89 bcsr_init(DB1200_BCSR_PHYS_ADDR, 90 DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS); 91 if (BCSR_WHOAMI_DB1200 == BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) { 92 unsigned short t = bcsr_read(BCSR_HEXLEDS); 93 bcsr_write(BCSR_HEXLEDS, ~t); 94 if (bcsr_read(BCSR_HEXLEDS) != t) { 95 bcsr_write(BCSR_HEXLEDS, t); 96 return 0; 97 } 98 } 99 100 /* okay, try the PB1200 then */ 101 bcsr_init(PB1200_BCSR_PHYS_ADDR, 102 PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS); 103 bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)); 104 if ((bid == BCSR_WHOAMI_PB1200_DDR1) || 105 (bid == BCSR_WHOAMI_PB1200_DDR2)) { 106 unsigned short t = bcsr_read(BCSR_HEXLEDS); 107 bcsr_write(BCSR_HEXLEDS, ~t); 108 if (bcsr_read(BCSR_HEXLEDS) != t) { 109 bcsr_write(BCSR_HEXLEDS, t); 110 return 0; 111 } 112 } 113 114 return 1; /* it's neither */ 115 } 116 117 int __init db1200_board_setup(void) 118 { 119 unsigned short whoami; 120 121 if (db1200_detect_board()) 122 return -ENODEV; 123 124 whoami = bcsr_read(BCSR_WHOAMI); 125 switch (BCSR_WHOAMI_BOARD(whoami)) { 126 case BCSR_WHOAMI_PB1200_DDR1: 127 case BCSR_WHOAMI_PB1200_DDR2: 128 case BCSR_WHOAMI_DB1200: 129 break; 130 default: 131 return -ENODEV; 132 } 133 134 printk(KERN_INFO "Alchemy/AMD/RMI %s Board, CPLD Rev %d" 135 " Board-ID %d Daughtercard ID %d\n", get_system_type(), 136 (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf); 137 138 return 0; 139 } 140 141 /******************************************************************************/ 142 143 static u64 au1200_all_dmamask = DMA_BIT_MASK(32); 144 145 static struct mtd_partition db1200_spiflash_parts[] = { 146 { 147 .name = "spi_flash", 148 .offset = 0, 149 .size = MTDPART_SIZ_FULL, 150 }, 151 }; 152 153 static struct flash_platform_data db1200_spiflash_data = { 154 .name = "s25fl001", 155 .parts = db1200_spiflash_parts, 156 .nr_parts = ARRAY_SIZE(db1200_spiflash_parts), 157 .type = "m25p10", 158 }; 159 160 static struct spi_board_info db1200_spi_devs[] __initdata = { 161 { 162 /* TI TMP121AIDBVR temp sensor */ 163 .modalias = "tmp121", 164 .max_speed_hz = 2000000, 165 .bus_num = 0, 166 .chip_select = 0, 167 .mode = 0, 168 }, 169 { 170 /* Spansion S25FL001D0FMA SPI flash */ 171 .modalias = "m25p80", 172 .max_speed_hz = 50000000, 173 .bus_num = 0, 174 .chip_select = 1, 175 .mode = 0, 176 .platform_data = &db1200_spiflash_data, 177 }, 178 }; 179 180 static struct i2c_board_info db1200_i2c_devs[] __initdata = { 181 { I2C_BOARD_INFO("24c04", 0x52), }, /* AT24C04-10 I2C eeprom */ 182 { I2C_BOARD_INFO("ne1619", 0x2d), }, /* adm1025-compat hwmon */ 183 { I2C_BOARD_INFO("wm8731", 0x1b), }, /* I2S audio codec WM8731 */ 184 }; 185 186 /**********************************************************************/ 187 188 static void au1200_nand_cmd_ctrl(struct nand_chip *this, int cmd, 189 unsigned int ctrl) 190 { 191 unsigned long ioaddr = (unsigned long)this->legacy.IO_ADDR_W; 192 193 ioaddr &= 0xffffff00; 194 195 if (ctrl & NAND_CLE) { 196 ioaddr += MEM_STNAND_CMD; 197 } else if (ctrl & NAND_ALE) { 198 ioaddr += MEM_STNAND_ADDR; 199 } else { 200 /* assume we want to r/w real data by default */ 201 ioaddr += MEM_STNAND_DATA; 202 } 203 this->legacy.IO_ADDR_R = this->legacy.IO_ADDR_W = (void __iomem *)ioaddr; 204 if (cmd != NAND_CMD_NONE) { 205 __raw_writeb(cmd, this->legacy.IO_ADDR_W); 206 wmb(); 207 } 208 } 209 210 static int au1200_nand_device_ready(struct nand_chip *this) 211 { 212 return alchemy_rdsmem(AU1000_MEM_STSTAT) & 1; 213 } 214 215 static struct mtd_partition db1200_nand_parts[] = { 216 { 217 .name = "NAND FS 0", 218 .offset = 0, 219 .size = 8 * 1024 * 1024, 220 }, 221 { 222 .name = "NAND FS 1", 223 .offset = MTDPART_OFS_APPEND, 224 .size = MTDPART_SIZ_FULL 225 }, 226 }; 227 228 struct platform_nand_data db1200_nand_platdata = { 229 .chip = { 230 .nr_chips = 1, 231 .chip_offset = 0, 232 .nr_partitions = ARRAY_SIZE(db1200_nand_parts), 233 .partitions = db1200_nand_parts, 234 .chip_delay = 20, 235 }, 236 .ctrl = { 237 .dev_ready = au1200_nand_device_ready, 238 .cmd_ctrl = au1200_nand_cmd_ctrl, 239 }, 240 }; 241 242 static struct resource db1200_nand_res[] = { 243 [0] = { 244 .start = DB1200_NAND_PHYS_ADDR, 245 .end = DB1200_NAND_PHYS_ADDR + 0xff, 246 .flags = IORESOURCE_MEM, 247 }, 248 }; 249 250 static struct platform_device db1200_nand_dev = { 251 .name = "gen_nand", 252 .num_resources = ARRAY_SIZE(db1200_nand_res), 253 .resource = db1200_nand_res, 254 .id = -1, 255 .dev = { 256 .platform_data = &db1200_nand_platdata, 257 } 258 }; 259 260 /**********************************************************************/ 261 262 static struct smc91x_platdata db1200_eth_data = { 263 .flags = SMC91X_NOWAIT | SMC91X_USE_16BIT, 264 .leda = RPC_LED_100_10, 265 .ledb = RPC_LED_TX_RX, 266 }; 267 268 static struct resource db1200_eth_res[] = { 269 [0] = { 270 .start = DB1200_ETH_PHYS_ADDR, 271 .end = DB1200_ETH_PHYS_ADDR + 0xf, 272 .flags = IORESOURCE_MEM, 273 }, 274 [1] = { 275 .start = DB1200_ETH_INT, 276 .end = DB1200_ETH_INT, 277 .flags = IORESOURCE_IRQ, 278 }, 279 }; 280 281 static struct platform_device db1200_eth_dev = { 282 .dev = { 283 .platform_data = &db1200_eth_data, 284 }, 285 .name = "smc91x", 286 .id = -1, 287 .num_resources = ARRAY_SIZE(db1200_eth_res), 288 .resource = db1200_eth_res, 289 }; 290 291 /**********************************************************************/ 292 293 static struct pata_platform_info db1200_ide_info = { 294 .ioport_shift = DB1200_IDE_REG_SHIFT, 295 }; 296 297 #define IDE_ALT_START (14 << DB1200_IDE_REG_SHIFT) 298 static struct resource db1200_ide_res[] = { 299 [0] = { 300 .start = DB1200_IDE_PHYS_ADDR, 301 .end = DB1200_IDE_PHYS_ADDR + IDE_ALT_START - 1, 302 .flags = IORESOURCE_MEM, 303 }, 304 [1] = { 305 .start = DB1200_IDE_PHYS_ADDR + IDE_ALT_START, 306 .end = DB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1, 307 .flags = IORESOURCE_MEM, 308 }, 309 [2] = { 310 .start = DB1200_IDE_INT, 311 .end = DB1200_IDE_INT, 312 .flags = IORESOURCE_IRQ, 313 }, 314 }; 315 316 static struct platform_device db1200_ide_dev = { 317 .name = "pata_platform", 318 .id = 0, 319 .dev = { 320 .dma_mask = &au1200_all_dmamask, 321 .coherent_dma_mask = DMA_BIT_MASK(32), 322 .platform_data = &db1200_ide_info, 323 }, 324 .num_resources = ARRAY_SIZE(db1200_ide_res), 325 .resource = db1200_ide_res, 326 }; 327 328 /**********************************************************************/ 329 330 #ifdef CONFIG_MMC_AU1X 331 /* SD carddetects: they're supposed to be edge-triggered, but ack 332 * doesn't seem to work (CPLD Rev 2). Instead, the screaming one 333 * is disabled and its counterpart enabled. The 200ms timeout is 334 * because the carddetect usually triggers twice, after debounce. 335 */ 336 static irqreturn_t db1200_mmc_cd(int irq, void *ptr) 337 { 338 disable_irq_nosync(irq); 339 return IRQ_WAKE_THREAD; 340 } 341 342 static irqreturn_t db1200_mmc_cdfn(int irq, void *ptr) 343 { 344 mmc_detect_change(ptr, msecs_to_jiffies(200)); 345 346 msleep(100); /* debounce */ 347 if (irq == DB1200_SD0_INSERT_INT) 348 enable_irq(DB1200_SD0_EJECT_INT); 349 else 350 enable_irq(DB1200_SD0_INSERT_INT); 351 352 return IRQ_HANDLED; 353 } 354 355 static int db1200_mmc_cd_setup(void *mmc_host, int en) 356 { 357 int ret; 358 359 if (en) { 360 ret = request_threaded_irq(DB1200_SD0_INSERT_INT, db1200_mmc_cd, 361 db1200_mmc_cdfn, 0, "sd_insert", mmc_host); 362 if (ret) 363 goto out; 364 365 ret = request_threaded_irq(DB1200_SD0_EJECT_INT, db1200_mmc_cd, 366 db1200_mmc_cdfn, 0, "sd_eject", mmc_host); 367 if (ret) { 368 free_irq(DB1200_SD0_INSERT_INT, mmc_host); 369 goto out; 370 } 371 372 if (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT) 373 enable_irq(DB1200_SD0_EJECT_INT); 374 else 375 enable_irq(DB1200_SD0_INSERT_INT); 376 377 } else { 378 free_irq(DB1200_SD0_INSERT_INT, mmc_host); 379 free_irq(DB1200_SD0_EJECT_INT, mmc_host); 380 } 381 ret = 0; 382 out: 383 return ret; 384 } 385 386 static void db1200_mmc_set_power(void *mmc_host, int state) 387 { 388 if (state) { 389 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD0PWR); 390 msleep(400); /* stabilization time */ 391 } else 392 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD0PWR, 0); 393 } 394 395 static int db1200_mmc_card_readonly(void *mmc_host) 396 { 397 return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 1 : 0; 398 } 399 400 static int db1200_mmc_card_inserted(void *mmc_host) 401 { 402 return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT) ? 1 : 0; 403 } 404 405 static void db1200_mmcled_set(struct led_classdev *led, 406 enum led_brightness brightness) 407 { 408 if (brightness != LED_OFF) 409 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0); 410 else 411 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0); 412 } 413 414 static struct led_classdev db1200_mmc_led = { 415 .brightness_set = db1200_mmcled_set, 416 }; 417 418 /* -- */ 419 420 static irqreturn_t pb1200_mmc1_cd(int irq, void *ptr) 421 { 422 disable_irq_nosync(irq); 423 return IRQ_WAKE_THREAD; 424 } 425 426 static irqreturn_t pb1200_mmc1_cdfn(int irq, void *ptr) 427 { 428 mmc_detect_change(ptr, msecs_to_jiffies(200)); 429 430 msleep(100); /* debounce */ 431 if (irq == PB1200_SD1_INSERT_INT) 432 enable_irq(PB1200_SD1_EJECT_INT); 433 else 434 enable_irq(PB1200_SD1_INSERT_INT); 435 436 return IRQ_HANDLED; 437 } 438 439 static int pb1200_mmc1_cd_setup(void *mmc_host, int en) 440 { 441 int ret; 442 443 if (en) { 444 ret = request_threaded_irq(PB1200_SD1_INSERT_INT, pb1200_mmc1_cd, 445 pb1200_mmc1_cdfn, 0, "sd1_insert", mmc_host); 446 if (ret) 447 goto out; 448 449 ret = request_threaded_irq(PB1200_SD1_EJECT_INT, pb1200_mmc1_cd, 450 pb1200_mmc1_cdfn, 0, "sd1_eject", mmc_host); 451 if (ret) { 452 free_irq(PB1200_SD1_INSERT_INT, mmc_host); 453 goto out; 454 } 455 456 if (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) 457 enable_irq(PB1200_SD1_EJECT_INT); 458 else 459 enable_irq(PB1200_SD1_INSERT_INT); 460 461 } else { 462 free_irq(PB1200_SD1_INSERT_INT, mmc_host); 463 free_irq(PB1200_SD1_EJECT_INT, mmc_host); 464 } 465 ret = 0; 466 out: 467 return ret; 468 } 469 470 static void pb1200_mmc1led_set(struct led_classdev *led, 471 enum led_brightness brightness) 472 { 473 if (brightness != LED_OFF) 474 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0); 475 else 476 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1); 477 } 478 479 static struct led_classdev pb1200_mmc1_led = { 480 .brightness_set = pb1200_mmc1led_set, 481 }; 482 483 static void pb1200_mmc1_set_power(void *mmc_host, int state) 484 { 485 if (state) { 486 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD1PWR); 487 msleep(400); /* stabilization time */ 488 } else 489 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD1PWR, 0); 490 } 491 492 static int pb1200_mmc1_card_readonly(void *mmc_host) 493 { 494 return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD1WP) ? 1 : 0; 495 } 496 497 static int pb1200_mmc1_card_inserted(void *mmc_host) 498 { 499 return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0; 500 } 501 502 503 static struct au1xmmc_platform_data db1200_mmc_platdata[2] = { 504 [0] = { 505 .cd_setup = db1200_mmc_cd_setup, 506 .set_power = db1200_mmc_set_power, 507 .card_inserted = db1200_mmc_card_inserted, 508 .card_readonly = db1200_mmc_card_readonly, 509 .led = &db1200_mmc_led, 510 }, 511 [1] = { 512 .cd_setup = pb1200_mmc1_cd_setup, 513 .set_power = pb1200_mmc1_set_power, 514 .card_inserted = pb1200_mmc1_card_inserted, 515 .card_readonly = pb1200_mmc1_card_readonly, 516 .led = &pb1200_mmc1_led, 517 }, 518 }; 519 520 static struct resource au1200_mmc0_resources[] = { 521 [0] = { 522 .start = AU1100_SD0_PHYS_ADDR, 523 .end = AU1100_SD0_PHYS_ADDR + 0xfff, 524 .flags = IORESOURCE_MEM, 525 }, 526 [1] = { 527 .start = AU1200_SD_INT, 528 .end = AU1200_SD_INT, 529 .flags = IORESOURCE_IRQ, 530 }, 531 [2] = { 532 .start = AU1200_DSCR_CMD0_SDMS_TX0, 533 .end = AU1200_DSCR_CMD0_SDMS_TX0, 534 .flags = IORESOURCE_DMA, 535 }, 536 [3] = { 537 .start = AU1200_DSCR_CMD0_SDMS_RX0, 538 .end = AU1200_DSCR_CMD0_SDMS_RX0, 539 .flags = IORESOURCE_DMA, 540 } 541 }; 542 543 static struct platform_device db1200_mmc0_dev = { 544 .name = "au1xxx-mmc", 545 .id = 0, 546 .dev = { 547 .dma_mask = &au1200_all_dmamask, 548 .coherent_dma_mask = DMA_BIT_MASK(32), 549 .platform_data = &db1200_mmc_platdata[0], 550 }, 551 .num_resources = ARRAY_SIZE(au1200_mmc0_resources), 552 .resource = au1200_mmc0_resources, 553 }; 554 555 static struct resource au1200_mmc1_res[] = { 556 [0] = { 557 .start = AU1100_SD1_PHYS_ADDR, 558 .end = AU1100_SD1_PHYS_ADDR + 0xfff, 559 .flags = IORESOURCE_MEM, 560 }, 561 [1] = { 562 .start = AU1200_SD_INT, 563 .end = AU1200_SD_INT, 564 .flags = IORESOURCE_IRQ, 565 }, 566 [2] = { 567 .start = AU1200_DSCR_CMD0_SDMS_TX1, 568 .end = AU1200_DSCR_CMD0_SDMS_TX1, 569 .flags = IORESOURCE_DMA, 570 }, 571 [3] = { 572 .start = AU1200_DSCR_CMD0_SDMS_RX1, 573 .end = AU1200_DSCR_CMD0_SDMS_RX1, 574 .flags = IORESOURCE_DMA, 575 } 576 }; 577 578 static struct platform_device pb1200_mmc1_dev = { 579 .name = "au1xxx-mmc", 580 .id = 1, 581 .dev = { 582 .dma_mask = &au1200_all_dmamask, 583 .coherent_dma_mask = DMA_BIT_MASK(32), 584 .platform_data = &db1200_mmc_platdata[1], 585 }, 586 .num_resources = ARRAY_SIZE(au1200_mmc1_res), 587 .resource = au1200_mmc1_res, 588 }; 589 #endif /* CONFIG_MMC_AU1X */ 590 591 /**********************************************************************/ 592 593 static int db1200fb_panel_index(void) 594 { 595 return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f; 596 } 597 598 static int db1200fb_panel_init(void) 599 { 600 /* Apply power */ 601 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | 602 BCSR_BOARD_LCDBL); 603 return 0; 604 } 605 606 static int db1200fb_panel_shutdown(void) 607 { 608 /* Remove power */ 609 bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | 610 BCSR_BOARD_LCDBL, 0); 611 return 0; 612 } 613 614 static struct au1200fb_platdata db1200fb_pd = { 615 .panel_index = db1200fb_panel_index, 616 .panel_init = db1200fb_panel_init, 617 .panel_shutdown = db1200fb_panel_shutdown, 618 }; 619 620 static struct resource au1200_lcd_res[] = { 621 [0] = { 622 .start = AU1200_LCD_PHYS_ADDR, 623 .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1, 624 .flags = IORESOURCE_MEM, 625 }, 626 [1] = { 627 .start = AU1200_LCD_INT, 628 .end = AU1200_LCD_INT, 629 .flags = IORESOURCE_IRQ, 630 } 631 }; 632 633 static struct platform_device au1200_lcd_dev = { 634 .name = "au1200-lcd", 635 .id = 0, 636 .dev = { 637 .dma_mask = &au1200_all_dmamask, 638 .coherent_dma_mask = DMA_BIT_MASK(32), 639 .platform_data = &db1200fb_pd, 640 }, 641 .num_resources = ARRAY_SIZE(au1200_lcd_res), 642 .resource = au1200_lcd_res, 643 }; 644 645 /**********************************************************************/ 646 647 static struct resource au1200_psc0_res[] = { 648 [0] = { 649 .start = AU1550_PSC0_PHYS_ADDR, 650 .end = AU1550_PSC0_PHYS_ADDR + 0xfff, 651 .flags = IORESOURCE_MEM, 652 }, 653 [1] = { 654 .start = AU1200_PSC0_INT, 655 .end = AU1200_PSC0_INT, 656 .flags = IORESOURCE_IRQ, 657 }, 658 [2] = { 659 .start = AU1200_DSCR_CMD0_PSC0_TX, 660 .end = AU1200_DSCR_CMD0_PSC0_TX, 661 .flags = IORESOURCE_DMA, 662 }, 663 [3] = { 664 .start = AU1200_DSCR_CMD0_PSC0_RX, 665 .end = AU1200_DSCR_CMD0_PSC0_RX, 666 .flags = IORESOURCE_DMA, 667 }, 668 }; 669 670 static struct platform_device db1200_i2c_dev = { 671 .name = "au1xpsc_smbus", 672 .id = 0, /* bus number */ 673 .num_resources = ARRAY_SIZE(au1200_psc0_res), 674 .resource = au1200_psc0_res, 675 }; 676 677 static void db1200_spi_cs_en(struct au1550_spi_info *spi, int cs, int pol) 678 { 679 if (cs) 680 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_SPISEL); 681 else 682 bcsr_mod(BCSR_RESETS, BCSR_RESETS_SPISEL, 0); 683 } 684 685 static struct au1550_spi_info db1200_spi_platdata = { 686 .mainclk_hz = 50000000, /* PSC0 clock */ 687 .num_chipselect = 2, 688 .activate_cs = db1200_spi_cs_en, 689 }; 690 691 static struct platform_device db1200_spi_dev = { 692 .dev = { 693 .dma_mask = &au1200_all_dmamask, 694 .coherent_dma_mask = DMA_BIT_MASK(32), 695 .platform_data = &db1200_spi_platdata, 696 }, 697 .name = "au1550-spi", 698 .id = 0, /* bus number */ 699 .num_resources = ARRAY_SIZE(au1200_psc0_res), 700 .resource = au1200_psc0_res, 701 }; 702 703 static struct resource au1200_psc1_res[] = { 704 [0] = { 705 .start = AU1550_PSC1_PHYS_ADDR, 706 .end = AU1550_PSC1_PHYS_ADDR + 0xfff, 707 .flags = IORESOURCE_MEM, 708 }, 709 [1] = { 710 .start = AU1200_PSC1_INT, 711 .end = AU1200_PSC1_INT, 712 .flags = IORESOURCE_IRQ, 713 }, 714 [2] = { 715 .start = AU1200_DSCR_CMD0_PSC1_TX, 716 .end = AU1200_DSCR_CMD0_PSC1_TX, 717 .flags = IORESOURCE_DMA, 718 }, 719 [3] = { 720 .start = AU1200_DSCR_CMD0_PSC1_RX, 721 .end = AU1200_DSCR_CMD0_PSC1_RX, 722 .flags = IORESOURCE_DMA, 723 }, 724 }; 725 726 /* AC97 or I2S device */ 727 static struct platform_device db1200_audio_dev = { 728 /* name assigned later based on switch setting */ 729 .id = 1, /* PSC ID */ 730 .num_resources = ARRAY_SIZE(au1200_psc1_res), 731 .resource = au1200_psc1_res, 732 }; 733 734 /* DB1200 ASoC card device */ 735 static struct platform_device db1200_sound_dev = { 736 /* name assigned later based on switch setting */ 737 .id = 1, /* PSC ID */ 738 .dev = { 739 .dma_mask = &au1200_all_dmamask, 740 .coherent_dma_mask = DMA_BIT_MASK(32), 741 }, 742 }; 743 744 static struct platform_device db1200_stac_dev = { 745 .name = "ac97-codec", 746 .id = 1, /* on PSC1 */ 747 }; 748 749 static struct platform_device db1200_audiodma_dev = { 750 .name = "au1xpsc-pcm", 751 .id = 1, /* PSC ID */ 752 }; 753 754 static struct platform_device *db1200_devs[] __initdata = { 755 NULL, /* PSC0, selected by S6.8 */ 756 &db1200_ide_dev, 757 #ifdef CONFIG_MMC_AU1X 758 &db1200_mmc0_dev, 759 #endif 760 &au1200_lcd_dev, 761 &db1200_eth_dev, 762 &db1200_nand_dev, 763 &db1200_audiodma_dev, 764 &db1200_audio_dev, 765 &db1200_stac_dev, 766 &db1200_sound_dev, 767 }; 768 769 static struct platform_device *pb1200_devs[] __initdata = { 770 #ifdef CONFIG_MMC_AU1X 771 &pb1200_mmc1_dev, 772 #endif 773 }; 774 775 /* Some peripheral base addresses differ on the PB1200 */ 776 static int __init pb1200_res_fixup(void) 777 { 778 /* CPLD Revs earlier than 4 cause problems */ 779 if (BCSR_WHOAMI_CPLD(bcsr_read(BCSR_WHOAMI)) <= 3) { 780 printk(KERN_ERR "WARNING!!!\n"); 781 printk(KERN_ERR "WARNING!!!\n"); 782 printk(KERN_ERR "PB1200 must be at CPLD rev 4. Please have\n"); 783 printk(KERN_ERR "the board updated to latest revisions.\n"); 784 printk(KERN_ERR "This software will not work reliably\n"); 785 printk(KERN_ERR "on anything older than CPLD rev 4.!\n"); 786 printk(KERN_ERR "WARNING!!!\n"); 787 printk(KERN_ERR "WARNING!!!\n"); 788 return 1; 789 } 790 791 db1200_nand_res[0].start = PB1200_NAND_PHYS_ADDR; 792 db1200_nand_res[0].end = PB1200_NAND_PHYS_ADDR + 0xff; 793 db1200_ide_res[0].start = PB1200_IDE_PHYS_ADDR; 794 db1200_ide_res[0].end = PB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1; 795 db1200_eth_res[0].start = PB1200_ETH_PHYS_ADDR; 796 db1200_eth_res[0].end = PB1200_ETH_PHYS_ADDR + 0xff; 797 return 0; 798 } 799 800 int __init db1200_dev_setup(void) 801 { 802 unsigned long pfc; 803 unsigned short sw; 804 int swapped, bid; 805 struct clk *c; 806 807 bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)); 808 if ((bid == BCSR_WHOAMI_PB1200_DDR1) || 809 (bid == BCSR_WHOAMI_PB1200_DDR2)) { 810 if (pb1200_res_fixup()) 811 return -ENODEV; 812 } 813 814 /* GPIO7 is low-level triggered CPLD cascade */ 815 irq_set_irq_type(AU1200_GPIO7_INT, IRQ_TYPE_LEVEL_LOW); 816 bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT); 817 818 /* SMBus/SPI on PSC0, Audio on PSC1 */ 819 pfc = alchemy_rdsys(AU1000_SYS_PINFUNC); 820 pfc &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B); 821 pfc &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B | SYS_PINFUNC_FS3); 822 pfc |= SYS_PINFUNC_P1C; /* SPI is configured later */ 823 alchemy_wrsys(pfc, AU1000_SYS_PINFUNC); 824 825 /* get 50MHz for I2C driver on PSC0 */ 826 c = clk_get(NULL, "psc0_intclk"); 827 if (!IS_ERR(c)) { 828 pfc = clk_round_rate(c, 50000000); 829 if ((pfc < 1) || (abs(50000000 - pfc) > 2500000)) 830 pr_warn("DB1200: can't get I2C close to 50MHz\n"); 831 else 832 clk_set_rate(c, pfc); 833 clk_prepare_enable(c); 834 clk_put(c); 835 } 836 837 /* insert/eject pairs: one of both is always screaming. To avoid 838 * issues they must not be automatically enabled when initially 839 * requested. 840 */ 841 irq_set_status_flags(DB1200_SD0_INSERT_INT, IRQ_NOAUTOEN); 842 irq_set_status_flags(DB1200_SD0_EJECT_INT, IRQ_NOAUTOEN); 843 irq_set_status_flags(DB1200_PC0_INSERT_INT, IRQ_NOAUTOEN); 844 irq_set_status_flags(DB1200_PC0_EJECT_INT, IRQ_NOAUTOEN); 845 irq_set_status_flags(DB1200_PC1_INSERT_INT, IRQ_NOAUTOEN); 846 irq_set_status_flags(DB1200_PC1_EJECT_INT, IRQ_NOAUTOEN); 847 848 i2c_register_board_info(0, db1200_i2c_devs, 849 ARRAY_SIZE(db1200_i2c_devs)); 850 spi_register_board_info(db1200_spi_devs, 851 ARRAY_SIZE(db1200_spi_devs)); 852 853 /* SWITCHES: S6.8 I2C/SPI selector (OFF=I2C ON=SPI) 854 * S6.7 AC97/I2S selector (OFF=AC97 ON=I2S) 855 * or S12 on the PB1200. 856 */ 857 858 /* NOTE: GPIO215 controls OTG VBUS supply. In SPI mode however 859 * this pin is claimed by PSC0 (unused though, but pinmux doesn't 860 * allow to free it without crippling the SPI interface). 861 * As a result, in SPI mode, OTG simply won't work (PSC0 uses 862 * it as an input pin which is pulled high on the boards). 863 */ 864 pfc = alchemy_rdsys(AU1000_SYS_PINFUNC) & ~SYS_PINFUNC_P0A; 865 866 /* switch off OTG VBUS supply */ 867 gpio_request(215, "otg-vbus"); 868 gpio_direction_output(215, 1); 869 870 printk(KERN_INFO "%s device configuration:\n", get_system_type()); 871 872 sw = bcsr_read(BCSR_SWITCHES); 873 if (sw & BCSR_SWITCHES_DIP_8) { 874 db1200_devs[0] = &db1200_i2c_dev; 875 bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0); 876 877 pfc |= (2 << 17); /* GPIO2 block owns GPIO215 */ 878 879 printk(KERN_INFO " S6.8 OFF: PSC0 mode I2C\n"); 880 printk(KERN_INFO " OTG port VBUS supply available!\n"); 881 } else { 882 db1200_devs[0] = &db1200_spi_dev; 883 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC0MUX); 884 885 pfc |= (1 << 17); /* PSC0 owns GPIO215 */ 886 887 printk(KERN_INFO " S6.8 ON : PSC0 mode SPI\n"); 888 printk(KERN_INFO " OTG port VBUS supply disabled\n"); 889 } 890 alchemy_wrsys(pfc, AU1000_SYS_PINFUNC); 891 892 /* Audio: DIP7 selects I2S(0)/AC97(1), but need I2C for I2S! 893 * so: DIP7=1 || DIP8=0 => AC97, DIP7=0 && DIP8=1 => I2S 894 */ 895 sw &= BCSR_SWITCHES_DIP_8 | BCSR_SWITCHES_DIP_7; 896 if (sw == BCSR_SWITCHES_DIP_8) { 897 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC1MUX); 898 db1200_audio_dev.name = "au1xpsc_i2s"; 899 db1200_sound_dev.name = "db1200-i2s"; 900 printk(KERN_INFO " S6.7 ON : PSC1 mode I2S\n"); 901 } else { 902 bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC1MUX, 0); 903 db1200_audio_dev.name = "au1xpsc_ac97"; 904 db1200_sound_dev.name = "db1200-ac97"; 905 printk(KERN_INFO " S6.7 OFF: PSC1 mode AC97\n"); 906 } 907 908 /* Audio PSC clock is supplied externally. (FIXME: platdata!!) */ 909 __raw_writel(PSC_SEL_CLK_SERCLK, 910 (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET); 911 wmb(); 912 913 db1x_register_pcmcia_socket( 914 AU1000_PCMCIA_ATTR_PHYS_ADDR, 915 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, 916 AU1000_PCMCIA_MEM_PHYS_ADDR, 917 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, 918 AU1000_PCMCIA_IO_PHYS_ADDR, 919 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, 920 DB1200_PC0_INT, DB1200_PC0_INSERT_INT, 921 /*DB1200_PC0_STSCHG_INT*/0, DB1200_PC0_EJECT_INT, 0); 922 923 db1x_register_pcmcia_socket( 924 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000, 925 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1, 926 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000, 927 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1, 928 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000, 929 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1, 930 DB1200_PC1_INT, DB1200_PC1_INSERT_INT, 931 /*DB1200_PC1_STSCHG_INT*/0, DB1200_PC1_EJECT_INT, 1); 932 933 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT; 934 db1x_register_norflash(64 << 20, 2, swapped); 935 936 platform_add_devices(db1200_devs, ARRAY_SIZE(db1200_devs)); 937 938 /* PB1200 is a DB1200 with a 2nd MMC and Camera connector */ 939 if ((bid == BCSR_WHOAMI_PB1200_DDR1) || 940 (bid == BCSR_WHOAMI_PB1200_DDR2)) 941 platform_add_devices(pb1200_devs, ARRAY_SIZE(pb1200_devs)); 942 943 return 0; 944 } 945