1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2018 Rockchip Electronics Co. Ltd.
4 *
5 * Author: Wyon Bi <bivvy.bi@rock-chips.com>
6 */
7
8 #include <linux/bits.h>
9 #include <linux/kernel.h>
10 #include <linux/clk.h>
11 #include <linux/iopoll.h>
12 #include <linux/clk-provider.h>
13 #include <linux/delay.h>
14 #include <linux/init.h>
15 #include <linux/mfd/syscon.h>
16 #include <linux/module.h>
17 #include <linux/of.h>
18 #include <linux/platform_device.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/reset.h>
21 #include <linux/time64.h>
22
23 #include <linux/phy/phy.h>
24 #include <linux/phy/phy-mipi-dphy.h>
25
26 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l)))
27
28 /*
29 * The offset address[7:0] is distributed two parts, one from the bit7 to bit5
30 * is the first address, the other from the bit4 to bit0 is the second address.
31 * when you configure the registers, you must set both of them. The Clock Lane
32 * and Data Lane use the same registers with the same second address, but the
33 * first address is different.
34 */
35 #define FIRST_ADDRESS(x) (((x) & 0x7) << 5)
36 #define SECOND_ADDRESS(x) (((x) & 0x1f) << 0)
37 #define PHY_REG(first, second) (FIRST_ADDRESS(first) | \
38 SECOND_ADDRESS(second))
39
40 /* Analog Register Part: reg00 */
41 #define BANDGAP_POWER_MASK BIT(7)
42 #define BANDGAP_POWER_DOWN BIT(7)
43 #define BANDGAP_POWER_ON 0
44 #define LANE_EN_MASK GENMASK(6, 2)
45 #define LANE_EN_CK BIT(6)
46 #define LANE_EN_3 BIT(5)
47 #define LANE_EN_2 BIT(4)
48 #define LANE_EN_1 BIT(3)
49 #define LANE_EN_0 BIT(2)
50 #define POWER_WORK_MASK GENMASK(1, 0)
51 #define POWER_WORK_ENABLE UPDATE(1, 1, 0)
52 #define POWER_WORK_DISABLE UPDATE(2, 1, 0)
53 /* Analog Register Part: reg01 */
54 #define REG_SYNCRST_MASK BIT(2)
55 #define REG_SYNCRST_RESET BIT(2)
56 #define REG_SYNCRST_NORMAL 0
57 #define REG_LDOPD_MASK BIT(1)
58 #define REG_LDOPD_POWER_DOWN BIT(1)
59 #define REG_LDOPD_POWER_ON 0
60 #define REG_PLLPD_MASK BIT(0)
61 #define REG_PLLPD_POWER_DOWN BIT(0)
62 #define REG_PLLPD_POWER_ON 0
63 /* Analog Register Part: reg03 */
64 #define REG_FBDIV_HI_MASK BIT(5)
65 #define REG_FBDIV_HI(x) UPDATE((x >> 8), 5, 5)
66 #define REG_PREDIV_MASK GENMASK(4, 0)
67 #define REG_PREDIV(x) UPDATE(x, 4, 0)
68 /* Analog Register Part: reg04 */
69 #define REG_FBDIV_LO_MASK GENMASK(7, 0)
70 #define REG_FBDIV_LO(x) UPDATE(x, 7, 0)
71 /* Analog Register Part: reg05 */
72 #define SAMPLE_CLOCK_PHASE_MASK GENMASK(6, 4)
73 #define SAMPLE_CLOCK_PHASE(x) UPDATE(x, 6, 4)
74 #define CLOCK_LANE_SKEW_PHASE_MASK GENMASK(2, 0)
75 #define CLOCK_LANE_SKEW_PHASE(x) UPDATE(x, 2, 0)
76 /* Analog Register Part: reg06 */
77 #define DATA_LANE_3_SKEW_PHASE_MASK GENMASK(6, 4)
78 #define DATA_LANE_3_SKEW_PHASE(x) UPDATE(x, 6, 4)
79 #define DATA_LANE_2_SKEW_PHASE_MASK GENMASK(2, 0)
80 #define DATA_LANE_2_SKEW_PHASE(x) UPDATE(x, 2, 0)
81 /* Analog Register Part: reg07 */
82 #define DATA_LANE_1_SKEW_PHASE_MASK GENMASK(6, 4)
83 #define DATA_LANE_1_SKEW_PHASE(x) UPDATE(x, 6, 4)
84 #define DATA_LANE_0_SKEW_PHASE_MASK GENMASK(2, 0)
85 #define DATA_LANE_0_SKEW_PHASE(x) UPDATE(x, 2, 0)
86 /* Analog Register Part: reg08 */
87 #define PLL_POST_DIV_ENABLE_MASK BIT(5)
88 #define PLL_POST_DIV_ENABLE BIT(5)
89 #define SAMPLE_CLOCK_DIRECTION_MASK BIT(4)
90 #define SAMPLE_CLOCK_DIRECTION_REVERSE BIT(4)
91 #define SAMPLE_CLOCK_DIRECTION_FORWARD 0
92 #define LOWFRE_EN_MASK BIT(5)
93 #define PLL_OUTPUT_FREQUENCY_DIV_BY_1 0
94 #define PLL_OUTPUT_FREQUENCY_DIV_BY_2 1
95 /* Analog Register Part: reg0b */
96 #define CLOCK_LANE_VOD_RANGE_SET_MASK GENMASK(3, 0)
97 #define CLOCK_LANE_VOD_RANGE_SET(x) UPDATE(x, 3, 0)
98 #define VOD_MIN_RANGE 0x1
99 #define VOD_MID_RANGE 0x3
100 #define VOD_BIG_RANGE 0x7
101 #define VOD_MAX_RANGE 0xf
102 /* Analog Register Part: reg18 */
103 #define LANE0_PRE_EMPHASIS_ENABLE_MASK BIT(6)
104 #define LANE0_PRE_EMPHASIS_ENABLE BIT(6)
105 #define LANE0_PRE_EMPHASIS_DISABLE 0
106 #define LANE1_PRE_EMPHASIS_ENABLE_MASK BIT(5)
107 #define LANE1_PRE_EMPHASIS_ENABLE BIT(5)
108 #define LANE1_PRE_EMPHASIS_DISABLE 0
109 /* Analog Register Part: reg19 */
110 #define PRE_EMPHASIS_RANGE_SET_MASK GENMASK(7, 6)
111 #define PRE_EMPHASIS_RANGE_SET(x) UPDATE(x, 7, 6)
112 /* Analog Register Part: reg1E */
113 #define PLL_MODE_SEL_MASK GENMASK(6, 5)
114 #define PLL_MODE_SEL_LVDS_MODE 0
115 #define PLL_MODE_SEL_MIPI_MODE BIT(5)
116 /* Analog Register Part: reg20 */
117 #define LANE0_PRE_EMPHASIS_RANGE_SET_MASK GENMASK(7, 6)
118 #define LANE0_PRE_EMPHASIS_RANGE_SET(x) UPDATE(x, 7, 6)
119 /* Analog Register Part: reg21 */
120 #define LANE1_PRE_EMPHASIS_RANGE_SET_MASK GENMASK(7, 6)
121 #define LANE1_PRE_EMPHASIS_RANGE_SET(x) UPDATE(x, 7, 6)
122 #define PRE_EMPHASIS_MIN_RANGE 0x0
123 #define PRE_EMPHASIS_MID_RANGE 0x1
124 #define PRE_EMPHASIS_MAX_RANGE 0x2
125 #define PRE_EMPHASIS_RESERVED_RANGE 0x3
126 /* Digital Register Part: reg00 */
127 #define REG_DIG_RSTN_MASK BIT(0)
128 #define REG_DIG_RSTN_NORMAL BIT(0)
129 #define REG_DIG_RSTN_RESET 0
130 /* Digital Register Part: reg01 */
131 #define INVERT_TXCLKESC_MASK BIT(1)
132 #define INVERT_TXCLKESC_ENABLE BIT(1)
133 #define INVERT_TXCLKESC_DISABLE 0
134 #define INVERT_TXBYTECLKHS_MASK BIT(0)
135 #define INVERT_TXBYTECLKHS_ENABLE BIT(0)
136 #define INVERT_TXBYTECLKHS_DISABLE 0
137 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg05 */
138 #define T_LPX_CNT_MASK GENMASK(5, 0)
139 #define T_LPX_CNT(x) UPDATE(x, 5, 0)
140 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg06 */
141 #define T_HS_ZERO_CNT_HI_MASK BIT(7)
142 #define T_HS_ZERO_CNT_HI(x) UPDATE(x, 7, 7)
143 #define T_HS_PREPARE_CNT_MASK GENMASK(6, 0)
144 #define T_HS_PREPARE_CNT(x) UPDATE(x, 6, 0)
145 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg07 */
146 #define T_HS_ZERO_CNT_LO_MASK GENMASK(5, 0)
147 #define T_HS_ZERO_CNT_LO(x) UPDATE(x, 5, 0)
148 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg08 */
149 #define T_HS_TRAIL_CNT_MASK GENMASK(6, 0)
150 #define T_HS_TRAIL_CNT(x) UPDATE(x, 6, 0)
151 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg09 */
152 #define T_HS_EXIT_CNT_LO_MASK GENMASK(4, 0)
153 #define T_HS_EXIT_CNT_LO(x) UPDATE(x, 4, 0)
154 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0a */
155 #define T_CLK_POST_CNT_LO_MASK GENMASK(3, 0)
156 #define T_CLK_POST_CNT_LO(x) UPDATE(x, 3, 0)
157 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0c */
158 #define LPDT_TX_PPI_SYNC_MASK BIT(2)
159 #define LPDT_TX_PPI_SYNC_ENABLE BIT(2)
160 #define LPDT_TX_PPI_SYNC_DISABLE 0
161 #define T_WAKEUP_CNT_HI_MASK GENMASK(1, 0)
162 #define T_WAKEUP_CNT_HI(x) UPDATE(x, 1, 0)
163 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0d */
164 #define T_WAKEUP_CNT_LO_MASK GENMASK(7, 0)
165 #define T_WAKEUP_CNT_LO(x) UPDATE(x, 7, 0)
166 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0e */
167 #define T_CLK_PRE_CNT_MASK GENMASK(3, 0)
168 #define T_CLK_PRE_CNT(x) UPDATE(x, 3, 0)
169 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg10 */
170 #define T_CLK_POST_CNT_HI_MASK GENMASK(7, 6)
171 #define T_CLK_POST_CNT_HI(x) UPDATE(x, 7, 6)
172 #define T_TA_GO_CNT_MASK GENMASK(5, 0)
173 #define T_TA_GO_CNT(x) UPDATE(x, 5, 0)
174 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg11 */
175 #define T_HS_EXIT_CNT_HI_MASK BIT(6)
176 #define T_HS_EXIT_CNT_HI(x) UPDATE(x, 6, 6)
177 #define T_TA_SURE_CNT_MASK GENMASK(5, 0)
178 #define T_TA_SURE_CNT(x) UPDATE(x, 5, 0)
179 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg12 */
180 #define T_TA_WAIT_CNT_MASK GENMASK(5, 0)
181 #define T_TA_WAIT_CNT(x) UPDATE(x, 5, 0)
182 /* LVDS Register Part: reg00 */
183 #define LVDS_DIGITAL_INTERNAL_RESET_MASK BIT(2)
184 #define LVDS_DIGITAL_INTERNAL_RESET_DISABLE BIT(2)
185 #define LVDS_DIGITAL_INTERNAL_RESET_ENABLE 0
186 /* LVDS Register Part: reg01 */
187 #define LVDS_DIGITAL_INTERNAL_ENABLE_MASK BIT(7)
188 #define LVDS_DIGITAL_INTERNAL_ENABLE BIT(7)
189 #define LVDS_DIGITAL_INTERNAL_DISABLE 0
190 /* LVDS Register Part: reg03 */
191 #define MODE_ENABLE_MASK GENMASK(2, 0)
192 #define TTL_MODE_ENABLE BIT(2)
193 #define LVDS_MODE_ENABLE BIT(1)
194 #define MIPI_MODE_ENABLE BIT(0)
195 /* LVDS Register Part: reg0b */
196 #define LVDS_LANE_EN_MASK GENMASK(7, 3)
197 #define LVDS_DATA_LANE0_EN BIT(7)
198 #define LVDS_DATA_LANE1_EN BIT(6)
199 #define LVDS_DATA_LANE2_EN BIT(5)
200 #define LVDS_DATA_LANE3_EN BIT(4)
201 #define LVDS_CLK_LANE_EN BIT(3)
202 #define LVDS_PLL_POWER_MASK BIT(2)
203 #define LVDS_PLL_POWER_OFF BIT(2)
204 #define LVDS_PLL_POWER_ON 0
205 #define LVDS_BANDGAP_POWER_MASK BIT(0)
206 #define LVDS_BANDGAP_POWER_DOWN BIT(0)
207 #define LVDS_BANDGAP_POWER_ON 0
208
209 #define DSI_PHY_RSTZ 0xa0
210 #define PHY_ENABLECLK BIT(2)
211 #define DSI_PHY_STATUS 0xb0
212 #define PHY_LOCK BIT(0)
213
214 enum phy_max_rate {
215 MAX_1GHZ,
216 MAX_1_5GHZ,
217 MAX_2_5GHZ,
218 };
219
220 struct inno_video_phy_plat_data {
221 const struct inno_mipi_dphy_timing *inno_mipi_dphy_timing_table;
222 const unsigned int num_timings;
223 enum phy_max_rate max_rate;
224 unsigned int max_lanes;
225 };
226
227 struct inno_dsidphy {
228 struct device *dev;
229 struct clk *ref_clk;
230 struct clk *pclk_phy;
231 struct clk *pclk_host;
232 const struct inno_video_phy_plat_data *pdata;
233 void __iomem *phy_base;
234 void __iomem *host_base;
235 struct reset_control *rst;
236 enum phy_mode mode;
237 struct phy_configure_opts_mipi_dphy dphy_cfg;
238
239 struct clk *pll_clk;
240 struct {
241 struct clk_hw hw;
242 u8 prediv;
243 u16 fbdiv;
244 unsigned long rate;
245 } pll;
246 };
247
248 enum {
249 REGISTER_PART_ANALOG,
250 REGISTER_PART_DIGITAL,
251 REGISTER_PART_CLOCK_LANE,
252 REGISTER_PART_DATA0_LANE,
253 REGISTER_PART_DATA1_LANE,
254 REGISTER_PART_DATA2_LANE,
255 REGISTER_PART_DATA3_LANE,
256 REGISTER_PART_LVDS,
257 };
258
259 struct inno_mipi_dphy_timing {
260 unsigned long rate;
261 u8 lpx;
262 u8 hs_prepare;
263 u8 clk_lane_hs_zero;
264 u8 data_lane_hs_zero;
265 u8 hs_trail;
266 };
267
268 static const
269 struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_1ghz[] = {
270 { 110000000, 0x0, 0x20, 0x16, 0x02, 0x22},
271 { 150000000, 0x0, 0x06, 0x16, 0x03, 0x45},
272 { 200000000, 0x0, 0x18, 0x17, 0x04, 0x0b},
273 { 250000000, 0x0, 0x05, 0x17, 0x05, 0x16},
274 { 300000000, 0x0, 0x51, 0x18, 0x06, 0x2c},
275 { 400000000, 0x0, 0x64, 0x19, 0x07, 0x33},
276 { 500000000, 0x0, 0x20, 0x1b, 0x07, 0x4e},
277 { 600000000, 0x0, 0x6a, 0x1d, 0x08, 0x3a},
278 { 700000000, 0x0, 0x3e, 0x1e, 0x08, 0x6a},
279 { 800000000, 0x0, 0x21, 0x1f, 0x09, 0x29},
280 {1000000000, 0x0, 0x09, 0x20, 0x09, 0x27},
281 };
282
283 static const
284 struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_1_5ghz[] = {
285 { 110, 0x02, 0x7f, 0x16, 0x02, 0x02},
286 { 150, 0x02, 0x7f, 0x16, 0x03, 0x02},
287 { 200, 0x02, 0x7f, 0x17, 0x04, 0x02},
288 { 250, 0x02, 0x7f, 0x17, 0x05, 0x04},
289 { 300, 0x02, 0x7f, 0x18, 0x06, 0x04},
290 { 400, 0x03, 0x7e, 0x19, 0x07, 0x04},
291 { 500, 0x03, 0x7c, 0x1b, 0x07, 0x08},
292 { 600, 0x03, 0x70, 0x1d, 0x08, 0x10},
293 { 700, 0x05, 0x40, 0x1e, 0x08, 0x30},
294 { 800, 0x05, 0x02, 0x1f, 0x09, 0x30},
295 {1000, 0x05, 0x08, 0x20, 0x09, 0x30},
296 {1200, 0x06, 0x03, 0x32, 0x14, 0x0f},
297 {1400, 0x09, 0x03, 0x32, 0x14, 0x0f},
298 {1500, 0x0d, 0x42, 0x36, 0x0e, 0x0f},
299 };
300
301 static const
302 struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_2_5ghz[] = {
303 { 110000000, 0x02, 0x7f, 0x16, 0x02, 0x02},
304 { 150000000, 0x02, 0x7f, 0x16, 0x03, 0x02},
305 { 200000000, 0x02, 0x7f, 0x17, 0x04, 0x02},
306 { 250000000, 0x02, 0x7f, 0x17, 0x05, 0x04},
307 { 300000000, 0x02, 0x7f, 0x18, 0x06, 0x04},
308 { 400000000, 0x03, 0x7e, 0x19, 0x07, 0x04},
309 { 500000000, 0x03, 0x7c, 0x1b, 0x07, 0x08},
310 { 600000000, 0x03, 0x70, 0x1d, 0x08, 0x10},
311 { 700000000, 0x05, 0x40, 0x1e, 0x08, 0x30},
312 { 800000000, 0x05, 0x02, 0x1f, 0x09, 0x30},
313 {1000000000, 0x05, 0x08, 0x20, 0x09, 0x30},
314 {1200000000, 0x06, 0x03, 0x32, 0x14, 0x0f},
315 {1400000000, 0x09, 0x03, 0x32, 0x14, 0x0f},
316 {1600000000, 0x0d, 0x42, 0x36, 0x0e, 0x0f},
317 {1800000000, 0x0e, 0x47, 0x7a, 0x0e, 0x0f},
318 {2000000000, 0x11, 0x64, 0x7a, 0x0e, 0x0b},
319 {2200000000, 0x13, 0x64, 0x7e, 0x15, 0x0b},
320 {2400000000, 0x13, 0x33, 0x7f, 0x15, 0x6a},
321 {2500000000, 0x15, 0x54, 0x7f, 0x15, 0x6a},
322 };
323
phy_update_bits(struct inno_dsidphy * inno,u8 first,u8 second,u8 mask,u8 val)324 static void phy_update_bits(struct inno_dsidphy *inno,
325 u8 first, u8 second, u8 mask, u8 val)
326 {
327 u32 reg = PHY_REG(first, second) << 2;
328 unsigned int tmp, orig;
329
330 orig = readl(inno->phy_base + reg);
331 tmp = orig & ~mask;
332 tmp |= val & mask;
333 writel(tmp, inno->phy_base + reg);
334 }
335
inno_dsidphy_pll_calc_rate(struct inno_dsidphy * inno,unsigned long rate)336 static unsigned long inno_dsidphy_pll_calc_rate(struct inno_dsidphy *inno,
337 unsigned long rate)
338 {
339 unsigned long prate = clk_get_rate(inno->ref_clk);
340 unsigned long best_freq = 0;
341 unsigned long fref, fout;
342 u8 min_prediv, max_prediv;
343 u8 _prediv, best_prediv = 1;
344 u16 _fbdiv, best_fbdiv = 1;
345 u32 min_delta = UINT_MAX;
346
347 /*
348 * The PLL output frequency can be calculated using a simple formula:
349 * PLL_Output_Frequency = (FREF / PREDIV * FBDIV) / 2
350 * PLL_Output_Frequency: it is equal to DDR-Clock-Frequency * 2
351 */
352 fref = prate / 2;
353 if (rate > 1000000000UL)
354 fout = 1000000000UL;
355 else
356 fout = rate;
357
358 /* 5Mhz < Fref / prediv < 40MHz */
359 min_prediv = DIV_ROUND_UP(fref, 40000000);
360 max_prediv = fref / 5000000;
361
362 for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) {
363 u64 tmp;
364 u32 delta;
365
366 tmp = (u64)fout * _prediv;
367 do_div(tmp, fref);
368 _fbdiv = tmp;
369
370 /*
371 * The possible settings of feedback divider are
372 * 12, 13, 14, 16, ~ 511
373 */
374 if (_fbdiv == 15)
375 continue;
376
377 if (_fbdiv < 12 || _fbdiv > 511)
378 continue;
379
380 tmp = (u64)_fbdiv * fref;
381 do_div(tmp, _prediv);
382
383 delta = abs(fout - tmp);
384 if (!delta) {
385 best_prediv = _prediv;
386 best_fbdiv = _fbdiv;
387 best_freq = tmp;
388 break;
389 } else if (delta < min_delta) {
390 best_prediv = _prediv;
391 best_fbdiv = _fbdiv;
392 best_freq = tmp;
393 min_delta = delta;
394 }
395 }
396
397 if (best_freq) {
398 inno->pll.prediv = best_prediv;
399 inno->pll.fbdiv = best_fbdiv;
400 inno->pll.rate = best_freq;
401 }
402
403 return best_freq;
404 }
405
inno_dsidphy_mipi_mode_enable(struct inno_dsidphy * inno)406 static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno)
407 {
408 struct phy_configure_opts_mipi_dphy *cfg = &inno->dphy_cfg;
409 const struct inno_mipi_dphy_timing *timings;
410 u32 t_txbyteclkhs, t_txclkesc;
411 u32 txbyteclkhs, txclkesc, esc_clk_div;
412 u32 hs_exit, clk_post, clk_pre, wakeup, lpx, ta_go, ta_sure, ta_wait;
413 u32 hs_prepare, hs_trail, hs_zero, clk_lane_hs_zero, data_lane_hs_zero;
414 unsigned int i;
415 u32 val;
416
417 timings = inno->pdata->inno_mipi_dphy_timing_table;
418
419 inno_dsidphy_pll_calc_rate(inno, cfg->hs_clk_rate);
420
421 /* Select MIPI mode */
422 phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
423 MODE_ENABLE_MASK, MIPI_MODE_ENABLE);
424 /* Configure PLL */
425 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
426 REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv));
427 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
428 REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv));
429 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04,
430 REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv));
431 if (inno->pdata->max_rate == MAX_2_5GHZ) {
432 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08,
433 PLL_POST_DIV_ENABLE_MASK, PLL_POST_DIV_ENABLE);
434 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x0b,
435 CLOCK_LANE_VOD_RANGE_SET_MASK,
436 CLOCK_LANE_VOD_RANGE_SET(VOD_MAX_RANGE));
437 } else if (inno->pdata->max_rate == MAX_1_5GHZ) {
438 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x18,
439 LANE0_PRE_EMPHASIS_ENABLE_MASK, LANE0_PRE_EMPHASIS_ENABLE);
440 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x18,
441 LANE1_PRE_EMPHASIS_ENABLE_MASK, LANE1_PRE_EMPHASIS_ENABLE);
442 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x19,
443 PRE_EMPHASIS_RANGE_SET_MASK,
444 PRE_EMPHASIS_RANGE_SET(PRE_EMPHASIS_MID_RANGE));
445 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x1a,
446 LANE0_PRE_EMPHASIS_RANGE_SET_MASK,
447 LANE0_PRE_EMPHASIS_RANGE_SET(PRE_EMPHASIS_MID_RANGE));
448 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x1b,
449 LANE1_PRE_EMPHASIS_RANGE_SET_MASK,
450 LANE1_PRE_EMPHASIS_RANGE_SET(PRE_EMPHASIS_MID_RANGE));
451 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x0b,
452 CLOCK_LANE_VOD_RANGE_SET_MASK,
453 CLOCK_LANE_VOD_RANGE_SET(VOD_MAX_RANGE));
454 }
455 /* Enable PLL and LDO */
456 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
457 REG_LDOPD_MASK | REG_PLLPD_MASK,
458 REG_LDOPD_POWER_ON | REG_PLLPD_POWER_ON);
459 /* Reset analog */
460 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
461 REG_SYNCRST_MASK, REG_SYNCRST_RESET);
462 udelay(1);
463 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
464 REG_SYNCRST_MASK, REG_SYNCRST_NORMAL);
465 /* Reset digital */
466 phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00,
467 REG_DIG_RSTN_MASK, REG_DIG_RSTN_RESET);
468 udelay(1);
469 phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00,
470 REG_DIG_RSTN_MASK, REG_DIG_RSTN_NORMAL);
471
472 txbyteclkhs = inno->pll.rate / 8;
473 t_txbyteclkhs = div_u64(PSEC_PER_SEC, txbyteclkhs);
474
475 esc_clk_div = DIV_ROUND_UP(txbyteclkhs, 20000000);
476 txclkesc = txbyteclkhs / esc_clk_div;
477 t_txclkesc = div_u64(PSEC_PER_SEC, txclkesc);
478
479 /*
480 * The value of counter for HS Ths-exit
481 * Ths-exit = Tpin_txbyteclkhs * value
482 */
483 hs_exit = DIV_ROUND_UP(cfg->hs_exit, t_txbyteclkhs);
484 /*
485 * The value of counter for HS Tclk-post
486 * Tclk-post = Tpin_txbyteclkhs * value
487 */
488 clk_post = DIV_ROUND_UP(cfg->clk_post, t_txbyteclkhs);
489 /*
490 * The value of counter for HS Tclk-pre
491 * Tclk-pre = Tpin_txbyteclkhs * value
492 */
493 clk_pre = DIV_ROUND_UP(cfg->clk_pre, BITS_PER_BYTE);
494
495 /*
496 * The value of counter for HS Tta-go
497 * Tta-go for turnaround
498 * Tta-go = Ttxclkesc * value
499 */
500 ta_go = DIV_ROUND_UP(cfg->ta_go, t_txclkesc);
501 /*
502 * The value of counter for HS Tta-sure
503 * Tta-sure for turnaround
504 * Tta-sure = Ttxclkesc * value
505 */
506 ta_sure = DIV_ROUND_UP(cfg->ta_sure, t_txclkesc);
507 /*
508 * The value of counter for HS Tta-wait
509 * Tta-wait for turnaround
510 * Tta-wait = Ttxclkesc * value
511 */
512 ta_wait = DIV_ROUND_UP(cfg->ta_get, t_txclkesc);
513
514 for (i = 0; i < inno->pdata->num_timings; i++)
515 if (inno->pll.rate <= timings[i].rate)
516 break;
517
518 if (i == inno->pdata->num_timings)
519 --i;
520
521 /*
522 * The value of counter for HS Tlpx Time
523 * Tlpx = Tpin_txbyteclkhs * (2 + value)
524 */
525 if (inno->pdata->max_rate == MAX_1GHZ) {
526 lpx = DIV_ROUND_UP(cfg->lpx, t_txbyteclkhs);
527 if (lpx >= 2)
528 lpx -= 2;
529 } else
530 lpx = timings[i].lpx;
531
532 hs_prepare = timings[i].hs_prepare;
533 hs_trail = timings[i].hs_trail;
534 clk_lane_hs_zero = timings[i].clk_lane_hs_zero;
535 data_lane_hs_zero = timings[i].data_lane_hs_zero;
536 wakeup = 0x3ff;
537
538 for (i = REGISTER_PART_CLOCK_LANE; i <= REGISTER_PART_DATA3_LANE; i++) {
539 if (i == REGISTER_PART_CLOCK_LANE)
540 hs_zero = clk_lane_hs_zero;
541 else
542 hs_zero = data_lane_hs_zero;
543
544 phy_update_bits(inno, i, 0x05, T_LPX_CNT_MASK,
545 T_LPX_CNT(lpx));
546 phy_update_bits(inno, i, 0x06, T_HS_PREPARE_CNT_MASK,
547 T_HS_PREPARE_CNT(hs_prepare));
548 if (inno->pdata->max_rate == MAX_2_5GHZ)
549 phy_update_bits(inno, i, 0x06, T_HS_ZERO_CNT_HI_MASK,
550 T_HS_ZERO_CNT_HI(hs_zero >> 6));
551 phy_update_bits(inno, i, 0x07, T_HS_ZERO_CNT_LO_MASK,
552 T_HS_ZERO_CNT_LO(hs_zero));
553 phy_update_bits(inno, i, 0x08, T_HS_TRAIL_CNT_MASK,
554 T_HS_TRAIL_CNT(hs_trail));
555 if (inno->pdata->max_rate == MAX_2_5GHZ)
556 phy_update_bits(inno, i, 0x11, T_HS_EXIT_CNT_HI_MASK,
557 T_HS_EXIT_CNT_HI(hs_exit >> 5));
558 phy_update_bits(inno, i, 0x09, T_HS_EXIT_CNT_LO_MASK,
559 T_HS_EXIT_CNT_LO(hs_exit));
560 if (inno->pdata->max_rate == MAX_2_5GHZ)
561 phy_update_bits(inno, i, 0x10, T_CLK_POST_CNT_HI_MASK,
562 T_CLK_POST_CNT_HI(clk_post >> 4));
563 phy_update_bits(inno, i, 0x0a, T_CLK_POST_CNT_LO_MASK,
564 T_CLK_POST_CNT_LO(clk_post));
565 phy_update_bits(inno, i, 0x0e, T_CLK_PRE_CNT_MASK,
566 T_CLK_PRE_CNT(clk_pre));
567 phy_update_bits(inno, i, 0x0c, T_WAKEUP_CNT_HI_MASK,
568 T_WAKEUP_CNT_HI(wakeup >> 8));
569 phy_update_bits(inno, i, 0x0d, T_WAKEUP_CNT_LO_MASK,
570 T_WAKEUP_CNT_LO(wakeup));
571 phy_update_bits(inno, i, 0x10, T_TA_GO_CNT_MASK,
572 T_TA_GO_CNT(ta_go));
573 phy_update_bits(inno, i, 0x11, T_TA_SURE_CNT_MASK,
574 T_TA_SURE_CNT(ta_sure));
575 phy_update_bits(inno, i, 0x12, T_TA_WAIT_CNT_MASK,
576 T_TA_WAIT_CNT(ta_wait));
577 }
578
579 /* Enable lanes on analog part */
580 switch (inno->pdata->max_lanes) {
581 case 1:
582 val = LANE_EN_0;
583 break;
584 case 2:
585 val = LANE_EN_0 | LANE_EN_1;
586 break;
587 case 3:
588 val = LANE_EN_0 | LANE_EN_1 | LANE_EN_2;
589 break;
590 case 4:
591 default:
592 val = LANE_EN_0 | LANE_EN_1 | LANE_EN_2 | LANE_EN_3;
593 break;
594 }
595
596 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
597 LANE_EN_MASK, LANE_EN_CK | val);
598 }
599
inno_dsidphy_lvds_mode_enable(struct inno_dsidphy * inno)600 static void inno_dsidphy_lvds_mode_enable(struct inno_dsidphy *inno)
601 {
602 u8 prediv = 2;
603 u16 fbdiv = 28;
604
605 /* Sample clock reverse direction */
606 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08,
607 SAMPLE_CLOCK_DIRECTION_MASK | LOWFRE_EN_MASK,
608 SAMPLE_CLOCK_DIRECTION_REVERSE |
609 PLL_OUTPUT_FREQUENCY_DIV_BY_1);
610
611 /* Select LVDS mode */
612 phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
613 MODE_ENABLE_MASK, LVDS_MODE_ENABLE);
614 /* Configure PLL */
615 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
616 REG_PREDIV_MASK, REG_PREDIV(prediv));
617 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
618 REG_FBDIV_HI_MASK, REG_FBDIV_HI(fbdiv));
619 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04,
620 REG_FBDIV_LO_MASK, REG_FBDIV_LO(fbdiv));
621 phy_update_bits(inno, REGISTER_PART_LVDS, 0x08, 0xff, 0xfc);
622 /* Enable PLL and Bandgap */
623 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
624 LVDS_PLL_POWER_MASK | LVDS_BANDGAP_POWER_MASK,
625 LVDS_PLL_POWER_ON | LVDS_BANDGAP_POWER_ON);
626
627 msleep(20);
628
629 /* Select PLL mode */
630 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x1e,
631 PLL_MODE_SEL_MASK, PLL_MODE_SEL_LVDS_MODE);
632
633 /* Reset LVDS digital logic */
634 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
635 LVDS_DIGITAL_INTERNAL_RESET_MASK,
636 LVDS_DIGITAL_INTERNAL_RESET_ENABLE);
637 udelay(1);
638 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
639 LVDS_DIGITAL_INTERNAL_RESET_MASK,
640 LVDS_DIGITAL_INTERNAL_RESET_DISABLE);
641 /* Enable LVDS digital logic */
642 phy_update_bits(inno, REGISTER_PART_LVDS, 0x01,
643 LVDS_DIGITAL_INTERNAL_ENABLE_MASK,
644 LVDS_DIGITAL_INTERNAL_ENABLE);
645 /* Enable LVDS analog driver */
646 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
647 LVDS_LANE_EN_MASK, LVDS_CLK_LANE_EN |
648 LVDS_DATA_LANE0_EN | LVDS_DATA_LANE1_EN |
649 LVDS_DATA_LANE2_EN | LVDS_DATA_LANE3_EN);
650 }
651
inno_dsidphy_power_on(struct phy * phy)652 static int inno_dsidphy_power_on(struct phy *phy)
653 {
654 struct inno_dsidphy *inno = phy_get_drvdata(phy);
655
656 clk_prepare_enable(inno->pclk_phy);
657 clk_prepare_enable(inno->ref_clk);
658 pm_runtime_get_sync(inno->dev);
659
660 /* Bandgap power on */
661 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
662 BANDGAP_POWER_MASK, BANDGAP_POWER_ON);
663 /* Enable power work */
664 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
665 POWER_WORK_MASK, POWER_WORK_ENABLE);
666
667 switch (inno->mode) {
668 case PHY_MODE_MIPI_DPHY:
669 inno_dsidphy_mipi_mode_enable(inno);
670 break;
671 case PHY_MODE_LVDS:
672 inno_dsidphy_lvds_mode_enable(inno);
673 break;
674 default:
675 return -EINVAL;
676 }
677
678 return 0;
679 }
680
inno_dsidphy_power_off(struct phy * phy)681 static int inno_dsidphy_power_off(struct phy *phy)
682 {
683 struct inno_dsidphy *inno = phy_get_drvdata(phy);
684
685 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, LANE_EN_MASK, 0);
686 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
687 REG_LDOPD_MASK | REG_PLLPD_MASK,
688 REG_LDOPD_POWER_DOWN | REG_PLLPD_POWER_DOWN);
689 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
690 POWER_WORK_MASK, POWER_WORK_DISABLE);
691 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
692 BANDGAP_POWER_MASK, BANDGAP_POWER_DOWN);
693
694 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, LVDS_LANE_EN_MASK, 0);
695 phy_update_bits(inno, REGISTER_PART_LVDS, 0x01,
696 LVDS_DIGITAL_INTERNAL_ENABLE_MASK,
697 LVDS_DIGITAL_INTERNAL_DISABLE);
698 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
699 LVDS_PLL_POWER_MASK | LVDS_BANDGAP_POWER_MASK,
700 LVDS_PLL_POWER_OFF | LVDS_BANDGAP_POWER_DOWN);
701
702 pm_runtime_put(inno->dev);
703 clk_disable_unprepare(inno->ref_clk);
704 clk_disable_unprepare(inno->pclk_phy);
705
706 return 0;
707 }
708
inno_dsidphy_set_mode(struct phy * phy,enum phy_mode mode,int submode)709 static int inno_dsidphy_set_mode(struct phy *phy, enum phy_mode mode,
710 int submode)
711 {
712 struct inno_dsidphy *inno = phy_get_drvdata(phy);
713
714 switch (mode) {
715 case PHY_MODE_MIPI_DPHY:
716 case PHY_MODE_LVDS:
717 inno->mode = mode;
718 break;
719 default:
720 return -EINVAL;
721 }
722
723 return 0;
724 }
725
inno_dsidphy_configure(struct phy * phy,union phy_configure_opts * opts)726 static int inno_dsidphy_configure(struct phy *phy,
727 union phy_configure_opts *opts)
728 {
729 struct inno_dsidphy *inno = phy_get_drvdata(phy);
730 int ret;
731
732 if (inno->mode != PHY_MODE_MIPI_DPHY)
733 return -EINVAL;
734
735 ret = phy_mipi_dphy_config_validate(&opts->mipi_dphy);
736 if (ret)
737 return ret;
738
739 memcpy(&inno->dphy_cfg, &opts->mipi_dphy, sizeof(inno->dphy_cfg));
740
741 return 0;
742 }
743
744 static const struct phy_ops inno_dsidphy_ops = {
745 .configure = inno_dsidphy_configure,
746 .set_mode = inno_dsidphy_set_mode,
747 .power_on = inno_dsidphy_power_on,
748 .power_off = inno_dsidphy_power_off,
749 .owner = THIS_MODULE,
750 };
751
752 static const struct inno_video_phy_plat_data max_1ghz_video_phy_plat_data = {
753 .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_1ghz,
754 .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1ghz),
755 .max_rate = MAX_1GHZ,
756 .max_lanes = 4,
757 };
758
759 static const struct inno_video_phy_plat_data max_1_5ghz_video_phy_plat_data = {
760 .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_1_5ghz,
761 .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1_5ghz),
762 .max_rate = MAX_1_5GHZ,
763 .max_lanes = 2,
764 };
765
766 static const struct inno_video_phy_plat_data max_2_5ghz_video_phy_plat_data = {
767 .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_2_5ghz,
768 .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_2_5ghz),
769 .max_rate = MAX_2_5GHZ,
770 .max_lanes = 4,
771 };
772
inno_dsidphy_probe(struct platform_device * pdev)773 static int inno_dsidphy_probe(struct platform_device *pdev)
774 {
775 struct device *dev = &pdev->dev;
776 struct inno_dsidphy *inno;
777 struct phy_provider *phy_provider;
778 struct phy *phy;
779 int ret;
780
781 inno = devm_kzalloc(dev, sizeof(*inno), GFP_KERNEL);
782 if (!inno)
783 return -ENOMEM;
784
785 inno->dev = dev;
786 inno->pdata = of_device_get_match_data(inno->dev);
787 platform_set_drvdata(pdev, inno);
788
789 inno->phy_base = devm_platform_ioremap_resource(pdev, 0);
790 if (IS_ERR(inno->phy_base))
791 return PTR_ERR(inno->phy_base);
792
793 inno->ref_clk = devm_clk_get(dev, "ref");
794 if (IS_ERR(inno->ref_clk)) {
795 ret = PTR_ERR(inno->ref_clk);
796 dev_err(dev, "failed to get ref clock: %d\n", ret);
797 return ret;
798 }
799
800 inno->pclk_phy = devm_clk_get(dev, "pclk");
801 if (IS_ERR(inno->pclk_phy)) {
802 ret = PTR_ERR(inno->pclk_phy);
803 dev_err(dev, "failed to get phy pclk: %d\n", ret);
804 return ret;
805 }
806
807 inno->rst = devm_reset_control_get(dev, "apb");
808 if (IS_ERR(inno->rst)) {
809 ret = PTR_ERR(inno->rst);
810 dev_err(dev, "failed to get system reset control: %d\n", ret);
811 return ret;
812 }
813
814 phy = devm_phy_create(dev, NULL, &inno_dsidphy_ops);
815 if (IS_ERR(phy)) {
816 ret = PTR_ERR(phy);
817 dev_err(dev, "failed to create phy: %d\n", ret);
818 return ret;
819 }
820
821 phy_set_drvdata(phy, inno);
822
823 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
824 if (IS_ERR(phy_provider)) {
825 ret = PTR_ERR(phy_provider);
826 dev_err(dev, "failed to register phy provider: %d\n", ret);
827 return ret;
828 }
829
830 pm_runtime_enable(dev);
831
832 return 0;
833 }
834
inno_dsidphy_remove(struct platform_device * pdev)835 static void inno_dsidphy_remove(struct platform_device *pdev)
836 {
837 struct inno_dsidphy *inno = platform_get_drvdata(pdev);
838
839 pm_runtime_disable(inno->dev);
840 }
841
842 static const struct of_device_id inno_dsidphy_of_match[] = {
843 {
844 .compatible = "rockchip,px30-dsi-dphy",
845 .data = &max_1ghz_video_phy_plat_data,
846 }, {
847 .compatible = "rockchip,rk3128-dsi-dphy",
848 .data = &max_1ghz_video_phy_plat_data,
849 }, {
850 .compatible = "rockchip,rk3368-dsi-dphy",
851 .data = &max_1ghz_video_phy_plat_data,
852 }, {
853 .compatible = "rockchip,rk3506-dsi-dphy",
854 .data = &max_1_5ghz_video_phy_plat_data,
855 }, {
856 .compatible = "rockchip,rk3568-dsi-dphy",
857 .data = &max_2_5ghz_video_phy_plat_data,
858 }, {
859 .compatible = "rockchip,rv1126-dsi-dphy",
860 .data = &max_2_5ghz_video_phy_plat_data,
861 },
862 {}
863 };
864 MODULE_DEVICE_TABLE(of, inno_dsidphy_of_match);
865
866 static struct platform_driver inno_dsidphy_driver = {
867 .driver = {
868 .name = "inno-dsidphy",
869 .of_match_table = of_match_ptr(inno_dsidphy_of_match),
870 },
871 .probe = inno_dsidphy_probe,
872 .remove = inno_dsidphy_remove,
873 };
874 module_platform_driver(inno_dsidphy_driver);
875
876 MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");
877 MODULE_DESCRIPTION("Innosilicon MIPI/LVDS/TTL Video Combo PHY driver");
878 MODULE_LICENSE("GPL v2");
879