1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for Cirrus Logic CS4281 based PCI soundcard 4 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>, 5 */ 6 7 #include <linux/io.h> 8 #include <linux/delay.h> 9 #include <linux/interrupt.h> 10 #include <linux/init.h> 11 #include <linux/pci.h> 12 #include <linux/slab.h> 13 #include <linux/gameport.h> 14 #include <linux/module.h> 15 #include <sound/core.h> 16 #include <sound/control.h> 17 #include <sound/pcm.h> 18 #include <sound/rawmidi.h> 19 #include <sound/ac97_codec.h> 20 #include <sound/tlv.h> 21 #include <sound/opl3.h> 22 #include <sound/initval.h> 23 24 25 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>"); 26 MODULE_DESCRIPTION("Cirrus Logic CS4281"); 27 MODULE_LICENSE("GPL"); 28 29 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 30 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 31 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */ 32 static bool dual_codec[SNDRV_CARDS]; /* dual codec */ 33 34 module_param_array(index, int, NULL, 0444); 35 MODULE_PARM_DESC(index, "Index value for CS4281 soundcard."); 36 module_param_array(id, charp, NULL, 0444); 37 MODULE_PARM_DESC(id, "ID string for CS4281 soundcard."); 38 module_param_array(enable, bool, NULL, 0444); 39 MODULE_PARM_DESC(enable, "Enable CS4281 soundcard."); 40 module_param_array(dual_codec, bool, NULL, 0444); 41 MODULE_PARM_DESC(dual_codec, "Secondary Codec ID (0 = disabled)."); 42 43 /* 44 * Direct registers 45 */ 46 47 #define CS4281_BA0_SIZE 0x1000 48 #define CS4281_BA1_SIZE 0x10000 49 50 /* 51 * BA0 registers 52 */ 53 #define BA0_HISR 0x0000 /* Host Interrupt Status Register */ 54 #define BA0_HISR_INTENA (1<<31) /* Internal Interrupt Enable Bit */ 55 #define BA0_HISR_MIDI (1<<22) /* MIDI port interrupt */ 56 #define BA0_HISR_FIFOI (1<<20) /* FIFO polled interrupt */ 57 #define BA0_HISR_DMAI (1<<18) /* DMA interrupt (half or end) */ 58 #define BA0_HISR_FIFO(c) (1<<(12+(c))) /* FIFO channel interrupt */ 59 #define BA0_HISR_DMA(c) (1<<(8+(c))) /* DMA channel interrupt */ 60 #define BA0_HISR_GPPI (1<<5) /* General Purpose Input (Primary chip) */ 61 #define BA0_HISR_GPSI (1<<4) /* General Purpose Input (Secondary chip) */ 62 #define BA0_HISR_GP3I (1<<3) /* GPIO3 pin Interrupt */ 63 #define BA0_HISR_GP1I (1<<2) /* GPIO1 pin Interrupt */ 64 #define BA0_HISR_VUPI (1<<1) /* VOLUP pin Interrupt */ 65 #define BA0_HISR_VDNI (1<<0) /* VOLDN pin Interrupt */ 66 67 #define BA0_HICR 0x0008 /* Host Interrupt Control Register */ 68 #define BA0_HICR_CHGM (1<<1) /* INTENA Change Mask */ 69 #define BA0_HICR_IEV (1<<0) /* INTENA Value */ 70 #define BA0_HICR_EOI (3<<0) /* End of Interrupt command */ 71 72 #define BA0_HIMR 0x000c /* Host Interrupt Mask Register */ 73 /* Use same contants as for BA0_HISR */ 74 75 #define BA0_IIER 0x0010 /* ISA Interrupt Enable Register */ 76 77 #define BA0_HDSR0 0x00f0 /* Host DMA Engine 0 Status Register */ 78 #define BA0_HDSR1 0x00f4 /* Host DMA Engine 1 Status Register */ 79 #define BA0_HDSR2 0x00f8 /* Host DMA Engine 2 Status Register */ 80 #define BA0_HDSR3 0x00fc /* Host DMA Engine 3 Status Register */ 81 82 #define BA0_HDSR_CH1P (1<<25) /* Channel 1 Pending */ 83 #define BA0_HDSR_CH2P (1<<24) /* Channel 2 Pending */ 84 #define BA0_HDSR_DHTC (1<<17) /* DMA Half Terminal Count */ 85 #define BA0_HDSR_DTC (1<<16) /* DMA Terminal Count */ 86 #define BA0_HDSR_DRUN (1<<15) /* DMA Running */ 87 #define BA0_HDSR_RQ (1<<7) /* Pending Request */ 88 89 #define BA0_DCA0 0x0110 /* Host DMA Engine 0 Current Address */ 90 #define BA0_DCC0 0x0114 /* Host DMA Engine 0 Current Count */ 91 #define BA0_DBA0 0x0118 /* Host DMA Engine 0 Base Address */ 92 #define BA0_DBC0 0x011c /* Host DMA Engine 0 Base Count */ 93 #define BA0_DCA1 0x0120 /* Host DMA Engine 1 Current Address */ 94 #define BA0_DCC1 0x0124 /* Host DMA Engine 1 Current Count */ 95 #define BA0_DBA1 0x0128 /* Host DMA Engine 1 Base Address */ 96 #define BA0_DBC1 0x012c /* Host DMA Engine 1 Base Count */ 97 #define BA0_DCA2 0x0130 /* Host DMA Engine 2 Current Address */ 98 #define BA0_DCC2 0x0134 /* Host DMA Engine 2 Current Count */ 99 #define BA0_DBA2 0x0138 /* Host DMA Engine 2 Base Address */ 100 #define BA0_DBC2 0x013c /* Host DMA Engine 2 Base Count */ 101 #define BA0_DCA3 0x0140 /* Host DMA Engine 3 Current Address */ 102 #define BA0_DCC3 0x0144 /* Host DMA Engine 3 Current Count */ 103 #define BA0_DBA3 0x0148 /* Host DMA Engine 3 Base Address */ 104 #define BA0_DBC3 0x014c /* Host DMA Engine 3 Base Count */ 105 #define BA0_DMR0 0x0150 /* Host DMA Engine 0 Mode */ 106 #define BA0_DCR0 0x0154 /* Host DMA Engine 0 Command */ 107 #define BA0_DMR1 0x0158 /* Host DMA Engine 1 Mode */ 108 #define BA0_DCR1 0x015c /* Host DMA Engine 1 Command */ 109 #define BA0_DMR2 0x0160 /* Host DMA Engine 2 Mode */ 110 #define BA0_DCR2 0x0164 /* Host DMA Engine 2 Command */ 111 #define BA0_DMR3 0x0168 /* Host DMA Engine 3 Mode */ 112 #define BA0_DCR3 0x016c /* Host DMA Engine 3 Command */ 113 114 #define BA0_DMR_DMA (1<<29) /* Enable DMA mode */ 115 #define BA0_DMR_POLL (1<<28) /* Enable poll mode */ 116 #define BA0_DMR_TBC (1<<25) /* Transfer By Channel */ 117 #define BA0_DMR_CBC (1<<24) /* Count By Channel (0 = frame resolution) */ 118 #define BA0_DMR_SWAPC (1<<22) /* Swap Left/Right Channels */ 119 #define BA0_DMR_SIZE20 (1<<20) /* Sample is 20-bit */ 120 #define BA0_DMR_USIGN (1<<19) /* Unsigned */ 121 #define BA0_DMR_BEND (1<<18) /* Big Endian */ 122 #define BA0_DMR_MONO (1<<17) /* Mono */ 123 #define BA0_DMR_SIZE8 (1<<16) /* Sample is 8-bit */ 124 #define BA0_DMR_TYPE_DEMAND (0<<6) 125 #define BA0_DMR_TYPE_SINGLE (1<<6) 126 #define BA0_DMR_TYPE_BLOCK (2<<6) 127 #define BA0_DMR_TYPE_CASCADE (3<<6) /* Not supported */ 128 #define BA0_DMR_DEC (1<<5) /* Access Increment (0) or Decrement (1) */ 129 #define BA0_DMR_AUTO (1<<4) /* Auto-Initialize */ 130 #define BA0_DMR_TR_VERIFY (0<<2) /* Verify Transfer */ 131 #define BA0_DMR_TR_WRITE (1<<2) /* Write Transfer */ 132 #define BA0_DMR_TR_READ (2<<2) /* Read Transfer */ 133 134 #define BA0_DCR_HTCIE (1<<17) /* Half Terminal Count Interrupt */ 135 #define BA0_DCR_TCIE (1<<16) /* Terminal Count Interrupt */ 136 #define BA0_DCR_MSK (1<<0) /* DMA Mask bit */ 137 138 #define BA0_FCR0 0x0180 /* FIFO Control 0 */ 139 #define BA0_FCR1 0x0184 /* FIFO Control 1 */ 140 #define BA0_FCR2 0x0188 /* FIFO Control 2 */ 141 #define BA0_FCR3 0x018c /* FIFO Control 3 */ 142 143 #define BA0_FCR_FEN (1<<31) /* FIFO Enable bit */ 144 #define BA0_FCR_DACZ (1<<30) /* DAC Zero */ 145 #define BA0_FCR_PSH (1<<29) /* Previous Sample Hold */ 146 #define BA0_FCR_RS(x) (((x)&0x1f)<<24) /* Right Slot Mapping */ 147 #define BA0_FCR_LS(x) (((x)&0x1f)<<16) /* Left Slot Mapping */ 148 #define BA0_FCR_SZ(x) (((x)&0x7f)<<8) /* FIFO buffer size (in samples) */ 149 #define BA0_FCR_OF(x) (((x)&0x7f)<<0) /* FIFO starting offset (in samples) */ 150 151 #define BA0_FPDR0 0x0190 /* FIFO Polled Data 0 */ 152 #define BA0_FPDR1 0x0194 /* FIFO Polled Data 1 */ 153 #define BA0_FPDR2 0x0198 /* FIFO Polled Data 2 */ 154 #define BA0_FPDR3 0x019c /* FIFO Polled Data 3 */ 155 156 #define BA0_FCHS 0x020c /* FIFO Channel Status */ 157 #define BA0_FCHS_RCO(x) (1<<(7+(((x)&3)<<3))) /* Right Channel Out */ 158 #define BA0_FCHS_LCO(x) (1<<(6+(((x)&3)<<3))) /* Left Channel Out */ 159 #define BA0_FCHS_MRP(x) (1<<(5+(((x)&3)<<3))) /* Move Read Pointer */ 160 #define BA0_FCHS_FE(x) (1<<(4+(((x)&3)<<3))) /* FIFO Empty */ 161 #define BA0_FCHS_FF(x) (1<<(3+(((x)&3)<<3))) /* FIFO Full */ 162 #define BA0_FCHS_IOR(x) (1<<(2+(((x)&3)<<3))) /* Internal Overrun Flag */ 163 #define BA0_FCHS_RCI(x) (1<<(1+(((x)&3)<<3))) /* Right Channel In */ 164 #define BA0_FCHS_LCI(x) (1<<(0+(((x)&3)<<3))) /* Left Channel In */ 165 166 #define BA0_FSIC0 0x0210 /* FIFO Status and Interrupt Control 0 */ 167 #define BA0_FSIC1 0x0214 /* FIFO Status and Interrupt Control 1 */ 168 #define BA0_FSIC2 0x0218 /* FIFO Status and Interrupt Control 2 */ 169 #define BA0_FSIC3 0x021c /* FIFO Status and Interrupt Control 3 */ 170 171 #define BA0_FSIC_FIC(x) (((x)&0x7f)<<24) /* FIFO Interrupt Count */ 172 #define BA0_FSIC_FORIE (1<<23) /* FIFO OverRun Interrupt Enable */ 173 #define BA0_FSIC_FURIE (1<<22) /* FIFO UnderRun Interrupt Enable */ 174 #define BA0_FSIC_FSCIE (1<<16) /* FIFO Sample Count Interrupt Enable */ 175 #define BA0_FSIC_FSC(x) (((x)&0x7f)<<8) /* FIFO Sample Count */ 176 #define BA0_FSIC_FOR (1<<7) /* FIFO OverRun */ 177 #define BA0_FSIC_FUR (1<<6) /* FIFO UnderRun */ 178 #define BA0_FSIC_FSCR (1<<0) /* FIFO Sample Count Reached */ 179 180 #define BA0_PMCS 0x0344 /* Power Management Control/Status */ 181 #define BA0_CWPR 0x03e0 /* Configuration Write Protect */ 182 183 #define BA0_EPPMC 0x03e4 /* Extended PCI Power Management Control */ 184 #define BA0_EPPMC_FPDN (1<<14) /* Full Power DowN */ 185 186 #define BA0_GPIOR 0x03e8 /* GPIO Pin Interface Register */ 187 188 #define BA0_SPMC 0x03ec /* Serial Port Power Management Control (& ASDIN2 enable) */ 189 #define BA0_SPMC_GIPPEN (1<<15) /* GP INT Primary PME# Enable */ 190 #define BA0_SPMC_GISPEN (1<<14) /* GP INT Secondary PME# Enable */ 191 #define BA0_SPMC_EESPD (1<<9) /* EEPROM Serial Port Disable */ 192 #define BA0_SPMC_ASDI2E (1<<8) /* ASDIN2 Enable */ 193 #define BA0_SPMC_ASDO (1<<7) /* Asynchronous ASDOUT Assertion */ 194 #define BA0_SPMC_WUP2 (1<<3) /* Wakeup for Secondary Input */ 195 #define BA0_SPMC_WUP1 (1<<2) /* Wakeup for Primary Input */ 196 #define BA0_SPMC_ASYNC (1<<1) /* Asynchronous ASYNC Assertion */ 197 #define BA0_SPMC_RSTN (1<<0) /* Reset Not! */ 198 199 #define BA0_CFLR 0x03f0 /* Configuration Load Register (EEPROM or BIOS) */ 200 #define BA0_CFLR_DEFAULT 0x00000001 /* CFLR must be in AC97 link mode */ 201 #define BA0_IISR 0x03f4 /* ISA Interrupt Select */ 202 #define BA0_TMS 0x03f8 /* Test Register */ 203 #define BA0_SSVID 0x03fc /* Subsystem ID register */ 204 205 #define BA0_CLKCR1 0x0400 /* Clock Control Register 1 */ 206 #define BA0_CLKCR1_CLKON (1<<25) /* Read Only */ 207 #define BA0_CLKCR1_DLLRDY (1<<24) /* DLL Ready */ 208 #define BA0_CLKCR1_DLLOS (1<<6) /* DLL Output Select */ 209 #define BA0_CLKCR1_SWCE (1<<5) /* Clock Enable */ 210 #define BA0_CLKCR1_DLLP (1<<4) /* DLL PowerUp */ 211 #define BA0_CLKCR1_DLLSS (((x)&3)<<3) /* DLL Source Select */ 212 213 #define BA0_FRR 0x0410 /* Feature Reporting Register */ 214 #define BA0_SLT12O 0x041c /* Slot 12 GPIO Output Register for AC-Link */ 215 216 #define BA0_SERMC 0x0420 /* Serial Port Master Control */ 217 #define BA0_SERMC_FCRN (1<<27) /* Force Codec Ready Not */ 218 #define BA0_SERMC_ODSEN2 (1<<25) /* On-Demand Support Enable ASDIN2 */ 219 #define BA0_SERMC_ODSEN1 (1<<24) /* On-Demand Support Enable ASDIN1 */ 220 #define BA0_SERMC_SXLB (1<<21) /* ASDIN2 to ASDOUT Loopback */ 221 #define BA0_SERMC_SLB (1<<20) /* ASDOUT to ASDIN2 Loopback */ 222 #define BA0_SERMC_LOVF (1<<19) /* Loopback Output Valid Frame bit */ 223 #define BA0_SERMC_TCID(x) (((x)&3)<<16) /* Target Secondary Codec ID */ 224 #define BA0_SERMC_PXLB (5<<1) /* Primary Port External Loopback */ 225 #define BA0_SERMC_PLB (4<<1) /* Primary Port Internal Loopback */ 226 #define BA0_SERMC_PTC (7<<1) /* Port Timing Configuration */ 227 #define BA0_SERMC_PTC_AC97 (1<<1) /* AC97 mode */ 228 #define BA0_SERMC_MSPE (1<<0) /* Master Serial Port Enable */ 229 230 #define BA0_SERC1 0x0428 /* Serial Port Configuration 1 */ 231 #define BA0_SERC1_SO1F(x) (((x)&7)>>1) /* Primary Output Port Format */ 232 #define BA0_SERC1_AC97 (1<<1) 233 #define BA0_SERC1_SO1EN (1<<0) /* Primary Output Port Enable */ 234 235 #define BA0_SERC2 0x042c /* Serial Port Configuration 2 */ 236 #define BA0_SERC2_SI1F(x) (((x)&7)>>1) /* Primary Input Port Format */ 237 #define BA0_SERC2_AC97 (1<<1) 238 #define BA0_SERC2_SI1EN (1<<0) /* Primary Input Port Enable */ 239 240 #define BA0_SLT12M 0x045c /* Slot 12 Monitor Register for Primary AC-Link */ 241 242 #define BA0_ACCTL 0x0460 /* AC'97 Control */ 243 #define BA0_ACCTL_TC (1<<6) /* Target Codec */ 244 #define BA0_ACCTL_CRW (1<<4) /* 0=Write, 1=Read Command */ 245 #define BA0_ACCTL_DCV (1<<3) /* Dynamic Command Valid */ 246 #define BA0_ACCTL_VFRM (1<<2) /* Valid Frame */ 247 #define BA0_ACCTL_ESYN (1<<1) /* Enable Sync */ 248 249 #define BA0_ACSTS 0x0464 /* AC'97 Status */ 250 #define BA0_ACSTS_VSTS (1<<1) /* Valid Status */ 251 #define BA0_ACSTS_CRDY (1<<0) /* Codec Ready */ 252 253 #define BA0_ACOSV 0x0468 /* AC'97 Output Slot Valid */ 254 #define BA0_ACOSV_SLV(x) (1<<((x)-3)) 255 256 #define BA0_ACCAD 0x046c /* AC'97 Command Address */ 257 #define BA0_ACCDA 0x0470 /* AC'97 Command Data */ 258 259 #define BA0_ACISV 0x0474 /* AC'97 Input Slot Valid */ 260 #define BA0_ACISV_SLV(x) (1<<((x)-3)) 261 262 #define BA0_ACSAD 0x0478 /* AC'97 Status Address */ 263 #define BA0_ACSDA 0x047c /* AC'97 Status Data */ 264 #define BA0_JSPT 0x0480 /* Joystick poll/trigger */ 265 #define BA0_JSCTL 0x0484 /* Joystick control */ 266 #define BA0_JSC1 0x0488 /* Joystick control */ 267 #define BA0_JSC2 0x048c /* Joystick control */ 268 #define BA0_JSIO 0x04a0 269 270 #define BA0_MIDCR 0x0490 /* MIDI Control */ 271 #define BA0_MIDCR_MRST (1<<5) /* Reset MIDI Interface */ 272 #define BA0_MIDCR_MLB (1<<4) /* MIDI Loop Back Enable */ 273 #define BA0_MIDCR_TIE (1<<3) /* MIDI Transmuit Interrupt Enable */ 274 #define BA0_MIDCR_RIE (1<<2) /* MIDI Receive Interrupt Enable */ 275 #define BA0_MIDCR_RXE (1<<1) /* MIDI Receive Enable */ 276 #define BA0_MIDCR_TXE (1<<0) /* MIDI Transmit Enable */ 277 278 #define BA0_MIDCMD 0x0494 /* MIDI Command (wo) */ 279 280 #define BA0_MIDSR 0x0494 /* MIDI Status (ro) */ 281 #define BA0_MIDSR_RDA (1<<15) /* Sticky bit (RBE 1->0) */ 282 #define BA0_MIDSR_TBE (1<<14) /* Sticky bit (TBF 0->1) */ 283 #define BA0_MIDSR_RBE (1<<7) /* Receive Buffer Empty */ 284 #define BA0_MIDSR_TBF (1<<6) /* Transmit Buffer Full */ 285 286 #define BA0_MIDWP 0x0498 /* MIDI Write */ 287 #define BA0_MIDRP 0x049c /* MIDI Read (ro) */ 288 289 #define BA0_AODSD1 0x04a8 /* AC'97 On-Demand Slot Disable for primary link (ro) */ 290 #define BA0_AODSD1_NDS(x) (1<<((x)-3)) 291 292 #define BA0_AODSD2 0x04ac /* AC'97 On-Demand Slot Disable for secondary link (ro) */ 293 #define BA0_AODSD2_NDS(x) (1<<((x)-3)) 294 295 #define BA0_CFGI 0x04b0 /* Configure Interface (EEPROM interface) */ 296 #define BA0_SLT12M2 0x04dc /* Slot 12 Monitor Register 2 for secondary AC-link */ 297 #define BA0_ACSTS2 0x04e4 /* AC'97 Status Register 2 */ 298 #define BA0_ACISV2 0x04f4 /* AC'97 Input Slot Valid Register 2 */ 299 #define BA0_ACSAD2 0x04f8 /* AC'97 Status Address Register 2 */ 300 #define BA0_ACSDA2 0x04fc /* AC'97 Status Data Register 2 */ 301 #define BA0_FMSR 0x0730 /* FM Synthesis Status (ro) */ 302 #define BA0_B0AP 0x0730 /* FM Bank 0 Address Port (wo) */ 303 #define BA0_FMDP 0x0734 /* FM Data Port */ 304 #define BA0_B1AP 0x0738 /* FM Bank 1 Address Port */ 305 #define BA0_B1DP 0x073c /* FM Bank 1 Data Port */ 306 307 #define BA0_SSPM 0x0740 /* Sound System Power Management */ 308 #define BA0_SSPM_MIXEN (1<<6) /* Playback SRC + FM/Wavetable MIX */ 309 #define BA0_SSPM_CSRCEN (1<<5) /* Capture Sample Rate Converter Enable */ 310 #define BA0_SSPM_PSRCEN (1<<4) /* Playback Sample Rate Converter Enable */ 311 #define BA0_SSPM_JSEN (1<<3) /* Joystick Enable */ 312 #define BA0_SSPM_ACLEN (1<<2) /* Serial Port Engine and AC-Link Enable */ 313 #define BA0_SSPM_FMEN (1<<1) /* FM Synthesis Block Enable */ 314 315 #define BA0_DACSR 0x0744 /* DAC Sample Rate - Playback SRC */ 316 #define BA0_ADCSR 0x0748 /* ADC Sample Rate - Capture SRC */ 317 318 #define BA0_SSCR 0x074c /* Sound System Control Register */ 319 #define BA0_SSCR_HVS1 (1<<23) /* Hardwave Volume Step (0=1,1=2) */ 320 #define BA0_SSCR_MVCS (1<<19) /* Master Volume Codec Select */ 321 #define BA0_SSCR_MVLD (1<<18) /* Master Volume Line Out Disable */ 322 #define BA0_SSCR_MVAD (1<<17) /* Master Volume Alternate Out Disable */ 323 #define BA0_SSCR_MVMD (1<<16) /* Master Volume Mono Out Disable */ 324 #define BA0_SSCR_XLPSRC (1<<8) /* External SRC Loopback Mode */ 325 #define BA0_SSCR_LPSRC (1<<7) /* SRC Loopback Mode */ 326 #define BA0_SSCR_CDTX (1<<5) /* CD Transfer Data */ 327 #define BA0_SSCR_HVC (1<<3) /* Harware Volume Control Enable */ 328 329 #define BA0_FMLVC 0x0754 /* FM Synthesis Left Volume Control */ 330 #define BA0_FMRVC 0x0758 /* FM Synthesis Right Volume Control */ 331 #define BA0_SRCSA 0x075c /* SRC Slot Assignments */ 332 #define BA0_PPLVC 0x0760 /* PCM Playback Left Volume Control */ 333 #define BA0_PPRVC 0x0764 /* PCM Playback Right Volume Control */ 334 #define BA0_PASR 0x0768 /* playback sample rate */ 335 #define BA0_CASR 0x076C /* capture sample rate */ 336 337 /* Source Slot Numbers - Playback */ 338 #define SRCSLOT_LEFT_PCM_PLAYBACK 0 339 #define SRCSLOT_RIGHT_PCM_PLAYBACK 1 340 #define SRCSLOT_PHONE_LINE_1_DAC 2 341 #define SRCSLOT_CENTER_PCM_PLAYBACK 3 342 #define SRCSLOT_LEFT_SURROUND_PCM_PLAYBACK 4 343 #define SRCSLOT_RIGHT_SURROUND_PCM_PLAYBACK 5 344 #define SRCSLOT_LFE_PCM_PLAYBACK 6 345 #define SRCSLOT_PHONE_LINE_2_DAC 7 346 #define SRCSLOT_HEADSET_DAC 8 347 #define SRCSLOT_LEFT_WT 29 /* invalid for BA0_SRCSA */ 348 #define SRCSLOT_RIGHT_WT 30 /* invalid for BA0_SRCSA */ 349 350 /* Source Slot Numbers - Capture */ 351 #define SRCSLOT_LEFT_PCM_RECORD 10 352 #define SRCSLOT_RIGHT_PCM_RECORD 11 353 #define SRCSLOT_PHONE_LINE_1_ADC 12 354 #define SRCSLOT_MIC_ADC 13 355 #define SRCSLOT_PHONE_LINE_2_ADC 17 356 #define SRCSLOT_HEADSET_ADC 18 357 #define SRCSLOT_SECONDARY_LEFT_PCM_RECORD 20 358 #define SRCSLOT_SECONDARY_RIGHT_PCM_RECORD 21 359 #define SRCSLOT_SECONDARY_PHONE_LINE_1_ADC 22 360 #define SRCSLOT_SECONDARY_MIC_ADC 23 361 #define SRCSLOT_SECONDARY_PHONE_LINE_2_ADC 27 362 #define SRCSLOT_SECONDARY_HEADSET_ADC 28 363 364 /* Source Slot Numbers - Others */ 365 #define SRCSLOT_POWER_DOWN 31 366 367 /* MIDI modes */ 368 #define CS4281_MODE_OUTPUT (1<<0) 369 #define CS4281_MODE_INPUT (1<<1) 370 371 /* joystick bits */ 372 /* Bits for JSPT */ 373 #define JSPT_CAX 0x00000001 374 #define JSPT_CAY 0x00000002 375 #define JSPT_CBX 0x00000004 376 #define JSPT_CBY 0x00000008 377 #define JSPT_BA1 0x00000010 378 #define JSPT_BA2 0x00000020 379 #define JSPT_BB1 0x00000040 380 #define JSPT_BB2 0x00000080 381 382 /* Bits for JSCTL */ 383 #define JSCTL_SP_MASK 0x00000003 384 #define JSCTL_SP_SLOW 0x00000000 385 #define JSCTL_SP_MEDIUM_SLOW 0x00000001 386 #define JSCTL_SP_MEDIUM_FAST 0x00000002 387 #define JSCTL_SP_FAST 0x00000003 388 #define JSCTL_ARE 0x00000004 389 390 /* Data register pairs masks */ 391 #define JSC1_Y1V_MASK 0x0000FFFF 392 #define JSC1_X1V_MASK 0xFFFF0000 393 #define JSC1_Y1V_SHIFT 0 394 #define JSC1_X1V_SHIFT 16 395 #define JSC2_Y2V_MASK 0x0000FFFF 396 #define JSC2_X2V_MASK 0xFFFF0000 397 #define JSC2_Y2V_SHIFT 0 398 #define JSC2_X2V_SHIFT 16 399 400 /* JS GPIO */ 401 #define JSIO_DAX 0x00000001 402 #define JSIO_DAY 0x00000002 403 #define JSIO_DBX 0x00000004 404 #define JSIO_DBY 0x00000008 405 #define JSIO_AXOE 0x00000010 406 #define JSIO_AYOE 0x00000020 407 #define JSIO_BXOE 0x00000040 408 #define JSIO_BYOE 0x00000080 409 410 /* 411 * 412 */ 413 414 struct cs4281_dma { 415 struct snd_pcm_substream *substream; 416 unsigned int regDBA; /* offset to DBA register */ 417 unsigned int regDCA; /* offset to DCA register */ 418 unsigned int regDBC; /* offset to DBC register */ 419 unsigned int regDCC; /* offset to DCC register */ 420 unsigned int regDMR; /* offset to DMR register */ 421 unsigned int regDCR; /* offset to DCR register */ 422 unsigned int regHDSR; /* offset to HDSR register */ 423 unsigned int regFCR; /* offset to FCR register */ 424 unsigned int regFSIC; /* offset to FSIC register */ 425 unsigned int valDMR; /* DMA mode */ 426 unsigned int valDCR; /* DMA command */ 427 unsigned int valFCR; /* FIFO control */ 428 unsigned int fifo_offset; /* FIFO offset within BA1 */ 429 unsigned char left_slot; /* FIFO left slot */ 430 unsigned char right_slot; /* FIFO right slot */ 431 int frag; /* period number */ 432 }; 433 434 #define SUSPEND_REGISTERS 20 435 436 struct cs4281 { 437 int irq; 438 439 void __iomem *ba0; /* virtual (accessible) address */ 440 void __iomem *ba1; /* virtual (accessible) address */ 441 unsigned long ba0_addr; 442 unsigned long ba1_addr; 443 444 int dual_codec; 445 446 struct snd_ac97_bus *ac97_bus; 447 struct snd_ac97 *ac97; 448 struct snd_ac97 *ac97_secondary; 449 450 struct pci_dev *pci; 451 struct snd_card *card; 452 struct snd_pcm *pcm; 453 struct snd_rawmidi *rmidi; 454 struct snd_rawmidi_substream *midi_input; 455 struct snd_rawmidi_substream *midi_output; 456 457 struct cs4281_dma dma[4]; 458 459 unsigned char src_left_play_slot; 460 unsigned char src_right_play_slot; 461 unsigned char src_left_rec_slot; 462 unsigned char src_right_rec_slot; 463 464 unsigned int spurious_dhtc_irq; 465 unsigned int spurious_dtc_irq; 466 467 spinlock_t reg_lock; 468 unsigned int midcr; 469 unsigned int uartm; 470 471 struct gameport *gameport; 472 473 u32 suspend_regs[SUSPEND_REGISTERS]; 474 }; 475 476 static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id); 477 478 static const struct pci_device_id snd_cs4281_ids[] = { 479 { PCI_VDEVICE(CIRRUS, 0x6005), 0, }, /* CS4281 */ 480 { 0, } 481 }; 482 483 MODULE_DEVICE_TABLE(pci, snd_cs4281_ids); 484 485 /* 486 * constants 487 */ 488 489 #define CS4281_FIFO_SIZE 32 490 491 /* 492 * common I/O routines 493 */ 494 495 static inline void snd_cs4281_pokeBA0(struct cs4281 *chip, unsigned long offset, 496 unsigned int val) 497 { 498 writel(val, chip->ba0 + offset); 499 } 500 501 static inline unsigned int snd_cs4281_peekBA0(struct cs4281 *chip, unsigned long offset) 502 { 503 return readl(chip->ba0 + offset); 504 } 505 506 static void snd_cs4281_ac97_write(struct snd_ac97 *ac97, 507 unsigned short reg, unsigned short val) 508 { 509 /* 510 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address 511 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97 512 * 3. Write ACCTL = Control Register = 460h for initiating the write 513 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h 514 * 5. if DCV not cleared, break and return error 515 */ 516 struct cs4281 *chip = ac97->private_data; 517 int count; 518 519 /* 520 * Setup the AC97 control registers on the CS461x to send the 521 * appropriate command to the AC97 to perform the read. 522 * ACCAD = Command Address Register = 46Ch 523 * ACCDA = Command Data Register = 470h 524 * ACCTL = Control Register = 460h 525 * set DCV - will clear when process completed 526 * reset CRW - Write command 527 * set VFRM - valid frame enabled 528 * set ESYN - ASYNC generation enabled 529 * set RSTN - ARST# inactive, AC97 codec not reset 530 */ 531 snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg); 532 snd_cs4281_pokeBA0(chip, BA0_ACCDA, val); 533 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_VFRM | 534 BA0_ACCTL_ESYN | (ac97->num ? BA0_ACCTL_TC : 0)); 535 for (count = 0; count < 2000; count++) { 536 /* 537 * First, we want to wait for a short time. 538 */ 539 udelay(10); 540 /* 541 * Now, check to see if the write has completed. 542 * ACCTL = 460h, DCV should be reset by now and 460h = 07h 543 */ 544 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV)) { 545 return; 546 } 547 } 548 dev_err(chip->card->dev, 549 "AC'97 write problem, reg = 0x%x, val = 0x%x\n", reg, val); 550 } 551 552 static unsigned short snd_cs4281_ac97_read(struct snd_ac97 *ac97, 553 unsigned short reg) 554 { 555 struct cs4281 *chip = ac97->private_data; 556 int count; 557 unsigned short result; 558 // FIXME: volatile is necessary in the following due to a bug of 559 // some gcc versions 560 volatile int ac97_num = ((volatile struct snd_ac97 *)ac97)->num; 561 562 /* 563 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address 564 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97 565 * 3. Write ACCTL = Control Register = 460h for initiating the write 566 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h 567 * 5. if DCV not cleared, break and return error 568 * 6. Read ACSTS = Status Register = 464h, check VSTS bit 569 */ 570 571 snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA); 572 573 /* 574 * Setup the AC97 control registers on the CS461x to send the 575 * appropriate command to the AC97 to perform the read. 576 * ACCAD = Command Address Register = 46Ch 577 * ACCDA = Command Data Register = 470h 578 * ACCTL = Control Register = 460h 579 * set DCV - will clear when process completed 580 * set CRW - Read command 581 * set VFRM - valid frame enabled 582 * set ESYN - ASYNC generation enabled 583 * set RSTN - ARST# inactive, AC97 codec not reset 584 */ 585 586 snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg); 587 snd_cs4281_pokeBA0(chip, BA0_ACCDA, 0); 588 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_CRW | 589 BA0_ACCTL_VFRM | BA0_ACCTL_ESYN | 590 (ac97_num ? BA0_ACCTL_TC : 0)); 591 592 593 /* 594 * Wait for the read to occur. 595 */ 596 for (count = 0; count < 500; count++) { 597 /* 598 * First, we want to wait for a short time. 599 */ 600 udelay(10); 601 /* 602 * Now, check to see if the read has completed. 603 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 604 */ 605 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV)) 606 goto __ok1; 607 } 608 609 dev_err(chip->card->dev, 610 "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg); 611 result = 0xffff; 612 goto __end; 613 614 __ok1: 615 /* 616 * Wait for the valid status bit to go active. 617 */ 618 for (count = 0; count < 100; count++) { 619 /* 620 * Read the AC97 status register. 621 * ACSTS = Status Register = 464h 622 * VSTS - Valid Status 623 */ 624 if (snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSTS2 : BA0_ACSTS) & BA0_ACSTS_VSTS) 625 goto __ok2; 626 udelay(10); 627 } 628 629 dev_err(chip->card->dev, 630 "AC'97 read problem (ACSTS_VSTS), reg = 0x%x\n", reg); 631 result = 0xffff; 632 goto __end; 633 634 __ok2: 635 /* 636 * Read the data returned from the AC97 register. 637 * ACSDA = Status Data Register = 474h 638 */ 639 result = snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA); 640 641 __end: 642 return result; 643 } 644 645 /* 646 * PCM part 647 */ 648 649 static int snd_cs4281_trigger(struct snd_pcm_substream *substream, int cmd) 650 { 651 struct cs4281_dma *dma = substream->runtime->private_data; 652 struct cs4281 *chip = snd_pcm_substream_chip(substream); 653 654 guard(spinlock)(&chip->reg_lock); 655 switch (cmd) { 656 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 657 dma->valDCR |= BA0_DCR_MSK; 658 dma->valFCR |= BA0_FCR_FEN; 659 break; 660 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 661 dma->valDCR &= ~BA0_DCR_MSK; 662 dma->valFCR &= ~BA0_FCR_FEN; 663 break; 664 case SNDRV_PCM_TRIGGER_START: 665 case SNDRV_PCM_TRIGGER_RESUME: 666 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR & ~BA0_DMR_DMA); 667 dma->valDMR |= BA0_DMR_DMA; 668 dma->valDCR &= ~BA0_DCR_MSK; 669 dma->valFCR |= BA0_FCR_FEN; 670 break; 671 case SNDRV_PCM_TRIGGER_STOP: 672 case SNDRV_PCM_TRIGGER_SUSPEND: 673 dma->valDMR &= ~(BA0_DMR_DMA|BA0_DMR_POLL); 674 dma->valDCR |= BA0_DCR_MSK; 675 dma->valFCR &= ~BA0_FCR_FEN; 676 /* Leave wave playback FIFO enabled for FM */ 677 if (dma->regFCR != BA0_FCR0) 678 dma->valFCR &= ~BA0_FCR_FEN; 679 break; 680 default: 681 return -EINVAL; 682 } 683 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR); 684 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR); 685 snd_cs4281_pokeBA0(chip, dma->regDCR, dma->valDCR); 686 return 0; 687 } 688 689 static unsigned int snd_cs4281_rate(unsigned int rate, unsigned int *real_rate) 690 { 691 unsigned int val; 692 693 if (real_rate) 694 *real_rate = rate; 695 /* special "hardcoded" rates */ 696 switch (rate) { 697 case 8000: return 5; 698 case 11025: return 4; 699 case 16000: return 3; 700 case 22050: return 2; 701 case 44100: return 1; 702 case 48000: return 0; 703 default: 704 break; 705 } 706 val = 1536000 / rate; 707 if (real_rate) 708 *real_rate = 1536000 / val; 709 return val; 710 } 711 712 static void snd_cs4281_mode(struct cs4281 *chip, struct cs4281_dma *dma, 713 struct snd_pcm_runtime *runtime, 714 int capture, int src) 715 { 716 int rec_mono; 717 718 dma->valDMR = BA0_DMR_TYPE_SINGLE | BA0_DMR_AUTO | 719 (capture ? BA0_DMR_TR_WRITE : BA0_DMR_TR_READ); 720 if (runtime->channels == 1) 721 dma->valDMR |= BA0_DMR_MONO; 722 if (snd_pcm_format_unsigned(runtime->format) > 0) 723 dma->valDMR |= BA0_DMR_USIGN; 724 if (snd_pcm_format_big_endian(runtime->format) > 0) 725 dma->valDMR |= BA0_DMR_BEND; 726 switch (snd_pcm_format_width(runtime->format)) { 727 case 8: dma->valDMR |= BA0_DMR_SIZE8; 728 if (runtime->channels == 1) 729 dma->valDMR |= BA0_DMR_SWAPC; 730 break; 731 case 32: dma->valDMR |= BA0_DMR_SIZE20; break; 732 } 733 dma->frag = 0; /* for workaround */ 734 dma->valDCR = BA0_DCR_TCIE | BA0_DCR_MSK; 735 if (runtime->buffer_size != runtime->period_size) 736 dma->valDCR |= BA0_DCR_HTCIE; 737 /* Initialize DMA */ 738 snd_cs4281_pokeBA0(chip, dma->regDBA, runtime->dma_addr); 739 snd_cs4281_pokeBA0(chip, dma->regDBC, runtime->buffer_size - 1); 740 rec_mono = (chip->dma[1].valDMR & BA0_DMR_MONO) == BA0_DMR_MONO; 741 snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) | 742 (chip->src_right_play_slot << 8) | 743 (chip->src_left_rec_slot << 16) | 744 ((rec_mono ? 31 : chip->src_right_rec_slot) << 24)); 745 if (!src) 746 goto __skip_src; 747 if (!capture) { 748 if (dma->left_slot == chip->src_left_play_slot) { 749 unsigned int val = snd_cs4281_rate(runtime->rate, NULL); 750 snd_BUG_ON(dma->right_slot != chip->src_right_play_slot); 751 snd_cs4281_pokeBA0(chip, BA0_DACSR, val); 752 } 753 } else { 754 if (dma->left_slot == chip->src_left_rec_slot) { 755 unsigned int val = snd_cs4281_rate(runtime->rate, NULL); 756 snd_BUG_ON(dma->right_slot != chip->src_right_rec_slot); 757 snd_cs4281_pokeBA0(chip, BA0_ADCSR, val); 758 } 759 } 760 __skip_src: 761 /* Deactivate wave playback FIFO before changing slot assignments */ 762 if (dma->regFCR == BA0_FCR0) 763 snd_cs4281_pokeBA0(chip, dma->regFCR, snd_cs4281_peekBA0(chip, dma->regFCR) & ~BA0_FCR_FEN); 764 /* Initialize FIFO */ 765 dma->valFCR = BA0_FCR_LS(dma->left_slot) | 766 BA0_FCR_RS(capture && (dma->valDMR & BA0_DMR_MONO) ? 31 : dma->right_slot) | 767 BA0_FCR_SZ(CS4281_FIFO_SIZE) | 768 BA0_FCR_OF(dma->fifo_offset); 769 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | (capture ? BA0_FCR_PSH : 0)); 770 /* Activate FIFO again for FM playback */ 771 if (dma->regFCR == BA0_FCR0) 772 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | BA0_FCR_FEN); 773 /* Clear FIFO Status and Interrupt Control Register */ 774 snd_cs4281_pokeBA0(chip, dma->regFSIC, 0); 775 } 776 777 static int snd_cs4281_playback_prepare(struct snd_pcm_substream *substream) 778 { 779 struct snd_pcm_runtime *runtime = substream->runtime; 780 struct cs4281_dma *dma = runtime->private_data; 781 struct cs4281 *chip = snd_pcm_substream_chip(substream); 782 783 guard(spinlock_irq)(&chip->reg_lock); 784 snd_cs4281_mode(chip, dma, runtime, 0, 1); 785 return 0; 786 } 787 788 static int snd_cs4281_capture_prepare(struct snd_pcm_substream *substream) 789 { 790 struct snd_pcm_runtime *runtime = substream->runtime; 791 struct cs4281_dma *dma = runtime->private_data; 792 struct cs4281 *chip = snd_pcm_substream_chip(substream); 793 794 guard(spinlock_irq)(&chip->reg_lock); 795 snd_cs4281_mode(chip, dma, runtime, 1, 1); 796 return 0; 797 } 798 799 static snd_pcm_uframes_t snd_cs4281_pointer(struct snd_pcm_substream *substream) 800 { 801 struct snd_pcm_runtime *runtime = substream->runtime; 802 struct cs4281_dma *dma = runtime->private_data; 803 struct cs4281 *chip = snd_pcm_substream_chip(substream); 804 805 /* 806 dev_dbg(chip->card->dev, 807 "DCC = 0x%x, buffer_size = 0x%x, jiffies = %li\n", 808 snd_cs4281_peekBA0(chip, dma->regDCC), runtime->buffer_size, 809 jiffies); 810 */ 811 return runtime->buffer_size - 812 snd_cs4281_peekBA0(chip, dma->regDCC) - 1; 813 } 814 815 static const struct snd_pcm_hardware snd_cs4281_playback = 816 { 817 .info = SNDRV_PCM_INFO_MMAP | 818 SNDRV_PCM_INFO_INTERLEAVED | 819 SNDRV_PCM_INFO_MMAP_VALID | 820 SNDRV_PCM_INFO_PAUSE | 821 SNDRV_PCM_INFO_RESUME, 822 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 | 823 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE | 824 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE | 825 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE | 826 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE, 827 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 828 .rate_min = 4000, 829 .rate_max = 48000, 830 .channels_min = 1, 831 .channels_max = 2, 832 .buffer_bytes_max = (512*1024), 833 .period_bytes_min = 64, 834 .period_bytes_max = (512*1024), 835 .periods_min = 1, 836 .periods_max = 2, 837 .fifo_size = CS4281_FIFO_SIZE, 838 }; 839 840 static const struct snd_pcm_hardware snd_cs4281_capture = 841 { 842 .info = SNDRV_PCM_INFO_MMAP | 843 SNDRV_PCM_INFO_INTERLEAVED | 844 SNDRV_PCM_INFO_MMAP_VALID | 845 SNDRV_PCM_INFO_PAUSE | 846 SNDRV_PCM_INFO_RESUME, 847 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 | 848 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE | 849 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE | 850 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE | 851 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE, 852 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 853 .rate_min = 4000, 854 .rate_max = 48000, 855 .channels_min = 1, 856 .channels_max = 2, 857 .buffer_bytes_max = (512*1024), 858 .period_bytes_min = 64, 859 .period_bytes_max = (512*1024), 860 .periods_min = 1, 861 .periods_max = 2, 862 .fifo_size = CS4281_FIFO_SIZE, 863 }; 864 865 static int snd_cs4281_playback_open(struct snd_pcm_substream *substream) 866 { 867 struct cs4281 *chip = snd_pcm_substream_chip(substream); 868 struct snd_pcm_runtime *runtime = substream->runtime; 869 struct cs4281_dma *dma; 870 871 dma = &chip->dma[0]; 872 dma->substream = substream; 873 dma->left_slot = 0; 874 dma->right_slot = 1; 875 runtime->private_data = dma; 876 runtime->hw = snd_cs4281_playback; 877 /* should be detected from the AC'97 layer, but it seems 878 that although CS4297A rev B reports 18-bit ADC resolution, 879 samples are 20-bit */ 880 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20); 881 return 0; 882 } 883 884 static int snd_cs4281_capture_open(struct snd_pcm_substream *substream) 885 { 886 struct cs4281 *chip = snd_pcm_substream_chip(substream); 887 struct snd_pcm_runtime *runtime = substream->runtime; 888 struct cs4281_dma *dma; 889 890 dma = &chip->dma[1]; 891 dma->substream = substream; 892 dma->left_slot = 10; 893 dma->right_slot = 11; 894 runtime->private_data = dma; 895 runtime->hw = snd_cs4281_capture; 896 /* should be detected from the AC'97 layer, but it seems 897 that although CS4297A rev B reports 18-bit ADC resolution, 898 samples are 20-bit */ 899 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20); 900 return 0; 901 } 902 903 static int snd_cs4281_playback_close(struct snd_pcm_substream *substream) 904 { 905 struct cs4281_dma *dma = substream->runtime->private_data; 906 907 dma->substream = NULL; 908 return 0; 909 } 910 911 static int snd_cs4281_capture_close(struct snd_pcm_substream *substream) 912 { 913 struct cs4281_dma *dma = substream->runtime->private_data; 914 915 dma->substream = NULL; 916 return 0; 917 } 918 919 static const struct snd_pcm_ops snd_cs4281_playback_ops = { 920 .open = snd_cs4281_playback_open, 921 .close = snd_cs4281_playback_close, 922 .prepare = snd_cs4281_playback_prepare, 923 .trigger = snd_cs4281_trigger, 924 .pointer = snd_cs4281_pointer, 925 }; 926 927 static const struct snd_pcm_ops snd_cs4281_capture_ops = { 928 .open = snd_cs4281_capture_open, 929 .close = snd_cs4281_capture_close, 930 .prepare = snd_cs4281_capture_prepare, 931 .trigger = snd_cs4281_trigger, 932 .pointer = snd_cs4281_pointer, 933 }; 934 935 static int snd_cs4281_pcm(struct cs4281 *chip, int device) 936 { 937 struct snd_pcm *pcm; 938 int err; 939 940 err = snd_pcm_new(chip->card, "CS4281", device, 1, 1, &pcm); 941 if (err < 0) 942 return err; 943 944 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4281_playback_ops); 945 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4281_capture_ops); 946 947 pcm->private_data = chip; 948 pcm->info_flags = 0; 949 strscpy(pcm->name, "CS4281"); 950 chip->pcm = pcm; 951 952 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &chip->pci->dev, 953 64*1024, 512*1024); 954 955 return 0; 956 } 957 958 /* 959 * Mixer section 960 */ 961 962 #define CS_VOL_MASK 0x1f 963 964 static int snd_cs4281_info_volume(struct snd_kcontrol *kcontrol, 965 struct snd_ctl_elem_info *uinfo) 966 { 967 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 968 uinfo->count = 2; 969 uinfo->value.integer.min = 0; 970 uinfo->value.integer.max = CS_VOL_MASK; 971 return 0; 972 } 973 974 static int snd_cs4281_get_volume(struct snd_kcontrol *kcontrol, 975 struct snd_ctl_elem_value *ucontrol) 976 { 977 struct cs4281 *chip = snd_kcontrol_chip(kcontrol); 978 int regL = (kcontrol->private_value >> 16) & 0xffff; 979 int regR = kcontrol->private_value & 0xffff; 980 int volL, volR; 981 982 volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK); 983 volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK); 984 985 ucontrol->value.integer.value[0] = volL; 986 ucontrol->value.integer.value[1] = volR; 987 return 0; 988 } 989 990 static int snd_cs4281_put_volume(struct snd_kcontrol *kcontrol, 991 struct snd_ctl_elem_value *ucontrol) 992 { 993 struct cs4281 *chip = snd_kcontrol_chip(kcontrol); 994 int change = 0; 995 int regL = (kcontrol->private_value >> 16) & 0xffff; 996 int regR = kcontrol->private_value & 0xffff; 997 int volL, volR; 998 999 volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK); 1000 volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK); 1001 1002 if (ucontrol->value.integer.value[0] != volL) { 1003 volL = CS_VOL_MASK - (ucontrol->value.integer.value[0] & CS_VOL_MASK); 1004 snd_cs4281_pokeBA0(chip, regL, volL); 1005 change = 1; 1006 } 1007 if (ucontrol->value.integer.value[1] != volR) { 1008 volR = CS_VOL_MASK - (ucontrol->value.integer.value[1] & CS_VOL_MASK); 1009 snd_cs4281_pokeBA0(chip, regR, volR); 1010 change = 1; 1011 } 1012 return change; 1013 } 1014 1015 static const DECLARE_TLV_DB_SCALE(db_scale_dsp, -4650, 150, 0); 1016 1017 static const struct snd_kcontrol_new snd_cs4281_fm_vol = 1018 { 1019 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1020 .name = "Synth Playback Volume", 1021 .info = snd_cs4281_info_volume, 1022 .get = snd_cs4281_get_volume, 1023 .put = snd_cs4281_put_volume, 1024 .private_value = ((BA0_FMLVC << 16) | BA0_FMRVC), 1025 .tlv = { .p = db_scale_dsp }, 1026 }; 1027 1028 static const struct snd_kcontrol_new snd_cs4281_pcm_vol = 1029 { 1030 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1031 .name = "PCM Stream Playback Volume", 1032 .info = snd_cs4281_info_volume, 1033 .get = snd_cs4281_get_volume, 1034 .put = snd_cs4281_put_volume, 1035 .private_value = ((BA0_PPLVC << 16) | BA0_PPRVC), 1036 .tlv = { .p = db_scale_dsp }, 1037 }; 1038 1039 static void snd_cs4281_mixer_free_ac97_bus(struct snd_ac97_bus *bus) 1040 { 1041 struct cs4281 *chip = bus->private_data; 1042 chip->ac97_bus = NULL; 1043 } 1044 1045 static void snd_cs4281_mixer_free_ac97(struct snd_ac97 *ac97) 1046 { 1047 struct cs4281 *chip = ac97->private_data; 1048 if (ac97->num) 1049 chip->ac97_secondary = NULL; 1050 else 1051 chip->ac97 = NULL; 1052 } 1053 1054 static int snd_cs4281_mixer(struct cs4281 *chip) 1055 { 1056 struct snd_card *card = chip->card; 1057 struct snd_ac97_template ac97; 1058 int err; 1059 static const struct snd_ac97_bus_ops ops = { 1060 .write = snd_cs4281_ac97_write, 1061 .read = snd_cs4281_ac97_read, 1062 }; 1063 1064 err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus); 1065 if (err < 0) 1066 return err; 1067 chip->ac97_bus->private_free = snd_cs4281_mixer_free_ac97_bus; 1068 1069 memset(&ac97, 0, sizeof(ac97)); 1070 ac97.private_data = chip; 1071 ac97.private_free = snd_cs4281_mixer_free_ac97; 1072 err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97); 1073 if (err < 0) 1074 return err; 1075 if (chip->dual_codec) { 1076 ac97.num = 1; 1077 err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97_secondary); 1078 if (err < 0) 1079 return err; 1080 } 1081 err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_fm_vol, chip)); 1082 if (err < 0) 1083 return err; 1084 err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_pcm_vol, chip)); 1085 if (err < 0) 1086 return err; 1087 return 0; 1088 } 1089 1090 1091 /* 1092 * proc interface 1093 */ 1094 1095 static void snd_cs4281_proc_read(struct snd_info_entry *entry, 1096 struct snd_info_buffer *buffer) 1097 { 1098 struct cs4281 *chip = entry->private_data; 1099 1100 snd_iprintf(buffer, "Cirrus Logic CS4281\n\n"); 1101 snd_iprintf(buffer, "Spurious half IRQs : %u\n", chip->spurious_dhtc_irq); 1102 snd_iprintf(buffer, "Spurious end IRQs : %u\n", chip->spurious_dtc_irq); 1103 } 1104 1105 static ssize_t snd_cs4281_BA0_read(struct snd_info_entry *entry, 1106 void *file_private_data, 1107 struct file *file, char __user *buf, 1108 size_t count, loff_t pos) 1109 { 1110 struct cs4281 *chip = entry->private_data; 1111 1112 if (copy_to_user_fromio(buf, chip->ba0 + pos, count)) 1113 return -EFAULT; 1114 return count; 1115 } 1116 1117 static ssize_t snd_cs4281_BA1_read(struct snd_info_entry *entry, 1118 void *file_private_data, 1119 struct file *file, char __user *buf, 1120 size_t count, loff_t pos) 1121 { 1122 struct cs4281 *chip = entry->private_data; 1123 1124 if (copy_to_user_fromio(buf, chip->ba1 + pos, count)) 1125 return -EFAULT; 1126 return count; 1127 } 1128 1129 static const struct snd_info_entry_ops snd_cs4281_proc_ops_BA0 = { 1130 .read = snd_cs4281_BA0_read, 1131 }; 1132 1133 static const struct snd_info_entry_ops snd_cs4281_proc_ops_BA1 = { 1134 .read = snd_cs4281_BA1_read, 1135 }; 1136 1137 static void snd_cs4281_proc_init(struct cs4281 *chip) 1138 { 1139 struct snd_info_entry *entry; 1140 1141 snd_card_ro_proc_new(chip->card, "cs4281", chip, snd_cs4281_proc_read); 1142 if (! snd_card_proc_new(chip->card, "cs4281_BA0", &entry)) { 1143 entry->content = SNDRV_INFO_CONTENT_DATA; 1144 entry->private_data = chip; 1145 entry->c.ops = &snd_cs4281_proc_ops_BA0; 1146 entry->size = CS4281_BA0_SIZE; 1147 } 1148 if (! snd_card_proc_new(chip->card, "cs4281_BA1", &entry)) { 1149 entry->content = SNDRV_INFO_CONTENT_DATA; 1150 entry->private_data = chip; 1151 entry->c.ops = &snd_cs4281_proc_ops_BA1; 1152 entry->size = CS4281_BA1_SIZE; 1153 } 1154 } 1155 1156 /* 1157 * joystick support 1158 */ 1159 1160 #if IS_REACHABLE(CONFIG_GAMEPORT) 1161 1162 static void snd_cs4281_gameport_trigger(struct gameport *gameport) 1163 { 1164 struct cs4281 *chip = gameport_get_port_data(gameport); 1165 1166 if (snd_BUG_ON(!chip)) 1167 return; 1168 snd_cs4281_pokeBA0(chip, BA0_JSPT, 0xff); 1169 } 1170 1171 static unsigned char snd_cs4281_gameport_read(struct gameport *gameport) 1172 { 1173 struct cs4281 *chip = gameport_get_port_data(gameport); 1174 1175 if (snd_BUG_ON(!chip)) 1176 return 0; 1177 return snd_cs4281_peekBA0(chip, BA0_JSPT); 1178 } 1179 1180 #ifdef COOKED_MODE 1181 static int snd_cs4281_gameport_cooked_read(struct gameport *gameport, 1182 int *axes, int *buttons) 1183 { 1184 struct cs4281 *chip = gameport_get_port_data(gameport); 1185 unsigned js1, js2, jst; 1186 1187 if (snd_BUG_ON(!chip)) 1188 return 0; 1189 1190 js1 = snd_cs4281_peekBA0(chip, BA0_JSC1); 1191 js2 = snd_cs4281_peekBA0(chip, BA0_JSC2); 1192 jst = snd_cs4281_peekBA0(chip, BA0_JSPT); 1193 1194 *buttons = (~jst >> 4) & 0x0F; 1195 1196 axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF; 1197 axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF; 1198 axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF; 1199 axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF; 1200 1201 for (jst = 0; jst < 4; ++jst) 1202 if (axes[jst] == 0xFFFF) axes[jst] = -1; 1203 return 0; 1204 } 1205 #else 1206 #define snd_cs4281_gameport_cooked_read NULL 1207 #endif 1208 1209 static int snd_cs4281_gameport_open(struct gameport *gameport, int mode) 1210 { 1211 switch (mode) { 1212 #ifdef COOKED_MODE 1213 case GAMEPORT_MODE_COOKED: 1214 return 0; 1215 #endif 1216 case GAMEPORT_MODE_RAW: 1217 return 0; 1218 default: 1219 return -1; 1220 } 1221 return 0; 1222 } 1223 1224 static int snd_cs4281_create_gameport(struct cs4281 *chip) 1225 { 1226 struct gameport *gp; 1227 1228 chip->gameport = gp = gameport_allocate_port(); 1229 if (!gp) { 1230 dev_err(chip->card->dev, 1231 "cannot allocate memory for gameport\n"); 1232 return -ENOMEM; 1233 } 1234 1235 gameport_set_name(gp, "CS4281 Gameport"); 1236 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci)); 1237 gameport_set_dev_parent(gp, &chip->pci->dev); 1238 gp->open = snd_cs4281_gameport_open; 1239 gp->read = snd_cs4281_gameport_read; 1240 gp->trigger = snd_cs4281_gameport_trigger; 1241 gp->cooked_read = snd_cs4281_gameport_cooked_read; 1242 gameport_set_port_data(gp, chip); 1243 1244 snd_cs4281_pokeBA0(chip, BA0_JSIO, 0xFF); // ? 1245 snd_cs4281_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW); 1246 1247 gameport_register_port(gp); 1248 1249 return 0; 1250 } 1251 1252 static void snd_cs4281_free_gameport(struct cs4281 *chip) 1253 { 1254 if (chip->gameport) { 1255 gameport_unregister_port(chip->gameport); 1256 chip->gameport = NULL; 1257 } 1258 } 1259 #else 1260 static inline int snd_cs4281_create_gameport(struct cs4281 *chip) { return -ENOSYS; } 1261 static inline void snd_cs4281_free_gameport(struct cs4281 *chip) { } 1262 #endif /* IS_REACHABLE(CONFIG_GAMEPORT) */ 1263 1264 static void snd_cs4281_free(struct snd_card *card) 1265 { 1266 struct cs4281 *chip = card->private_data; 1267 1268 snd_cs4281_free_gameport(chip); 1269 1270 /* Mask interrupts */ 1271 snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff); 1272 /* Stop the DLL Clock logic. */ 1273 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0); 1274 /* Sound System Power Management - Turn Everything OFF */ 1275 snd_cs4281_pokeBA0(chip, BA0_SSPM, 0); 1276 } 1277 1278 static int snd_cs4281_chip_init(struct cs4281 *chip); /* defined below */ 1279 1280 static int snd_cs4281_create(struct snd_card *card, 1281 struct pci_dev *pci, 1282 int dual_codec) 1283 { 1284 struct cs4281 *chip = card->private_data; 1285 int err; 1286 1287 err = pcim_enable_device(pci); 1288 if (err < 0) 1289 return err; 1290 spin_lock_init(&chip->reg_lock); 1291 chip->card = card; 1292 chip->pci = pci; 1293 chip->irq = -1; 1294 pci_set_master(pci); 1295 if (dual_codec < 0 || dual_codec > 3) { 1296 dev_err(card->dev, "invalid dual_codec option %d\n", dual_codec); 1297 dual_codec = 0; 1298 } 1299 chip->dual_codec = dual_codec; 1300 1301 chip->ba0 = pcim_iomap_region(pci, 0, "CS4281"); 1302 if (IS_ERR(chip->ba0)) 1303 return PTR_ERR(chip->ba0); 1304 chip->ba0_addr = pci_resource_start(pci, 0); 1305 1306 chip->ba1 = pcim_iomap_region(pci, 1, "CS4281"); 1307 if (IS_ERR(chip->ba1)) 1308 return PTR_ERR(chip->ba1); 1309 chip->ba1_addr = pci_resource_start(pci, 1); 1310 1311 if (devm_request_irq(&pci->dev, pci->irq, snd_cs4281_interrupt, 1312 IRQF_SHARED, KBUILD_MODNAME, chip)) { 1313 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq); 1314 return -ENOMEM; 1315 } 1316 chip->irq = pci->irq; 1317 card->sync_irq = chip->irq; 1318 card->private_free = snd_cs4281_free; 1319 1320 err = snd_cs4281_chip_init(chip); 1321 if (err) 1322 return err; 1323 1324 snd_cs4281_proc_init(chip); 1325 return 0; 1326 } 1327 1328 static int snd_cs4281_chip_init(struct cs4281 *chip) 1329 { 1330 unsigned int tmp; 1331 unsigned long end_time; 1332 int retry_count = 2; 1333 1334 /* Having EPPMC.FPDN=1 prevent proper chip initialisation */ 1335 tmp = snd_cs4281_peekBA0(chip, BA0_EPPMC); 1336 if (tmp & BA0_EPPMC_FPDN) 1337 snd_cs4281_pokeBA0(chip, BA0_EPPMC, tmp & ~BA0_EPPMC_FPDN); 1338 1339 __retry: 1340 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR); 1341 if (tmp != BA0_CFLR_DEFAULT) { 1342 snd_cs4281_pokeBA0(chip, BA0_CFLR, BA0_CFLR_DEFAULT); 1343 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR); 1344 if (tmp != BA0_CFLR_DEFAULT) { 1345 dev_err(chip->card->dev, 1346 "CFLR setup failed (0x%x)\n", tmp); 1347 return -EIO; 1348 } 1349 } 1350 1351 /* Set the 'Configuration Write Protect' register 1352 * to 4281h. Allows vendor-defined configuration 1353 * space between 0e4h and 0ffh to be written. */ 1354 snd_cs4281_pokeBA0(chip, BA0_CWPR, 0x4281); 1355 1356 tmp = snd_cs4281_peekBA0(chip, BA0_SERC1); 1357 if (tmp != (BA0_SERC1_SO1EN | BA0_SERC1_AC97)) { 1358 dev_err(chip->card->dev, 1359 "SERC1 AC'97 check failed (0x%x)\n", tmp); 1360 return -EIO; 1361 } 1362 tmp = snd_cs4281_peekBA0(chip, BA0_SERC2); 1363 if (tmp != (BA0_SERC2_SI1EN | BA0_SERC2_AC97)) { 1364 dev_err(chip->card->dev, 1365 "SERC2 AC'97 check failed (0x%x)\n", tmp); 1366 return -EIO; 1367 } 1368 1369 /* Sound System Power Management */ 1370 snd_cs4281_pokeBA0(chip, BA0_SSPM, BA0_SSPM_MIXEN | BA0_SSPM_CSRCEN | 1371 BA0_SSPM_PSRCEN | BA0_SSPM_JSEN | 1372 BA0_SSPM_ACLEN | BA0_SSPM_FMEN); 1373 1374 /* Serial Port Power Management */ 1375 /* Blast the clock control register to zero so that the 1376 * PLL starts out in a known state, and blast the master serial 1377 * port control register to zero so that the serial ports also 1378 * start out in a known state. */ 1379 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0); 1380 snd_cs4281_pokeBA0(chip, BA0_SERMC, 0); 1381 1382 /* Make ESYN go to zero to turn off 1383 * the Sync pulse on the AC97 link. */ 1384 snd_cs4281_pokeBA0(chip, BA0_ACCTL, 0); 1385 udelay(50); 1386 1387 /* Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97 1388 * spec) and then drive it high. This is done for non AC97 modes since 1389 * there might be logic external to the CS4281 that uses the ARST# line 1390 * for a reset. */ 1391 snd_cs4281_pokeBA0(chip, BA0_SPMC, 0); 1392 udelay(50); 1393 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN); 1394 msleep(50); 1395 1396 if (chip->dual_codec) 1397 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN | BA0_SPMC_ASDI2E); 1398 1399 /* 1400 * Set the serial port timing configuration. 1401 */ 1402 snd_cs4281_pokeBA0(chip, BA0_SERMC, 1403 (chip->dual_codec ? BA0_SERMC_TCID(chip->dual_codec) : BA0_SERMC_TCID(1)) | 1404 BA0_SERMC_PTC_AC97 | BA0_SERMC_MSPE); 1405 1406 /* 1407 * Start the DLL Clock logic. 1408 */ 1409 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_DLLP); 1410 msleep(50); 1411 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_SWCE | BA0_CLKCR1_DLLP); 1412 1413 /* 1414 * Wait for the DLL ready signal from the clock logic. 1415 */ 1416 end_time = jiffies + HZ; 1417 do { 1418 /* 1419 * Read the AC97 status register to see if we've seen a CODEC 1420 * signal from the AC97 codec. 1421 */ 1422 if (snd_cs4281_peekBA0(chip, BA0_CLKCR1) & BA0_CLKCR1_DLLRDY) 1423 goto __ok0; 1424 schedule_timeout_uninterruptible(1); 1425 } while (time_after_eq(end_time, jiffies)); 1426 1427 dev_err(chip->card->dev, "DLLRDY not seen\n"); 1428 return -EIO; 1429 1430 __ok0: 1431 1432 /* 1433 * The first thing we do here is to enable sync generation. As soon 1434 * as we start receiving bit clock, we'll start producing the SYNC 1435 * signal. 1436 */ 1437 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_ESYN); 1438 1439 /* 1440 * Wait for the codec ready signal from the AC97 codec. 1441 */ 1442 end_time = jiffies + HZ; 1443 do { 1444 /* 1445 * Read the AC97 status register to see if we've seen a CODEC 1446 * signal from the AC97 codec. 1447 */ 1448 if (snd_cs4281_peekBA0(chip, BA0_ACSTS) & BA0_ACSTS_CRDY) 1449 goto __ok1; 1450 schedule_timeout_uninterruptible(1); 1451 } while (time_after_eq(end_time, jiffies)); 1452 1453 dev_err(chip->card->dev, 1454 "never read codec ready from AC'97 (0x%x)\n", 1455 snd_cs4281_peekBA0(chip, BA0_ACSTS)); 1456 return -EIO; 1457 1458 __ok1: 1459 if (chip->dual_codec) { 1460 end_time = jiffies + HZ; 1461 do { 1462 if (snd_cs4281_peekBA0(chip, BA0_ACSTS2) & BA0_ACSTS_CRDY) 1463 goto __codec2_ok; 1464 schedule_timeout_uninterruptible(1); 1465 } while (time_after_eq(end_time, jiffies)); 1466 dev_info(chip->card->dev, 1467 "secondary codec doesn't respond. disable it...\n"); 1468 chip->dual_codec = 0; 1469 __codec2_ok: ; 1470 } 1471 1472 /* 1473 * Assert the valid frame signal so that we can start sending commands 1474 * to the AC97 codec. 1475 */ 1476 1477 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_VFRM | BA0_ACCTL_ESYN); 1478 1479 /* 1480 * Wait until we've sampled input slots 3 and 4 as valid, meaning that 1481 * the codec is pumping ADC data across the AC-link. 1482 */ 1483 1484 end_time = jiffies + HZ; 1485 do { 1486 /* 1487 * Read the input slot valid register and see if input slots 3 1488 * 4 are valid yet. 1489 */ 1490 if ((snd_cs4281_peekBA0(chip, BA0_ACISV) & (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) == (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) 1491 goto __ok2; 1492 schedule_timeout_uninterruptible(1); 1493 } while (time_after_eq(end_time, jiffies)); 1494 1495 if (--retry_count > 0) 1496 goto __retry; 1497 dev_err(chip->card->dev, "never read ISV3 and ISV4 from AC'97\n"); 1498 return -EIO; 1499 1500 __ok2: 1501 1502 /* 1503 * Now, assert valid frame and the slot 3 and 4 valid bits. This will 1504 * commense the transfer of digital audio data to the AC97 codec. 1505 */ 1506 snd_cs4281_pokeBA0(chip, BA0_ACOSV, BA0_ACOSV_SLV(3) | BA0_ACOSV_SLV(4)); 1507 1508 /* 1509 * Initialize DMA structures 1510 */ 1511 for (tmp = 0; tmp < 4; tmp++) { 1512 struct cs4281_dma *dma = &chip->dma[tmp]; 1513 dma->regDBA = BA0_DBA0 + (tmp * 0x10); 1514 dma->regDCA = BA0_DCA0 + (tmp * 0x10); 1515 dma->regDBC = BA0_DBC0 + (tmp * 0x10); 1516 dma->regDCC = BA0_DCC0 + (tmp * 0x10); 1517 dma->regDMR = BA0_DMR0 + (tmp * 8); 1518 dma->regDCR = BA0_DCR0 + (tmp * 8); 1519 dma->regHDSR = BA0_HDSR0 + (tmp * 4); 1520 dma->regFCR = BA0_FCR0 + (tmp * 4); 1521 dma->regFSIC = BA0_FSIC0 + (tmp * 4); 1522 dma->fifo_offset = tmp * CS4281_FIFO_SIZE; 1523 snd_cs4281_pokeBA0(chip, dma->regFCR, 1524 BA0_FCR_LS(31) | 1525 BA0_FCR_RS(31) | 1526 BA0_FCR_SZ(CS4281_FIFO_SIZE) | 1527 BA0_FCR_OF(dma->fifo_offset)); 1528 } 1529 1530 chip->src_left_play_slot = 0; /* AC'97 left PCM playback (3) */ 1531 chip->src_right_play_slot = 1; /* AC'97 right PCM playback (4) */ 1532 chip->src_left_rec_slot = 10; /* AC'97 left PCM record (3) */ 1533 chip->src_right_rec_slot = 11; /* AC'97 right PCM record (4) */ 1534 1535 /* Activate wave playback FIFO for FM playback */ 1536 chip->dma[0].valFCR = BA0_FCR_FEN | BA0_FCR_LS(0) | 1537 BA0_FCR_RS(1) | 1538 BA0_FCR_SZ(CS4281_FIFO_SIZE) | 1539 BA0_FCR_OF(chip->dma[0].fifo_offset); 1540 snd_cs4281_pokeBA0(chip, chip->dma[0].regFCR, chip->dma[0].valFCR); 1541 snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) | 1542 (chip->src_right_play_slot << 8) | 1543 (chip->src_left_rec_slot << 16) | 1544 (chip->src_right_rec_slot << 24)); 1545 1546 /* Initialize digital volume */ 1547 snd_cs4281_pokeBA0(chip, BA0_PPLVC, 0); 1548 snd_cs4281_pokeBA0(chip, BA0_PPRVC, 0); 1549 1550 /* Enable IRQs */ 1551 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI); 1552 /* Unmask interrupts */ 1553 snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff & ~( 1554 BA0_HISR_MIDI | 1555 BA0_HISR_DMAI | 1556 BA0_HISR_DMA(0) | 1557 BA0_HISR_DMA(1) | 1558 BA0_HISR_DMA(2) | 1559 BA0_HISR_DMA(3))); 1560 1561 return 0; 1562 } 1563 1564 /* 1565 * MIDI section 1566 */ 1567 1568 static void snd_cs4281_midi_reset(struct cs4281 *chip) 1569 { 1570 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr | BA0_MIDCR_MRST); 1571 udelay(100); 1572 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); 1573 } 1574 1575 static int snd_cs4281_midi_input_open(struct snd_rawmidi_substream *substream) 1576 { 1577 struct cs4281 *chip = substream->rmidi->private_data; 1578 1579 guard(spinlock_irq)(&chip->reg_lock); 1580 chip->midcr |= BA0_MIDCR_RXE; 1581 chip->midi_input = substream; 1582 if (!(chip->uartm & CS4281_MODE_OUTPUT)) { 1583 snd_cs4281_midi_reset(chip); 1584 } else { 1585 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); 1586 } 1587 return 0; 1588 } 1589 1590 static int snd_cs4281_midi_input_close(struct snd_rawmidi_substream *substream) 1591 { 1592 struct cs4281 *chip = substream->rmidi->private_data; 1593 1594 guard(spinlock_irq)(&chip->reg_lock); 1595 chip->midcr &= ~(BA0_MIDCR_RXE | BA0_MIDCR_RIE); 1596 chip->midi_input = NULL; 1597 if (!(chip->uartm & CS4281_MODE_OUTPUT)) { 1598 snd_cs4281_midi_reset(chip); 1599 } else { 1600 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); 1601 } 1602 chip->uartm &= ~CS4281_MODE_INPUT; 1603 return 0; 1604 } 1605 1606 static int snd_cs4281_midi_output_open(struct snd_rawmidi_substream *substream) 1607 { 1608 struct cs4281 *chip = substream->rmidi->private_data; 1609 1610 guard(spinlock_irq)(&chip->reg_lock); 1611 chip->uartm |= CS4281_MODE_OUTPUT; 1612 chip->midcr |= BA0_MIDCR_TXE; 1613 chip->midi_output = substream; 1614 if (!(chip->uartm & CS4281_MODE_INPUT)) { 1615 snd_cs4281_midi_reset(chip); 1616 } else { 1617 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); 1618 } 1619 return 0; 1620 } 1621 1622 static int snd_cs4281_midi_output_close(struct snd_rawmidi_substream *substream) 1623 { 1624 struct cs4281 *chip = substream->rmidi->private_data; 1625 1626 guard(spinlock_irq)(&chip->reg_lock); 1627 chip->midcr &= ~(BA0_MIDCR_TXE | BA0_MIDCR_TIE); 1628 chip->midi_output = NULL; 1629 if (!(chip->uartm & CS4281_MODE_INPUT)) { 1630 snd_cs4281_midi_reset(chip); 1631 } else { 1632 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); 1633 } 1634 chip->uartm &= ~CS4281_MODE_OUTPUT; 1635 return 0; 1636 } 1637 1638 static void snd_cs4281_midi_input_trigger(struct snd_rawmidi_substream *substream, int up) 1639 { 1640 struct cs4281 *chip = substream->rmidi->private_data; 1641 1642 guard(spinlock_irqsave)(&chip->reg_lock); 1643 if (up) { 1644 if ((chip->midcr & BA0_MIDCR_RIE) == 0) { 1645 chip->midcr |= BA0_MIDCR_RIE; 1646 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); 1647 } 1648 } else { 1649 if (chip->midcr & BA0_MIDCR_RIE) { 1650 chip->midcr &= ~BA0_MIDCR_RIE; 1651 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); 1652 } 1653 } 1654 } 1655 1656 static void snd_cs4281_midi_output_trigger(struct snd_rawmidi_substream *substream, int up) 1657 { 1658 struct cs4281 *chip = substream->rmidi->private_data; 1659 unsigned char byte; 1660 1661 guard(spinlock_irqsave)(&chip->reg_lock); 1662 if (up) { 1663 if ((chip->midcr & BA0_MIDCR_TIE) == 0) { 1664 chip->midcr |= BA0_MIDCR_TIE; 1665 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */ 1666 while ((chip->midcr & BA0_MIDCR_TIE) && 1667 (snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) { 1668 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) { 1669 chip->midcr &= ~BA0_MIDCR_TIE; 1670 } else { 1671 snd_cs4281_pokeBA0(chip, BA0_MIDWP, byte); 1672 } 1673 } 1674 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); 1675 } 1676 } else { 1677 if (chip->midcr & BA0_MIDCR_TIE) { 1678 chip->midcr &= ~BA0_MIDCR_TIE; 1679 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); 1680 } 1681 } 1682 } 1683 1684 static const struct snd_rawmidi_ops snd_cs4281_midi_output = 1685 { 1686 .open = snd_cs4281_midi_output_open, 1687 .close = snd_cs4281_midi_output_close, 1688 .trigger = snd_cs4281_midi_output_trigger, 1689 }; 1690 1691 static const struct snd_rawmidi_ops snd_cs4281_midi_input = 1692 { 1693 .open = snd_cs4281_midi_input_open, 1694 .close = snd_cs4281_midi_input_close, 1695 .trigger = snd_cs4281_midi_input_trigger, 1696 }; 1697 1698 static int snd_cs4281_midi(struct cs4281 *chip, int device) 1699 { 1700 struct snd_rawmidi *rmidi; 1701 int err; 1702 1703 err = snd_rawmidi_new(chip->card, "CS4281", device, 1, 1, &rmidi); 1704 if (err < 0) 1705 return err; 1706 strscpy(rmidi->name, "CS4281"); 1707 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs4281_midi_output); 1708 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs4281_midi_input); 1709 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX; 1710 rmidi->private_data = chip; 1711 chip->rmidi = rmidi; 1712 return 0; 1713 } 1714 1715 /* 1716 * Interrupt handler 1717 */ 1718 1719 static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id) 1720 { 1721 struct cs4281 *chip = dev_id; 1722 unsigned int status, dma, val; 1723 struct cs4281_dma *cdma; 1724 1725 if (chip == NULL) 1726 return IRQ_NONE; 1727 status = snd_cs4281_peekBA0(chip, BA0_HISR); 1728 if ((status & 0x7fffffff) == 0) { 1729 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI); 1730 return IRQ_NONE; 1731 } 1732 1733 if (status & (BA0_HISR_DMA(0)|BA0_HISR_DMA(1)|BA0_HISR_DMA(2)|BA0_HISR_DMA(3))) { 1734 for (dma = 0; dma < 4; dma++) { 1735 bool period_elapsed = false; 1736 cdma = &chip->dma[dma]; 1737 1738 if (status & BA0_HISR_DMA(dma)) { 1739 guard(spinlock)(&chip->reg_lock); 1740 /* ack DMA IRQ */ 1741 val = snd_cs4281_peekBA0(chip, cdma->regHDSR); 1742 /* workaround, sometimes CS4281 acknowledges */ 1743 /* end or middle transfer position twice */ 1744 cdma->frag++; 1745 if ((val & BA0_HDSR_DHTC) && !(cdma->frag & 1)) { 1746 cdma->frag--; 1747 chip->spurious_dhtc_irq++; 1748 continue; 1749 } 1750 if ((val & BA0_HDSR_DTC) && (cdma->frag & 1)) { 1751 cdma->frag--; 1752 chip->spurious_dtc_irq++; 1753 continue; 1754 } 1755 period_elapsed = true; 1756 } 1757 if (period_elapsed) 1758 snd_pcm_period_elapsed(cdma->substream); 1759 } 1760 } 1761 1762 if ((status & BA0_HISR_MIDI) && chip->rmidi) { 1763 unsigned char c; 1764 1765 guard(spinlock)(&chip->reg_lock); 1766 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_RBE) == 0) { 1767 c = snd_cs4281_peekBA0(chip, BA0_MIDRP); 1768 if ((chip->midcr & BA0_MIDCR_RIE) == 0) 1769 continue; 1770 snd_rawmidi_receive(chip->midi_input, &c, 1); 1771 } 1772 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) { 1773 if ((chip->midcr & BA0_MIDCR_TIE) == 0) 1774 break; 1775 if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) { 1776 chip->midcr &= ~BA0_MIDCR_TIE; 1777 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); 1778 break; 1779 } 1780 snd_cs4281_pokeBA0(chip, BA0_MIDWP, c); 1781 } 1782 } 1783 1784 /* EOI to the PCI part... reenables interrupts */ 1785 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI); 1786 1787 return IRQ_HANDLED; 1788 } 1789 1790 1791 /* 1792 * OPL3 command 1793 */ 1794 static void snd_cs4281_opl3_command(struct snd_opl3 *opl3, unsigned short cmd, 1795 unsigned char val) 1796 { 1797 struct cs4281 *chip = opl3->private_data; 1798 void __iomem *port; 1799 1800 if (cmd & OPL3_RIGHT) 1801 port = chip->ba0 + BA0_B1AP; /* right port */ 1802 else 1803 port = chip->ba0 + BA0_B0AP; /* left port */ 1804 1805 guard(spinlock_irqsave)(&opl3->reg_lock); 1806 1807 writel((unsigned int)cmd, port); 1808 udelay(10); 1809 1810 writel((unsigned int)val, port + 4); 1811 udelay(30); 1812 } 1813 1814 static int __snd_cs4281_probe(struct pci_dev *pci, 1815 const struct pci_device_id *pci_id) 1816 { 1817 static int dev; 1818 struct snd_card *card; 1819 struct cs4281 *chip; 1820 struct snd_opl3 *opl3; 1821 int err; 1822 1823 if (dev >= SNDRV_CARDS) 1824 return -ENODEV; 1825 if (!enable[dev]) { 1826 dev++; 1827 return -ENOENT; 1828 } 1829 1830 err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 1831 sizeof(*chip), &card); 1832 if (err < 0) 1833 return err; 1834 chip = card->private_data; 1835 1836 err = snd_cs4281_create(card, pci, dual_codec[dev]); 1837 if (err < 0) 1838 return err; 1839 1840 err = snd_cs4281_mixer(chip); 1841 if (err < 0) 1842 return err; 1843 err = snd_cs4281_pcm(chip, 0); 1844 if (err < 0) 1845 return err; 1846 err = snd_cs4281_midi(chip, 0); 1847 if (err < 0) 1848 return err; 1849 err = snd_opl3_new(card, OPL3_HW_OPL3_CS4281, &opl3); 1850 if (err < 0) 1851 return err; 1852 opl3->private_data = chip; 1853 opl3->command = snd_cs4281_opl3_command; 1854 snd_opl3_init(opl3); 1855 err = snd_opl3_hwdep_new(opl3, 0, 1, NULL); 1856 if (err < 0) 1857 return err; 1858 snd_cs4281_create_gameport(chip); 1859 strscpy(card->driver, "CS4281"); 1860 strscpy(card->shortname, "Cirrus Logic CS4281"); 1861 sprintf(card->longname, "%s at 0x%lx, irq %d", 1862 card->shortname, 1863 chip->ba0_addr, 1864 chip->irq); 1865 1866 err = snd_card_register(card); 1867 if (err < 0) 1868 return err; 1869 1870 pci_set_drvdata(pci, card); 1871 dev++; 1872 return 0; 1873 } 1874 1875 static int snd_cs4281_probe(struct pci_dev *pci, 1876 const struct pci_device_id *pci_id) 1877 { 1878 return snd_card_free_on_error(&pci->dev, __snd_cs4281_probe(pci, pci_id)); 1879 } 1880 1881 /* 1882 * Power Management 1883 */ 1884 static const int saved_regs[SUSPEND_REGISTERS] = { 1885 BA0_JSCTL, 1886 BA0_GPIOR, 1887 BA0_SSCR, 1888 BA0_MIDCR, 1889 BA0_SRCSA, 1890 BA0_PASR, 1891 BA0_CASR, 1892 BA0_DACSR, 1893 BA0_ADCSR, 1894 BA0_FMLVC, 1895 BA0_FMRVC, 1896 BA0_PPLVC, 1897 BA0_PPRVC, 1898 }; 1899 1900 #define CLKCR1_CKRA 0x00010000L 1901 1902 static int cs4281_suspend(struct device *dev) 1903 { 1904 struct snd_card *card = dev_get_drvdata(dev); 1905 struct cs4281 *chip = card->private_data; 1906 u32 ulCLK; 1907 unsigned int i; 1908 1909 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 1910 snd_ac97_suspend(chip->ac97); 1911 snd_ac97_suspend(chip->ac97_secondary); 1912 1913 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1); 1914 ulCLK |= CLKCR1_CKRA; 1915 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK); 1916 1917 /* Disable interrupts. */ 1918 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_CHGM); 1919 1920 /* remember the status registers */ 1921 for (i = 0; i < ARRAY_SIZE(saved_regs); i++) 1922 if (saved_regs[i]) 1923 chip->suspend_regs[i] = snd_cs4281_peekBA0(chip, saved_regs[i]); 1924 1925 /* Turn off the serial ports. */ 1926 snd_cs4281_pokeBA0(chip, BA0_SERMC, 0); 1927 1928 /* Power off FM, Joystick, AC link, */ 1929 snd_cs4281_pokeBA0(chip, BA0_SSPM, 0); 1930 1931 /* DLL off. */ 1932 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0); 1933 1934 /* AC link off. */ 1935 snd_cs4281_pokeBA0(chip, BA0_SPMC, 0); 1936 1937 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1); 1938 ulCLK &= ~CLKCR1_CKRA; 1939 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK); 1940 return 0; 1941 } 1942 1943 static int cs4281_resume(struct device *dev) 1944 { 1945 struct snd_card *card = dev_get_drvdata(dev); 1946 struct cs4281 *chip = card->private_data; 1947 unsigned int i; 1948 u32 ulCLK; 1949 1950 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1); 1951 ulCLK |= CLKCR1_CKRA; 1952 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK); 1953 1954 snd_cs4281_chip_init(chip); 1955 1956 /* restore the status registers */ 1957 for (i = 0; i < ARRAY_SIZE(saved_regs); i++) 1958 if (saved_regs[i]) 1959 snd_cs4281_pokeBA0(chip, saved_regs[i], chip->suspend_regs[i]); 1960 1961 snd_ac97_resume(chip->ac97); 1962 snd_ac97_resume(chip->ac97_secondary); 1963 1964 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1); 1965 ulCLK &= ~CLKCR1_CKRA; 1966 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK); 1967 1968 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 1969 return 0; 1970 } 1971 1972 static DEFINE_SIMPLE_DEV_PM_OPS(cs4281_pm, cs4281_suspend, cs4281_resume); 1973 1974 static struct pci_driver cs4281_driver = { 1975 .name = KBUILD_MODNAME, 1976 .id_table = snd_cs4281_ids, 1977 .probe = snd_cs4281_probe, 1978 .driver = { 1979 .pm = &cs4281_pm, 1980 }, 1981 }; 1982 1983 module_pci_driver(cs4281_driver); 1984