1 /* 2 * B53 switch driver main logic 3 * 4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org> 5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com> 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include <linux/delay.h> 21 #include <linux/export.h> 22 #include <linux/gpio/consumer.h> 23 #include <linux/kernel.h> 24 #include <linux/math.h> 25 #include <linux/minmax.h> 26 #include <linux/module.h> 27 #include <linux/platform_data/b53.h> 28 #include <linux/phy.h> 29 #include <linux/phylink.h> 30 #include <linux/etherdevice.h> 31 #include <linux/if_bridge.h> 32 #include <linux/if_vlan.h> 33 #include <net/dsa.h> 34 35 #include "b53_regs.h" 36 #include "b53_priv.h" 37 38 struct b53_mib_desc { 39 u8 size; 40 u8 offset; 41 const char *name; 42 }; 43 44 /* BCM5365 MIB counters */ 45 static const struct b53_mib_desc b53_mibs_65[] = { 46 { 8, 0x00, "TxOctets" }, 47 { 4, 0x08, "TxDropPkts" }, 48 { 4, 0x10, "TxBroadcastPkts" }, 49 { 4, 0x14, "TxMulticastPkts" }, 50 { 4, 0x18, "TxUnicastPkts" }, 51 { 4, 0x1c, "TxCollisions" }, 52 { 4, 0x20, "TxSingleCollision" }, 53 { 4, 0x24, "TxMultipleCollision" }, 54 { 4, 0x28, "TxDeferredTransmit" }, 55 { 4, 0x2c, "TxLateCollision" }, 56 { 4, 0x30, "TxExcessiveCollision" }, 57 { 4, 0x38, "TxPausePkts" }, 58 { 8, 0x44, "RxOctets" }, 59 { 4, 0x4c, "RxUndersizePkts" }, 60 { 4, 0x50, "RxPausePkts" }, 61 { 4, 0x54, "Pkts64Octets" }, 62 { 4, 0x58, "Pkts65to127Octets" }, 63 { 4, 0x5c, "Pkts128to255Octets" }, 64 { 4, 0x60, "Pkts256to511Octets" }, 65 { 4, 0x64, "Pkts512to1023Octets" }, 66 { 4, 0x68, "Pkts1024to1522Octets" }, 67 { 4, 0x6c, "RxOversizePkts" }, 68 { 4, 0x70, "RxJabbers" }, 69 { 4, 0x74, "RxAlignmentErrors" }, 70 { 4, 0x78, "RxFCSErrors" }, 71 { 8, 0x7c, "RxGoodOctets" }, 72 { 4, 0x84, "RxDropPkts" }, 73 { 4, 0x88, "RxUnicastPkts" }, 74 { 4, 0x8c, "RxMulticastPkts" }, 75 { 4, 0x90, "RxBroadcastPkts" }, 76 { 4, 0x94, "RxSAChanges" }, 77 { 4, 0x98, "RxFragments" }, 78 }; 79 80 #define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65) 81 82 /* BCM63xx MIB counters */ 83 static const struct b53_mib_desc b53_mibs_63xx[] = { 84 { 8, 0x00, "TxOctets" }, 85 { 4, 0x08, "TxDropPkts" }, 86 { 4, 0x0c, "TxQoSPkts" }, 87 { 4, 0x10, "TxBroadcastPkts" }, 88 { 4, 0x14, "TxMulticastPkts" }, 89 { 4, 0x18, "TxUnicastPkts" }, 90 { 4, 0x1c, "TxCollisions" }, 91 { 4, 0x20, "TxSingleCollision" }, 92 { 4, 0x24, "TxMultipleCollision" }, 93 { 4, 0x28, "TxDeferredTransmit" }, 94 { 4, 0x2c, "TxLateCollision" }, 95 { 4, 0x30, "TxExcessiveCollision" }, 96 { 4, 0x38, "TxPausePkts" }, 97 { 8, 0x3c, "TxQoSOctets" }, 98 { 8, 0x44, "RxOctets" }, 99 { 4, 0x4c, "RxUndersizePkts" }, 100 { 4, 0x50, "RxPausePkts" }, 101 { 4, 0x54, "Pkts64Octets" }, 102 { 4, 0x58, "Pkts65to127Octets" }, 103 { 4, 0x5c, "Pkts128to255Octets" }, 104 { 4, 0x60, "Pkts256to511Octets" }, 105 { 4, 0x64, "Pkts512to1023Octets" }, 106 { 4, 0x68, "Pkts1024to1522Octets" }, 107 { 4, 0x6c, "RxOversizePkts" }, 108 { 4, 0x70, "RxJabbers" }, 109 { 4, 0x74, "RxAlignmentErrors" }, 110 { 4, 0x78, "RxFCSErrors" }, 111 { 8, 0x7c, "RxGoodOctets" }, 112 { 4, 0x84, "RxDropPkts" }, 113 { 4, 0x88, "RxUnicastPkts" }, 114 { 4, 0x8c, "RxMulticastPkts" }, 115 { 4, 0x90, "RxBroadcastPkts" }, 116 { 4, 0x94, "RxSAChanges" }, 117 { 4, 0x98, "RxFragments" }, 118 { 4, 0xa0, "RxSymbolErrors" }, 119 { 4, 0xa4, "RxQoSPkts" }, 120 { 8, 0xa8, "RxQoSOctets" }, 121 { 4, 0xb0, "Pkts1523to2047Octets" }, 122 { 4, 0xb4, "Pkts2048to4095Octets" }, 123 { 4, 0xb8, "Pkts4096to8191Octets" }, 124 { 4, 0xbc, "Pkts8192to9728Octets" }, 125 { 4, 0xc0, "RxDiscarded" }, 126 }; 127 128 #define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx) 129 130 /* MIB counters */ 131 static const struct b53_mib_desc b53_mibs[] = { 132 { 8, 0x00, "TxOctets" }, 133 { 4, 0x08, "TxDropPkts" }, 134 { 4, 0x10, "TxBroadcastPkts" }, 135 { 4, 0x14, "TxMulticastPkts" }, 136 { 4, 0x18, "TxUnicastPkts" }, 137 { 4, 0x1c, "TxCollisions" }, 138 { 4, 0x20, "TxSingleCollision" }, 139 { 4, 0x24, "TxMultipleCollision" }, 140 { 4, 0x28, "TxDeferredTransmit" }, 141 { 4, 0x2c, "TxLateCollision" }, 142 { 4, 0x30, "TxExcessiveCollision" }, 143 { 4, 0x38, "TxPausePkts" }, 144 { 8, 0x50, "RxOctets" }, 145 { 4, 0x58, "RxUndersizePkts" }, 146 { 4, 0x5c, "RxPausePkts" }, 147 { 4, 0x60, "Pkts64Octets" }, 148 { 4, 0x64, "Pkts65to127Octets" }, 149 { 4, 0x68, "Pkts128to255Octets" }, 150 { 4, 0x6c, "Pkts256to511Octets" }, 151 { 4, 0x70, "Pkts512to1023Octets" }, 152 { 4, 0x74, "Pkts1024to1522Octets" }, 153 { 4, 0x78, "RxOversizePkts" }, 154 { 4, 0x7c, "RxJabbers" }, 155 { 4, 0x80, "RxAlignmentErrors" }, 156 { 4, 0x84, "RxFCSErrors" }, 157 { 8, 0x88, "RxGoodOctets" }, 158 { 4, 0x90, "RxDropPkts" }, 159 { 4, 0x94, "RxUnicastPkts" }, 160 { 4, 0x98, "RxMulticastPkts" }, 161 { 4, 0x9c, "RxBroadcastPkts" }, 162 { 4, 0xa0, "RxSAChanges" }, 163 { 4, 0xa4, "RxFragments" }, 164 { 4, 0xa8, "RxJumboPkts" }, 165 { 4, 0xac, "RxSymbolErrors" }, 166 { 4, 0xc0, "RxDiscarded" }, 167 }; 168 169 #define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs) 170 171 static const struct b53_mib_desc b53_mibs_58xx[] = { 172 { 8, 0x00, "TxOctets" }, 173 { 4, 0x08, "TxDropPkts" }, 174 { 4, 0x0c, "TxQPKTQ0" }, 175 { 4, 0x10, "TxBroadcastPkts" }, 176 { 4, 0x14, "TxMulticastPkts" }, 177 { 4, 0x18, "TxUnicastPKts" }, 178 { 4, 0x1c, "TxCollisions" }, 179 { 4, 0x20, "TxSingleCollision" }, 180 { 4, 0x24, "TxMultipleCollision" }, 181 { 4, 0x28, "TxDeferredCollision" }, 182 { 4, 0x2c, "TxLateCollision" }, 183 { 4, 0x30, "TxExcessiveCollision" }, 184 { 4, 0x34, "TxFrameInDisc" }, 185 { 4, 0x38, "TxPausePkts" }, 186 { 4, 0x3c, "TxQPKTQ1" }, 187 { 4, 0x40, "TxQPKTQ2" }, 188 { 4, 0x44, "TxQPKTQ3" }, 189 { 4, 0x48, "TxQPKTQ4" }, 190 { 4, 0x4c, "TxQPKTQ5" }, 191 { 8, 0x50, "RxOctets" }, 192 { 4, 0x58, "RxUndersizePkts" }, 193 { 4, 0x5c, "RxPausePkts" }, 194 { 4, 0x60, "RxPkts64Octets" }, 195 { 4, 0x64, "RxPkts65to127Octets" }, 196 { 4, 0x68, "RxPkts128to255Octets" }, 197 { 4, 0x6c, "RxPkts256to511Octets" }, 198 { 4, 0x70, "RxPkts512to1023Octets" }, 199 { 4, 0x74, "RxPkts1024toMaxPktsOctets" }, 200 { 4, 0x78, "RxOversizePkts" }, 201 { 4, 0x7c, "RxJabbers" }, 202 { 4, 0x80, "RxAlignmentErrors" }, 203 { 4, 0x84, "RxFCSErrors" }, 204 { 8, 0x88, "RxGoodOctets" }, 205 { 4, 0x90, "RxDropPkts" }, 206 { 4, 0x94, "RxUnicastPkts" }, 207 { 4, 0x98, "RxMulticastPkts" }, 208 { 4, 0x9c, "RxBroadcastPkts" }, 209 { 4, 0xa0, "RxSAChanges" }, 210 { 4, 0xa4, "RxFragments" }, 211 { 4, 0xa8, "RxJumboPkt" }, 212 { 4, 0xac, "RxSymblErr" }, 213 { 4, 0xb0, "InRangeErrCount" }, 214 { 4, 0xb4, "OutRangeErrCount" }, 215 { 4, 0xb8, "EEELpiEvent" }, 216 { 4, 0xbc, "EEELpiDuration" }, 217 { 4, 0xc0, "RxDiscard" }, 218 { 4, 0xc8, "TxQPKTQ6" }, 219 { 4, 0xcc, "TxQPKTQ7" }, 220 { 4, 0xd0, "TxPkts64Octets" }, 221 { 4, 0xd4, "TxPkts65to127Octets" }, 222 { 4, 0xd8, "TxPkts128to255Octets" }, 223 { 4, 0xdc, "TxPkts256to511Ocets" }, 224 { 4, 0xe0, "TxPkts512to1023Ocets" }, 225 { 4, 0xe4, "TxPkts1024toMaxPktOcets" }, 226 }; 227 228 #define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx) 229 230 #define B53_MAX_MTU_25 (1536 - ETH_HLEN - VLAN_HLEN - ETH_FCS_LEN) 231 #define B53_MAX_MTU (9720 - ETH_HLEN - VLAN_HLEN - ETH_FCS_LEN) 232 233 static int b53_do_vlan_op(struct b53_device *dev, u8 op) 234 { 235 unsigned int i; 236 237 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op); 238 239 for (i = 0; i < 10; i++) { 240 u8 vta; 241 242 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta); 243 if (!(vta & VTA_START_CMD)) 244 return 0; 245 246 usleep_range(100, 200); 247 } 248 249 return -EIO; 250 } 251 252 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid, 253 struct b53_vlan *vlan) 254 { 255 if (is5325(dev)) { 256 u32 entry = 0; 257 258 if (vlan->members) { 259 entry = ((vlan->untag & VA_UNTAG_MASK_25) << 260 VA_UNTAG_S_25) | vlan->members; 261 if (dev->core_rev >= 3) 262 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S; 263 else 264 entry |= VA_VALID_25; 265 } 266 267 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry); 268 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 269 VTA_RW_STATE_WR | VTA_RW_OP_EN); 270 } else if (is5365(dev)) { 271 u16 entry = 0; 272 273 if (vlan->members) 274 entry = ((vlan->untag & VA_UNTAG_MASK_65) << 275 VA_UNTAG_S_65) | vlan->members | VA_VALID_65; 276 277 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry); 278 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 279 VTA_RW_STATE_WR | VTA_RW_OP_EN); 280 } else { 281 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 282 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], 283 (vlan->untag << VTE_UNTAG_S) | vlan->members); 284 285 b53_do_vlan_op(dev, VTA_CMD_WRITE); 286 } 287 288 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n", 289 vid, vlan->members, vlan->untag); 290 } 291 292 static void b53_get_vlan_entry(struct b53_device *dev, u16 vid, 293 struct b53_vlan *vlan) 294 { 295 if (is5325(dev)) { 296 u32 entry = 0; 297 298 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 299 VTA_RW_STATE_RD | VTA_RW_OP_EN); 300 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry); 301 302 if (dev->core_rev >= 3) 303 vlan->valid = !!(entry & VA_VALID_25_R4); 304 else 305 vlan->valid = !!(entry & VA_VALID_25); 306 vlan->members = entry & VA_MEMBER_MASK; 307 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25; 308 309 } else if (is5365(dev)) { 310 u16 entry = 0; 311 312 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 313 VTA_RW_STATE_WR | VTA_RW_OP_EN); 314 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry); 315 316 vlan->valid = !!(entry & VA_VALID_65); 317 vlan->members = entry & VA_MEMBER_MASK; 318 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65; 319 } else { 320 u32 entry = 0; 321 322 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 323 b53_do_vlan_op(dev, VTA_CMD_READ); 324 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry); 325 vlan->members = entry & VTE_MEMBERS; 326 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS; 327 vlan->valid = true; 328 } 329 } 330 331 static void b53_set_eap_mode(struct b53_device *dev, int port, int mode) 332 { 333 u64 eap_conf; 334 335 if (is5325(dev) || is5365(dev) || dev->chip_id == BCM5389_DEVICE_ID) 336 return; 337 338 b53_read64(dev, B53_EAP_PAGE, B53_PORT_EAP_CONF(port), &eap_conf); 339 340 if (is63xx(dev)) { 341 eap_conf &= ~EAP_MODE_MASK_63XX; 342 eap_conf |= (u64)mode << EAP_MODE_SHIFT_63XX; 343 } else { 344 eap_conf &= ~EAP_MODE_MASK; 345 eap_conf |= (u64)mode << EAP_MODE_SHIFT; 346 } 347 348 b53_write64(dev, B53_EAP_PAGE, B53_PORT_EAP_CONF(port), eap_conf); 349 } 350 351 static void b53_set_forwarding(struct b53_device *dev, int enable) 352 { 353 u8 mgmt; 354 355 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 356 357 if (enable) 358 mgmt |= SM_SW_FWD_EN; 359 else 360 mgmt &= ~SM_SW_FWD_EN; 361 362 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 363 364 if (!is5325(dev)) { 365 /* Include IMP port in dumb forwarding mode */ 366 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt); 367 mgmt |= B53_MII_DUMB_FWDG_EN; 368 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt); 369 370 /* Look at B53_UC_FWD_EN and B53_MC_FWD_EN to decide whether 371 * frames should be flooded or not. 372 */ 373 b53_read8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, &mgmt); 374 mgmt |= B53_UC_FWD_EN | B53_MC_FWD_EN | B53_IP_MC; 375 b53_write8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, mgmt); 376 } else { 377 b53_read8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, &mgmt); 378 mgmt |= B53_IP_MC; 379 b53_write8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, mgmt); 380 } 381 } 382 383 static void b53_enable_vlan(struct b53_device *dev, int port, bool enable, 384 bool enable_filtering) 385 { 386 u8 mgmt, vc0, vc1, vc4 = 0, vc5; 387 388 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 389 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0); 390 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1); 391 392 if (is5325(dev) || is5365(dev)) { 393 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 394 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5); 395 } else if (is63xx(dev)) { 396 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4); 397 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5); 398 } else { 399 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4); 400 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5); 401 } 402 403 vc1 &= ~VC1_RX_MCST_FWD_EN; 404 405 if (enable) { 406 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID; 407 vc1 |= VC1_RX_MCST_UNTAG_EN; 408 vc4 &= ~VC4_ING_VID_CHECK_MASK; 409 if (enable_filtering) { 410 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S; 411 vc5 |= VC5_DROP_VTABLE_MISS; 412 } else { 413 vc4 |= VC4_NO_ING_VID_CHK << VC4_ING_VID_CHECK_S; 414 vc5 &= ~VC5_DROP_VTABLE_MISS; 415 } 416 417 if (is5325(dev)) 418 vc0 &= ~VC0_RESERVED_1; 419 420 if (is5325(dev) || is5365(dev)) 421 vc1 |= VC1_RX_MCST_TAG_EN; 422 423 } else { 424 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID); 425 vc1 &= ~VC1_RX_MCST_UNTAG_EN; 426 vc4 &= ~VC4_ING_VID_CHECK_MASK; 427 vc5 &= ~VC5_DROP_VTABLE_MISS; 428 429 if (is5325(dev) || is5365(dev)) 430 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S; 431 else 432 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S; 433 434 if (is5325(dev) || is5365(dev)) 435 vc1 &= ~VC1_RX_MCST_TAG_EN; 436 } 437 438 if (!is5325(dev) && !is5365(dev)) 439 vc5 &= ~VC5_VID_FFF_EN; 440 441 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0); 442 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1); 443 444 if (is5325(dev) || is5365(dev)) { 445 /* enable the high 8 bit vid check on 5325 */ 446 if (is5325(dev) && enable) 447 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 448 VC3_HIGH_8BIT_EN); 449 else 450 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 451 452 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4); 453 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5); 454 } else if (is63xx(dev)) { 455 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0); 456 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4); 457 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5); 458 } else { 459 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 460 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4); 461 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5); 462 } 463 464 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 465 466 dev->vlan_enabled = enable; 467 468 dev_dbg(dev->dev, "Port %d VLAN enabled: %d, filtering: %d\n", 469 port, enable, enable_filtering); 470 } 471 472 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100) 473 { 474 u32 port_mask = 0; 475 u16 max_size = JMS_MIN_SIZE; 476 477 if (is5325(dev) || is5365(dev)) 478 return -EINVAL; 479 480 if (enable) { 481 port_mask = dev->enabled_ports; 482 max_size = JMS_MAX_SIZE; 483 if (allow_10_100) 484 port_mask |= JPM_10_100_JUMBO_EN; 485 } 486 487 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask); 488 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size); 489 } 490 491 static int b53_flush_arl(struct b53_device *dev, u8 mask) 492 { 493 unsigned int i; 494 495 if (is5325(dev)) 496 return 0; 497 498 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 499 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask); 500 501 for (i = 0; i < 10; i++) { 502 u8 fast_age_ctrl; 503 504 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 505 &fast_age_ctrl); 506 507 if (!(fast_age_ctrl & FAST_AGE_DONE)) 508 goto out; 509 510 msleep(1); 511 } 512 513 return -ETIMEDOUT; 514 out: 515 /* Only age dynamic entries (default behavior) */ 516 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC); 517 return 0; 518 } 519 520 static int b53_fast_age_port(struct b53_device *dev, int port) 521 { 522 if (is5325(dev)) 523 return 0; 524 525 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port); 526 527 return b53_flush_arl(dev, FAST_AGE_PORT); 528 } 529 530 static int b53_fast_age_vlan(struct b53_device *dev, u16 vid) 531 { 532 if (is5325(dev)) 533 return 0; 534 535 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid); 536 537 return b53_flush_arl(dev, FAST_AGE_VLAN); 538 } 539 540 void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port) 541 { 542 struct b53_device *dev = ds->priv; 543 unsigned int i; 544 u16 pvlan; 545 546 /* BCM5325 CPU port is at 8 */ 547 if ((is5325(dev) || is5365(dev)) && cpu_port == B53_CPU_PORT_25) 548 cpu_port = B53_CPU_PORT; 549 550 /* Enable the IMP port to be in the same VLAN as the other ports 551 * on a per-port basis such that we only have Port i and IMP in 552 * the same VLAN. 553 */ 554 b53_for_each_port(dev, i) { 555 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan); 556 pvlan |= BIT(cpu_port); 557 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan); 558 } 559 } 560 EXPORT_SYMBOL(b53_imp_vlan_setup); 561 562 static void b53_port_set_ucast_flood(struct b53_device *dev, int port, 563 bool unicast) 564 { 565 u16 uc; 566 567 if (is5325(dev)) { 568 if (port == B53_CPU_PORT_25) 569 port = B53_CPU_PORT; 570 571 b53_read16(dev, B53_IEEE_PAGE, B53_IEEE_UCAST_DLF, &uc); 572 if (unicast) 573 uc |= BIT(port) | B53_IEEE_UCAST_DROP_EN; 574 else 575 uc &= ~BIT(port); 576 b53_write16(dev, B53_IEEE_PAGE, B53_IEEE_UCAST_DLF, uc); 577 } else { 578 b53_read16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, &uc); 579 if (unicast) 580 uc |= BIT(port); 581 else 582 uc &= ~BIT(port); 583 b53_write16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, uc); 584 } 585 } 586 587 static void b53_port_set_mcast_flood(struct b53_device *dev, int port, 588 bool multicast) 589 { 590 u16 mc; 591 592 if (is5325(dev)) { 593 if (port == B53_CPU_PORT_25) 594 port = B53_CPU_PORT; 595 596 b53_read16(dev, B53_IEEE_PAGE, B53_IEEE_MCAST_DLF, &mc); 597 if (multicast) 598 mc |= BIT(port) | B53_IEEE_MCAST_DROP_EN; 599 else 600 mc &= ~BIT(port); 601 b53_write16(dev, B53_IEEE_PAGE, B53_IEEE_MCAST_DLF, mc); 602 } else { 603 b53_read16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, &mc); 604 if (multicast) 605 mc |= BIT(port); 606 else 607 mc &= ~BIT(port); 608 b53_write16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, mc); 609 610 b53_read16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, &mc); 611 if (multicast) 612 mc |= BIT(port); 613 else 614 mc &= ~BIT(port); 615 b53_write16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, mc); 616 } 617 } 618 619 static void b53_port_set_learning(struct b53_device *dev, int port, 620 bool learning) 621 { 622 u16 reg; 623 624 if (is5325(dev)) 625 return; 626 627 b53_read16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, ®); 628 if (learning) 629 reg &= ~BIT(port); 630 else 631 reg |= BIT(port); 632 b53_write16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, reg); 633 } 634 635 static void b53_port_set_isolated(struct b53_device *dev, int port, 636 bool isolated) 637 { 638 u8 offset; 639 u16 reg; 640 641 if (is5325(dev)) 642 offset = B53_PROTECTED_PORT_SEL_25; 643 else 644 offset = B53_PROTECTED_PORT_SEL; 645 646 b53_read16(dev, B53_CTRL_PAGE, offset, ®); 647 if (isolated) 648 reg |= BIT(port); 649 else 650 reg &= ~BIT(port); 651 b53_write16(dev, B53_CTRL_PAGE, offset, reg); 652 } 653 654 static void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable) 655 { 656 struct b53_device *dev = ds->priv; 657 u16 reg; 658 659 b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, ®); 660 if (enable) 661 reg |= BIT(port); 662 else 663 reg &= ~BIT(port); 664 b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg); 665 } 666 667 int b53_setup_port(struct dsa_switch *ds, int port) 668 { 669 struct b53_device *dev = ds->priv; 670 671 b53_port_set_ucast_flood(dev, port, true); 672 b53_port_set_mcast_flood(dev, port, true); 673 b53_port_set_learning(dev, port, false); 674 b53_port_set_isolated(dev, port, false); 675 676 /* Force all traffic to go to the CPU port to prevent the ASIC from 677 * trying to forward to bridged ports on matching FDB entries, then 678 * dropping frames because it isn't allowed to forward there. 679 */ 680 if (dsa_is_user_port(ds, port)) 681 b53_set_eap_mode(dev, port, EAP_MODE_SIMPLIFIED); 682 683 if (is5325(dev) && 684 in_range(port, 1, 4)) { 685 u8 reg; 686 687 b53_read8(dev, B53_CTRL_PAGE, B53_PD_MODE_CTRL_25, ®); 688 reg &= ~PD_MODE_POWER_DOWN_PORT(0); 689 if (dsa_is_unused_port(ds, port)) 690 reg |= PD_MODE_POWER_DOWN_PORT(port); 691 else 692 reg &= ~PD_MODE_POWER_DOWN_PORT(port); 693 b53_write8(dev, B53_CTRL_PAGE, B53_PD_MODE_CTRL_25, reg); 694 } 695 696 return 0; 697 } 698 EXPORT_SYMBOL(b53_setup_port); 699 700 int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy) 701 { 702 struct b53_device *dev = ds->priv; 703 unsigned int cpu_port; 704 int ret = 0; 705 u16 pvlan; 706 707 if (!dsa_is_user_port(ds, port)) 708 return 0; 709 710 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 711 712 if (dev->ops->phy_enable) 713 dev->ops->phy_enable(dev, port); 714 715 if (dev->ops->irq_enable) 716 ret = dev->ops->irq_enable(dev, port); 717 if (ret) 718 return ret; 719 720 /* Clear the Rx and Tx disable bits and set to no spanning tree */ 721 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0); 722 723 /* Set this port, and only this one to be in the default VLAN, 724 * if member of a bridge, restore its membership prior to 725 * bringing down this port. 726 */ 727 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 728 pvlan &= ~0x1ff; 729 pvlan |= BIT(port); 730 pvlan |= dev->ports[port].vlan_ctl_mask; 731 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 732 733 b53_imp_vlan_setup(ds, cpu_port); 734 735 /* If EEE was enabled, restore it */ 736 if (dev->ports[port].eee.eee_enabled) 737 b53_eee_enable_set(ds, port, true); 738 739 return 0; 740 } 741 EXPORT_SYMBOL(b53_enable_port); 742 743 void b53_disable_port(struct dsa_switch *ds, int port) 744 { 745 struct b53_device *dev = ds->priv; 746 u8 reg; 747 748 /* Disable Tx/Rx for the port */ 749 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 750 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE; 751 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 752 753 if (dev->ops->phy_disable) 754 dev->ops->phy_disable(dev, port); 755 756 if (dev->ops->irq_disable) 757 dev->ops->irq_disable(dev, port); 758 } 759 EXPORT_SYMBOL(b53_disable_port); 760 761 void b53_brcm_hdr_setup(struct dsa_switch *ds, int port) 762 { 763 struct b53_device *dev = ds->priv; 764 bool tag_en = !(dev->tag_protocol == DSA_TAG_PROTO_NONE); 765 u8 hdr_ctl, val; 766 u16 reg; 767 768 /* Resolve which bit controls the Broadcom tag */ 769 switch (port) { 770 case 8: 771 val = BRCM_HDR_P8_EN; 772 break; 773 case 7: 774 val = BRCM_HDR_P7_EN; 775 break; 776 case 5: 777 val = BRCM_HDR_P5_EN; 778 break; 779 default: 780 val = 0; 781 break; 782 } 783 784 /* Enable management mode if tagging is requested */ 785 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &hdr_ctl); 786 if (tag_en) 787 hdr_ctl |= SM_SW_FWD_MODE; 788 else 789 hdr_ctl &= ~SM_SW_FWD_MODE; 790 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, hdr_ctl); 791 792 /* Configure the appropriate IMP port */ 793 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &hdr_ctl); 794 if (port == 8) 795 hdr_ctl |= GC_FRM_MGMT_PORT_MII; 796 else if (port == 5) 797 hdr_ctl |= GC_FRM_MGMT_PORT_M; 798 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, hdr_ctl); 799 800 /* B53_BRCM_HDR not present on devices with legacy tags */ 801 if (dev->tag_protocol == DSA_TAG_PROTO_BRCM_LEGACY || 802 dev->tag_protocol == DSA_TAG_PROTO_BRCM_LEGACY_FCS) 803 return; 804 805 /* Enable Broadcom tags for IMP port */ 806 b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl); 807 if (tag_en) 808 hdr_ctl |= val; 809 else 810 hdr_ctl &= ~val; 811 b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl); 812 813 /* Registers below are only accessible on newer devices */ 814 if (!is58xx(dev)) 815 return; 816 817 /* Enable reception Broadcom tag for CPU TX (switch RX) to 818 * allow us to tag outgoing frames 819 */ 820 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, ®); 821 if (tag_en) 822 reg &= ~BIT(port); 823 else 824 reg |= BIT(port); 825 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg); 826 827 /* Enable transmission of Broadcom tags from the switch (CPU RX) to 828 * allow delivering frames to the per-port net_devices 829 */ 830 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, ®); 831 if (tag_en) 832 reg &= ~BIT(port); 833 else 834 reg |= BIT(port); 835 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg); 836 } 837 EXPORT_SYMBOL(b53_brcm_hdr_setup); 838 839 int b53_enable_mcast_snooping(struct b53_device *dev) 840 { 841 u16 val16; 842 u32 val; 843 int ret; 844 845 /* Older switches use different IGMP controls, not HL_PRTC_CTRL. */ 846 if (is5325(dev) || is5365(dev) || dev->chip_id == BCM5389_DEVICE_ID || 847 is5397_98(dev) || is63xx(dev)) 848 return 0; 849 850 /* IGMPv2 and MLDv1 reports use the group's destination MAC. Once 851 * the first listener is offloaded, ordinary multicast forwarding 852 * can keep subsequent reports from reaching the bridge CPU. 853 */ 854 855 /* BCM5395 has a narrower register and a single IGMP classifier. 856 * Its ICMPv6 classifier also covers MLD. 857 */ 858 if (dev->chip_id == BCM5395_DEVICE_ID) { 859 ret = b53_read16(dev, B53_MGMT_PAGE, B53_HL_PRTC_CTRL, &val16); 860 if (ret) 861 return ret; 862 863 val16 |= HL_PRTC_IGMP_IP_EN_5395 | HL_PRTC_ICMPV6_EN; 864 /* Zero forwarding modes copy control traffic to the CPU 865 * independently of the ARL lookup, retaining L2 forwarding. 866 */ 867 val16 &= ~(HL_PRTC_IGMP_FWD_MODE_5395 | 868 HL_PRTC_ICMPV6_FWD_MODE); 869 870 return b53_write16(dev, B53_MGMT_PAGE, B53_HL_PRTC_CTRL, 871 val16); 872 } 873 874 ret = b53_read32(dev, B53_MGMT_PAGE, B53_HL_PRTC_CTRL, &val); 875 if (ret) 876 return ret; 877 878 val |= HL_PRTC_IGMP_RPTLVE_EN | HL_PRTC_IGMP_QRY_EN | 879 HL_PRTC_IGMP_UKN_EN | HL_PRTC_MLD_RPTDONE_EN | 880 HL_PRTC_MLD_QRY_EN; 881 /* Zero forwarding modes copy control traffic to the CPU 882 * independently of the ARL lookup, retaining L2 forwarding. 883 */ 884 val &= ~(HL_PRTC_IGMP_RPTLVE_FWD_MODE | HL_PRTC_IGMP_QRY_FWD_MODE | 885 HL_PRTC_IGMP_UKN_FWD_MODE | HL_PRTC_MLD_RPTDONE_FWD_MODE | 886 HL_PRTC_MLD_QRY_FWD_MODE); 887 888 return b53_write32(dev, B53_MGMT_PAGE, B53_HL_PRTC_CTRL, val); 889 } 890 EXPORT_SYMBOL(b53_enable_mcast_snooping); 891 892 static void b53_enable_cpu_port(struct b53_device *dev, int port) 893 { 894 u8 port_ctrl; 895 896 /* BCM5325 CPU port is at 8 */ 897 if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25) 898 port = B53_CPU_PORT; 899 900 port_ctrl = PORT_CTRL_RX_BCST_EN | 901 PORT_CTRL_RX_MCST_EN | 902 PORT_CTRL_RX_UCST_EN; 903 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl); 904 905 b53_brcm_hdr_setup(dev->ds, port); 906 } 907 908 static void b53_enable_mib(struct b53_device *dev) 909 { 910 u8 gc; 911 912 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 913 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN); 914 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc); 915 } 916 917 static void b53_enable_stp(struct b53_device *dev) 918 { 919 u8 gc; 920 921 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 922 gc |= GC_RX_BPDU_EN; 923 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc); 924 } 925 926 static u16 b53_default_pvid(struct b53_device *dev) 927 { 928 return 0; 929 } 930 931 static bool b53_vlan_port_needs_forced_tagged(struct dsa_switch *ds, int port) 932 { 933 struct b53_device *dev = ds->priv; 934 935 return dev->tag_protocol == DSA_TAG_PROTO_NONE && dsa_is_cpu_port(ds, port); 936 } 937 938 static bool b53_vlan_port_may_join_untagged(struct dsa_switch *ds, int port) 939 { 940 struct b53_device *dev = ds->priv; 941 struct dsa_port *dp; 942 943 if (!dev->vlan_filtering) 944 return true; 945 946 dp = dsa_to_port(ds, port); 947 948 if (dsa_port_is_cpu(dp)) 949 return true; 950 951 return dp->bridge == NULL; 952 } 953 954 int b53_configure_vlan(struct dsa_switch *ds) 955 { 956 struct b53_device *dev = ds->priv; 957 struct b53_vlan vl = { 0 }; 958 struct b53_vlan *v; 959 int i, def_vid; 960 u16 vid; 961 962 def_vid = b53_default_pvid(dev); 963 964 /* clear all vlan entries */ 965 if (is5325(dev) || is5365(dev)) { 966 for (i = def_vid; i < dev->num_vlans; i++) 967 b53_set_vlan_entry(dev, i, &vl); 968 } else { 969 b53_do_vlan_op(dev, VTA_CMD_CLEAR); 970 } 971 972 b53_enable_vlan(dev, -1, dev->vlan_enabled, dev->vlan_filtering); 973 974 /* Create an untagged VLAN entry for the default PVID in case 975 * CONFIG_VLAN_8021Q is disabled and there are no calls to 976 * dsa_user_vlan_rx_add_vid() to create the default VLAN 977 * entry. Do this only when the tagging protocol is not 978 * DSA_TAG_PROTO_NONE 979 */ 980 v = &dev->vlans[def_vid]; 981 b53_for_each_port(dev, i) { 982 if (!b53_vlan_port_may_join_untagged(ds, i)) 983 continue; 984 985 vl.members |= BIT(i); 986 if (!b53_vlan_port_needs_forced_tagged(ds, i)) 987 vl.untag = vl.members; 988 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(i), 989 def_vid); 990 } 991 b53_set_vlan_entry(dev, def_vid, &vl); 992 993 if (dev->vlan_filtering) { 994 /* Upon initial call we have not set-up any VLANs, but upon 995 * system resume, we need to restore all VLAN entries. 996 */ 997 for (vid = def_vid + 1; vid < dev->num_vlans; vid++) { 998 v = &dev->vlans[vid]; 999 1000 if (!v->members) 1001 continue; 1002 1003 b53_set_vlan_entry(dev, vid, v); 1004 b53_fast_age_vlan(dev, vid); 1005 } 1006 1007 b53_for_each_port(dev, i) { 1008 if (!dsa_is_cpu_port(ds, i)) 1009 b53_write16(dev, B53_VLAN_PAGE, 1010 B53_VLAN_PORT_DEF_TAG(i), 1011 dev->ports[i].pvid); 1012 } 1013 } 1014 1015 return 0; 1016 } 1017 EXPORT_SYMBOL(b53_configure_vlan); 1018 1019 static void b53_switch_reset_gpio(struct b53_device *dev) 1020 { 1021 struct gpio_desc *gpio = dev->reset_gpio; 1022 1023 if (IS_ERR(gpio)) 1024 return; 1025 1026 /* Reset sequence: RESET low(50ms)->high(20ms) 1027 */ 1028 gpiod_set_value(gpio, 0); 1029 mdelay(50); 1030 1031 gpiod_set_value(gpio, 1); 1032 mdelay(20); 1033 1034 dev->current_page = 0xff; 1035 } 1036 1037 static int b53_switch_reset(struct b53_device *dev) 1038 { 1039 unsigned int timeout = 1000; 1040 u8 mgmt, reg; 1041 1042 b53_switch_reset_gpio(dev); 1043 1044 if (is539x(dev)) { 1045 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83); 1046 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00); 1047 } 1048 1049 /* This is specific to 58xx devices here, do not use is58xx() which 1050 * covers the larger Starfigther 2 family, including 7445/7278 which 1051 * still use this driver as a library and need to perform the reset 1052 * earlier. 1053 */ 1054 if (dev->chip_id == BCM58XX_DEVICE_ID || 1055 dev->chip_id == BCM583XX_DEVICE_ID) { 1056 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 1057 reg |= SW_RST | EN_SW_RST | EN_CH_RST; 1058 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg); 1059 1060 do { 1061 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 1062 if (!(reg & SW_RST)) 1063 break; 1064 1065 usleep_range(1000, 2000); 1066 } while (timeout-- > 0); 1067 1068 if (timeout == 0) { 1069 dev_err(dev->dev, 1070 "Timeout waiting for SW_RST to clear!\n"); 1071 return -ETIMEDOUT; 1072 } 1073 } 1074 1075 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 1076 1077 if (!(mgmt & SM_SW_FWD_EN)) { 1078 mgmt &= ~SM_SW_FWD_MODE; 1079 mgmt |= SM_SW_FWD_EN; 1080 1081 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 1082 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 1083 1084 if (!(mgmt & SM_SW_FWD_EN)) { 1085 dev_err(dev->dev, "Failed to enable switch!\n"); 1086 return -EINVAL; 1087 } 1088 } 1089 1090 b53_enable_mib(dev); 1091 b53_enable_stp(dev); 1092 1093 return b53_flush_arl(dev, FAST_AGE_STATIC); 1094 } 1095 1096 static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg) 1097 { 1098 struct b53_device *priv = ds->priv; 1099 u16 value = 0; 1100 int ret; 1101 1102 if (priv->ops->phy_read16) 1103 ret = priv->ops->phy_read16(priv, addr, reg, &value); 1104 else 1105 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr), 1106 reg * 2, &value); 1107 1108 return ret ? ret : value; 1109 } 1110 1111 static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 1112 { 1113 struct b53_device *priv = ds->priv; 1114 1115 if (priv->ops->phy_write16) 1116 return priv->ops->phy_write16(priv, addr, reg, val); 1117 1118 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val); 1119 } 1120 1121 static int b53_reset_switch(struct b53_device *priv) 1122 { 1123 /* reset vlans */ 1124 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans); 1125 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports); 1126 1127 priv->serdes_lane = B53_INVALID_LANE; 1128 1129 return b53_switch_reset(priv); 1130 } 1131 1132 static int b53_apply_config(struct b53_device *priv) 1133 { 1134 /* disable switching */ 1135 b53_set_forwarding(priv, 0); 1136 1137 b53_configure_vlan(priv->ds); 1138 1139 /* enable switching */ 1140 b53_set_forwarding(priv, 1); 1141 1142 return 0; 1143 } 1144 1145 static void b53_reset_mib(struct b53_device *priv) 1146 { 1147 u8 gc; 1148 1149 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 1150 1151 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB); 1152 msleep(1); 1153 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB); 1154 msleep(1); 1155 } 1156 1157 static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev) 1158 { 1159 if (is5365(dev)) 1160 return b53_mibs_65; 1161 else if (is63xx(dev)) 1162 return b53_mibs_63xx; 1163 else if (is58xx(dev)) 1164 return b53_mibs_58xx; 1165 else 1166 return b53_mibs; 1167 } 1168 1169 static unsigned int b53_get_mib_size(struct b53_device *dev) 1170 { 1171 if (is5365(dev)) 1172 return B53_MIBS_65_SIZE; 1173 else if (is63xx(dev)) 1174 return B53_MIBS_63XX_SIZE; 1175 else if (is58xx(dev)) 1176 return B53_MIBS_58XX_SIZE; 1177 else 1178 return B53_MIBS_SIZE; 1179 } 1180 1181 static struct phy_device *b53_get_phy_device(struct dsa_switch *ds, int port) 1182 { 1183 /* These ports typically do not have built-in PHYs */ 1184 switch (port) { 1185 case B53_CPU_PORT_25: 1186 case 7: 1187 case B53_CPU_PORT: 1188 return NULL; 1189 } 1190 1191 return mdiobus_get_phy(ds->user_mii_bus, port); 1192 } 1193 1194 void b53_get_strings(struct dsa_switch *ds, int port, u32 stringset, 1195 uint8_t *data) 1196 { 1197 struct b53_device *dev = ds->priv; 1198 const struct b53_mib_desc *mibs = b53_get_mib(dev); 1199 unsigned int mib_size = b53_get_mib_size(dev); 1200 struct phy_device *phydev; 1201 unsigned int i; 1202 1203 if (stringset == ETH_SS_STATS) { 1204 for (i = 0; i < mib_size; i++) 1205 ethtool_puts(&data, mibs[i].name); 1206 } else if (stringset == ETH_SS_PHY_STATS) { 1207 phydev = b53_get_phy_device(ds, port); 1208 if (!phydev) 1209 return; 1210 1211 phy_ethtool_get_strings(phydev, data); 1212 } 1213 } 1214 EXPORT_SYMBOL(b53_get_strings); 1215 1216 void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data) 1217 { 1218 struct b53_device *dev = ds->priv; 1219 const struct b53_mib_desc *mibs = b53_get_mib(dev); 1220 unsigned int mib_size = b53_get_mib_size(dev); 1221 const struct b53_mib_desc *s; 1222 unsigned int i; 1223 u64 val = 0; 1224 1225 if (is5365(dev) && port == 5) 1226 port = 8; 1227 1228 mutex_lock(&dev->stats_mutex); 1229 1230 for (i = 0; i < mib_size; i++) { 1231 s = &mibs[i]; 1232 1233 if (s->size == 8) { 1234 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val); 1235 } else { 1236 u32 val32; 1237 1238 b53_read32(dev, B53_MIB_PAGE(port), s->offset, 1239 &val32); 1240 val = val32; 1241 } 1242 data[i] = (u64)val; 1243 } 1244 1245 mutex_unlock(&dev->stats_mutex); 1246 } 1247 EXPORT_SYMBOL(b53_get_ethtool_stats); 1248 1249 void b53_get_ethtool_phy_stats(struct dsa_switch *ds, int port, uint64_t *data) 1250 { 1251 struct phy_device *phydev; 1252 1253 phydev = b53_get_phy_device(ds, port); 1254 if (!phydev) 1255 return; 1256 1257 phy_ethtool_get_stats(phydev, NULL, data); 1258 } 1259 EXPORT_SYMBOL(b53_get_ethtool_phy_stats); 1260 1261 int b53_get_sset_count(struct dsa_switch *ds, int port, int sset) 1262 { 1263 struct b53_device *dev = ds->priv; 1264 struct phy_device *phydev; 1265 1266 if (sset == ETH_SS_STATS) { 1267 return b53_get_mib_size(dev); 1268 } else if (sset == ETH_SS_PHY_STATS) { 1269 phydev = b53_get_phy_device(ds, port); 1270 if (!phydev) 1271 return 0; 1272 1273 return phy_ethtool_get_sset_count(phydev); 1274 } 1275 1276 return 0; 1277 } 1278 EXPORT_SYMBOL(b53_get_sset_count); 1279 1280 enum b53_devlink_resource_id { 1281 B53_DEVLINK_PARAM_ID_NONE, /* DEVLINK_RESOURCE_ID_PARENT_TOP */ 1282 B53_DEVLINK_PARAM_ID_VLAN_TABLE, 1283 }; 1284 1285 static u64 b53_devlink_vlan_table_get(void *priv) 1286 { 1287 struct b53_device *dev = priv; 1288 struct b53_vlan *vl; 1289 unsigned int i; 1290 u64 count = 0; 1291 1292 for (i = 0; i < dev->num_vlans; i++) { 1293 vl = &dev->vlans[i]; 1294 if (vl->members) 1295 count++; 1296 } 1297 1298 return count; 1299 } 1300 1301 int b53_setup_devlink_resources(struct dsa_switch *ds) 1302 { 1303 struct devlink_resource_size_params size_params; 1304 struct b53_device *dev = ds->priv; 1305 int err; 1306 1307 devlink_resource_size_params_init(&size_params, dev->num_vlans, 1308 dev->num_vlans, 1309 1, DEVLINK_RESOURCE_UNIT_ENTRY); 1310 1311 err = dsa_devlink_resource_register(ds, "VLAN", dev->num_vlans, 1312 B53_DEVLINK_PARAM_ID_VLAN_TABLE, 1313 DEVLINK_RESOURCE_ID_PARENT_TOP, 1314 &size_params); 1315 if (err) 1316 goto out; 1317 1318 dsa_devlink_resource_occ_get_register(ds, 1319 B53_DEVLINK_PARAM_ID_VLAN_TABLE, 1320 b53_devlink_vlan_table_get, dev); 1321 1322 return 0; 1323 out: 1324 dsa_devlink_resources_unregister(ds); 1325 return err; 1326 } 1327 EXPORT_SYMBOL(b53_setup_devlink_resources); 1328 1329 static int b53_setup(struct dsa_switch *ds) 1330 { 1331 struct b53_device *dev = ds->priv; 1332 struct b53_vlan *vl; 1333 unsigned int port; 1334 u16 pvid; 1335 int ret; 1336 1337 /* Request bridge PVID untagged when DSA_TAG_PROTO_NONE is set 1338 * which forces the CPU port to be tagged in all VLANs. 1339 */ 1340 ds->untag_bridge_pvid = dev->tag_protocol == DSA_TAG_PROTO_NONE; 1341 1342 /* The switch does not tell us the original VLAN for untagged 1343 * packets, so keep the CPU port always tagged. 1344 */ 1345 ds->untag_vlan_aware_bridge_pvid = true; 1346 1347 if (dev->chip_id == BCM53101_DEVICE_ID) { 1348 /* BCM53101 uses 0.5 second increments */ 1349 ds->ageing_time_min = 1 * 500; 1350 ds->ageing_time_max = AGE_TIME_MAX * 500; 1351 } else { 1352 /* Everything else uses 1 second increments */ 1353 ds->ageing_time_min = 1 * 1000; 1354 ds->ageing_time_max = AGE_TIME_MAX * 1000; 1355 } 1356 1357 ret = b53_reset_switch(dev); 1358 if (ret) { 1359 dev_err(ds->dev, "failed to reset switch\n"); 1360 return ret; 1361 } 1362 1363 /* setup default vlan for filtering mode */ 1364 pvid = b53_default_pvid(dev); 1365 vl = &dev->vlans[pvid]; 1366 b53_for_each_port(dev, port) { 1367 vl->members |= BIT(port); 1368 if (!b53_vlan_port_needs_forced_tagged(ds, port)) 1369 vl->untag |= BIT(port); 1370 } 1371 1372 b53_reset_mib(dev); 1373 1374 ret = b53_apply_config(dev); 1375 if (ret) { 1376 dev_err(ds->dev, "failed to apply configuration\n"); 1377 return ret; 1378 } 1379 1380 /* Configure IMP/CPU port, disable all other ports. Enabled 1381 * ports will be configured with .port_enable 1382 */ 1383 for (port = 0; port < dev->num_ports; port++) { 1384 if (dsa_is_cpu_port(ds, port)) 1385 b53_enable_cpu_port(dev, port); 1386 else 1387 b53_disable_port(ds, port); 1388 } 1389 1390 ret = b53_enable_mcast_snooping(dev); 1391 if (ret) 1392 return ret; 1393 1394 return b53_setup_devlink_resources(ds); 1395 } 1396 1397 static void b53_teardown(struct dsa_switch *ds) 1398 { 1399 dsa_devlink_resources_unregister(ds); 1400 } 1401 1402 static void b53_force_link(struct b53_device *dev, int port, int link) 1403 { 1404 u8 reg, val, off; 1405 1406 /* Override the port settings */ 1407 if (port == dev->imp_port) { 1408 off = B53_PORT_OVERRIDE_CTRL; 1409 val = PORT_OVERRIDE_EN; 1410 } else if (is5325(dev)) { 1411 return; 1412 } else { 1413 off = B53_GMII_PORT_OVERRIDE_CTRL(port); 1414 val = GMII_PO_EN; 1415 } 1416 1417 b53_read8(dev, B53_CTRL_PAGE, off, ®); 1418 reg |= val; 1419 if (link) 1420 reg |= PORT_OVERRIDE_LINK; 1421 else 1422 reg &= ~PORT_OVERRIDE_LINK; 1423 b53_write8(dev, B53_CTRL_PAGE, off, reg); 1424 } 1425 1426 static void b53_force_port_config(struct b53_device *dev, int port, 1427 int speed, int duplex, 1428 bool tx_pause, bool rx_pause) 1429 { 1430 u8 reg, val, off; 1431 1432 /* Override the port settings */ 1433 if (port == dev->imp_port) { 1434 off = B53_PORT_OVERRIDE_CTRL; 1435 val = PORT_OVERRIDE_EN; 1436 } else if (is5325(dev)) { 1437 return; 1438 } else { 1439 off = B53_GMII_PORT_OVERRIDE_CTRL(port); 1440 val = GMII_PO_EN; 1441 } 1442 1443 b53_read8(dev, B53_CTRL_PAGE, off, ®); 1444 reg |= val; 1445 if (duplex == DUPLEX_FULL) 1446 reg |= PORT_OVERRIDE_FULL_DUPLEX; 1447 else 1448 reg &= ~PORT_OVERRIDE_FULL_DUPLEX; 1449 1450 reg &= ~(0x3 << GMII_PO_SPEED_S); 1451 if (is5301x(dev) || is58xx(dev)) 1452 reg &= ~PORT_OVERRIDE_SPEED_2000M; 1453 1454 switch (speed) { 1455 case 2000: 1456 reg |= PORT_OVERRIDE_SPEED_2000M; 1457 fallthrough; 1458 case SPEED_1000: 1459 reg |= PORT_OVERRIDE_SPEED_1000M; 1460 break; 1461 case SPEED_100: 1462 reg |= PORT_OVERRIDE_SPEED_100M; 1463 break; 1464 case SPEED_10: 1465 reg |= PORT_OVERRIDE_SPEED_10M; 1466 break; 1467 default: 1468 dev_err(dev->dev, "unknown speed: %d\n", speed); 1469 return; 1470 } 1471 1472 if (is5325(dev)) 1473 reg &= ~PORT_OVERRIDE_LP_FLOW_25; 1474 else 1475 reg &= ~(PORT_OVERRIDE_RX_FLOW | PORT_OVERRIDE_TX_FLOW); 1476 1477 if (rx_pause) { 1478 if (is5325(dev)) 1479 reg |= PORT_OVERRIDE_LP_FLOW_25; 1480 else 1481 reg |= PORT_OVERRIDE_RX_FLOW; 1482 } 1483 1484 if (tx_pause) { 1485 if (is5325(dev)) 1486 reg |= PORT_OVERRIDE_LP_FLOW_25; 1487 else 1488 reg |= PORT_OVERRIDE_TX_FLOW; 1489 } 1490 1491 b53_write8(dev, B53_CTRL_PAGE, off, reg); 1492 } 1493 1494 static void b53_adjust_63xx_rgmii(struct dsa_switch *ds, int port, 1495 phy_interface_t interface) 1496 { 1497 struct b53_device *dev = ds->priv; 1498 u8 rgmii_ctrl = 0; 1499 1500 b53_read8(dev, B53_CTRL_PAGE, B53_RGMII_CTRL_P(port), &rgmii_ctrl); 1501 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC); 1502 1503 if (is6318_268(dev)) 1504 rgmii_ctrl |= RGMII_CTRL_MII_OVERRIDE; 1505 1506 rgmii_ctrl |= RGMII_CTRL_ENABLE_GMII; 1507 1508 b53_write8(dev, B53_CTRL_PAGE, B53_RGMII_CTRL_P(port), rgmii_ctrl); 1509 1510 dev_dbg(ds->dev, "Configured port %d for %s\n", port, 1511 phy_modes(interface)); 1512 } 1513 1514 static void b53_adjust_531x5_rgmii(struct dsa_switch *ds, int port, 1515 phy_interface_t interface) 1516 { 1517 struct b53_device *dev = ds->priv; 1518 u8 rgmii_ctrl = 0, off; 1519 1520 if (port == dev->imp_port) 1521 off = B53_RGMII_CTRL_IMP; 1522 else 1523 off = B53_RGMII_CTRL_P(port); 1524 1525 /* Configure the port RGMII clock delay by DLL disabled and 1526 * tx_clk aligned timing (restoring to reset defaults) 1527 */ 1528 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl); 1529 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC); 1530 1531 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make 1532 * sure that we enable the port TX clock internal delay to 1533 * account for this internal delay that is inserted, otherwise 1534 * the switch won't be able to receive correctly. 1535 * 1536 * PHY_INTERFACE_MODE_RGMII means that we are not introducing 1537 * any delay neither on transmission nor reception, so the 1538 * BCM53125 must also be configured accordingly to account for 1539 * the lack of delay and introduce 1540 * 1541 * The BCM53125 switch has its RX clock and TX clock control 1542 * swapped, hence the reason why we modify the TX clock path in 1543 * the "RGMII" case 1544 */ 1545 if (interface == PHY_INTERFACE_MODE_RGMII_TXID) 1546 rgmii_ctrl |= RGMII_CTRL_DLL_TXC; 1547 if (interface == PHY_INTERFACE_MODE_RGMII) 1548 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC; 1549 1550 if (dev->chip_id != BCM53115_DEVICE_ID) 1551 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL; 1552 1553 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl); 1554 1555 dev_info(ds->dev, "Configured port %d for %s\n", port, 1556 phy_modes(interface)); 1557 } 1558 1559 static void b53_adjust_5325_mii(struct dsa_switch *ds, int port) 1560 { 1561 struct b53_device *dev = ds->priv; 1562 u8 reg = 0; 1563 1564 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1565 ®); 1566 1567 /* reverse mii needs to be enabled */ 1568 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 1569 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1570 reg | PORT_OVERRIDE_RV_MII_25); 1571 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1572 ®); 1573 1574 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 1575 dev_err(ds->dev, 1576 "Failed to enable reverse MII mode\n"); 1577 return; 1578 } 1579 } 1580 } 1581 1582 void b53_port_event(struct dsa_switch *ds, int port) 1583 { 1584 struct b53_device *dev = ds->priv; 1585 bool link; 1586 u16 sts; 1587 1588 b53_read16(dev, B53_STAT_PAGE, B53_LINK_STAT, &sts); 1589 link = !!(sts & BIT(port)); 1590 dsa_port_phylink_mac_change(ds, port, link); 1591 } 1592 EXPORT_SYMBOL(b53_port_event); 1593 1594 static void b53_phylink_get_caps(struct dsa_switch *ds, int port, 1595 struct phylink_config *config) 1596 { 1597 struct b53_device *dev = ds->priv; 1598 1599 /* Internal ports need GMII for PHYLIB */ 1600 __set_bit(PHY_INTERFACE_MODE_GMII, config->supported_interfaces); 1601 1602 /* These switches appear to support MII and RevMII too, but beyond 1603 * this, the code gives very few clues. FIXME: We probably need more 1604 * interface modes here. 1605 * 1606 * According to b53_srab_mux_init(), ports 3..5 can support: 1607 * SGMII, MII, GMII, RGMII or INTERNAL depending on the MUX setting. 1608 * However, the interface mode read from the MUX configuration is 1609 * not passed back to DSA, so phylink uses NA. 1610 * DT can specify RGMII for ports 0, 1. 1611 * For MDIO, port 8 can be RGMII_TXID. 1612 */ 1613 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 1614 __set_bit(PHY_INTERFACE_MODE_REVMII, config->supported_interfaces); 1615 1616 /* BCM63xx RGMII ports support RGMII */ 1617 if (is63xx(dev) && in_range(port, B53_63XX_RGMII0, 4)) 1618 phy_interface_set_rgmii(config->supported_interfaces); 1619 1620 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 1621 MAC_10 | MAC_100; 1622 1623 /* 5325/5365 are not capable of gigabit speeds, everything else is. 1624 * Note: the original code also exclulded Gigagbit for MII, RevMII 1625 * and 802.3z modes. MII and RevMII are not able to work above 100M, 1626 * so will be excluded by the generic validator implementation. 1627 * However, the exclusion of Gigabit for 802.3z just seems wrong. 1628 */ 1629 if (!(is5325(dev) || is5365(dev))) 1630 config->mac_capabilities |= MAC_1000; 1631 1632 /* Get the implementation specific capabilities */ 1633 if (dev->ops->phylink_get_caps) 1634 dev->ops->phylink_get_caps(dev, port, config); 1635 } 1636 1637 static struct phylink_pcs *b53_phylink_mac_select_pcs(struct phylink_config *config, 1638 phy_interface_t interface) 1639 { 1640 struct dsa_port *dp = dsa_phylink_to_port(config); 1641 struct b53_device *dev = dp->ds->priv; 1642 1643 if (!dev->ops->phylink_mac_select_pcs) 1644 return NULL; 1645 1646 return dev->ops->phylink_mac_select_pcs(dev, dp->index, interface); 1647 } 1648 1649 static void b53_phylink_mac_config(struct phylink_config *config, 1650 unsigned int mode, 1651 const struct phylink_link_state *state) 1652 { 1653 struct dsa_port *dp = dsa_phylink_to_port(config); 1654 phy_interface_t interface = state->interface; 1655 struct dsa_switch *ds = dp->ds; 1656 struct b53_device *dev = ds->priv; 1657 int port = dp->index; 1658 1659 if (is63xx(dev) && in_range(port, B53_63XX_RGMII0, 4)) 1660 b53_adjust_63xx_rgmii(ds, port, interface); 1661 1662 if (mode == MLO_AN_FIXED) { 1663 if (is531x5(dev) && phy_interface_mode_is_rgmii(interface)) 1664 b53_adjust_531x5_rgmii(ds, port, interface); 1665 1666 /* configure MII port if necessary */ 1667 if (is5325(dev)) 1668 b53_adjust_5325_mii(ds, port); 1669 } 1670 } 1671 1672 static void b53_phylink_mac_link_down(struct phylink_config *config, 1673 unsigned int mode, 1674 phy_interface_t interface) 1675 { 1676 struct dsa_port *dp = dsa_phylink_to_port(config); 1677 struct b53_device *dev = dp->ds->priv; 1678 int port = dp->index; 1679 1680 if (mode == MLO_AN_PHY) { 1681 if (is63xx(dev) && in_range(port, B53_63XX_RGMII0, 4)) 1682 b53_force_link(dev, port, false); 1683 return; 1684 } 1685 1686 if (mode == MLO_AN_FIXED) { 1687 b53_force_link(dev, port, false); 1688 return; 1689 } 1690 1691 if (phy_interface_mode_is_8023z(interface) && 1692 dev->ops->serdes_link_set) 1693 dev->ops->serdes_link_set(dev, port, mode, interface, false); 1694 } 1695 1696 static void b53_phylink_mac_link_up(struct phylink_config *config, 1697 struct phy_device *phydev, 1698 unsigned int mode, 1699 phy_interface_t interface, 1700 int speed, int duplex, 1701 bool tx_pause, bool rx_pause) 1702 { 1703 struct dsa_port *dp = dsa_phylink_to_port(config); 1704 struct dsa_switch *ds = dp->ds; 1705 struct b53_device *dev = ds->priv; 1706 struct ethtool_keee *p = &dev->ports[dp->index].eee; 1707 int port = dp->index; 1708 1709 if (mode == MLO_AN_PHY) { 1710 /* Re-negotiate EEE if it was enabled already */ 1711 p->eee_enabled = b53_eee_init(ds, port, phydev); 1712 1713 if (is63xx(dev) && in_range(port, B53_63XX_RGMII0, 4)) { 1714 b53_force_port_config(dev, port, speed, duplex, 1715 tx_pause, rx_pause); 1716 b53_force_link(dev, port, true); 1717 } 1718 1719 return; 1720 } 1721 1722 if (mode == MLO_AN_FIXED) { 1723 /* Force flow control and 2Gbits/sec on BCM5301x and NSP CPU 1724 * ports 1725 */ 1726 if ((is5301x(dev) || dev->chip_id == BCM58XX_DEVICE_ID) && 1727 dsa_is_cpu_port(ds, port)) { 1728 tx_pause = true; 1729 rx_pause = true; 1730 speed = 2000; 1731 } 1732 1733 b53_force_port_config(dev, port, speed, duplex, 1734 tx_pause, rx_pause); 1735 b53_force_link(dev, port, true); 1736 return; 1737 } 1738 1739 if (phy_interface_mode_is_8023z(interface) && 1740 dev->ops->serdes_link_set) 1741 dev->ops->serdes_link_set(dev, port, mode, interface, true); 1742 } 1743 1744 int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, 1745 struct netlink_ext_ack *extack) 1746 { 1747 struct b53_device *dev = ds->priv; 1748 1749 if (dev->vlan_filtering != vlan_filtering) { 1750 dev->vlan_filtering = vlan_filtering; 1751 b53_apply_config(dev); 1752 } 1753 1754 return 0; 1755 } 1756 EXPORT_SYMBOL(b53_vlan_filtering); 1757 1758 static int b53_vlan_prepare(struct dsa_switch *ds, int port, 1759 const struct switchdev_obj_port_vlan *vlan) 1760 { 1761 struct b53_device *dev = ds->priv; 1762 1763 /* Port 7 on 7278 connects to the ASP's UniMAC which is not capable of 1764 * receiving VLAN tagged frames at all, we can still allow the port to 1765 * be configured for egress untagged. 1766 */ 1767 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7 && 1768 !(vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)) 1769 return -EINVAL; 1770 1771 if (vlan->vid >= dev->num_vlans) 1772 return -ERANGE; 1773 1774 b53_enable_vlan(dev, port, true, dev->vlan_filtering); 1775 1776 return 0; 1777 } 1778 1779 int b53_vlan_add(struct dsa_switch *ds, int port, 1780 const struct switchdev_obj_port_vlan *vlan, 1781 struct netlink_ext_ack *extack) 1782 { 1783 struct b53_device *dev = ds->priv; 1784 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1785 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1786 struct b53_vlan *vl; 1787 u16 old_pvid, new_pvid; 1788 int err; 1789 1790 err = b53_vlan_prepare(ds, port, vlan); 1791 if (err) 1792 return err; 1793 1794 if (vlan->vid == 0) 1795 return 0; 1796 1797 old_pvid = dev->ports[port].pvid; 1798 if (pvid) 1799 new_pvid = vlan->vid; 1800 else if (!pvid && vlan->vid == old_pvid) 1801 new_pvid = b53_default_pvid(dev); 1802 else 1803 new_pvid = old_pvid; 1804 dev->ports[port].pvid = new_pvid; 1805 1806 vl = &dev->vlans[vlan->vid]; 1807 1808 if (dsa_is_cpu_port(ds, port)) 1809 untagged = false; 1810 1811 vl->members |= BIT(port); 1812 if (untagged && !b53_vlan_port_needs_forced_tagged(ds, port)) 1813 vl->untag |= BIT(port); 1814 else 1815 vl->untag &= ~BIT(port); 1816 1817 if (!dev->vlan_filtering) 1818 return 0; 1819 1820 b53_set_vlan_entry(dev, vlan->vid, vl); 1821 b53_fast_age_vlan(dev, vlan->vid); 1822 1823 if (!dsa_is_cpu_port(ds, port) && new_pvid != old_pvid) { 1824 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), 1825 new_pvid); 1826 b53_fast_age_vlan(dev, old_pvid); 1827 } 1828 1829 return 0; 1830 } 1831 EXPORT_SYMBOL(b53_vlan_add); 1832 1833 int b53_vlan_del(struct dsa_switch *ds, int port, 1834 const struct switchdev_obj_port_vlan *vlan) 1835 { 1836 struct b53_device *dev = ds->priv; 1837 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1838 struct b53_vlan *vl; 1839 u16 pvid; 1840 1841 if (vlan->vid == 0) 1842 return 0; 1843 1844 pvid = dev->ports[port].pvid; 1845 1846 vl = &dev->vlans[vlan->vid]; 1847 1848 vl->members &= ~BIT(port); 1849 1850 if (pvid == vlan->vid) 1851 pvid = b53_default_pvid(dev); 1852 dev->ports[port].pvid = pvid; 1853 1854 if (untagged && !b53_vlan_port_needs_forced_tagged(ds, port)) 1855 vl->untag &= ~(BIT(port)); 1856 1857 if (!dev->vlan_filtering) 1858 return 0; 1859 1860 b53_set_vlan_entry(dev, vlan->vid, vl); 1861 b53_fast_age_vlan(dev, vlan->vid); 1862 1863 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid); 1864 b53_fast_age_vlan(dev, pvid); 1865 1866 return 0; 1867 } 1868 EXPORT_SYMBOL(b53_vlan_del); 1869 1870 /* Address Resolution Logic routines. Caller must hold &dev->arl_mutex. */ 1871 static int b53_arl_op_wait(struct b53_device *dev) 1872 { 1873 unsigned int timeout = 10; 1874 u8 reg; 1875 1876 do { 1877 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1878 if (!(reg & ARLTBL_START_DONE)) 1879 return 0; 1880 1881 usleep_range(1000, 2000); 1882 } while (timeout--); 1883 1884 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg); 1885 1886 return -ETIMEDOUT; 1887 } 1888 1889 static int b53_arl_rw_op(struct b53_device *dev, unsigned int op) 1890 { 1891 u8 reg; 1892 1893 if (op > ARLTBL_RW) 1894 return -EINVAL; 1895 1896 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1897 reg |= ARLTBL_START_DONE; 1898 if (op) 1899 reg |= ARLTBL_RW; 1900 else 1901 reg &= ~ARLTBL_RW; 1902 if (dev->vlan_enabled) 1903 reg &= ~ARLTBL_IVL_SVL_SELECT; 1904 else 1905 reg |= ARLTBL_IVL_SVL_SELECT; 1906 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg); 1907 1908 return b53_arl_op_wait(dev); 1909 } 1910 1911 static void b53_arl_read_entry_25(struct b53_device *dev, 1912 struct b53_arl_entry *ent, u8 idx) 1913 { 1914 u8 vid_entry; 1915 u64 mac_vid; 1916 1917 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_VID_ENTRY_25(idx), 1918 &vid_entry); 1919 b53_read64(dev, B53_ARLIO_PAGE, B53_ARLTBL_MAC_VID_ENTRY(idx), 1920 &mac_vid); 1921 b53_arl_to_entry_25(ent, mac_vid, vid_entry); 1922 } 1923 1924 static void b53_arl_write_entry_25(struct b53_device *dev, 1925 const struct b53_arl_entry *ent, u8 idx) 1926 { 1927 u8 vid_entry; 1928 u64 mac_vid; 1929 1930 b53_arl_from_entry_25(&mac_vid, &vid_entry, ent); 1931 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_VID_ENTRY_25(idx), vid_entry); 1932 b53_write64(dev, B53_ARLIO_PAGE, B53_ARLTBL_MAC_VID_ENTRY(idx), 1933 mac_vid); 1934 } 1935 1936 static void b53_arl_read_entry_89(struct b53_device *dev, 1937 struct b53_arl_entry *ent, u8 idx) 1938 { 1939 u64 mac_vid; 1940 u16 fwd_entry; 1941 1942 b53_read64(dev, B53_ARLIO_PAGE, B53_ARLTBL_MAC_VID_ENTRY(idx), 1943 &mac_vid); 1944 b53_read16(dev, B53_ARLIO_PAGE, B53_ARLTBL_DATA_ENTRY(idx), &fwd_entry); 1945 b53_arl_to_entry_89(ent, mac_vid, fwd_entry); 1946 } 1947 1948 static void b53_arl_write_entry_89(struct b53_device *dev, 1949 const struct b53_arl_entry *ent, u8 idx) 1950 { 1951 u32 fwd_entry; 1952 u64 mac_vid; 1953 1954 b53_arl_from_entry_89(&mac_vid, &fwd_entry, ent); 1955 b53_write64(dev, B53_ARLIO_PAGE, 1956 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid); 1957 b53_write16(dev, B53_ARLIO_PAGE, 1958 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry); 1959 } 1960 1961 static void b53_arl_read_entry_95(struct b53_device *dev, 1962 struct b53_arl_entry *ent, u8 idx) 1963 { 1964 u32 fwd_entry; 1965 u64 mac_vid; 1966 1967 b53_read64(dev, B53_ARLIO_PAGE, B53_ARLTBL_MAC_VID_ENTRY(idx), 1968 &mac_vid); 1969 b53_read32(dev, B53_ARLIO_PAGE, B53_ARLTBL_DATA_ENTRY(idx), &fwd_entry); 1970 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1971 } 1972 1973 static void b53_arl_write_entry_95(struct b53_device *dev, 1974 const struct b53_arl_entry *ent, u8 idx) 1975 { 1976 u32 fwd_entry; 1977 u64 mac_vid; 1978 1979 b53_arl_from_entry(&mac_vid, &fwd_entry, ent); 1980 b53_write64(dev, B53_ARLIO_PAGE, B53_ARLTBL_MAC_VID_ENTRY(idx), 1981 mac_vid); 1982 b53_write32(dev, B53_ARLIO_PAGE, B53_ARLTBL_DATA_ENTRY(idx), 1983 fwd_entry); 1984 } 1985 1986 static int b53_arl_read(struct b53_device *dev, const u8 *mac, 1987 u16 vid, struct b53_arl_entry *ent, u8 *idx) 1988 { 1989 DECLARE_BITMAP(free_bins, B53_ARLTBL_MAX_BIN_ENTRIES); 1990 unsigned int i; 1991 int ret; 1992 1993 ret = b53_arl_op_wait(dev); 1994 if (ret) 1995 return ret; 1996 1997 bitmap_zero(free_bins, dev->num_arl_bins); 1998 1999 /* Read the bins */ 2000 for (i = 0; i < dev->num_arl_bins; i++) { 2001 b53_arl_read_entry(dev, ent, i); 2002 2003 if (!ent->is_valid) { 2004 set_bit(i, free_bins); 2005 continue; 2006 } 2007 if (!ether_addr_equal(ent->mac, mac)) 2008 continue; 2009 if (dev->vlan_enabled && ent->vid != vid) 2010 continue; 2011 *idx = i; 2012 return 0; 2013 } 2014 2015 *idx = find_first_bit(free_bins, dev->num_arl_bins); 2016 return *idx >= dev->num_arl_bins ? -ENOSPC : -ENOENT; 2017 } 2018 2019 static int b53_arl_op(struct b53_device *dev, int op, int port, 2020 const unsigned char *addr, u16 vid, bool is_valid) 2021 { 2022 struct b53_arl_entry ent; 2023 u8 idx = 0; 2024 u64 mac; 2025 int ret; 2026 2027 /* Convert the array into a 64-bit MAC */ 2028 mac = ether_addr_to_u64(addr); 2029 2030 /* Perform a read for the given MAC and VID */ 2031 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac); 2032 if (!is5325m(dev)) { 2033 if (is5325(dev) || is5365(dev)) 2034 b53_write8(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid); 2035 else 2036 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid); 2037 } 2038 2039 /* Issue a read operation for this MAC */ 2040 ret = b53_arl_rw_op(dev, 1); 2041 if (ret) 2042 return ret; 2043 2044 ret = b53_arl_read(dev, addr, vid, &ent, &idx); 2045 2046 /* If this is a read, just finish now */ 2047 if (op) 2048 return ret; 2049 2050 switch (ret) { 2051 case -ETIMEDOUT: 2052 return ret; 2053 case -ENOSPC: 2054 dev_dbg(dev->dev, "{%pM,%.4d} no space left in ARL\n", 2055 addr, vid); 2056 return is_valid ? ret : 0; 2057 case -ENOENT: 2058 /* We could not find a matching MAC, so reset to a new entry */ 2059 dev_dbg(dev->dev, "{%pM,%.4d} not found, using idx: %d\n", 2060 addr, vid, idx); 2061 break; 2062 default: 2063 dev_dbg(dev->dev, "{%pM,%.4d} found, using idx: %d\n", 2064 addr, vid, idx); 2065 break; 2066 } 2067 2068 /* For multicast address, the port is a bitmask and the validity 2069 * is determined by having at least one port being still active 2070 */ 2071 if (!is_multicast_ether_addr(addr)) { 2072 ent.port = port; 2073 ent.is_valid = is_valid; 2074 } else { 2075 if (is_valid) 2076 ent.port |= BIT(port); 2077 else 2078 ent.port &= ~BIT(port); 2079 2080 ent.is_valid = !!(ent.port); 2081 } 2082 2083 ent.vid = vid; 2084 ent.is_static = true; 2085 ent.is_age = false; 2086 memcpy(ent.mac, addr, ETH_ALEN); 2087 b53_arl_write_entry(dev, &ent, idx); 2088 2089 return b53_arl_rw_op(dev, 0); 2090 } 2091 2092 int b53_fdb_add(struct dsa_switch *ds, int port, 2093 const unsigned char *addr, u16 vid, 2094 struct dsa_db db) 2095 { 2096 struct b53_device *priv = ds->priv; 2097 int ret; 2098 2099 mutex_lock(&priv->arl_mutex); 2100 ret = b53_arl_op(priv, 0, port, addr, vid, true); 2101 mutex_unlock(&priv->arl_mutex); 2102 2103 return ret; 2104 } 2105 EXPORT_SYMBOL(b53_fdb_add); 2106 2107 int b53_fdb_del(struct dsa_switch *ds, int port, 2108 const unsigned char *addr, u16 vid, 2109 struct dsa_db db) 2110 { 2111 struct b53_device *priv = ds->priv; 2112 int ret; 2113 2114 mutex_lock(&priv->arl_mutex); 2115 ret = b53_arl_op(priv, 0, port, addr, vid, false); 2116 mutex_unlock(&priv->arl_mutex); 2117 2118 return ret; 2119 } 2120 EXPORT_SYMBOL(b53_fdb_del); 2121 2122 static void b53_read_arl_srch_ctl(struct b53_device *dev, u8 *val) 2123 { 2124 u8 offset; 2125 2126 if (is5325(dev) || is5365(dev)) 2127 offset = B53_ARL_SRCH_CTL_25; 2128 else if (dev->chip_id == BCM5389_DEVICE_ID || is5397_98(dev) || 2129 is63xx(dev)) 2130 offset = B53_ARL_SRCH_CTL_89; 2131 else 2132 offset = B53_ARL_SRCH_CTL; 2133 2134 if (is63xx(dev)) { 2135 u16 val16; 2136 2137 b53_read16(dev, B53_ARLIO_PAGE, offset, &val16); 2138 *val = val16 & 0xff; 2139 } else { 2140 b53_read8(dev, B53_ARLIO_PAGE, offset, val); 2141 } 2142 } 2143 2144 static void b53_write_arl_srch_ctl(struct b53_device *dev, u8 val) 2145 { 2146 u8 offset; 2147 2148 if (is5325(dev) || is5365(dev)) 2149 offset = B53_ARL_SRCH_CTL_25; 2150 else if (dev->chip_id == BCM5389_DEVICE_ID || is5397_98(dev) || 2151 is63xx(dev)) 2152 offset = B53_ARL_SRCH_CTL_89; 2153 else 2154 offset = B53_ARL_SRCH_CTL; 2155 2156 if (is63xx(dev)) 2157 b53_write16(dev, B53_ARLIO_PAGE, offset, val); 2158 else 2159 b53_write8(dev, B53_ARLIO_PAGE, offset, val); 2160 } 2161 2162 static int b53_arl_search_wait(struct b53_device *dev) 2163 { 2164 unsigned int timeout = 1000; 2165 u8 reg; 2166 2167 do { 2168 b53_read_arl_srch_ctl(dev, ®); 2169 if (!(reg & ARL_SRCH_STDN)) 2170 return -ENOENT; 2171 2172 if (reg & ARL_SRCH_VLID) 2173 return 0; 2174 2175 usleep_range(1000, 2000); 2176 } while (timeout--); 2177 2178 return -ETIMEDOUT; 2179 } 2180 2181 static void b53_arl_search_read_25(struct b53_device *dev, u8 idx, 2182 struct b53_arl_entry *ent) 2183 { 2184 u64 mac_vid; 2185 u8 ext; 2186 2187 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_RSLT_EXT_25, &ext); 2188 b53_read64(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_RSTL_0_MACVID_25, 2189 &mac_vid); 2190 b53_arl_search_to_entry_25(ent, mac_vid, ext); 2191 } 2192 2193 static void b53_arl_search_read_89(struct b53_device *dev, u8 idx, 2194 struct b53_arl_entry *ent) 2195 { 2196 u16 fwd_entry; 2197 u64 mac_vid; 2198 2199 b53_read64(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_RSLT_MACVID_89, 2200 &mac_vid); 2201 b53_read16(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_RSLT_89, &fwd_entry); 2202 b53_arl_to_entry_89(ent, mac_vid, fwd_entry); 2203 } 2204 2205 static void b53_arl_search_read_63xx(struct b53_device *dev, u8 idx, 2206 struct b53_arl_entry *ent) 2207 { 2208 u16 fwd_entry; 2209 u64 mac_vid; 2210 2211 b53_read64(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_RSLT_MACVID_63XX, 2212 &mac_vid); 2213 b53_read16(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_RSLT_63XX, &fwd_entry); 2214 b53_arl_search_to_entry_63xx(ent, mac_vid, fwd_entry); 2215 } 2216 2217 static void b53_arl_search_read_95(struct b53_device *dev, u8 idx, 2218 struct b53_arl_entry *ent) 2219 { 2220 u32 fwd_entry; 2221 u64 mac_vid; 2222 2223 b53_read64(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_RSTL_MACVID(idx), 2224 &mac_vid); 2225 b53_read32(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_RSTL(idx), 2226 &fwd_entry); 2227 b53_arl_to_entry(ent, mac_vid, fwd_entry); 2228 } 2229 2230 static int b53_fdb_copy(int port, const struct b53_arl_entry *ent, 2231 dsa_fdb_dump_cb_t *cb, void *data) 2232 { 2233 if (!ent->is_valid) 2234 return 0; 2235 2236 if (is_multicast_ether_addr(ent->mac)) 2237 return 0; 2238 2239 if (port != ent->port) 2240 return 0; 2241 2242 return cb(ent->mac, ent->vid, ent->is_static, data); 2243 } 2244 2245 int b53_fdb_dump(struct dsa_switch *ds, int port, 2246 dsa_fdb_dump_cb_t *cb, void *data) 2247 { 2248 unsigned int count = 0, results_per_hit = 1; 2249 struct b53_device *priv = ds->priv; 2250 struct b53_arl_entry results[2]; 2251 int ret; 2252 2253 if (priv->num_arl_bins > 2) 2254 results_per_hit = 2; 2255 2256 mutex_lock(&priv->arl_mutex); 2257 2258 /* Start search operation */ 2259 b53_write_arl_srch_ctl(priv, ARL_SRCH_STDN); 2260 2261 do { 2262 ret = b53_arl_search_wait(priv); 2263 if (ret) 2264 break; 2265 2266 b53_arl_search_read(priv, 0, &results[0]); 2267 ret = b53_fdb_copy(port, &results[0], cb, data); 2268 if (ret) 2269 break; 2270 2271 if (results_per_hit == 2) { 2272 b53_arl_search_read(priv, 1, &results[1]); 2273 ret = b53_fdb_copy(port, &results[1], cb, data); 2274 if (ret) 2275 break; 2276 2277 if (!results[0].is_valid && !results[1].is_valid) 2278 break; 2279 } 2280 2281 } while (count++ < b53_max_arl_entries(priv) / results_per_hit); 2282 2283 mutex_unlock(&priv->arl_mutex); 2284 2285 return ret; 2286 } 2287 EXPORT_SYMBOL(b53_fdb_dump); 2288 2289 int b53_mdb_add(struct dsa_switch *ds, int port, 2290 const struct switchdev_obj_port_mdb *mdb, 2291 struct dsa_db db) 2292 { 2293 struct b53_device *priv = ds->priv; 2294 int ret; 2295 2296 /* 5325 and 5365 require some more massaging, but could 2297 * be supported eventually 2298 */ 2299 if (is5325(priv) || is5365(priv)) 2300 return -EOPNOTSUPP; 2301 2302 mutex_lock(&priv->arl_mutex); 2303 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, true); 2304 mutex_unlock(&priv->arl_mutex); 2305 2306 return ret; 2307 } 2308 EXPORT_SYMBOL(b53_mdb_add); 2309 2310 int b53_mdb_del(struct dsa_switch *ds, int port, 2311 const struct switchdev_obj_port_mdb *mdb, 2312 struct dsa_db db) 2313 { 2314 struct b53_device *priv = ds->priv; 2315 int ret; 2316 2317 mutex_lock(&priv->arl_mutex); 2318 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, false); 2319 mutex_unlock(&priv->arl_mutex); 2320 if (ret) 2321 dev_err(ds->dev, "failed to delete MDB entry\n"); 2322 2323 return ret; 2324 } 2325 EXPORT_SYMBOL(b53_mdb_del); 2326 2327 int b53_br_join(struct dsa_switch *ds, int port, struct dsa_bridge bridge, 2328 bool *tx_fwd_offload, struct netlink_ext_ack *extack) 2329 { 2330 struct b53_device *dev = ds->priv; 2331 struct b53_vlan *vl; 2332 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 2333 u16 pvlan, reg, pvid; 2334 unsigned int i; 2335 2336 /* On 7278, port 7 which connects to the ASP should only receive 2337 * traffic from matching CFP rules. 2338 */ 2339 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7) 2340 return -EINVAL; 2341 2342 pvid = b53_default_pvid(dev); 2343 vl = &dev->vlans[pvid]; 2344 2345 if (dev->vlan_filtering) { 2346 /* Make this port leave the all VLANs join since we will have 2347 * proper VLAN entries from now on 2348 */ 2349 if (is58xx(dev)) { 2350 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, 2351 ®); 2352 reg &= ~BIT(port); 2353 if ((reg & BIT(cpu_port)) == BIT(cpu_port)) 2354 reg &= ~BIT(cpu_port); 2355 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, 2356 reg); 2357 } 2358 2359 b53_get_vlan_entry(dev, pvid, vl); 2360 vl->members &= ~BIT(port); 2361 b53_set_vlan_entry(dev, pvid, vl); 2362 } 2363 2364 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 2365 2366 b53_for_each_port(dev, i) { 2367 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge)) 2368 continue; 2369 2370 /* Add this local port to the remote port VLAN control 2371 * membership and update the remote port bitmask 2372 */ 2373 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 2374 reg |= BIT(port); 2375 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 2376 dev->ports[i].vlan_ctl_mask = reg; 2377 2378 pvlan |= BIT(i); 2379 } 2380 2381 /* Disable redirection of unknown SA to the CPU port */ 2382 b53_set_eap_mode(dev, port, EAP_MODE_BASIC); 2383 2384 /* Configure the local port VLAN control membership to include 2385 * remote ports and update the local port bitmask 2386 */ 2387 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 2388 dev->ports[port].vlan_ctl_mask = pvlan; 2389 2390 return 0; 2391 } 2392 EXPORT_SYMBOL(b53_br_join); 2393 2394 void b53_br_leave(struct dsa_switch *ds, int port, struct dsa_bridge bridge) 2395 { 2396 struct b53_device *dev = ds->priv; 2397 struct b53_vlan *vl; 2398 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 2399 unsigned int i; 2400 u16 pvlan, reg, pvid; 2401 2402 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 2403 2404 b53_for_each_port(dev, i) { 2405 /* Don't touch the remaining ports */ 2406 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge)) 2407 continue; 2408 2409 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 2410 reg &= ~BIT(port); 2411 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 2412 dev->ports[port].vlan_ctl_mask = reg; 2413 2414 /* Prevent self removal to preserve isolation */ 2415 if (port != i) 2416 pvlan &= ~BIT(i); 2417 } 2418 2419 /* Enable redirection of unknown SA to the CPU port */ 2420 b53_set_eap_mode(dev, port, EAP_MODE_SIMPLIFIED); 2421 2422 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 2423 dev->ports[port].vlan_ctl_mask = pvlan; 2424 2425 pvid = b53_default_pvid(dev); 2426 vl = &dev->vlans[pvid]; 2427 2428 if (dev->vlan_filtering) { 2429 /* Make this port join all VLANs without VLAN entries */ 2430 if (is58xx(dev)) { 2431 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); 2432 reg |= BIT(port); 2433 if (!(reg & BIT(cpu_port))) 2434 reg |= BIT(cpu_port); 2435 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); 2436 } 2437 2438 b53_get_vlan_entry(dev, pvid, vl); 2439 vl->members |= BIT(port); 2440 b53_set_vlan_entry(dev, pvid, vl); 2441 } 2442 } 2443 EXPORT_SYMBOL(b53_br_leave); 2444 2445 void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state) 2446 { 2447 struct b53_device *dev = ds->priv; 2448 u8 hw_state; 2449 u8 reg; 2450 2451 switch (state) { 2452 case BR_STATE_DISABLED: 2453 hw_state = PORT_CTRL_DIS_STATE; 2454 break; 2455 case BR_STATE_LISTENING: 2456 hw_state = PORT_CTRL_LISTEN_STATE; 2457 break; 2458 case BR_STATE_LEARNING: 2459 hw_state = PORT_CTRL_LEARN_STATE; 2460 break; 2461 case BR_STATE_FORWARDING: 2462 hw_state = PORT_CTRL_FWD_STATE; 2463 break; 2464 case BR_STATE_BLOCKING: 2465 hw_state = PORT_CTRL_BLOCK_STATE; 2466 break; 2467 default: 2468 dev_err(ds->dev, "invalid STP state: %d\n", state); 2469 return; 2470 } 2471 2472 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 2473 reg &= ~PORT_CTRL_STP_STATE_MASK; 2474 reg |= hw_state; 2475 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 2476 } 2477 EXPORT_SYMBOL(b53_br_set_stp_state); 2478 2479 void b53_br_fast_age(struct dsa_switch *ds, int port) 2480 { 2481 struct b53_device *dev = ds->priv; 2482 2483 if (b53_fast_age_port(dev, port)) 2484 dev_err(ds->dev, "fast ageing failed\n"); 2485 } 2486 EXPORT_SYMBOL(b53_br_fast_age); 2487 2488 int b53_br_flags_pre(struct dsa_switch *ds, int port, 2489 struct switchdev_brport_flags flags, 2490 struct netlink_ext_ack *extack) 2491 { 2492 struct b53_device *dev = ds->priv; 2493 unsigned long mask = (BR_FLOOD | BR_MCAST_FLOOD | BR_ISOLATED); 2494 2495 if (!is5325(dev)) 2496 mask |= BR_LEARNING; 2497 2498 if (flags.mask & ~mask) 2499 return -EINVAL; 2500 2501 return 0; 2502 } 2503 EXPORT_SYMBOL(b53_br_flags_pre); 2504 2505 int b53_br_flags(struct dsa_switch *ds, int port, 2506 struct switchdev_brport_flags flags, 2507 struct netlink_ext_ack *extack) 2508 { 2509 if (flags.mask & BR_FLOOD) 2510 b53_port_set_ucast_flood(ds->priv, port, 2511 !!(flags.val & BR_FLOOD)); 2512 if (flags.mask & BR_MCAST_FLOOD) 2513 b53_port_set_mcast_flood(ds->priv, port, 2514 !!(flags.val & BR_MCAST_FLOOD)); 2515 if (flags.mask & BR_LEARNING) 2516 b53_port_set_learning(ds->priv, port, 2517 !!(flags.val & BR_LEARNING)); 2518 if (flags.mask & BR_ISOLATED) 2519 b53_port_set_isolated(ds->priv, port, 2520 !!(flags.val & BR_ISOLATED)); 2521 2522 return 0; 2523 } 2524 EXPORT_SYMBOL(b53_br_flags); 2525 2526 static bool b53_possible_cpu_port(struct dsa_switch *ds, int port) 2527 { 2528 /* Broadcom switches will accept enabling Broadcom tags on the 2529 * following ports: 5, 7 and 8, any other port is not supported 2530 */ 2531 switch (port) { 2532 case B53_CPU_PORT_25: 2533 case 7: 2534 case B53_CPU_PORT: 2535 return true; 2536 } 2537 2538 return false; 2539 } 2540 2541 static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port, 2542 enum dsa_tag_protocol tag_protocol) 2543 { 2544 bool ret = b53_possible_cpu_port(ds, port); 2545 2546 if (!ret) { 2547 dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n", 2548 port); 2549 return ret; 2550 } 2551 2552 switch (tag_protocol) { 2553 case DSA_TAG_PROTO_BRCM: 2554 case DSA_TAG_PROTO_BRCM_PREPEND: 2555 dev_warn(ds->dev, 2556 "Port %d is stacked to Broadcom tag switch\n", port); 2557 ret = false; 2558 break; 2559 default: 2560 ret = true; 2561 break; 2562 } 2563 2564 return ret; 2565 } 2566 2567 enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds, int port, 2568 enum dsa_tag_protocol mprot) 2569 { 2570 struct b53_device *dev = ds->priv; 2571 2572 if (!b53_can_enable_brcm_tags(ds, port, mprot)) { 2573 dev->tag_protocol = DSA_TAG_PROTO_NONE; 2574 goto out; 2575 } 2576 2577 /* Older models require different 6 byte tags */ 2578 if (is5325(dev) || is5365(dev)) { 2579 dev->tag_protocol = DSA_TAG_PROTO_BRCM_LEGACY_FCS; 2580 goto out; 2581 } else if (is63xx(dev)) { 2582 dev->tag_protocol = DSA_TAG_PROTO_BRCM_LEGACY; 2583 goto out; 2584 } 2585 2586 /* Broadcom BCM58xx chips have a flow accelerator on Port 8 2587 * which requires us to use the prepended Broadcom tag type 2588 */ 2589 if (dev->chip_id == BCM58XX_DEVICE_ID && port == B53_CPU_PORT) { 2590 dev->tag_protocol = DSA_TAG_PROTO_BRCM_PREPEND; 2591 goto out; 2592 } 2593 2594 dev->tag_protocol = DSA_TAG_PROTO_BRCM; 2595 out: 2596 return dev->tag_protocol; 2597 } 2598 EXPORT_SYMBOL(b53_get_tag_protocol); 2599 2600 int b53_mirror_add(struct dsa_switch *ds, int port, 2601 struct dsa_mall_mirror_tc_entry *mirror, bool ingress, 2602 struct netlink_ext_ack *extack) 2603 { 2604 struct b53_device *dev = ds->priv; 2605 u16 reg, loc; 2606 2607 if (ingress) 2608 loc = B53_IG_MIR_CTL; 2609 else 2610 loc = B53_EG_MIR_CTL; 2611 2612 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 2613 reg |= BIT(port); 2614 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 2615 2616 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 2617 reg &= ~CAP_PORT_MASK; 2618 reg |= mirror->to_local_port; 2619 reg |= MIRROR_EN; 2620 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 2621 2622 return 0; 2623 } 2624 EXPORT_SYMBOL(b53_mirror_add); 2625 2626 void b53_mirror_del(struct dsa_switch *ds, int port, 2627 struct dsa_mall_mirror_tc_entry *mirror) 2628 { 2629 struct b53_device *dev = ds->priv; 2630 bool loc_disable = false, other_loc_disable = false; 2631 u16 reg, loc; 2632 2633 if (mirror->ingress) 2634 loc = B53_IG_MIR_CTL; 2635 else 2636 loc = B53_EG_MIR_CTL; 2637 2638 /* Update the desired ingress/egress register */ 2639 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 2640 reg &= ~BIT(port); 2641 if (!(reg & MIRROR_MASK)) 2642 loc_disable = true; 2643 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 2644 2645 /* Now look at the other one to know if we can disable mirroring 2646 * entirely 2647 */ 2648 if (mirror->ingress) 2649 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, ®); 2650 else 2651 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, ®); 2652 if (!(reg & MIRROR_MASK)) 2653 other_loc_disable = true; 2654 2655 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 2656 /* Both no longer have ports, let's disable mirroring */ 2657 if (loc_disable && other_loc_disable) { 2658 reg &= ~MIRROR_EN; 2659 reg &= ~mirror->to_local_port; 2660 } 2661 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 2662 } 2663 EXPORT_SYMBOL(b53_mirror_del); 2664 2665 /* Returns 0 if EEE was not enabled, or 1 otherwise 2666 */ 2667 int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy) 2668 { 2669 int ret; 2670 2671 if (!b53_support_eee(ds, port)) 2672 return 0; 2673 2674 ret = phy_init_eee(phy, false); 2675 if (ret) 2676 return 0; 2677 2678 b53_eee_enable_set(ds, port, true); 2679 2680 return 1; 2681 } 2682 EXPORT_SYMBOL(b53_eee_init); 2683 2684 bool b53_support_eee(struct dsa_switch *ds, int port) 2685 { 2686 struct b53_device *dev = ds->priv; 2687 2688 return !is5325(dev) && !is5365(dev) && !is63xx(dev); 2689 } 2690 EXPORT_SYMBOL(b53_support_eee); 2691 2692 int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_keee *e) 2693 { 2694 struct b53_device *dev = ds->priv; 2695 struct ethtool_keee *p = &dev->ports[port].eee; 2696 2697 p->eee_enabled = e->eee_enabled; 2698 b53_eee_enable_set(ds, port, e->eee_enabled); 2699 2700 return 0; 2701 } 2702 EXPORT_SYMBOL(b53_set_mac_eee); 2703 2704 static int b53_change_mtu(struct dsa_switch *ds, int port, int mtu) 2705 { 2706 struct b53_device *dev = ds->priv; 2707 bool enable_jumbo; 2708 bool allow_10_100; 2709 2710 if (is5325(dev) || is5365(dev)) 2711 return 0; 2712 2713 if (!dsa_is_cpu_port(ds, port)) 2714 return 0; 2715 2716 enable_jumbo = (mtu > ETH_DATA_LEN); 2717 allow_10_100 = !is63xx(dev); 2718 2719 return b53_set_jumbo(dev, enable_jumbo, allow_10_100); 2720 } 2721 2722 static int b53_get_max_mtu(struct dsa_switch *ds, int port) 2723 { 2724 struct b53_device *dev = ds->priv; 2725 2726 if (is5325(dev) || is5365(dev)) 2727 return B53_MAX_MTU_25; 2728 2729 return B53_MAX_MTU; 2730 } 2731 2732 int b53_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 2733 { 2734 struct b53_device *dev = ds->priv; 2735 u32 atc; 2736 int reg; 2737 2738 if (is63xx(dev)) 2739 reg = B53_AGING_TIME_CONTROL_63XX; 2740 else 2741 reg = B53_AGING_TIME_CONTROL; 2742 2743 if (dev->chip_id == BCM53101_DEVICE_ID) 2744 atc = DIV_ROUND_CLOSEST(msecs, 500); 2745 else 2746 atc = DIV_ROUND_CLOSEST(msecs, 1000); 2747 2748 if (!is5325(dev) && !is5365(dev)) 2749 atc |= AGE_CHANGE; 2750 2751 b53_write32(dev, B53_MGMT_PAGE, reg, atc); 2752 2753 return 0; 2754 } 2755 EXPORT_SYMBOL_GPL(b53_set_ageing_time); 2756 2757 static const struct phylink_mac_ops b53_phylink_mac_ops = { 2758 .mac_select_pcs = b53_phylink_mac_select_pcs, 2759 .mac_config = b53_phylink_mac_config, 2760 .mac_link_down = b53_phylink_mac_link_down, 2761 .mac_link_up = b53_phylink_mac_link_up, 2762 }; 2763 2764 static const struct dsa_switch_ops b53_switch_ops = { 2765 .get_tag_protocol = b53_get_tag_protocol, 2766 .setup = b53_setup, 2767 .teardown = b53_teardown, 2768 .get_strings = b53_get_strings, 2769 .get_ethtool_stats = b53_get_ethtool_stats, 2770 .get_sset_count = b53_get_sset_count, 2771 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats, 2772 .phy_read = b53_phy_read16, 2773 .phy_write = b53_phy_write16, 2774 .phylink_get_caps = b53_phylink_get_caps, 2775 .port_setup = b53_setup_port, 2776 .port_enable = b53_enable_port, 2777 .port_disable = b53_disable_port, 2778 .support_eee = b53_support_eee, 2779 .set_mac_eee = b53_set_mac_eee, 2780 .set_ageing_time = b53_set_ageing_time, 2781 .port_bridge_join = b53_br_join, 2782 .port_bridge_leave = b53_br_leave, 2783 .port_pre_bridge_flags = b53_br_flags_pre, 2784 .port_bridge_flags = b53_br_flags, 2785 .port_stp_state_set = b53_br_set_stp_state, 2786 .port_fast_age = b53_br_fast_age, 2787 .port_vlan_filtering = b53_vlan_filtering, 2788 .port_vlan_add = b53_vlan_add, 2789 .port_vlan_del = b53_vlan_del, 2790 .port_fdb_dump = b53_fdb_dump, 2791 .port_fdb_add = b53_fdb_add, 2792 .port_fdb_del = b53_fdb_del, 2793 .port_mirror_add = b53_mirror_add, 2794 .port_mirror_del = b53_mirror_del, 2795 .port_mdb_add = b53_mdb_add, 2796 .port_mdb_del = b53_mdb_del, 2797 .port_max_mtu = b53_get_max_mtu, 2798 .port_change_mtu = b53_change_mtu, 2799 }; 2800 2801 static const struct b53_arl_ops b53_arl_ops_25 = { 2802 .arl_read_entry = b53_arl_read_entry_25, 2803 .arl_write_entry = b53_arl_write_entry_25, 2804 .arl_search_read = b53_arl_search_read_25, 2805 }; 2806 2807 static const struct b53_arl_ops b53_arl_ops_89 = { 2808 .arl_read_entry = b53_arl_read_entry_89, 2809 .arl_write_entry = b53_arl_write_entry_89, 2810 .arl_search_read = b53_arl_search_read_89, 2811 }; 2812 2813 static const struct b53_arl_ops b53_arl_ops_63xx = { 2814 .arl_read_entry = b53_arl_read_entry_89, 2815 .arl_write_entry = b53_arl_write_entry_89, 2816 .arl_search_read = b53_arl_search_read_63xx, 2817 }; 2818 2819 static const struct b53_arl_ops b53_arl_ops_95 = { 2820 .arl_read_entry = b53_arl_read_entry_95, 2821 .arl_write_entry = b53_arl_write_entry_95, 2822 .arl_search_read = b53_arl_search_read_95, 2823 }; 2824 2825 struct b53_chip_data { 2826 u32 chip_id; 2827 const char *dev_name; 2828 u16 vlans; 2829 u16 enabled_ports; 2830 u8 imp_port; 2831 u8 cpu_port; 2832 u8 vta_regs[3]; 2833 u8 arl_bins; 2834 u16 arl_buckets; 2835 u8 duplex_reg; 2836 u8 jumbo_pm_reg; 2837 u8 jumbo_size_reg; 2838 const struct b53_arl_ops *arl_ops; 2839 }; 2840 2841 #define B53_VTA_REGS \ 2842 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY } 2843 #define B53_VTA_REGS_9798 \ 2844 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 } 2845 #define B53_VTA_REGS_63XX \ 2846 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX } 2847 2848 static const struct b53_chip_data b53_switch_chips[] = { 2849 { 2850 .chip_id = BCM5325_DEVICE_ID, 2851 .dev_name = "BCM5325", 2852 .vlans = 16, 2853 .enabled_ports = 0x3f, 2854 .arl_bins = 2, 2855 .arl_buckets = 1024, 2856 .imp_port = 5, 2857 .duplex_reg = B53_DUPLEX_STAT_FE, 2858 .arl_ops = &b53_arl_ops_25, 2859 }, 2860 { 2861 .chip_id = BCM5365_DEVICE_ID, 2862 .dev_name = "BCM5365", 2863 .vlans = 256, 2864 .enabled_ports = 0x3f, 2865 .arl_bins = 2, 2866 .arl_buckets = 1024, 2867 .imp_port = 5, 2868 .duplex_reg = B53_DUPLEX_STAT_FE, 2869 .arl_ops = &b53_arl_ops_25, 2870 }, 2871 { 2872 .chip_id = BCM5389_DEVICE_ID, 2873 .dev_name = "BCM5389", 2874 .vlans = 4096, 2875 .enabled_ports = 0x11f, 2876 .arl_bins = 4, 2877 .arl_buckets = 1024, 2878 .imp_port = 8, 2879 .vta_regs = B53_VTA_REGS, 2880 .duplex_reg = B53_DUPLEX_STAT_GE, 2881 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2882 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2883 .arl_ops = &b53_arl_ops_89, 2884 }, 2885 { 2886 .chip_id = BCM5395_DEVICE_ID, 2887 .dev_name = "BCM5395", 2888 .vlans = 4096, 2889 .enabled_ports = 0x11f, 2890 .arl_bins = 4, 2891 .arl_buckets = 1024, 2892 .imp_port = 8, 2893 .vta_regs = B53_VTA_REGS, 2894 .duplex_reg = B53_DUPLEX_STAT_GE, 2895 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2896 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2897 .arl_ops = &b53_arl_ops_95, 2898 }, 2899 { 2900 .chip_id = BCM5397_DEVICE_ID, 2901 .dev_name = "BCM5397", 2902 .vlans = 4096, 2903 .enabled_ports = 0x11f, 2904 .arl_bins = 4, 2905 .arl_buckets = 1024, 2906 .imp_port = 8, 2907 .vta_regs = B53_VTA_REGS_9798, 2908 .duplex_reg = B53_DUPLEX_STAT_GE, 2909 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2910 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2911 .arl_ops = &b53_arl_ops_89, 2912 }, 2913 { 2914 .chip_id = BCM5398_DEVICE_ID, 2915 .dev_name = "BCM5398", 2916 .vlans = 4096, 2917 .enabled_ports = 0x17f, 2918 .arl_bins = 4, 2919 .arl_buckets = 1024, 2920 .imp_port = 8, 2921 .vta_regs = B53_VTA_REGS_9798, 2922 .duplex_reg = B53_DUPLEX_STAT_GE, 2923 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2924 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2925 .arl_ops = &b53_arl_ops_89, 2926 }, 2927 { 2928 .chip_id = BCM53101_DEVICE_ID, 2929 .dev_name = "BCM53101", 2930 .vlans = 4096, 2931 .enabled_ports = 0x11f, 2932 .arl_bins = 4, 2933 .arl_buckets = 512, 2934 .vta_regs = B53_VTA_REGS, 2935 .imp_port = 8, 2936 .duplex_reg = B53_DUPLEX_STAT_GE, 2937 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2938 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2939 .arl_ops = &b53_arl_ops_95, 2940 }, 2941 { 2942 .chip_id = BCM53115_DEVICE_ID, 2943 .dev_name = "BCM53115", 2944 .vlans = 4096, 2945 .enabled_ports = 0x11f, 2946 .arl_bins = 4, 2947 .arl_buckets = 1024, 2948 .vta_regs = B53_VTA_REGS, 2949 .imp_port = 8, 2950 .duplex_reg = B53_DUPLEX_STAT_GE, 2951 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2952 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2953 .arl_ops = &b53_arl_ops_95, 2954 }, 2955 { 2956 .chip_id = BCM53125_DEVICE_ID, 2957 .dev_name = "BCM53125", 2958 .vlans = 4096, 2959 .enabled_ports = 0x1ff, 2960 .arl_bins = 4, 2961 .arl_buckets = 1024, 2962 .imp_port = 8, 2963 .vta_regs = B53_VTA_REGS, 2964 .duplex_reg = B53_DUPLEX_STAT_GE, 2965 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2966 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2967 .arl_ops = &b53_arl_ops_95, 2968 }, 2969 { 2970 .chip_id = BCM53128_DEVICE_ID, 2971 .dev_name = "BCM53128", 2972 .vlans = 4096, 2973 .enabled_ports = 0x1ff, 2974 .arl_bins = 4, 2975 .arl_buckets = 1024, 2976 .imp_port = 8, 2977 .vta_regs = B53_VTA_REGS, 2978 .duplex_reg = B53_DUPLEX_STAT_GE, 2979 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2980 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2981 .arl_ops = &b53_arl_ops_95, 2982 }, 2983 { 2984 .chip_id = BCM63XX_DEVICE_ID, 2985 .dev_name = "BCM63xx", 2986 .vlans = 4096, 2987 .enabled_ports = 0, /* pdata must provide them */ 2988 .arl_bins = 1, 2989 .arl_buckets = 4096, 2990 .imp_port = 8, 2991 .vta_regs = B53_VTA_REGS_63XX, 2992 .duplex_reg = B53_DUPLEX_STAT_63XX, 2993 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX, 2994 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX, 2995 .arl_ops = &b53_arl_ops_63xx, 2996 }, 2997 { 2998 .chip_id = BCM53010_DEVICE_ID, 2999 .dev_name = "BCM53010", 3000 .vlans = 4096, 3001 .enabled_ports = 0x1bf, 3002 .arl_bins = 4, 3003 .arl_buckets = 1024, 3004 .imp_port = 8, 3005 .vta_regs = B53_VTA_REGS, 3006 .duplex_reg = B53_DUPLEX_STAT_GE, 3007 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 3008 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 3009 .arl_ops = &b53_arl_ops_95, 3010 }, 3011 { 3012 .chip_id = BCM53011_DEVICE_ID, 3013 .dev_name = "BCM53011", 3014 .vlans = 4096, 3015 .enabled_ports = 0x1bf, 3016 .arl_bins = 4, 3017 .arl_buckets = 1024, 3018 .imp_port = 8, 3019 .vta_regs = B53_VTA_REGS, 3020 .duplex_reg = B53_DUPLEX_STAT_GE, 3021 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 3022 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 3023 .arl_ops = &b53_arl_ops_95, 3024 }, 3025 { 3026 .chip_id = BCM53012_DEVICE_ID, 3027 .dev_name = "BCM53012", 3028 .vlans = 4096, 3029 .enabled_ports = 0x1bf, 3030 .arl_bins = 4, 3031 .arl_buckets = 1024, 3032 .imp_port = 8, 3033 .vta_regs = B53_VTA_REGS, 3034 .duplex_reg = B53_DUPLEX_STAT_GE, 3035 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 3036 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 3037 .arl_ops = &b53_arl_ops_95, 3038 }, 3039 { 3040 .chip_id = BCM53018_DEVICE_ID, 3041 .dev_name = "BCM53018", 3042 .vlans = 4096, 3043 .enabled_ports = 0x1bf, 3044 .arl_bins = 4, 3045 .arl_buckets = 1024, 3046 .imp_port = 8, 3047 .vta_regs = B53_VTA_REGS, 3048 .duplex_reg = B53_DUPLEX_STAT_GE, 3049 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 3050 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 3051 .arl_ops = &b53_arl_ops_95, 3052 }, 3053 { 3054 .chip_id = BCM53019_DEVICE_ID, 3055 .dev_name = "BCM53019", 3056 .vlans = 4096, 3057 .enabled_ports = 0x1bf, 3058 .arl_bins = 4, 3059 .arl_buckets = 1024, 3060 .imp_port = 8, 3061 .vta_regs = B53_VTA_REGS, 3062 .duplex_reg = B53_DUPLEX_STAT_GE, 3063 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 3064 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 3065 .arl_ops = &b53_arl_ops_95, 3066 }, 3067 { 3068 .chip_id = BCM58XX_DEVICE_ID, 3069 .dev_name = "BCM585xx/586xx/88312", 3070 .vlans = 4096, 3071 .enabled_ports = 0x1ff, 3072 .arl_bins = 4, 3073 .arl_buckets = 1024, 3074 .imp_port = 8, 3075 .vta_regs = B53_VTA_REGS, 3076 .duplex_reg = B53_DUPLEX_STAT_GE, 3077 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 3078 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 3079 .arl_ops = &b53_arl_ops_95, 3080 }, 3081 { 3082 .chip_id = BCM583XX_DEVICE_ID, 3083 .dev_name = "BCM583xx/11360", 3084 .vlans = 4096, 3085 .enabled_ports = 0x103, 3086 .arl_bins = 4, 3087 .arl_buckets = 1024, 3088 .imp_port = 8, 3089 .vta_regs = B53_VTA_REGS, 3090 .duplex_reg = B53_DUPLEX_STAT_GE, 3091 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 3092 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 3093 .arl_ops = &b53_arl_ops_95, 3094 }, 3095 /* Starfighter 2 */ 3096 { 3097 .chip_id = BCM4908_DEVICE_ID, 3098 .dev_name = "BCM4908", 3099 .vlans = 4096, 3100 .enabled_ports = 0x1bf, 3101 .arl_bins = 4, 3102 .arl_buckets = 256, 3103 .imp_port = 8, 3104 .vta_regs = B53_VTA_REGS, 3105 .duplex_reg = B53_DUPLEX_STAT_GE, 3106 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 3107 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 3108 .arl_ops = &b53_arl_ops_95, 3109 }, 3110 { 3111 .chip_id = BCM7445_DEVICE_ID, 3112 .dev_name = "BCM7445", 3113 .vlans = 4096, 3114 .enabled_ports = 0x1ff, 3115 .arl_bins = 4, 3116 .arl_buckets = 1024, 3117 .imp_port = 8, 3118 .vta_regs = B53_VTA_REGS, 3119 .duplex_reg = B53_DUPLEX_STAT_GE, 3120 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 3121 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 3122 .arl_ops = &b53_arl_ops_95, 3123 }, 3124 { 3125 .chip_id = BCM7278_DEVICE_ID, 3126 .dev_name = "BCM7278", 3127 .vlans = 4096, 3128 .enabled_ports = 0x1ff, 3129 .arl_bins = 4, 3130 .arl_buckets = 256, 3131 .imp_port = 8, 3132 .vta_regs = B53_VTA_REGS, 3133 .duplex_reg = B53_DUPLEX_STAT_GE, 3134 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 3135 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 3136 .arl_ops = &b53_arl_ops_95, 3137 }, 3138 { 3139 .chip_id = BCM53134_DEVICE_ID, 3140 .dev_name = "BCM53134", 3141 .vlans = 4096, 3142 .enabled_ports = 0x12f, 3143 .imp_port = 8, 3144 .cpu_port = B53_CPU_PORT, 3145 .vta_regs = B53_VTA_REGS, 3146 .arl_bins = 4, 3147 .arl_buckets = 1024, 3148 .duplex_reg = B53_DUPLEX_STAT_GE, 3149 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 3150 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 3151 .arl_ops = &b53_arl_ops_95, 3152 }, 3153 }; 3154 3155 static int b53_switch_init(struct b53_device *dev) 3156 { 3157 u32 chip_id = dev->chip_id; 3158 unsigned int i; 3159 3160 if (is63xx(dev)) 3161 chip_id = BCM63XX_DEVICE_ID; 3162 3163 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) { 3164 const struct b53_chip_data *chip = &b53_switch_chips[i]; 3165 3166 if (chip->chip_id == chip_id) { 3167 if (!dev->enabled_ports) 3168 dev->enabled_ports = chip->enabled_ports; 3169 dev->name = chip->dev_name; 3170 dev->duplex_reg = chip->duplex_reg; 3171 dev->vta_regs[0] = chip->vta_regs[0]; 3172 dev->vta_regs[1] = chip->vta_regs[1]; 3173 dev->vta_regs[2] = chip->vta_regs[2]; 3174 dev->jumbo_pm_reg = chip->jumbo_pm_reg; 3175 dev->imp_port = chip->imp_port; 3176 dev->num_vlans = chip->vlans; 3177 dev->num_arl_bins = chip->arl_bins; 3178 dev->num_arl_buckets = chip->arl_buckets; 3179 dev->arl_ops = chip->arl_ops; 3180 break; 3181 } 3182 } 3183 3184 /* check which BCM5325x version we have */ 3185 if (is5325(dev)) { 3186 u8 vc4; 3187 3188 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 3189 3190 /* check reserved bits */ 3191 switch (vc4 & 3) { 3192 case 1: 3193 /* BCM5325E */ 3194 break; 3195 case 3: 3196 /* BCM5325F - do not use port 4 */ 3197 dev->enabled_ports &= ~BIT(4); 3198 break; 3199 default: 3200 /* On the BCM47XX SoCs this is the supported internal switch.*/ 3201 #ifndef CONFIG_BCM47XX 3202 /* BCM5325M */ 3203 return -EINVAL; 3204 #else 3205 break; 3206 #endif 3207 } 3208 } 3209 3210 if (is5325e(dev)) 3211 dev->num_arl_buckets = 512; 3212 3213 dev->num_ports = fls(dev->enabled_ports); 3214 3215 dev->ds->num_ports = min_t(unsigned int, dev->num_ports, DSA_MAX_PORTS); 3216 3217 /* Include non standard CPU port built-in PHYs to be probed */ 3218 if (is539x(dev) || is531x5(dev)) { 3219 for (i = 0; i < dev->num_ports; i++) { 3220 if (!(dev->ds->phys_mii_mask & BIT(i)) && 3221 !b53_possible_cpu_port(dev->ds, i)) 3222 dev->ds->phys_mii_mask |= BIT(i); 3223 } 3224 } 3225 3226 dev->ports = devm_kzalloc_objs(dev->dev, struct b53_port, 3227 dev->num_ports); 3228 if (!dev->ports) 3229 return -ENOMEM; 3230 3231 dev->vlans = devm_kzalloc_objs(dev->dev, struct b53_vlan, 3232 dev->num_vlans); 3233 if (!dev->vlans) 3234 return -ENOMEM; 3235 3236 dev->reset_gpio = b53_switch_get_reset_gpio(dev); 3237 3238 if (PTR_ERR(dev->reset_gpio) == -EPROBE_DEFER) 3239 return -EPROBE_DEFER; 3240 3241 return 0; 3242 } 3243 3244 struct b53_device *b53_switch_alloc(struct device *base, 3245 const struct b53_io_ops *ops, 3246 void *priv) 3247 { 3248 struct dsa_switch *ds; 3249 struct b53_device *dev; 3250 3251 ds = devm_kzalloc_obj(base, *ds); 3252 if (!ds) 3253 return NULL; 3254 3255 ds->dev = base; 3256 3257 dev = devm_kzalloc_obj(base, *dev); 3258 if (!dev) 3259 return NULL; 3260 3261 ds->priv = dev; 3262 dev->dev = base; 3263 3264 dev->ds = ds; 3265 dev->priv = priv; 3266 dev->ops = ops; 3267 ds->ops = &b53_switch_ops; 3268 ds->phylink_mac_ops = &b53_phylink_mac_ops; 3269 dev->vlan_enabled = true; 3270 dev->vlan_filtering = false; 3271 /* Let DSA handle the case were multiple bridges span the same switch 3272 * device and different VLAN awareness settings are requested, which 3273 * would be breaking filtering semantics for any of the other bridge 3274 * devices. (not hardware supported) 3275 */ 3276 ds->vlan_filtering_is_global = true; 3277 3278 mutex_init(&dev->reg_mutex); 3279 mutex_init(&dev->stats_mutex); 3280 mutex_init(&dev->arl_mutex); 3281 3282 return dev; 3283 } 3284 EXPORT_SYMBOL(b53_switch_alloc); 3285 3286 int b53_switch_detect(struct b53_device *dev) 3287 { 3288 u32 id32; 3289 u16 tmp; 3290 u8 id8; 3291 int ret; 3292 3293 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8); 3294 if (ret) 3295 return ret; 3296 3297 switch (id8) { 3298 case 0: 3299 /* BCM5325 and BCM5365 do not have this register so reads 3300 * return 0. But the read operation did succeed, so assume this 3301 * is one of them. 3302 * 3303 * Next check if we can write to the 5325's VTA register; for 3304 * 5365 it is read only. 3305 */ 3306 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf); 3307 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp); 3308 3309 if (tmp == 0xf) { 3310 u32 phy_id; 3311 int val; 3312 3313 dev->chip_id = BCM5325_DEVICE_ID; 3314 3315 val = b53_phy_read16(dev->ds, 0, MII_PHYSID1); 3316 phy_id = (val & 0xffff) << 16; 3317 val = b53_phy_read16(dev->ds, 0, MII_PHYSID2); 3318 phy_id |= (val & 0xfff0); 3319 3320 if (phy_id == 0x00406330) 3321 dev->variant_id = B53_VARIANT_5325M; 3322 else if (phy_id == 0x0143bc30) 3323 dev->variant_id = B53_VARIANT_5325E; 3324 } else { 3325 dev->chip_id = BCM5365_DEVICE_ID; 3326 } 3327 break; 3328 case BCM5389_DEVICE_ID: 3329 case BCM5395_DEVICE_ID: 3330 case BCM5397_DEVICE_ID: 3331 case BCM5398_DEVICE_ID: 3332 dev->chip_id = id8; 3333 break; 3334 default: 3335 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32); 3336 if (ret) 3337 return ret; 3338 3339 switch (id32) { 3340 case BCM53101_DEVICE_ID: 3341 case BCM53115_DEVICE_ID: 3342 case BCM53125_DEVICE_ID: 3343 case BCM53128_DEVICE_ID: 3344 case BCM53010_DEVICE_ID: 3345 case BCM53011_DEVICE_ID: 3346 case BCM53012_DEVICE_ID: 3347 case BCM53018_DEVICE_ID: 3348 case BCM53019_DEVICE_ID: 3349 case BCM53134_DEVICE_ID: 3350 dev->chip_id = id32; 3351 break; 3352 default: 3353 dev_err(dev->dev, 3354 "unsupported switch detected (BCM53%02x/BCM%x)\n", 3355 id8, id32); 3356 return -ENODEV; 3357 } 3358 } 3359 3360 if (dev->chip_id == BCM5325_DEVICE_ID) 3361 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25, 3362 &dev->core_rev); 3363 else 3364 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID, 3365 &dev->core_rev); 3366 } 3367 EXPORT_SYMBOL(b53_switch_detect); 3368 3369 int b53_switch_register(struct b53_device *dev) 3370 { 3371 int ret; 3372 3373 if (dev->pdata) { 3374 dev->chip_id = dev->pdata->chip_id; 3375 dev->enabled_ports = dev->pdata->enabled_ports; 3376 } 3377 3378 if (!dev->chip_id && b53_switch_detect(dev)) 3379 return -EINVAL; 3380 3381 ret = b53_switch_init(dev); 3382 if (ret) 3383 return ret; 3384 3385 dev_info(dev->dev, "found switch: %s, rev %i\n", 3386 dev->name, dev->core_rev); 3387 3388 return dsa_register_switch(dev->ds); 3389 } 3390 EXPORT_SYMBOL(b53_switch_register); 3391 3392 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>"); 3393 MODULE_DESCRIPTION("B53 switch library"); 3394 MODULE_LICENSE("Dual BSD/GPL"); 3395