| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCCallingConv.cpp | 71 static const MCPhysReg ArgRegs[] = { in CC_PPC32_SVR4_Custom_AlignArgRegs() local
96 static const MCPhysReg ArgRegs[] = { in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128() local
121 static const MCPhysReg ArgRegs[] = { in CC_PPC32_SVR4_Custom_AlignFPArgRegs() local
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| H A D | PPCFastISel.cpp | 1364 SmallVectorImpl<Register> &ArgRegs, in processCallArgs()
1589 SmallVector<Register, 8> ArgRegs; in fastLowerCall() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVCallLowering.h | 34 SmallVector<Register> ArgRegs; member
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsCallLowering.cpp | 406 ArrayRef<MCPhysReg> ArgRegs = in lowerFormalArguments() local
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| H A D | MipsISelLowering.cpp | 4607 ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs(); in passByValArg() local
4690 ArrayRef<MCPhysReg> ArgRegs = ABI.getVarArgRegs(Subtarget.isGP64bit()); in writeVarArgRegs() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 1938 SmallVectorImpl<Register> &ArgRegs, in ProcessCallArgs()
2288 SmallVector<Register, 8> ArgRegs; in ARMEmitLibcall() local
2399 SmallVector<Register, 8> ArgRegs; in SelectCall() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVCallLowering.cpp | 471 ArrayRef<MCPhysReg> ArgRegs = RISCV::getArgGPRs(Subtarget.getTargetABI()); in saveVarArgRegisters() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCISelLowering.cpp | 542 static const MCPhysReg ArgRegs[] = {ARC::R0, ARC::R1, ARC::R2, ARC::R3, in LowerCallArguments() local
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CallLowering.cpp | 95 ArrayRef<ArrayRef<Register>> ArgRegs, in lowerCall()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 371 ArrayRef<MCPhysReg> ArgRegs = ArrayRef(GPRArgRegs); in LowerFormalArguments() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUCallLowering.cpp | 754 … SmallVectorImpl<std::pair<MCRegister, Register>> &ArgRegs, in passSpecialInputs()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 1222 static const MCPhysReg ArgRegs[] = { in LowerCCCArguments() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 3326 SmallVector<Register, 16> ArgRegs; in fastLowerCall() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 588 static const MCPhysReg ArgRegs[] = { in LowerFormalArguments_32() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 141 static const MCPhysReg ArgRegs[] = { in CC_SkipOdd() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 7153 ArrayRef<MCPhysReg> ArgRegs = ArrayRef(ArgGPRs); in LowerFormalArguments() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 22363 ArrayRef<MCPhysReg> ArgRegs = RISCV::getArgGPRs(Subtarget.getTargetABI()); in LowerFormalArguments() local
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