1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 *
4 * hda_intel.c - Implementation of primary alsa driver code base
5 * for Intel HD Audio.
6 *
7 * Copyright(c) 2004 Intel Corporation
8 *
9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
10 * PeiSen Hou <pshou@realtek.com.tw>
11 *
12 * CONTACTS:
13 *
14 * Matt Jared matt.jared@intel.com
15 * Andy Kopp andy.kopp@intel.com
16 * Dan Kogan dan.d.kogan@intel.com
17 *
18 * CHANGES:
19 *
20 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
21 */
22
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/moduleparam.h>
29 #include <linux/init.h>
30 #include <linux/slab.h>
31 #include <linux/pci.h>
32 #include <linux/mutex.h>
33 #include <linux/io.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/clocksource.h>
36 #include <linux/time.h>
37 #include <linux/completion.h>
38 #include <linux/acpi.h>
39 #include <linux/pgtable.h>
40 #include <linux/dmi.h>
41
42 #ifdef CONFIG_X86
43 /* for snoop control */
44 #include <asm/set_memory.h>
45 #include <asm/cpufeature.h>
46 #endif
47 #include <sound/core.h>
48 #include <sound/initval.h>
49 #include <sound/hdaudio.h>
50 #include <sound/hda_i915.h>
51 #include <sound/intel-dsp-config.h>
52 #include <linux/vgaarb.h>
53 #include <linux/vga_switcheroo.h>
54 #include <linux/apple-gmux.h>
55 #include <linux/firmware.h>
56 #include <sound/hda_codec.h>
57 #include "intel.h"
58
59 #define CREATE_TRACE_POINTS
60 #include "intel_trace.h"
61
62 /* position fix mode */
63 enum {
64 POS_FIX_AUTO,
65 POS_FIX_LPIB,
66 POS_FIX_POSBUF,
67 POS_FIX_VIACOMBO,
68 POS_FIX_COMBO,
69 POS_FIX_SKL,
70 POS_FIX_FIFO,
71 };
72
73 /* Defines for ATI HD Audio support in SB450 south bridge */
74 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
75 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
76
77 /* Defines for Nvidia HDA support */
78 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
79 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
80 #define NVIDIA_HDA_ISTRM_COH 0x4d
81 #define NVIDIA_HDA_OSTRM_COH 0x4c
82 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
83
84 /* Defines for Intel SCH HDA snoop control */
85 #define INTEL_HDA_CGCTL 0x48
86 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
87 #define INTEL_SCH_HDA_DEVC 0x78
88 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
89
90 /* max number of SDs */
91 /* ICH, ATI and VIA have 4 playback and 4 capture */
92 #define ICH6_NUM_CAPTURE 4
93 #define ICH6_NUM_PLAYBACK 4
94
95 /* ULI has 6 playback and 5 capture */
96 #define ULI_NUM_CAPTURE 5
97 #define ULI_NUM_PLAYBACK 6
98
99 /* ATI HDMI may have up to 8 playbacks and 0 capture */
100 #define ATIHDMI_NUM_CAPTURE 0
101 #define ATIHDMI_NUM_PLAYBACK 8
102
103
104 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
105 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
106 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
107 static char *model[SNDRV_CARDS];
108 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
109 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
110 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
111 static int probe_only[SNDRV_CARDS];
112 static int jackpoll_ms[SNDRV_CARDS];
113 static int single_cmd = -1;
114 static int enable_msi = -1;
115 #ifdef CONFIG_SND_HDA_PATCH_LOADER
116 static char *patch[SNDRV_CARDS];
117 #endif
118 #ifdef CONFIG_SND_HDA_INPUT_BEEP
119 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
120 CONFIG_SND_HDA_INPUT_BEEP_MODE};
121 #endif
122 static bool dmic_detect = 1;
123 static bool ctl_dev_id = IS_ENABLED(CONFIG_SND_HDA_CTL_DEV_ID) ? 1 : 0;
124
125 module_param_array(index, int, NULL, 0444);
126 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
127 module_param_array(id, charp, NULL, 0444);
128 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
129 module_param_array(enable, bool, NULL, 0444);
130 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
131 module_param_array(model, charp, NULL, 0444);
132 MODULE_PARM_DESC(model, "Use the given board model.");
133 module_param_array(position_fix, int, NULL, 0444);
134 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
135 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO).");
136 module_param_array(bdl_pos_adj, int, NULL, 0644);
137 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
138 module_param_array(probe_mask, int, NULL, 0444);
139 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
140 module_param_array(probe_only, int, NULL, 0444);
141 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
142 module_param_array(jackpoll_ms, int, NULL, 0444);
143 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
144 module_param(single_cmd, bint, 0444);
145 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
146 "(for debugging only).");
147 module_param(enable_msi, bint, 0444);
148 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
149 #ifdef CONFIG_SND_HDA_PATCH_LOADER
150 module_param_array(patch, charp, NULL, 0444);
151 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
152 #endif
153 #ifdef CONFIG_SND_HDA_INPUT_BEEP
154 module_param_array(beep_mode, bool, NULL, 0444);
155 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
156 "(0=off, 1=on) (default=1).");
157 #endif
158 module_param(dmic_detect, bool, 0444);
159 MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) "
160 "(0=off, 1=on) (default=1); "
161 "deprecated, use snd-intel-dspcfg.dsp_driver option instead");
162 module_param(ctl_dev_id, bool, 0444);
163 MODULE_PARM_DESC(ctl_dev_id, "Use control device identifier (based on codec address).");
164
165 #ifdef CONFIG_PM
166 static int param_set_xint(const char *val, const struct kernel_param *kp);
167 static const struct kernel_param_ops param_ops_xint = {
168 .set = param_set_xint,
169 .get = param_get_int,
170 };
171 #define param_check_xint param_check_int
172
173 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
174 module_param(power_save, xint, 0644);
175 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
176 "(in second, 0 = disable).");
177
178 static int pm_blacklist = -1;
179 module_param(pm_blacklist, bint, 0644);
180 MODULE_PARM_DESC(pm_blacklist, "Enable power-management denylist");
181
182 /* reset the HD-audio controller in power save mode.
183 * this may give more power-saving, but will take longer time to
184 * wake up.
185 */
186 static bool power_save_controller = 1;
187 module_param(power_save_controller, bool, 0644);
188 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
189 #else /* CONFIG_PM */
190 #define power_save 0
191 #define pm_blacklist 0
192 #define power_save_controller false
193 #endif /* CONFIG_PM */
194
195 static int align_buffer_size = -1;
196 module_param(align_buffer_size, bint, 0644);
197 MODULE_PARM_DESC(align_buffer_size,
198 "Force buffer and period sizes to be multiple of 128 bytes.");
199
200 #ifdef CONFIG_X86
201 static int hda_snoop = -1;
202 module_param_named(snoop, hda_snoop, bint, 0444);
203 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
204 #else
205 #define hda_snoop true
206 #endif
207
208
209 MODULE_LICENSE("GPL");
210 MODULE_DESCRIPTION("Intel HDA driver");
211
212 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
213 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
214 #define SUPPORT_VGA_SWITCHEROO
215 #endif
216 #endif
217
218
219 /*
220 */
221
222 /* driver types */
223 enum {
224 AZX_DRIVER_ICH,
225 AZX_DRIVER_PCH,
226 AZX_DRIVER_SCH,
227 AZX_DRIVER_SKL,
228 AZX_DRIVER_HDMI,
229 AZX_DRIVER_ATI,
230 AZX_DRIVER_ATIHDMI,
231 AZX_DRIVER_ATIHDMI_NS,
232 AZX_DRIVER_GFHDMI,
233 AZX_DRIVER_VIA,
234 AZX_DRIVER_SIS,
235 AZX_DRIVER_ULI,
236 AZX_DRIVER_NVIDIA,
237 AZX_DRIVER_TERA,
238 AZX_DRIVER_CTX,
239 AZX_DRIVER_CTHDA,
240 AZX_DRIVER_CMEDIA,
241 AZX_DRIVER_ZHAOXIN,
242 AZX_DRIVER_ZHAOXINHDMI,
243 AZX_DRIVER_LOONGSON,
244 AZX_DRIVER_GENERIC,
245 AZX_NUM_DRIVERS, /* keep this as last entry */
246 };
247
248 #define azx_get_snoop_type(chip) \
249 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
250 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
251
252 /* quirks for old Intel chipsets */
253 #define AZX_DCAPS_INTEL_ICH \
254 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
255
256 /* quirks for Intel PCH */
257 #define AZX_DCAPS_INTEL_PCH_BASE \
258 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
259 AZX_DCAPS_SNOOP_TYPE(SCH))
260
261 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
262 #define AZX_DCAPS_INTEL_PCH_NOPM \
263 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
264
265 /* PCH for HSW/BDW; with runtime PM */
266 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
267 #define AZX_DCAPS_INTEL_PCH \
268 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
269
270 /* HSW HDMI */
271 #define AZX_DCAPS_INTEL_HASWELL \
272 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
273 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
274 AZX_DCAPS_SNOOP_TYPE(SCH))
275
276 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
277 #define AZX_DCAPS_INTEL_BROADWELL \
278 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
279 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
280 AZX_DCAPS_SNOOP_TYPE(SCH))
281
282 #define AZX_DCAPS_INTEL_BAYTRAIL \
283 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
284
285 #define AZX_DCAPS_INTEL_BRASWELL \
286 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
287 AZX_DCAPS_I915_COMPONENT)
288
289 #define AZX_DCAPS_INTEL_SKYLAKE \
290 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
291 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
292
293 #define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE
294
295 #define AZX_DCAPS_INTEL_LNL \
296 (AZX_DCAPS_INTEL_SKYLAKE | AZX_DCAPS_PIO_COMMANDS)
297
298 /* quirks for ATI SB / AMD Hudson */
299 #define AZX_DCAPS_PRESET_ATI_SB \
300 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB |\
301 AZX_DCAPS_SNOOP_TYPE(ATI))
302
303 /* quirks for ATI/AMD HDMI */
304 #define AZX_DCAPS_PRESET_ATI_HDMI \
305 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB|\
306 AZX_DCAPS_NO_MSI64)
307
308 /* quirks for ATI HDMI with snoop off */
309 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
310 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
311
312 /* quirks for AMD SB */
313 #define AZX_DCAPS_PRESET_AMD_SB \
314 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_AMD_WORKAROUND |\
315 AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME |\
316 AZX_DCAPS_RETRY_PROBE)
317
318 /* quirks for Nvidia */
319 #define AZX_DCAPS_PRESET_NVIDIA \
320 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
321 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
322
323 #define AZX_DCAPS_PRESET_CTHDA \
324 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
325 AZX_DCAPS_NO_64BIT |\
326 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
327
328 /*
329 * vga_switcheroo support
330 */
331 #ifdef SUPPORT_VGA_SWITCHEROO
332 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
333 #define needs_eld_notify_link(chip) ((chip)->bus.keep_power)
334 #else
335 #define use_vga_switcheroo(chip) 0
336 #define needs_eld_notify_link(chip) false
337 #endif
338
339 static const char * const driver_short_names[] = {
340 [AZX_DRIVER_ICH] = "HDA Intel",
341 [AZX_DRIVER_PCH] = "HDA Intel PCH",
342 [AZX_DRIVER_SCH] = "HDA Intel MID",
343 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
344 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
345 [AZX_DRIVER_ATI] = "HDA ATI SB",
346 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
347 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
348 [AZX_DRIVER_GFHDMI] = "HDA GF HDMI",
349 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
350 [AZX_DRIVER_SIS] = "HDA SIS966",
351 [AZX_DRIVER_ULI] = "HDA ULI M5461",
352 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
353 [AZX_DRIVER_TERA] = "HDA Teradici",
354 [AZX_DRIVER_CTX] = "HDA Creative",
355 [AZX_DRIVER_CTHDA] = "HDA Creative",
356 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
357 [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin",
358 [AZX_DRIVER_ZHAOXINHDMI] = "HDA Zhaoxin HDMI",
359 [AZX_DRIVER_LOONGSON] = "HDA Loongson",
360 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
361 };
362
363 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
364 static void set_default_power_save(struct azx *chip);
365
366 /*
367 * initialize the PCI registers
368 */
369 /* update bits in a PCI register byte */
update_pci_byte(struct pci_dev * pci,unsigned int reg,unsigned char mask,unsigned char val)370 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
371 unsigned char mask, unsigned char val)
372 {
373 unsigned char data;
374
375 pci_read_config_byte(pci, reg, &data);
376 data &= ~mask;
377 data |= (val & mask);
378 pci_write_config_byte(pci, reg, data);
379 }
380
azx_init_pci(struct azx * chip)381 static void azx_init_pci(struct azx *chip)
382 {
383 int snoop_type = azx_get_snoop_type(chip);
384
385 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
386 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
387 * Ensuring these bits are 0 clears playback static on some HD Audio
388 * codecs.
389 * The PCI register TCSEL is defined in the Intel manuals.
390 */
391 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
392 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
393 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
394 }
395
396 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
397 * we need to enable snoop.
398 */
399 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
400 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
401 azx_snoop(chip));
402 update_pci_byte(chip->pci,
403 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
404 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
405 }
406
407 /* For NVIDIA HDA, enable snoop */
408 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
409 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
410 azx_snoop(chip));
411 update_pci_byte(chip->pci,
412 NVIDIA_HDA_TRANSREG_ADDR,
413 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
414 update_pci_byte(chip->pci,
415 NVIDIA_HDA_ISTRM_COH,
416 0x01, NVIDIA_HDA_ENABLE_COHBIT);
417 update_pci_byte(chip->pci,
418 NVIDIA_HDA_OSTRM_COH,
419 0x01, NVIDIA_HDA_ENABLE_COHBIT);
420 }
421
422 /* Enable SCH/PCH snoop if needed */
423 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
424 unsigned short snoop;
425 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
426 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
427 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
428 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
429 if (!azx_snoop(chip))
430 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
431 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
432 pci_read_config_word(chip->pci,
433 INTEL_SCH_HDA_DEVC, &snoop);
434 }
435 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
436 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
437 "Disabled" : "Enabled");
438 }
439 }
440
441 /*
442 * In BXT-P A0, HD-Audio DMA requests is later than expected,
443 * and makes an audio stream sensitive to system latencies when
444 * 24/32 bits are playing.
445 * Adjusting threshold of DMA fifo to force the DMA request
446 * sooner to improve latency tolerance at the expense of power.
447 */
bxt_reduce_dma_latency(struct azx * chip)448 static void bxt_reduce_dma_latency(struct azx *chip)
449 {
450 u32 val;
451
452 val = azx_readl(chip, VS_EM4L);
453 val &= (0x3 << 20);
454 azx_writel(chip, VS_EM4L, val);
455 }
456
457 /*
458 * ML_LCAP bits:
459 * bit 0: 6 MHz Supported
460 * bit 1: 12 MHz Supported
461 * bit 2: 24 MHz Supported
462 * bit 3: 48 MHz Supported
463 * bit 4: 96 MHz Supported
464 * bit 5: 192 MHz Supported
465 */
intel_get_lctl_scf(struct azx * chip)466 static int intel_get_lctl_scf(struct azx *chip)
467 {
468 struct hdac_bus *bus = azx_bus(chip);
469 static const int preferred_bits[] = { 2, 3, 1, 4, 5 };
470 u32 val, t;
471 int i;
472
473 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
474
475 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
476 t = preferred_bits[i];
477 if (val & (1 << t))
478 return t;
479 }
480
481 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
482 return 0;
483 }
484
intel_ml_lctl_set_power(struct azx * chip,int state)485 static int intel_ml_lctl_set_power(struct azx *chip, int state)
486 {
487 struct hdac_bus *bus = azx_bus(chip);
488 u32 val;
489 int timeout;
490
491 /*
492 * Changes to LCTL.SCF are only needed for the first multi-link dealing
493 * with external codecs
494 */
495 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
496 val &= ~AZX_ML_LCTL_SPA;
497 val |= state << AZX_ML_LCTL_SPA_SHIFT;
498 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
499 /* wait for CPA */
500 timeout = 50;
501 while (timeout) {
502 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
503 AZX_ML_LCTL_CPA) == (state << AZX_ML_LCTL_CPA_SHIFT))
504 return 0;
505 timeout--;
506 udelay(10);
507 }
508
509 return -1;
510 }
511
intel_init_lctl(struct azx * chip)512 static void intel_init_lctl(struct azx *chip)
513 {
514 struct hdac_bus *bus = azx_bus(chip);
515 u32 val;
516 int ret;
517
518 /* 0. check lctl register value is correct or not */
519 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
520 /* only perform additional configurations if the SCF is initially based on 6MHz */
521 if ((val & AZX_ML_LCTL_SCF) != 0)
522 return;
523
524 /*
525 * Before operating on SPA, CPA must match SPA.
526 * Any deviation may result in undefined behavior.
527 */
528 if (((val & AZX_ML_LCTL_SPA) >> AZX_ML_LCTL_SPA_SHIFT) !=
529 ((val & AZX_ML_LCTL_CPA) >> AZX_ML_LCTL_CPA_SHIFT))
530 return;
531
532 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
533 ret = intel_ml_lctl_set_power(chip, 0);
534 udelay(100);
535 if (ret)
536 goto set_spa;
537
538 /* 2. update SCF to select an audio clock different from 6MHz */
539 val &= ~AZX_ML_LCTL_SCF;
540 val |= intel_get_lctl_scf(chip);
541 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
542
543 set_spa:
544 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
545 intel_ml_lctl_set_power(chip, 1);
546 udelay(100);
547 }
548
hda_intel_init_chip(struct azx * chip,bool full_reset)549 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
550 {
551 struct hdac_bus *bus = azx_bus(chip);
552 struct pci_dev *pci = chip->pci;
553 u32 val;
554
555 snd_hdac_set_codec_wakeup(bus, true);
556 if (chip->driver_type == AZX_DRIVER_SKL) {
557 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
558 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
559 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
560 }
561 azx_init_chip(chip, full_reset);
562 if (chip->driver_type == AZX_DRIVER_SKL) {
563 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
564 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
565 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
566 }
567
568 snd_hdac_set_codec_wakeup(bus, false);
569
570 /* reduce dma latency to avoid noise */
571 if (HDA_CONTROLLER_IS_APL(pci))
572 bxt_reduce_dma_latency(chip);
573
574 if (bus->mlcap != NULL)
575 intel_init_lctl(chip);
576 }
577
578 /* calculate runtime delay from LPIB */
azx_get_delay_from_lpib(struct azx * chip,struct azx_dev * azx_dev,unsigned int pos)579 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
580 unsigned int pos)
581 {
582 struct snd_pcm_substream *substream = azx_dev->core.substream;
583 int stream = substream->stream;
584 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
585 int delay;
586
587 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
588 delay = pos - lpib_pos;
589 else
590 delay = lpib_pos - pos;
591 if (delay < 0) {
592 if (delay >= azx_dev->core.delay_negative_threshold)
593 delay = 0;
594 else
595 delay += azx_dev->core.bufsize;
596 }
597
598 if (delay >= azx_dev->core.period_bytes) {
599 dev_info(chip->card->dev,
600 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
601 delay, azx_dev->core.period_bytes);
602 delay = 0;
603 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
604 chip->get_delay[stream] = NULL;
605 }
606
607 return bytes_to_frames(substream->runtime, delay);
608 }
609
610 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
611
612 /* called from IRQ */
azx_position_check(struct azx * chip,struct azx_dev * azx_dev)613 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
614 {
615 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
616 int ok;
617
618 ok = azx_position_ok(chip, azx_dev);
619 if (ok == 1) {
620 azx_dev->irq_pending = 0;
621 return ok;
622 } else if (ok == 0) {
623 /* bogus IRQ, process it later */
624 azx_dev->irq_pending = 1;
625 schedule_work(&hda->irq_pending_work);
626 }
627 return 0;
628 }
629
630 #define display_power(chip, enable) \
631 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
632
633 /*
634 * Check whether the current DMA position is acceptable for updating
635 * periods. Returns non-zero if it's OK.
636 *
637 * Many HD-audio controllers appear pretty inaccurate about
638 * the update-IRQ timing. The IRQ is issued before actually the
639 * data is processed. So, we need to process it afterwords in a
640 * workqueue.
641 *
642 * Returns 1 if OK to proceed, 0 for delay handling, -1 for skipping update
643 */
azx_position_ok(struct azx * chip,struct azx_dev * azx_dev)644 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
645 {
646 struct snd_pcm_substream *substream = azx_dev->core.substream;
647 struct snd_pcm_runtime *runtime = substream->runtime;
648 int stream = substream->stream;
649 u32 wallclk;
650 unsigned int pos;
651 snd_pcm_uframes_t hwptr, target;
652
653 /*
654 * The value of the WALLCLK register is always 0
655 * on the Loongson controller, so we return directly.
656 */
657 if (chip->driver_type == AZX_DRIVER_LOONGSON)
658 return 1;
659
660 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
661 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
662 return -1; /* bogus (too early) interrupt */
663
664 if (chip->get_position[stream])
665 pos = chip->get_position[stream](chip, azx_dev);
666 else { /* use the position buffer as default */
667 pos = azx_get_pos_posbuf(chip, azx_dev);
668 if (!pos || pos == (u32)-1) {
669 dev_info(chip->card->dev,
670 "Invalid position buffer, using LPIB read method instead.\n");
671 chip->get_position[stream] = azx_get_pos_lpib;
672 if (chip->get_position[0] == azx_get_pos_lpib &&
673 chip->get_position[1] == azx_get_pos_lpib)
674 azx_bus(chip)->use_posbuf = false;
675 pos = azx_get_pos_lpib(chip, azx_dev);
676 chip->get_delay[stream] = NULL;
677 } else {
678 chip->get_position[stream] = azx_get_pos_posbuf;
679 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
680 chip->get_delay[stream] = azx_get_delay_from_lpib;
681 }
682 }
683
684 if (pos >= azx_dev->core.bufsize)
685 pos = 0;
686
687 if (WARN_ONCE(!azx_dev->core.period_bytes,
688 "hda-intel: zero azx_dev->period_bytes"))
689 return -1; /* this shouldn't happen! */
690 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
691 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
692 /* NG - it's below the first next period boundary */
693 return chip->bdl_pos_adj ? 0 : -1;
694 azx_dev->core.start_wallclk += wallclk;
695
696 if (azx_dev->core.no_period_wakeup)
697 return 1; /* OK, no need to check period boundary */
698
699 if (runtime->hw_ptr_base != runtime->hw_ptr_interrupt)
700 return 1; /* OK, already in hwptr updating process */
701
702 /* check whether the period gets really elapsed */
703 pos = bytes_to_frames(runtime, pos);
704 hwptr = runtime->hw_ptr_base + pos;
705 if (hwptr < runtime->status->hw_ptr)
706 hwptr += runtime->buffer_size;
707 target = runtime->hw_ptr_interrupt + runtime->period_size;
708 if (hwptr < target) {
709 /* too early wakeup, process it later */
710 return chip->bdl_pos_adj ? 0 : -1;
711 }
712
713 return 1; /* OK, it's fine */
714 }
715
716 /*
717 * The work for pending PCM period updates.
718 */
azx_irq_pending_work(struct work_struct * work)719 static void azx_irq_pending_work(struct work_struct *work)
720 {
721 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
722 struct azx *chip = &hda->chip;
723 struct hdac_bus *bus = azx_bus(chip);
724 struct hdac_stream *s;
725 int pending, ok;
726
727 if (!hda->irq_pending_warned) {
728 dev_info(chip->card->dev,
729 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
730 chip->card->number);
731 hda->irq_pending_warned = 1;
732 }
733
734 for (;;) {
735 pending = 0;
736 spin_lock_irq(&bus->reg_lock);
737 list_for_each_entry(s, &bus->stream_list, list) {
738 struct azx_dev *azx_dev = stream_to_azx_dev(s);
739 if (!azx_dev->irq_pending ||
740 !s->substream ||
741 !s->running)
742 continue;
743 ok = azx_position_ok(chip, azx_dev);
744 if (ok > 0) {
745 azx_dev->irq_pending = 0;
746 spin_unlock(&bus->reg_lock);
747 snd_pcm_period_elapsed(s->substream);
748 spin_lock(&bus->reg_lock);
749 } else if (ok < 0) {
750 pending = 0; /* too early */
751 } else
752 pending++;
753 }
754 spin_unlock_irq(&bus->reg_lock);
755 if (!pending)
756 return;
757 msleep(1);
758 }
759 }
760
761 /* clear irq_pending flags and assure no on-going workq */
azx_clear_irq_pending(struct azx * chip)762 static void azx_clear_irq_pending(struct azx *chip)
763 {
764 struct hdac_bus *bus = azx_bus(chip);
765 struct hdac_stream *s;
766
767 spin_lock_irq(&bus->reg_lock);
768 list_for_each_entry(s, &bus->stream_list, list) {
769 struct azx_dev *azx_dev = stream_to_azx_dev(s);
770 azx_dev->irq_pending = 0;
771 }
772 spin_unlock_irq(&bus->reg_lock);
773 }
774
azx_acquire_irq(struct azx * chip,int do_disconnect)775 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
776 {
777 struct hdac_bus *bus = azx_bus(chip);
778 int ret;
779
780 if (!chip->msi || pci_alloc_irq_vectors(chip->pci, 1, 1, PCI_IRQ_MSI) < 0) {
781 ret = pci_alloc_irq_vectors(chip->pci, 1, 1, PCI_IRQ_INTX);
782 if (ret < 0)
783 return ret;
784 chip->msi = 0;
785 }
786
787 if (request_irq(chip->pci->irq, azx_interrupt,
788 chip->msi ? 0 : IRQF_SHARED,
789 chip->card->irq_descr, chip)) {
790 dev_err(chip->card->dev,
791 "unable to grab IRQ %d, disabling device\n",
792 chip->pci->irq);
793 if (do_disconnect)
794 snd_card_disconnect(chip->card);
795 return -1;
796 }
797 bus->irq = chip->pci->irq;
798 chip->card->sync_irq = bus->irq;
799 return 0;
800 }
801
802 /* get the current DMA position with correction on VIA chips */
azx_via_get_position(struct azx * chip,struct azx_dev * azx_dev)803 static unsigned int azx_via_get_position(struct azx *chip,
804 struct azx_dev *azx_dev)
805 {
806 unsigned int link_pos, mini_pos, bound_pos;
807 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
808 unsigned int fifo_size;
809
810 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
811 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
812 /* Playback, no problem using link position */
813 return link_pos;
814 }
815
816 /* Capture */
817 /* For new chipset,
818 * use mod to get the DMA position just like old chipset
819 */
820 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
821 mod_dma_pos %= azx_dev->core.period_bytes;
822
823 fifo_size = azx_stream(azx_dev)->fifo_size;
824
825 if (azx_dev->insufficient) {
826 /* Link position never gather than FIFO size */
827 if (link_pos <= fifo_size)
828 return 0;
829
830 azx_dev->insufficient = 0;
831 }
832
833 if (link_pos <= fifo_size)
834 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
835 else
836 mini_pos = link_pos - fifo_size;
837
838 /* Find nearest previous boudary */
839 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
840 mod_link_pos = link_pos % azx_dev->core.period_bytes;
841 if (mod_link_pos >= fifo_size)
842 bound_pos = link_pos - mod_link_pos;
843 else if (mod_dma_pos >= mod_mini_pos)
844 bound_pos = mini_pos - mod_mini_pos;
845 else {
846 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
847 if (bound_pos >= azx_dev->core.bufsize)
848 bound_pos = 0;
849 }
850
851 /* Calculate real DMA position we want */
852 return bound_pos + mod_dma_pos;
853 }
854
855 #define AMD_FIFO_SIZE 32
856
857 /* get the current DMA position with FIFO size correction */
azx_get_pos_fifo(struct azx * chip,struct azx_dev * azx_dev)858 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev)
859 {
860 struct snd_pcm_substream *substream = azx_dev->core.substream;
861 struct snd_pcm_runtime *runtime = substream->runtime;
862 unsigned int pos, delay;
863
864 pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
865 if (!runtime)
866 return pos;
867
868 runtime->delay = AMD_FIFO_SIZE;
869 delay = frames_to_bytes(runtime, AMD_FIFO_SIZE);
870 if (azx_dev->insufficient) {
871 if (pos < delay) {
872 delay = pos;
873 runtime->delay = bytes_to_frames(runtime, pos);
874 } else {
875 azx_dev->insufficient = 0;
876 }
877 }
878
879 /* correct the DMA position for capture stream */
880 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
881 if (pos < delay)
882 pos += azx_dev->core.bufsize;
883 pos -= delay;
884 }
885
886 return pos;
887 }
888
azx_get_delay_from_fifo(struct azx * chip,struct azx_dev * azx_dev,unsigned int pos)889 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev,
890 unsigned int pos)
891 {
892 struct snd_pcm_substream *substream = azx_dev->core.substream;
893
894 /* just read back the calculated value in the above */
895 return substream->runtime->delay;
896 }
897
__azx_shutdown_chip(struct azx * chip,bool skip_link_reset)898 static void __azx_shutdown_chip(struct azx *chip, bool skip_link_reset)
899 {
900 azx_stop_chip(chip);
901 if (!skip_link_reset)
902 azx_enter_link_reset(chip);
903 azx_clear_irq_pending(chip);
904 display_power(chip, false);
905 }
906
907 static DEFINE_MUTEX(card_list_lock);
908 static LIST_HEAD(card_list);
909
azx_shutdown_chip(struct azx * chip)910 static void azx_shutdown_chip(struct azx *chip)
911 {
912 __azx_shutdown_chip(chip, false);
913 }
914
azx_add_card_list(struct azx * chip)915 static void azx_add_card_list(struct azx *chip)
916 {
917 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
918 mutex_lock(&card_list_lock);
919 list_add(&hda->list, &card_list);
920 mutex_unlock(&card_list_lock);
921 }
922
azx_del_card_list(struct azx * chip)923 static void azx_del_card_list(struct azx *chip)
924 {
925 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
926 mutex_lock(&card_list_lock);
927 list_del_init(&hda->list);
928 mutex_unlock(&card_list_lock);
929 }
930
931 /* trigger power-save check at writing parameter */
param_set_xint(const char * val,const struct kernel_param * kp)932 static int __maybe_unused param_set_xint(const char *val, const struct kernel_param *kp)
933 {
934 struct hda_intel *hda;
935 struct azx *chip;
936 int prev = power_save;
937 int ret = param_set_int(val, kp);
938
939 if (ret || prev == power_save)
940 return ret;
941
942 if (pm_blacklist > 0)
943 return 0;
944
945 mutex_lock(&card_list_lock);
946 list_for_each_entry(hda, &card_list, list) {
947 chip = &hda->chip;
948 if (!hda->probe_continued || chip->disabled ||
949 hda->runtime_pm_disabled)
950 continue;
951 snd_hda_set_power_save(&chip->bus, power_save * 1000);
952 }
953 mutex_unlock(&card_list_lock);
954 return 0;
955 }
956
957 /*
958 * power management
959 */
azx_is_pm_ready(struct snd_card * card)960 static bool azx_is_pm_ready(struct snd_card *card)
961 {
962 struct azx *chip;
963 struct hda_intel *hda;
964
965 if (!card)
966 return false;
967 chip = card->private_data;
968 hda = container_of(chip, struct hda_intel, chip);
969 if (chip->disabled || hda->init_failed || !chip->running)
970 return false;
971 return true;
972 }
973
__azx_runtime_resume(struct azx * chip)974 static void __azx_runtime_resume(struct azx *chip)
975 {
976 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
977 struct hdac_bus *bus = azx_bus(chip);
978 struct hda_codec *codec;
979 int status;
980
981 display_power(chip, true);
982 if (hda->need_i915_power)
983 snd_hdac_i915_set_bclk(bus);
984
985 /* Read STATESTS before controller reset */
986 status = azx_readw(chip, STATESTS);
987
988 azx_init_pci(chip);
989 hda_intel_init_chip(chip, true);
990
991 /* Avoid codec resume if runtime resume is for system suspend */
992 if (!chip->pm_prepared) {
993 list_for_each_codec(codec, &chip->bus) {
994 if (codec->relaxed_resume)
995 continue;
996
997 if (codec->forced_resume || (status & (1 << codec->addr)))
998 pm_request_resume(hda_codec_dev(codec));
999 }
1000 }
1001
1002 /* power down again for link-controlled chips */
1003 if (!hda->need_i915_power)
1004 display_power(chip, false);
1005 }
1006
azx_prepare(struct device * dev)1007 static int azx_prepare(struct device *dev)
1008 {
1009 struct snd_card *card = dev_get_drvdata(dev);
1010 struct azx *chip;
1011
1012 if (!azx_is_pm_ready(card))
1013 return 0;
1014
1015 chip = card->private_data;
1016 chip->pm_prepared = 1;
1017 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1018
1019 flush_work(&azx_bus(chip)->unsol_work);
1020
1021 /* HDA controller always requires different WAKEEN for runtime suspend
1022 * and system suspend, so don't use direct-complete here.
1023 */
1024 return 0;
1025 }
1026
azx_complete(struct device * dev)1027 static void azx_complete(struct device *dev)
1028 {
1029 struct snd_card *card = dev_get_drvdata(dev);
1030 struct azx *chip;
1031
1032 if (!azx_is_pm_ready(card))
1033 return;
1034
1035 chip = card->private_data;
1036 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1037 chip->pm_prepared = 0;
1038 }
1039
azx_suspend(struct device * dev)1040 static int azx_suspend(struct device *dev)
1041 {
1042 struct snd_card *card = dev_get_drvdata(dev);
1043 struct azx *chip;
1044
1045 if (!azx_is_pm_ready(card))
1046 return 0;
1047
1048 chip = card->private_data;
1049 azx_shutdown_chip(chip);
1050
1051 trace_azx_suspend(chip);
1052 return 0;
1053 }
1054
azx_resume(struct device * dev)1055 static int azx_resume(struct device *dev)
1056 {
1057 struct snd_card *card = dev_get_drvdata(dev);
1058 struct azx *chip;
1059
1060 if (!azx_is_pm_ready(card))
1061 return 0;
1062
1063 chip = card->private_data;
1064
1065 __azx_runtime_resume(chip);
1066
1067 trace_azx_resume(chip);
1068 return 0;
1069 }
1070
1071 /* put codec down to D3 at hibernation for Intel SKL+;
1072 * otherwise BIOS may still access the codec and screw up the driver
1073 */
azx_freeze_noirq(struct device * dev)1074 static int azx_freeze_noirq(struct device *dev)
1075 {
1076 struct snd_card *card = dev_get_drvdata(dev);
1077 struct azx *chip = card->private_data;
1078 struct pci_dev *pci = to_pci_dev(dev);
1079
1080 if (!azx_is_pm_ready(card))
1081 return 0;
1082 if (chip->driver_type == AZX_DRIVER_SKL)
1083 pci_set_power_state(pci, PCI_D3hot);
1084
1085 return 0;
1086 }
1087
azx_thaw_noirq(struct device * dev)1088 static int azx_thaw_noirq(struct device *dev)
1089 {
1090 struct snd_card *card = dev_get_drvdata(dev);
1091 struct azx *chip = card->private_data;
1092 struct pci_dev *pci = to_pci_dev(dev);
1093
1094 if (!azx_is_pm_ready(card))
1095 return 0;
1096 if (chip->driver_type == AZX_DRIVER_SKL)
1097 pci_set_power_state(pci, PCI_D0);
1098
1099 return 0;
1100 }
1101
azx_runtime_suspend(struct device * dev)1102 static int azx_runtime_suspend(struct device *dev)
1103 {
1104 struct snd_card *card = dev_get_drvdata(dev);
1105 struct azx *chip;
1106
1107 if (!azx_is_pm_ready(card))
1108 return 0;
1109 chip = card->private_data;
1110
1111 /* enable controller wake up event */
1112 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | STATESTS_INT_MASK);
1113
1114 azx_shutdown_chip(chip);
1115 trace_azx_runtime_suspend(chip);
1116 return 0;
1117 }
1118
azx_runtime_resume(struct device * dev)1119 static int azx_runtime_resume(struct device *dev)
1120 {
1121 struct snd_card *card = dev_get_drvdata(dev);
1122 struct azx *chip;
1123
1124 if (!azx_is_pm_ready(card))
1125 return 0;
1126 chip = card->private_data;
1127 __azx_runtime_resume(chip);
1128
1129 /* disable controller Wake Up event*/
1130 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & ~STATESTS_INT_MASK);
1131
1132 trace_azx_runtime_resume(chip);
1133 return 0;
1134 }
1135
azx_runtime_idle(struct device * dev)1136 static int azx_runtime_idle(struct device *dev)
1137 {
1138 struct snd_card *card = dev_get_drvdata(dev);
1139 struct azx *chip;
1140 struct hda_intel *hda;
1141
1142 if (!card)
1143 return 0;
1144
1145 chip = card->private_data;
1146 hda = container_of(chip, struct hda_intel, chip);
1147 if (chip->disabled || hda->init_failed)
1148 return 0;
1149
1150 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1151 azx_bus(chip)->codec_powered || !chip->running)
1152 return -EBUSY;
1153
1154 /* ELD notification gets broken when HD-audio bus is off */
1155 if (needs_eld_notify_link(chip))
1156 return -EBUSY;
1157
1158 return 0;
1159 }
1160
1161 static const struct dev_pm_ops azx_pm = {
1162 SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1163 .prepare = pm_sleep_ptr(azx_prepare),
1164 .complete = pm_sleep_ptr(azx_complete),
1165 .freeze_noirq = pm_sleep_ptr(azx_freeze_noirq),
1166 .thaw_noirq = pm_sleep_ptr(azx_thaw_noirq),
1167 RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1168 };
1169
1170
1171 static int azx_probe_continue(struct azx *chip);
1172
1173 #ifdef SUPPORT_VGA_SWITCHEROO
1174 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1175
azx_vs_set_state(struct pci_dev * pci,enum vga_switcheroo_state state)1176 static void azx_vs_set_state(struct pci_dev *pci,
1177 enum vga_switcheroo_state state)
1178 {
1179 struct snd_card *card = pci_get_drvdata(pci);
1180 struct azx *chip = card->private_data;
1181 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1182 struct hda_codec *codec;
1183 bool disabled;
1184
1185 wait_for_completion(&hda->probe_wait);
1186 if (hda->init_failed)
1187 return;
1188
1189 disabled = (state == VGA_SWITCHEROO_OFF);
1190 if (chip->disabled == disabled)
1191 return;
1192
1193 if (!hda->probe_continued) {
1194 chip->disabled = disabled;
1195 if (!disabled) {
1196 dev_info(chip->card->dev,
1197 "Start delayed initialization\n");
1198 if (azx_probe_continue(chip) < 0)
1199 dev_err(chip->card->dev, "initialization error\n");
1200 }
1201 } else {
1202 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1203 disabled ? "Disabling" : "Enabling");
1204 if (disabled) {
1205 list_for_each_codec(codec, &chip->bus) {
1206 pm_runtime_suspend(hda_codec_dev(codec));
1207 pm_runtime_disable(hda_codec_dev(codec));
1208 }
1209 pm_runtime_suspend(card->dev);
1210 pm_runtime_disable(card->dev);
1211 /* when we get suspended by vga_switcheroo we end up in D3cold,
1212 * however we have no ACPI handle, so pci/acpi can't put us there,
1213 * put ourselves there */
1214 pci->current_state = PCI_D3cold;
1215 chip->disabled = true;
1216 if (snd_hda_lock_devices(&chip->bus))
1217 dev_warn(chip->card->dev,
1218 "Cannot lock devices!\n");
1219 } else {
1220 snd_hda_unlock_devices(&chip->bus);
1221 chip->disabled = false;
1222 pm_runtime_enable(card->dev);
1223 list_for_each_codec(codec, &chip->bus) {
1224 pm_runtime_enable(hda_codec_dev(codec));
1225 pm_runtime_resume(hda_codec_dev(codec));
1226 }
1227 }
1228 }
1229 }
1230
azx_vs_can_switch(struct pci_dev * pci)1231 static bool azx_vs_can_switch(struct pci_dev *pci)
1232 {
1233 struct snd_card *card = pci_get_drvdata(pci);
1234 struct azx *chip = card->private_data;
1235 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1236
1237 wait_for_completion(&hda->probe_wait);
1238 if (hda->init_failed)
1239 return false;
1240 if (chip->disabled || !hda->probe_continued)
1241 return true;
1242 if (snd_hda_lock_devices(&chip->bus))
1243 return false;
1244 snd_hda_unlock_devices(&chip->bus);
1245 return true;
1246 }
1247
1248 /*
1249 * The discrete GPU cannot power down unless the HDA controller runtime
1250 * suspends, so activate runtime PM on codecs even if power_save == 0.
1251 */
setup_vga_switcheroo_runtime_pm(struct azx * chip)1252 static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1253 {
1254 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1255 struct hda_codec *codec;
1256
1257 if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) {
1258 list_for_each_codec(codec, &chip->bus)
1259 codec->auto_runtime_pm = 1;
1260 /* reset the power save setup */
1261 if (chip->running)
1262 set_default_power_save(chip);
1263 }
1264 }
1265
azx_vs_gpu_bound(struct pci_dev * pci,enum vga_switcheroo_client_id client_id)1266 static void azx_vs_gpu_bound(struct pci_dev *pci,
1267 enum vga_switcheroo_client_id client_id)
1268 {
1269 struct snd_card *card = pci_get_drvdata(pci);
1270 struct azx *chip = card->private_data;
1271
1272 if (client_id == VGA_SWITCHEROO_DIS)
1273 chip->bus.keep_power = 0;
1274 setup_vga_switcheroo_runtime_pm(chip);
1275 }
1276
init_vga_switcheroo(struct azx * chip)1277 static void init_vga_switcheroo(struct azx *chip)
1278 {
1279 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1280 struct pci_dev *p = get_bound_vga(chip->pci);
1281 struct pci_dev *parent;
1282 if (p) {
1283 dev_info(chip->card->dev,
1284 "Handle vga_switcheroo audio client\n");
1285 hda->use_vga_switcheroo = 1;
1286
1287 /* cleared in either gpu_bound op or codec probe, or when its
1288 * upstream port has _PR3 (i.e. dGPU).
1289 */
1290 parent = pci_upstream_bridge(p);
1291 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1;
1292 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
1293 pci_dev_put(p);
1294 }
1295 }
1296
1297 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1298 .set_gpu_state = azx_vs_set_state,
1299 .can_switch = azx_vs_can_switch,
1300 .gpu_bound = azx_vs_gpu_bound,
1301 };
1302
register_vga_switcheroo(struct azx * chip)1303 static int register_vga_switcheroo(struct azx *chip)
1304 {
1305 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1306 struct pci_dev *p;
1307 int err;
1308
1309 if (!hda->use_vga_switcheroo)
1310 return 0;
1311
1312 p = get_bound_vga(chip->pci);
1313 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1314 pci_dev_put(p);
1315
1316 if (err < 0)
1317 return err;
1318 hda->vga_switcheroo_registered = 1;
1319
1320 return 0;
1321 }
1322 #else
1323 #define init_vga_switcheroo(chip) /* NOP */
1324 #define register_vga_switcheroo(chip) 0
1325 #define check_hdmi_disabled(pci) false
1326 #define setup_vga_switcheroo_runtime_pm(chip) /* NOP */
1327 #endif /* SUPPORT_VGA_SWITCHER */
1328
1329 /*
1330 * destructor
1331 */
azx_free(struct azx * chip)1332 static void azx_free(struct azx *chip)
1333 {
1334 struct pci_dev *pci = chip->pci;
1335 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1336 struct hdac_bus *bus = azx_bus(chip);
1337
1338 if (hda->freed)
1339 return;
1340
1341 if (azx_has_pm_runtime(chip) && chip->running) {
1342 pm_runtime_get_noresume(&pci->dev);
1343 pm_runtime_forbid(&pci->dev);
1344 pm_runtime_dont_use_autosuspend(&pci->dev);
1345 }
1346
1347 chip->running = 0;
1348
1349 azx_del_card_list(chip);
1350
1351 hda->init_failed = 1; /* to be sure */
1352 complete_all(&hda->probe_wait);
1353
1354 if (use_vga_switcheroo(hda)) {
1355 if (chip->disabled && hda->probe_continued)
1356 snd_hda_unlock_devices(&chip->bus);
1357 if (hda->vga_switcheroo_registered) {
1358 vga_switcheroo_unregister_client(chip->pci);
1359
1360 /* Some GPUs don't have sound, and azx_first_init fails,
1361 * leaving the device probed but non-functional. As long
1362 * as it's probed, the PCI subsystem keeps its runtime
1363 * PM status as active. Force it to suspended (as we
1364 * actually stop the chip) to allow GPU to suspend via
1365 * vga_switcheroo, and print a warning.
1366 */
1367 dev_warn(&pci->dev, "GPU sound probed, but not operational: please add a quirk to driver_denylist\n");
1368 pm_runtime_disable(&pci->dev);
1369 pm_runtime_set_suspended(&pci->dev);
1370 pm_runtime_enable(&pci->dev);
1371 }
1372 }
1373
1374 if (bus->chip_init) {
1375 azx_clear_irq_pending(chip);
1376 azx_stop_all_streams(chip);
1377 azx_stop_chip(chip);
1378 }
1379
1380 if (bus->irq >= 0)
1381 free_irq(bus->irq, (void*)chip);
1382
1383 azx_free_stream_pages(chip);
1384 azx_free_streams(chip);
1385 snd_hdac_bus_exit(bus);
1386
1387 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1388 release_firmware(chip->fw);
1389 #endif
1390 display_power(chip, false);
1391
1392 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
1393 snd_hdac_i915_exit(bus);
1394
1395 hda->freed = 1;
1396 }
1397
azx_dev_disconnect(struct snd_device * device)1398 static int azx_dev_disconnect(struct snd_device *device)
1399 {
1400 struct azx *chip = device->device_data;
1401 struct hdac_bus *bus = azx_bus(chip);
1402
1403 chip->bus.shutdown = 1;
1404 cancel_work_sync(&bus->unsol_work);
1405
1406 return 0;
1407 }
1408
azx_dev_free(struct snd_device * device)1409 static int azx_dev_free(struct snd_device *device)
1410 {
1411 azx_free(device->device_data);
1412 return 0;
1413 }
1414
1415 #ifdef SUPPORT_VGA_SWITCHEROO
1416 #ifdef CONFIG_ACPI
1417 /* ATPX is in the integrated GPU's namespace */
atpx_present(void)1418 static bool atpx_present(void)
1419 {
1420 struct pci_dev *pdev = NULL;
1421 acpi_handle dhandle, atpx_handle;
1422 acpi_status status;
1423
1424 while ((pdev = pci_get_base_class(PCI_BASE_CLASS_DISPLAY, pdev))) {
1425 if ((pdev->class != PCI_CLASS_DISPLAY_VGA << 8) &&
1426 (pdev->class != PCI_CLASS_DISPLAY_OTHER << 8))
1427 continue;
1428
1429 dhandle = ACPI_HANDLE(&pdev->dev);
1430 if (dhandle) {
1431 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
1432 if (ACPI_SUCCESS(status)) {
1433 pci_dev_put(pdev);
1434 return true;
1435 }
1436 }
1437 }
1438 return false;
1439 }
1440 #else
atpx_present(void)1441 static bool atpx_present(void)
1442 {
1443 return false;
1444 }
1445 #endif
1446
1447 /*
1448 * Check of disabled HDMI controller by vga_switcheroo
1449 */
get_bound_vga(struct pci_dev * pci)1450 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1451 {
1452 struct pci_dev *p;
1453
1454 /* check only discrete GPU */
1455 switch (pci->vendor) {
1456 case PCI_VENDOR_ID_ATI:
1457 case PCI_VENDOR_ID_AMD:
1458 if (pci->devfn == 1) {
1459 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1460 pci->bus->number, 0);
1461 if (p) {
1462 /* ATPX is in the integrated GPU's ACPI namespace
1463 * rather than the dGPU's namespace. However,
1464 * the dGPU is the one who is involved in
1465 * vgaswitcheroo.
1466 */
1467 if (pci_is_display(p) &&
1468 (atpx_present() || apple_gmux_detect(NULL, NULL)))
1469 return p;
1470 pci_dev_put(p);
1471 }
1472 }
1473 break;
1474 case PCI_VENDOR_ID_NVIDIA:
1475 if (pci->devfn == 1) {
1476 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1477 pci->bus->number, 0);
1478 if (p) {
1479 if (pci_is_display(p))
1480 return p;
1481 pci_dev_put(p);
1482 }
1483 }
1484 break;
1485 }
1486 return NULL;
1487 }
1488
check_hdmi_disabled(struct pci_dev * pci)1489 static bool check_hdmi_disabled(struct pci_dev *pci)
1490 {
1491 bool vga_inactive = false;
1492 struct pci_dev *p = get_bound_vga(pci);
1493
1494 if (p) {
1495 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1496 vga_inactive = true;
1497 pci_dev_put(p);
1498 }
1499 return vga_inactive;
1500 }
1501 #endif /* SUPPORT_VGA_SWITCHEROO */
1502
1503 /*
1504 * allow/deny-listing for position_fix
1505 */
1506 static const struct snd_pci_quirk position_fix_list[] = {
1507 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1508 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1509 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1510 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1511 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1512 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1513 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1514 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1515 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1516 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1517 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1518 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1519 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1520 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1521 {}
1522 };
1523
check_position_fix(struct azx * chip,int fix)1524 static int check_position_fix(struct azx *chip, int fix)
1525 {
1526 const struct snd_pci_quirk *q;
1527
1528 switch (fix) {
1529 case POS_FIX_AUTO:
1530 case POS_FIX_LPIB:
1531 case POS_FIX_POSBUF:
1532 case POS_FIX_VIACOMBO:
1533 case POS_FIX_COMBO:
1534 case POS_FIX_SKL:
1535 case POS_FIX_FIFO:
1536 return fix;
1537 }
1538
1539 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1540 if (q) {
1541 dev_info(chip->card->dev,
1542 "position_fix set to %d for device %04x:%04x\n",
1543 q->value, q->subvendor, q->subdevice);
1544 return q->value;
1545 }
1546
1547 /* Check VIA/ATI HD Audio Controller exist */
1548 if (chip->driver_type == AZX_DRIVER_VIA) {
1549 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1550 return POS_FIX_VIACOMBO;
1551 }
1552 if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) {
1553 dev_dbg(chip->card->dev, "Using FIFO position fix\n");
1554 return POS_FIX_FIFO;
1555 }
1556 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1557 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1558 return POS_FIX_LPIB;
1559 }
1560 if (chip->driver_type == AZX_DRIVER_SKL) {
1561 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1562 return POS_FIX_SKL;
1563 }
1564 return POS_FIX_AUTO;
1565 }
1566
assign_position_fix(struct azx * chip,int fix)1567 static void assign_position_fix(struct azx *chip, int fix)
1568 {
1569 static const azx_get_pos_callback_t callbacks[] = {
1570 [POS_FIX_AUTO] = NULL,
1571 [POS_FIX_LPIB] = azx_get_pos_lpib,
1572 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1573 [POS_FIX_VIACOMBO] = azx_via_get_position,
1574 [POS_FIX_COMBO] = azx_get_pos_lpib,
1575 [POS_FIX_SKL] = azx_get_pos_posbuf,
1576 [POS_FIX_FIFO] = azx_get_pos_fifo,
1577 };
1578
1579 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1580
1581 /* combo mode uses LPIB only for playback */
1582 if (fix == POS_FIX_COMBO)
1583 chip->get_position[1] = NULL;
1584
1585 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1586 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1587 chip->get_delay[0] = chip->get_delay[1] =
1588 azx_get_delay_from_lpib;
1589 }
1590
1591 if (fix == POS_FIX_FIFO)
1592 chip->get_delay[0] = chip->get_delay[1] =
1593 azx_get_delay_from_fifo;
1594 }
1595
1596 /*
1597 * deny-lists for probe_mask
1598 */
1599 static const struct snd_pci_quirk probe_mask_list[] = {
1600 /* Thinkpad often breaks the controller communication when accessing
1601 * to the non-working (or non-existing) modem codec slot.
1602 */
1603 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1604 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1605 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1606 /* broken BIOS */
1607 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1608 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1609 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1610 /* forced codec slots */
1611 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1612 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1613 SND_PCI_QUIRK(0x1558, 0x0351, "Schenker Dock 15", 0x105),
1614 /* WinFast VP200 H (Teradici) user reported broken communication */
1615 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1616 {}
1617 };
1618
1619 #define AZX_FORCE_CODEC_MASK 0x100
1620
check_probe_mask(struct azx * chip,int dev)1621 static void check_probe_mask(struct azx *chip, int dev)
1622 {
1623 const struct snd_pci_quirk *q;
1624
1625 chip->codec_probe_mask = probe_mask[dev];
1626 if (chip->codec_probe_mask == -1) {
1627 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1628 if (q) {
1629 dev_info(chip->card->dev,
1630 "probe_mask set to 0x%x for device %04x:%04x\n",
1631 q->value, q->subvendor, q->subdevice);
1632 chip->codec_probe_mask = q->value;
1633 }
1634 }
1635
1636 /* check forced option */
1637 if (chip->codec_probe_mask != -1 &&
1638 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1639 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1640 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1641 (int)azx_bus(chip)->codec_mask);
1642 }
1643 }
1644
1645 /*
1646 * allow/deny-list for enable_msi
1647 */
1648 static const struct snd_pci_quirk msi_deny_list[] = {
1649 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1650 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1651 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1652 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1653 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1654 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1655 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1656 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1657 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1658 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1659 {}
1660 };
1661
check_msi(struct azx * chip)1662 static void check_msi(struct azx *chip)
1663 {
1664 const struct snd_pci_quirk *q;
1665
1666 if (enable_msi >= 0) {
1667 chip->msi = !!enable_msi;
1668 return;
1669 }
1670 chip->msi = 1; /* enable MSI as default */
1671 q = snd_pci_quirk_lookup(chip->pci, msi_deny_list);
1672 if (q) {
1673 dev_info(chip->card->dev,
1674 "msi for device %04x:%04x set to %d\n",
1675 q->subvendor, q->subdevice, q->value);
1676 chip->msi = q->value;
1677 return;
1678 }
1679
1680 /* NVidia chipsets seem to cause troubles with MSI */
1681 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1682 dev_info(chip->card->dev, "Disabling MSI\n");
1683 chip->msi = 0;
1684 }
1685 }
1686
1687 /* check the snoop mode availability */
azx_check_snoop_available(struct azx * chip)1688 static void azx_check_snoop_available(struct azx *chip)
1689 {
1690 int snoop = hda_snoop;
1691
1692 if (snoop >= 0) {
1693 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1694 snoop ? "snoop" : "non-snoop");
1695 chip->snoop = snoop;
1696 chip->uc_buffer = !snoop;
1697 return;
1698 }
1699
1700 snoop = true;
1701 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1702 chip->driver_type == AZX_DRIVER_VIA) {
1703 /* force to non-snoop mode for a new VIA controller
1704 * when BIOS is set
1705 */
1706 u8 val;
1707 pci_read_config_byte(chip->pci, 0x42, &val);
1708 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1709 chip->pci->revision == 0x20))
1710 snoop = false;
1711 }
1712
1713 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1714 snoop = false;
1715
1716 chip->snoop = snoop;
1717 if (!snoop) {
1718 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1719 /* C-Media requires non-cached pages only for CORB/RIRB */
1720 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1721 chip->uc_buffer = true;
1722 }
1723 }
1724
azx_probe_work(struct work_struct * work)1725 static void azx_probe_work(struct work_struct *work)
1726 {
1727 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work.work);
1728 azx_probe_continue(&hda->chip);
1729 }
1730
default_bdl_pos_adj(struct azx * chip)1731 static int default_bdl_pos_adj(struct azx *chip)
1732 {
1733 /* some exceptions: Atoms seem problematic with value 1 */
1734 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1735 switch (chip->pci->device) {
1736 case PCI_DEVICE_ID_INTEL_HDA_BYT:
1737 case PCI_DEVICE_ID_INTEL_HDA_BSW:
1738 return 32;
1739 case PCI_DEVICE_ID_INTEL_HDA_APL:
1740 return 64;
1741 }
1742 }
1743
1744 switch (chip->driver_type) {
1745 /*
1746 * increase the bdl size for Glenfly Gpus for hardware
1747 * limitation on hdac interrupt interval
1748 */
1749 case AZX_DRIVER_GFHDMI:
1750 return 128;
1751 case AZX_DRIVER_ICH:
1752 case AZX_DRIVER_PCH:
1753 return 1;
1754 case AZX_DRIVER_ZHAOXINHDMI:
1755 return 128;
1756 default:
1757 return 32;
1758 }
1759 }
1760
1761 /*
1762 * constructor
1763 */
1764 static const struct hda_controller_ops pci_hda_ops;
1765
azx_create(struct snd_card * card,struct pci_dev * pci,int dev,unsigned int driver_caps,struct azx ** rchip)1766 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1767 int dev, unsigned int driver_caps,
1768 struct azx **rchip)
1769 {
1770 static const struct snd_device_ops ops = {
1771 .dev_disconnect = azx_dev_disconnect,
1772 .dev_free = azx_dev_free,
1773 };
1774 struct hda_intel *hda;
1775 struct azx *chip;
1776 int err;
1777
1778 *rchip = NULL;
1779
1780 err = pcim_enable_device(pci);
1781 if (err < 0)
1782 return err;
1783
1784 hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL);
1785 if (!hda)
1786 return -ENOMEM;
1787
1788 chip = &hda->chip;
1789 mutex_init(&chip->open_mutex);
1790 chip->card = card;
1791 chip->pci = pci;
1792 chip->ops = &pci_hda_ops;
1793 chip->driver_caps = driver_caps;
1794 chip->driver_type = driver_caps & 0xff;
1795 check_msi(chip);
1796 chip->dev_index = dev;
1797 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1798 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
1799 INIT_LIST_HEAD(&chip->pcm_list);
1800 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1801 INIT_LIST_HEAD(&hda->list);
1802 init_vga_switcheroo(chip);
1803 init_completion(&hda->probe_wait);
1804
1805 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1806
1807 if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1808 chip->fallback_to_single_cmd = 1;
1809 else /* explicitly set to single_cmd or not */
1810 chip->single_cmd = single_cmd;
1811
1812 azx_check_snoop_available(chip);
1813
1814 if (bdl_pos_adj[dev] < 0)
1815 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1816 else
1817 chip->bdl_pos_adj = bdl_pos_adj[dev];
1818
1819 err = azx_bus_init(chip, model[dev]);
1820 if (err < 0)
1821 return err;
1822
1823 /* use the non-cached pages in non-snoop mode */
1824 if (!azx_snoop(chip))
1825 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_WC;
1826
1827 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1828 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1829 chip->bus.core.needs_damn_long_delay = 1;
1830 }
1831
1832 check_probe_mask(chip, dev);
1833
1834 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1835 if (err < 0) {
1836 dev_err(card->dev, "Error creating device [card]!\n");
1837 azx_free(chip);
1838 return err;
1839 }
1840
1841 /* continue probing in work context as may trigger request module */
1842 INIT_DELAYED_WORK(&hda->probe_work, azx_probe_work);
1843
1844 *rchip = chip;
1845
1846 return 0;
1847 }
1848
azx_first_init(struct azx * chip)1849 static int azx_first_init(struct azx *chip)
1850 {
1851 int dev = chip->dev_index;
1852 struct pci_dev *pci = chip->pci;
1853 struct snd_card *card = chip->card;
1854 struct hdac_bus *bus = azx_bus(chip);
1855 int err;
1856 unsigned short gcap;
1857 unsigned int dma_bits = 64;
1858
1859 #if BITS_PER_LONG != 64
1860 /* Fix up base address on ULI M5461 */
1861 if (chip->driver_type == AZX_DRIVER_ULI) {
1862 u16 tmp3;
1863 pci_read_config_word(pci, 0x40, &tmp3);
1864 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1865 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1866 }
1867 #endif
1868 /*
1869 * Fix response write request not synced to memory when handle
1870 * hdac interrupt on Glenfly Gpus
1871 */
1872 if (chip->driver_type == AZX_DRIVER_GFHDMI)
1873 bus->polling_mode = 1;
1874
1875 if (chip->driver_type == AZX_DRIVER_LOONGSON) {
1876 bus->polling_mode = 1;
1877 bus->not_use_interrupts = 1;
1878 bus->access_sdnctl_in_dword = 1;
1879 if (!chip->jackpoll_interval)
1880 chip->jackpoll_interval = msecs_to_jiffies(1500);
1881 }
1882
1883 if (chip->driver_type == AZX_DRIVER_ZHAOXINHDMI)
1884 bus->polling_mode = 1;
1885
1886 bus->remap_addr = pcim_iomap_region(pci, 0, "ICH HD audio");
1887 if (IS_ERR(bus->remap_addr))
1888 return PTR_ERR(bus->remap_addr);
1889
1890 bus->addr = pci_resource_start(pci, 0);
1891
1892 if (chip->driver_type == AZX_DRIVER_SKL)
1893 snd_hdac_bus_parse_capabilities(bus);
1894
1895 /*
1896 * Some Intel CPUs has always running timer (ART) feature and
1897 * controller may have Global time sync reporting capability, so
1898 * check both of these before declaring synchronized time reporting
1899 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1900 */
1901 chip->gts_present = false;
1902
1903 #ifdef CONFIG_X86
1904 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1905 chip->gts_present = true;
1906 #endif
1907
1908 if (chip->msi && chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1909 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1910 pci->no_64bit_msi = true;
1911 }
1912
1913 pci_set_master(pci);
1914
1915 gcap = azx_readw(chip, GCAP);
1916 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1917
1918 /* AMD devices support 40 or 48bit DMA, take the safe one */
1919 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1920 dma_bits = 40;
1921
1922 /* disable SB600 64bit support for safety */
1923 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1924 struct pci_dev *p_smbus;
1925 dma_bits = 40;
1926 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1927 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1928 NULL);
1929 if (p_smbus) {
1930 if (p_smbus->revision < 0x30)
1931 gcap &= ~AZX_GCAP_64OK;
1932 pci_dev_put(p_smbus);
1933 }
1934 }
1935
1936 /* NVidia hardware normally only supports up to 40 bits of DMA */
1937 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1938 dma_bits = 40;
1939
1940 /* disable 64bit DMA address on some devices */
1941 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1942 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1943 gcap &= ~AZX_GCAP_64OK;
1944 }
1945
1946 /* disable buffer size rounding to 128-byte multiples if supported */
1947 if (align_buffer_size >= 0)
1948 chip->align_buffer_size = !!align_buffer_size;
1949 else {
1950 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1951 chip->align_buffer_size = 0;
1952 else
1953 chip->align_buffer_size = 1;
1954 }
1955
1956 /* allow 64bit DMA address if supported by H/W */
1957 if (!(gcap & AZX_GCAP_64OK))
1958 dma_bits = 32;
1959 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(dma_bits)))
1960 dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32));
1961 dma_set_max_seg_size(&pci->dev, UINT_MAX);
1962
1963 /* read number of streams from GCAP register instead of using
1964 * hardcoded value
1965 */
1966 chip->capture_streams = (gcap >> 8) & 0x0f;
1967 chip->playback_streams = (gcap >> 12) & 0x0f;
1968 if (!chip->playback_streams && !chip->capture_streams) {
1969 /* gcap didn't give any info, switching to old method */
1970
1971 switch (chip->driver_type) {
1972 case AZX_DRIVER_ULI:
1973 chip->playback_streams = ULI_NUM_PLAYBACK;
1974 chip->capture_streams = ULI_NUM_CAPTURE;
1975 break;
1976 case AZX_DRIVER_ATIHDMI:
1977 case AZX_DRIVER_ATIHDMI_NS:
1978 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1979 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1980 break;
1981 case AZX_DRIVER_GFHDMI:
1982 case AZX_DRIVER_ZHAOXINHDMI:
1983 case AZX_DRIVER_GENERIC:
1984 default:
1985 chip->playback_streams = ICH6_NUM_PLAYBACK;
1986 chip->capture_streams = ICH6_NUM_CAPTURE;
1987 break;
1988 }
1989 }
1990 chip->capture_index_offset = 0;
1991 chip->playback_index_offset = chip->capture_streams;
1992 chip->num_streams = chip->playback_streams + chip->capture_streams;
1993
1994 /* sanity check for the SDxCTL.STRM field overflow */
1995 if (chip->num_streams > 15 &&
1996 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1997 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1998 "forcing separate stream tags", chip->num_streams);
1999 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
2000 }
2001
2002 /* initialize streams */
2003 err = azx_init_streams(chip);
2004 if (err < 0)
2005 return err;
2006
2007 err = azx_alloc_stream_pages(chip);
2008 if (err < 0)
2009 return err;
2010
2011 /* initialize chip */
2012 azx_init_pci(chip);
2013
2014 snd_hdac_i915_set_bclk(bus);
2015
2016 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
2017
2018 /* codec detection */
2019 if (!azx_bus(chip)->codec_mask) {
2020 dev_err(card->dev, "no codecs found!\n");
2021 /* keep running the rest for the runtime PM */
2022 }
2023
2024 if (azx_acquire_irq(chip, 0) < 0)
2025 return -EBUSY;
2026
2027 strscpy(card->driver, "HDA-Intel");
2028 strscpy(card->shortname, driver_short_names[chip->driver_type],
2029 sizeof(card->shortname));
2030 snprintf(card->longname, sizeof(card->longname),
2031 "%s at 0x%lx irq %i",
2032 card->shortname, bus->addr, bus->irq);
2033
2034 return 0;
2035 }
2036
2037 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2038 /* callback from request_firmware_nowait() */
azx_firmware_cb(const struct firmware * fw,void * context)2039 static void azx_firmware_cb(const struct firmware *fw, void *context)
2040 {
2041 struct snd_card *card = context;
2042 struct azx *chip = card->private_data;
2043
2044 if (fw)
2045 chip->fw = fw;
2046 else
2047 dev_err(card->dev, "Cannot load firmware, continue without patching\n");
2048 if (!chip->disabled) {
2049 /* continue probing */
2050 azx_probe_continue(chip);
2051 }
2052 }
2053 #endif
2054
disable_msi_reset_irq(struct azx * chip)2055 static int disable_msi_reset_irq(struct azx *chip)
2056 {
2057 struct hdac_bus *bus = azx_bus(chip);
2058 int err;
2059
2060 free_irq(bus->irq, chip);
2061 bus->irq = -1;
2062 chip->card->sync_irq = -1;
2063 pci_free_irq_vectors(chip->pci);
2064 chip->msi = 0;
2065 err = azx_acquire_irq(chip, 1);
2066 if (err < 0)
2067 return err;
2068
2069 return 0;
2070 }
2071
2072 /* Denylist for skipping the whole probe:
2073 * some HD-audio PCI entries are exposed without any codecs, and such devices
2074 * should be ignored from the beginning.
2075 */
2076 static const struct pci_device_id driver_denylist[] = {
2077 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */
2078 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */
2079 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */
2080 { PCI_DEVICE_SUB(0x1022, 0x15e3, 0x1022, 0xd601) }, /* ASRock X670E Taichi */
2081 {}
2082 };
2083
2084 static struct pci_device_id driver_denylist_ideapad_z570[] = {
2085 { PCI_DEVICE_SUB(0x10de, 0x0bea, 0x0000, 0x0000) }, /* NVIDIA GF108 HDA */
2086 {}
2087 };
2088
2089 /* DMI-based denylist, to be used when:
2090 * - PCI subsystem IDs are zero, impossible to distinguish from valid sound cards.
2091 * - Different modifications of the same laptop use different GPU models.
2092 */
2093 static const struct dmi_system_id driver_denylist_dmi[] = {
2094 {
2095 /* No HDA in NVIDIA DGPU. BIOS disables it, but quirk_nvidia_hda() reenables. */
2096 .matches = {
2097 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
2098 DMI_MATCH(DMI_PRODUCT_VERSION, "Ideapad Z570"),
2099 },
2100 .driver_data = &driver_denylist_ideapad_z570,
2101 },
2102 {}
2103 };
2104
2105 static const struct hda_controller_ops pci_hda_ops = {
2106 .disable_msi_reset_irq = disable_msi_reset_irq,
2107 .position_check = azx_position_check,
2108 };
2109
2110 static DECLARE_BITMAP(probed_devs, SNDRV_CARDS);
2111
azx_probe(struct pci_dev * pci,const struct pci_device_id * pci_id)2112 static int azx_probe(struct pci_dev *pci,
2113 const struct pci_device_id *pci_id)
2114 {
2115 const struct dmi_system_id *dmi;
2116 struct snd_card *card;
2117 struct hda_intel *hda;
2118 struct azx *chip;
2119 bool schedule_probe;
2120 int dev;
2121 int err;
2122
2123 if (pci_match_id(driver_denylist, pci)) {
2124 dev_info(&pci->dev, "Skipping the device on the denylist\n");
2125 return -ENODEV;
2126 }
2127
2128 dmi = dmi_first_match(driver_denylist_dmi);
2129 if (dmi && pci_match_id(dmi->driver_data, pci)) {
2130 dev_info(&pci->dev, "Skipping the device on the DMI denylist\n");
2131 return -ENODEV;
2132 }
2133
2134 dev = find_first_zero_bit(probed_devs, SNDRV_CARDS);
2135 if (dev >= SNDRV_CARDS)
2136 return -ENODEV;
2137 if (!enable[dev]) {
2138 set_bit(dev, probed_devs);
2139 return -ENOENT;
2140 }
2141
2142 /*
2143 * stop probe if another Intel's DSP driver should be activated
2144 */
2145 if (dmic_detect) {
2146 err = snd_intel_dsp_driver_probe(pci);
2147 if (err != SND_INTEL_DSP_DRIVER_ANY && err != SND_INTEL_DSP_DRIVER_LEGACY) {
2148 dev_dbg(&pci->dev, "HDAudio driver not selected, aborting probe\n");
2149 return -ENODEV;
2150 }
2151 } else {
2152 dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n");
2153 }
2154
2155 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2156 0, &card);
2157 if (err < 0) {
2158 dev_err(&pci->dev, "Error creating card!\n");
2159 return err;
2160 }
2161
2162 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2163 if (err < 0)
2164 goto out_free;
2165 card->private_data = chip;
2166 hda = container_of(chip, struct hda_intel, chip);
2167
2168 pci_set_drvdata(pci, card);
2169
2170 #ifdef CONFIG_SND_HDA_I915
2171 /* bind with i915 if needed */
2172 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
2173 err = snd_hdac_i915_init(azx_bus(chip));
2174 if (err < 0) {
2175 if (err == -EPROBE_DEFER)
2176 goto out_free;
2177
2178 /* if the controller is bound only with HDMI/DP
2179 * (for HSW and BDW), we need to abort the probe;
2180 * for other chips, still continue probing as other
2181 * codecs can be on the same link.
2182 */
2183 if (HDA_CONTROLLER_IN_GPU(pci)) {
2184 dev_err_probe(card->dev, err,
2185 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2186
2187 goto out_free;
2188 } else {
2189 /* don't bother any longer */
2190 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
2191 }
2192 }
2193
2194 /* HSW/BDW controllers need this power */
2195 if (HDA_CONTROLLER_IN_GPU(pci))
2196 hda->need_i915_power = true;
2197 }
2198 #else
2199 if (HDA_CONTROLLER_IN_GPU(pci))
2200 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2201 #endif
2202
2203 err = register_vga_switcheroo(chip);
2204 if (err < 0) {
2205 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2206 goto out_free;
2207 }
2208
2209 if (check_hdmi_disabled(pci)) {
2210 dev_info(card->dev, "VGA controller is disabled\n");
2211 dev_info(card->dev, "Delaying initialization\n");
2212 chip->disabled = true;
2213 }
2214
2215 schedule_probe = !chip->disabled;
2216
2217 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2218 if (patch[dev] && *patch[dev]) {
2219 dev_info(card->dev, "Applying patch firmware '%s'\n",
2220 patch[dev]);
2221 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2222 &pci->dev, GFP_KERNEL, card,
2223 azx_firmware_cb);
2224 if (err < 0)
2225 goto out_free;
2226 schedule_probe = false; /* continued in azx_firmware_cb() */
2227 }
2228 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2229
2230 if (schedule_probe)
2231 schedule_delayed_work(&hda->probe_work, 0);
2232
2233 set_bit(dev, probed_devs);
2234 if (chip->disabled)
2235 complete_all(&hda->probe_wait);
2236 return 0;
2237
2238 out_free:
2239 pci_set_drvdata(pci, NULL);
2240 snd_card_free(card);
2241 return err;
2242 }
2243
2244 /* On some boards setting power_save to a non 0 value leads to clicking /
2245 * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2246 * figure out how to avoid these sounds, but that is not always feasible.
2247 * So we keep a list of devices where we disable powersaving as its known
2248 * to causes problems on these devices.
2249 */
2250 static const struct snd_pci_quirk power_save_denylist[] = {
2251 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2252 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2253 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2254 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2255 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2256 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2257 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2258 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2259 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2260 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2261 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2262 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2263 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
2264 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2265 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
2266 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2267 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
2268 /* https://bugs.launchpad.net/bugs/1821663 */
2269 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
2270 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2271 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
2272 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2273 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2274 SND_PCI_QUIRK(0x17aa, 0x316e, "Lenovo ThinkCentre M70q", 0),
2275 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2276 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2277 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2278 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2279 /* https://bugs.launchpad.net/bugs/1821663 */
2280 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
2281 /* KONTRON SinglePC may cause a stall at runtime resume */
2282 SND_PCI_QUIRK(0x1734, 0x1232, "KONTRON SinglePC", 0),
2283 /* Dell ALC3271 */
2284 SND_PCI_QUIRK(0x1028, 0x0962, "Dell ALC3271", 0),
2285 /* https://bugzilla.kernel.org/show_bug.cgi?id=220210 */
2286 SND_PCI_QUIRK(0x17aa, 0x5079, "Lenovo Thinkpad E15", 0),
2287 {}
2288 };
2289
set_default_power_save(struct azx * chip)2290 static void set_default_power_save(struct azx *chip)
2291 {
2292 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2293 int val = power_save;
2294
2295 if (pm_blacklist < 0) {
2296 const struct snd_pci_quirk *q;
2297
2298 q = snd_pci_quirk_lookup(chip->pci, power_save_denylist);
2299 if (q && val) {
2300 dev_info(chip->card->dev, "device %04x:%04x is on the power_save denylist, forcing power_save to 0\n",
2301 q->subvendor, q->subdevice);
2302 val = 0;
2303 hda->runtime_pm_disabled = 1;
2304 }
2305 } else if (pm_blacklist > 0) {
2306 dev_info(chip->card->dev, "Forcing power_save to 0 via option\n");
2307 val = 0;
2308 }
2309 snd_hda_set_power_save(&chip->bus, val * 1000);
2310 }
2311
2312 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2313 static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2314 [AZX_DRIVER_NVIDIA] = 8,
2315 [AZX_DRIVER_TERA] = 1,
2316 };
2317
azx_probe_continue(struct azx * chip)2318 static int azx_probe_continue(struct azx *chip)
2319 {
2320 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2321 struct hdac_bus *bus = azx_bus(chip);
2322 struct pci_dev *pci = chip->pci;
2323 int dev = chip->dev_index;
2324 int err;
2325
2326 if (chip->disabled || hda->init_failed)
2327 return -EIO;
2328 if (hda->probe_retry)
2329 goto probe_retry;
2330
2331 to_hda_bus(bus)->bus_probing = 1;
2332 hda->probe_continued = 1;
2333
2334 /* Request display power well for the HDA controller or codec. For
2335 * Haswell/Broadwell, both the display HDA controller and codec need
2336 * this power. For other platforms, like Baytrail/Braswell, only the
2337 * display codec needs the power and it can be released after probe.
2338 */
2339 display_power(chip, true);
2340
2341 err = azx_first_init(chip);
2342 if (err < 0)
2343 goto out_free;
2344
2345 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2346 chip->beep_mode = beep_mode[dev];
2347 #endif
2348
2349 chip->ctl_dev_id = ctl_dev_id;
2350
2351 /* create codec instances */
2352 if (bus->codec_mask) {
2353 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2354 if (err < 0)
2355 goto out_free;
2356 }
2357
2358 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2359 if (chip->fw) {
2360 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2361 chip->fw->data);
2362 if (err < 0)
2363 goto out_free;
2364 }
2365 #endif
2366
2367 probe_retry:
2368 if (bus->codec_mask && !(probe_only[dev] & 1)) {
2369 err = azx_codec_configure(chip);
2370 if (err) {
2371 if ((chip->driver_caps & AZX_DCAPS_RETRY_PROBE) &&
2372 ++hda->probe_retry < 60) {
2373 schedule_delayed_work(&hda->probe_work,
2374 msecs_to_jiffies(1000));
2375 return 0; /* keep things up */
2376 }
2377 dev_err(chip->card->dev, "Cannot probe codecs, giving up\n");
2378 goto out_free;
2379 }
2380 }
2381
2382 err = snd_card_register(chip->card);
2383 if (err < 0)
2384 goto out_free;
2385
2386 setup_vga_switcheroo_runtime_pm(chip);
2387
2388 chip->running = 1;
2389 azx_add_card_list(chip);
2390
2391 set_default_power_save(chip);
2392
2393 if (azx_has_pm_runtime(chip)) {
2394 pm_runtime_use_autosuspend(&pci->dev);
2395 pm_runtime_allow(&pci->dev);
2396 pm_runtime_put_autosuspend(&pci->dev);
2397 }
2398
2399 out_free:
2400 if (err < 0) {
2401 pci_set_drvdata(pci, NULL);
2402 snd_card_free(chip->card);
2403 return err;
2404 }
2405
2406 if (!hda->need_i915_power)
2407 display_power(chip, false);
2408 complete_all(&hda->probe_wait);
2409 to_hda_bus(bus)->bus_probing = 0;
2410 hda->probe_retry = 0;
2411 return 0;
2412 }
2413
azx_remove(struct pci_dev * pci)2414 static void azx_remove(struct pci_dev *pci)
2415 {
2416 struct snd_card *card = pci_get_drvdata(pci);
2417 struct azx *chip;
2418 struct hda_intel *hda;
2419
2420 if (card) {
2421 /* cancel the pending probing work */
2422 chip = card->private_data;
2423 hda = container_of(chip, struct hda_intel, chip);
2424 /* FIXME: below is an ugly workaround.
2425 * Both device_release_driver() and driver_probe_device()
2426 * take *both* the device's and its parent's lock before
2427 * calling the remove() and probe() callbacks. The codec
2428 * probe takes the locks of both the codec itself and its
2429 * parent, i.e. the PCI controller dev. Meanwhile, when
2430 * the PCI controller is unbound, it takes its lock, too
2431 * ==> ouch, a deadlock!
2432 * As a workaround, we unlock temporarily here the controller
2433 * device during cancel_work_sync() call.
2434 */
2435 device_unlock(&pci->dev);
2436 cancel_delayed_work_sync(&hda->probe_work);
2437 device_lock(&pci->dev);
2438
2439 clear_bit(chip->dev_index, probed_devs);
2440 pci_set_drvdata(pci, NULL);
2441 snd_card_free(card);
2442 }
2443 }
2444
azx_shutdown(struct pci_dev * pci)2445 static void azx_shutdown(struct pci_dev *pci)
2446 {
2447 struct snd_card *card = pci_get_drvdata(pci);
2448 struct azx *chip;
2449
2450 if (!card)
2451 return;
2452 chip = card->private_data;
2453 if (chip && chip->running)
2454 __azx_shutdown_chip(chip, true);
2455 }
2456
2457 /* PCI IDs */
2458 static const struct pci_device_id azx_ids[] = {
2459 /* CPT */
2460 { PCI_DEVICE_DATA(INTEL, HDA_CPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) },
2461 /* PBG */
2462 { PCI_DEVICE_DATA(INTEL, HDA_PBG, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) },
2463 /* Panther Point */
2464 { PCI_DEVICE_DATA(INTEL, HDA_PPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) },
2465 /* Lynx Point */
2466 { PCI_DEVICE_DATA(INTEL, HDA_LPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
2467 /* 9 Series */
2468 { PCI_DEVICE_DATA(INTEL, HDA_9_SERIES, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
2469 /* Wellsburg */
2470 { PCI_DEVICE_DATA(INTEL, HDA_WBG_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
2471 { PCI_DEVICE_DATA(INTEL, HDA_WBG_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
2472 /* Lewisburg */
2473 { PCI_DEVICE_DATA(INTEL, HDA_LBG_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE) },
2474 { PCI_DEVICE_DATA(INTEL, HDA_LBG_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE) },
2475 /* Lynx Point-LP */
2476 { PCI_DEVICE_DATA(INTEL, HDA_LPT_LP_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
2477 /* Lynx Point-LP */
2478 { PCI_DEVICE_DATA(INTEL, HDA_LPT_LP_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
2479 /* Wildcat Point-LP */
2480 { PCI_DEVICE_DATA(INTEL, HDA_WPT_LP, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
2481 /* Skylake (Sunrise Point) */
2482 { PCI_DEVICE_DATA(INTEL, HDA_SKL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2483 /* Skylake-LP (Sunrise Point-LP) */
2484 { PCI_DEVICE_DATA(INTEL, HDA_SKL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2485 /* Kabylake */
2486 { PCI_DEVICE_DATA(INTEL, HDA_KBL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2487 /* Kabylake-LP */
2488 { PCI_DEVICE_DATA(INTEL, HDA_KBL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2489 /* Kabylake-H */
2490 { PCI_DEVICE_DATA(INTEL, HDA_KBL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2491 /* Coffelake */
2492 { PCI_DEVICE_DATA(INTEL, HDA_CNL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2493 /* Cannonlake */
2494 { PCI_DEVICE_DATA(INTEL, HDA_CNL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2495 /* CometLake-LP */
2496 { PCI_DEVICE_DATA(INTEL, HDA_CML_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2497 /* CometLake-H */
2498 { PCI_DEVICE_DATA(INTEL, HDA_CML_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2499 { PCI_DEVICE_DATA(INTEL, HDA_RKL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2500 /* CometLake-S */
2501 { PCI_DEVICE_DATA(INTEL, HDA_CML_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2502 /* CometLake-R */
2503 { PCI_DEVICE_DATA(INTEL, HDA_CML_R, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2504 /* Icelake */
2505 { PCI_DEVICE_DATA(INTEL, HDA_ICL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2506 /* Icelake-H */
2507 { PCI_DEVICE_DATA(INTEL, HDA_ICL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2508 /* Jasperlake */
2509 { PCI_DEVICE_DATA(INTEL, HDA_ICL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2510 { PCI_DEVICE_DATA(INTEL, HDA_JSL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2511 /* Tigerlake */
2512 { PCI_DEVICE_DATA(INTEL, HDA_TGL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2513 /* Tigerlake-H */
2514 { PCI_DEVICE_DATA(INTEL, HDA_TGL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2515 /* DG1 */
2516 { PCI_DEVICE_DATA(INTEL, HDA_DG1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2517 /* DG2 */
2518 { PCI_DEVICE_DATA(INTEL, HDA_DG2_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2519 { PCI_DEVICE_DATA(INTEL, HDA_DG2_1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2520 { PCI_DEVICE_DATA(INTEL, HDA_DG2_2, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2521 /* Alderlake-S */
2522 { PCI_DEVICE_DATA(INTEL, HDA_ADL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2523 /* Alderlake-P */
2524 { PCI_DEVICE_DATA(INTEL, HDA_ADL_P, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2525 { PCI_DEVICE_DATA(INTEL, HDA_ADL_PS, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2526 { PCI_DEVICE_DATA(INTEL, HDA_ADL_PX, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2527 /* Alderlake-M */
2528 { PCI_DEVICE_DATA(INTEL, HDA_ADL_M, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2529 /* Alderlake-N */
2530 { PCI_DEVICE_DATA(INTEL, HDA_ADL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2531 /* Elkhart Lake */
2532 { PCI_DEVICE_DATA(INTEL, HDA_EHL_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2533 { PCI_DEVICE_DATA(INTEL, HDA_EHL_3, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2534 /* Raptor Lake */
2535 { PCI_DEVICE_DATA(INTEL, HDA_RPL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2536 { PCI_DEVICE_DATA(INTEL, HDA_RPL_P_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2537 { PCI_DEVICE_DATA(INTEL, HDA_RPL_P_1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2538 { PCI_DEVICE_DATA(INTEL, HDA_RPL_M, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2539 { PCI_DEVICE_DATA(INTEL, HDA_RPL_PX, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2540 { PCI_DEVICE_DATA(INTEL, HDA_MTL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2541 /* Battlemage */
2542 { PCI_DEVICE_DATA(INTEL, HDA_BMG, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2543 /* Lunarlake-P */
2544 { PCI_DEVICE_DATA(INTEL, HDA_LNL_P, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_LNL) },
2545 /* Arrow Lake-S */
2546 { PCI_DEVICE_DATA(INTEL, HDA_ARL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2547 /* Arrow Lake */
2548 { PCI_DEVICE_DATA(INTEL, HDA_ARL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2549 /* Panther Lake */
2550 { PCI_DEVICE_DATA(INTEL, HDA_PTL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_LNL) },
2551 /* Panther Lake-H */
2552 { PCI_DEVICE_DATA(INTEL, HDA_PTL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_LNL) },
2553 /* Wildcat Lake */
2554 { PCI_DEVICE_DATA(INTEL, HDA_WCL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_LNL) },
2555 /* Apollolake (Broxton-P) */
2556 { PCI_DEVICE_DATA(INTEL, HDA_APL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON) },
2557 /* Gemini-Lake */
2558 { PCI_DEVICE_DATA(INTEL, HDA_GML, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON) },
2559 /* Haswell */
2560 { PCI_DEVICE_DATA(INTEL, HDA_HSW_0, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) },
2561 { PCI_DEVICE_DATA(INTEL, HDA_HSW_2, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) },
2562 { PCI_DEVICE_DATA(INTEL, HDA_HSW_3, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) },
2563 /* Broadwell */
2564 { PCI_DEVICE_DATA(INTEL, HDA_BDW, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL) },
2565 /* 5 Series/3400 */
2566 { PCI_DEVICE_DATA(INTEL, HDA_5_3400_SERIES_0, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM) },
2567 { PCI_DEVICE_DATA(INTEL, HDA_5_3400_SERIES_1, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM) },
2568 /* Poulsbo */
2569 { PCI_DEVICE_DATA(INTEL, HDA_POULSBO, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE |
2570 AZX_DCAPS_POSFIX_LPIB) },
2571 /* Oaktrail */
2572 { PCI_DEVICE_DATA(INTEL, HDA_OAKTRAIL, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE) },
2573 /* BayTrail */
2574 { PCI_DEVICE_DATA(INTEL, HDA_BYT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL) },
2575 /* Braswell */
2576 { PCI_DEVICE_DATA(INTEL, HDA_BSW, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL) },
2577 /* ICH6 */
2578 { PCI_DEVICE_DATA(INTEL, HDA_ICH6, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
2579 /* ICH7 */
2580 { PCI_DEVICE_DATA(INTEL, HDA_ICH7, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
2581 /* ESB2 */
2582 { PCI_DEVICE_DATA(INTEL, HDA_ESB2, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
2583 /* ICH8 */
2584 { PCI_DEVICE_DATA(INTEL, HDA_ICH8, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
2585 /* ICH9 */
2586 { PCI_DEVICE_DATA(INTEL, HDA_ICH9_0, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
2587 /* ICH9 */
2588 { PCI_DEVICE_DATA(INTEL, HDA_ICH9_1, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
2589 /* ICH10 */
2590 { PCI_DEVICE_DATA(INTEL, HDA_ICH10_0, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
2591 /* ICH10 */
2592 { PCI_DEVICE_DATA(INTEL, HDA_ICH10_1, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
2593 /* Generic Intel */
2594 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2595 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2596 .class_mask = 0xffffff,
2597 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2598 /* ATI SB 450/600/700/800/900 */
2599 { PCI_VDEVICE(ATI, 0x437b),
2600 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2601 { PCI_VDEVICE(ATI, 0x4383),
2602 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2603 /* AMD Hudson */
2604 { PCI_VDEVICE(AMD, 0x780d),
2605 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2606 /* AMD, X370 & co */
2607 { PCI_VDEVICE(AMD, 0x1457),
2608 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2609 /* AMD, X570 & co */
2610 { PCI_VDEVICE(AMD, 0x1487),
2611 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2612 /* AMD Stoney */
2613 { PCI_VDEVICE(AMD, 0x157a),
2614 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2615 AZX_DCAPS_PM_RUNTIME },
2616 /* AMD Raven */
2617 { PCI_VDEVICE(AMD, 0x15e3),
2618 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2619 /* ATI HDMI */
2620 { PCI_VDEVICE(ATI, 0x0002),
2621 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2622 AZX_DCAPS_PM_RUNTIME },
2623 { PCI_VDEVICE(ATI, 0x1308),
2624 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2625 { PCI_VDEVICE(ATI, 0x157a),
2626 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2627 { PCI_VDEVICE(ATI, 0x15b3),
2628 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2629 { PCI_VDEVICE(ATI, 0x793b),
2630 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2631 { PCI_VDEVICE(ATI, 0x7919),
2632 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2633 { PCI_VDEVICE(ATI, 0x960f),
2634 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2635 { PCI_VDEVICE(ATI, 0x970f),
2636 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2637 { PCI_VDEVICE(ATI, 0x9840),
2638 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2639 { PCI_VDEVICE(ATI, 0xaa00),
2640 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2641 { PCI_VDEVICE(ATI, 0xaa08),
2642 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2643 { PCI_VDEVICE(ATI, 0xaa10),
2644 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2645 { PCI_VDEVICE(ATI, 0xaa18),
2646 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2647 { PCI_VDEVICE(ATI, 0xaa20),
2648 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2649 { PCI_VDEVICE(ATI, 0xaa28),
2650 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2651 { PCI_VDEVICE(ATI, 0xaa30),
2652 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2653 { PCI_VDEVICE(ATI, 0xaa38),
2654 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2655 { PCI_VDEVICE(ATI, 0xaa40),
2656 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2657 { PCI_VDEVICE(ATI, 0xaa48),
2658 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2659 { PCI_VDEVICE(ATI, 0xaa50),
2660 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2661 { PCI_VDEVICE(ATI, 0xaa58),
2662 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2663 { PCI_VDEVICE(ATI, 0xaa60),
2664 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2665 { PCI_VDEVICE(ATI, 0xaa68),
2666 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2667 { PCI_VDEVICE(ATI, 0xaa80),
2668 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2669 { PCI_VDEVICE(ATI, 0xaa88),
2670 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2671 { PCI_VDEVICE(ATI, 0xaa90),
2672 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2673 { PCI_VDEVICE(ATI, 0xaa98),
2674 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2675 { PCI_VDEVICE(ATI, 0x9902),
2676 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2677 { PCI_VDEVICE(ATI, 0xaaa0),
2678 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2679 { PCI_VDEVICE(ATI, 0xaaa8),
2680 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2681 { PCI_VDEVICE(ATI, 0xaab0),
2682 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2683 { PCI_VDEVICE(ATI, 0xaac0),
2684 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2685 AZX_DCAPS_PM_RUNTIME },
2686 { PCI_VDEVICE(ATI, 0xaac8),
2687 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2688 AZX_DCAPS_PM_RUNTIME },
2689 { PCI_VDEVICE(ATI, 0xaad8),
2690 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2691 AZX_DCAPS_PM_RUNTIME },
2692 { PCI_VDEVICE(ATI, 0xaae0),
2693 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2694 AZX_DCAPS_PM_RUNTIME },
2695 { PCI_VDEVICE(ATI, 0xaae8),
2696 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2697 AZX_DCAPS_PM_RUNTIME },
2698 { PCI_VDEVICE(ATI, 0xaaf0),
2699 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2700 AZX_DCAPS_PM_RUNTIME },
2701 { PCI_VDEVICE(ATI, 0xaaf8),
2702 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2703 AZX_DCAPS_PM_RUNTIME },
2704 { PCI_VDEVICE(ATI, 0xab00),
2705 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2706 AZX_DCAPS_PM_RUNTIME },
2707 { PCI_VDEVICE(ATI, 0xab08),
2708 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2709 AZX_DCAPS_PM_RUNTIME },
2710 { PCI_VDEVICE(ATI, 0xab10),
2711 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2712 AZX_DCAPS_PM_RUNTIME },
2713 { PCI_VDEVICE(ATI, 0xab18),
2714 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2715 AZX_DCAPS_PM_RUNTIME },
2716 { PCI_VDEVICE(ATI, 0xab20),
2717 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2718 AZX_DCAPS_PM_RUNTIME },
2719 { PCI_VDEVICE(ATI, 0xab28),
2720 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2721 AZX_DCAPS_PM_RUNTIME },
2722 { PCI_VDEVICE(ATI, 0xab30),
2723 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2724 AZX_DCAPS_PM_RUNTIME },
2725 { PCI_VDEVICE(ATI, 0xab38),
2726 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2727 AZX_DCAPS_PM_RUNTIME },
2728 { PCI_VDEVICE(ATI, 0xab40),
2729 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2730 AZX_DCAPS_PM_RUNTIME },
2731 /* GLENFLY */
2732 { PCI_DEVICE(PCI_VENDOR_ID_GLENFLY, PCI_ANY_ID),
2733 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2734 .class_mask = 0xffffff,
2735 .driver_data = AZX_DRIVER_GFHDMI | AZX_DCAPS_POSFIX_LPIB |
2736 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT },
2737 /* VIA VT8251/VT8237A */
2738 { PCI_VDEVICE(VIA, 0x3288), .driver_data = AZX_DRIVER_VIA },
2739 /* VIA GFX VT7122/VX900 */
2740 { PCI_VDEVICE(VIA, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2741 /* VIA GFX VT6122/VX11 */
2742 { PCI_VDEVICE(VIA, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2743 /* SIS966 */
2744 { PCI_VDEVICE(SI, 0x7502), .driver_data = AZX_DRIVER_SIS },
2745 /* ULI M5461 */
2746 { PCI_VDEVICE(AL, 0x5461), .driver_data = AZX_DRIVER_ULI },
2747 /* NVIDIA MCP */
2748 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2749 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2750 .class_mask = 0xffffff,
2751 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2752 /* Teradici */
2753 { PCI_DEVICE(0x6549, 0x1200),
2754 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2755 { PCI_DEVICE(0x6549, 0x2200),
2756 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2757 /* Creative X-Fi (CA0110-IBG) */
2758 /* CTHDA chips */
2759 { PCI_VDEVICE(CREATIVE, 0x0010),
2760 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2761 { PCI_VDEVICE(CREATIVE, 0x0012),
2762 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2763 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2764 /* the following entry conflicts with snd-ctxfi driver,
2765 * as ctxfi driver mutates from HD-audio to native mode with
2766 * a special command sequence.
2767 */
2768 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2769 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2770 .class_mask = 0xffffff,
2771 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2772 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2773 #else
2774 /* this entry seems still valid -- i.e. without emu20kx chip */
2775 { PCI_VDEVICE(CREATIVE, 0x0009),
2776 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2777 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2778 #endif
2779 /* CM8888 */
2780 { PCI_VDEVICE(CMEDIA, 0x5011),
2781 .driver_data = AZX_DRIVER_CMEDIA |
2782 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2783 /* Vortex86MX */
2784 { PCI_VDEVICE(RDC, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2785 /* VMware HDAudio */
2786 { PCI_VDEVICE(VMWARE, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2787 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2788 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2789 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2790 .class_mask = 0xffffff,
2791 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2792 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2793 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2794 .class_mask = 0xffffff,
2795 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2796 /* Zhaoxin */
2797 { PCI_VDEVICE(ZHAOXIN, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN },
2798 { PCI_VDEVICE(ZHAOXIN, 0x9141),
2799 .driver_data = AZX_DRIVER_ZHAOXINHDMI | AZX_DCAPS_POSFIX_LPIB |
2800 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT },
2801 { PCI_VDEVICE(ZHAOXIN, 0x9142),
2802 .driver_data = AZX_DRIVER_ZHAOXINHDMI | AZX_DCAPS_POSFIX_LPIB |
2803 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT },
2804 { PCI_VDEVICE(ZHAOXIN, 0x9144),
2805 .driver_data = AZX_DRIVER_ZHAOXINHDMI | AZX_DCAPS_POSFIX_LPIB |
2806 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT },
2807 { PCI_VDEVICE(ZHAOXIN, 0x9145),
2808 .driver_data = AZX_DRIVER_ZHAOXINHDMI | AZX_DCAPS_POSFIX_LPIB |
2809 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT },
2810 { PCI_VDEVICE(ZHAOXIN, 0x9146),
2811 .driver_data = AZX_DRIVER_ZHAOXINHDMI | AZX_DCAPS_POSFIX_LPIB |
2812 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT },
2813 /* Loongson HDAudio*/
2814 { PCI_VDEVICE(LOONGSON, PCI_DEVICE_ID_LOONGSON_HDA),
2815 .driver_data = AZX_DRIVER_LOONGSON | AZX_DCAPS_NO_TCSEL },
2816 { PCI_VDEVICE(LOONGSON, PCI_DEVICE_ID_LOONGSON_HDMI),
2817 .driver_data = AZX_DRIVER_LOONGSON | AZX_DCAPS_NO_TCSEL },
2818 { 0, }
2819 };
2820 MODULE_DEVICE_TABLE(pci, azx_ids);
2821
2822 /* pci_driver definition */
2823 static struct pci_driver azx_driver = {
2824 .name = KBUILD_MODNAME,
2825 .id_table = azx_ids,
2826 .probe = azx_probe,
2827 .remove = azx_remove,
2828 .shutdown = azx_shutdown,
2829 .driver = {
2830 .pm = pm_ptr(&azx_pm),
2831 },
2832 };
2833
2834 module_pci_driver(azx_driver);
2835