1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Header file for Analogix DP (Display Port) core interface driver. 4 * 5 * Copyright (C) 2012 Samsung Electronics Co., Ltd. 6 * Author: Jingoo Han <jg1.han@samsung.com> 7 */ 8 9 #ifndef _ANALOGIX_DP_CORE_H 10 #define _ANALOGIX_DP_CORE_H 11 12 #include <drm/display/drm_dp_helper.h> 13 #include <drm/drm_crtc.h> 14 15 #define DP_TIMEOUT_LOOP_COUNT 100 16 #define MAX_CR_LOOP 5 17 #define MAX_EQ_LOOP 5 18 #define MAX_PLL_LOCK_LOOP 5 19 20 /* Training takes 22ms if AUX channel comm fails. Use this as retry interval */ 21 #define DP_TIMEOUT_TRAINING_US 22000 22 #define DP_TIMEOUT_PSR_LOOP_MS 300 23 24 /* DP_MAX_LANE_COUNT */ 25 #define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1) 26 #define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f) 27 28 /* DP_LANE_COUNT_SET */ 29 #define DPCD_LANE_COUNT_SET(x) ((x) & 0x1f) 30 31 /* DP_TRAINING_LANE0_SET */ 32 #define DPCD_PRE_EMPHASIS_SET(x) (((x) & 0x3) << 3) 33 #define DPCD_PRE_EMPHASIS_GET(x) (((x) >> 3) & 0x3) 34 #define DPCD_VOLTAGE_SWING_SET(x) (((x) & 0x3) << 0) 35 #define DPCD_VOLTAGE_SWING_GET(x) (((x) >> 0) & 0x3) 36 37 struct gpio_desc; 38 39 enum link_lane_count_type { 40 LANE_COUNT1 = 1, 41 LANE_COUNT2 = 2, 42 LANE_COUNT4 = 4 43 }; 44 45 enum link_training_state { 46 START, 47 CLOCK_RECOVERY, 48 EQUALIZER_TRAINING, 49 FINISHED, 50 FAILED 51 }; 52 53 enum voltage_swing_level { 54 VOLTAGE_LEVEL_0, 55 VOLTAGE_LEVEL_1, 56 VOLTAGE_LEVEL_2, 57 VOLTAGE_LEVEL_3, 58 }; 59 60 enum pre_emphasis_level { 61 PRE_EMPHASIS_LEVEL_0, 62 PRE_EMPHASIS_LEVEL_1, 63 PRE_EMPHASIS_LEVEL_2, 64 PRE_EMPHASIS_LEVEL_3, 65 }; 66 67 enum pattern_set { 68 PRBS7, 69 D10_2, 70 TRAINING_PTN1, 71 TRAINING_PTN2, 72 DP_NONE 73 }; 74 75 enum color_space { 76 COLOR_RGB, 77 COLOR_YCBCR422, 78 COLOR_YCBCR444 79 }; 80 81 enum color_depth { 82 COLOR_6, 83 COLOR_8, 84 COLOR_10, 85 COLOR_12 86 }; 87 88 enum color_coefficient { 89 COLOR_YCBCR601, 90 COLOR_YCBCR709 91 }; 92 93 enum dynamic_range { 94 VESA, 95 CEA 96 }; 97 98 enum clock_recovery_m_value_type { 99 CALCULATED_M, 100 REGISTER_M 101 }; 102 103 enum video_timing_recognition_type { 104 VIDEO_TIMING_FROM_CAPTURE, 105 VIDEO_TIMING_FROM_REGISTER 106 }; 107 108 enum analog_power_block { 109 AUX_BLOCK, 110 CH0_BLOCK, 111 CH1_BLOCK, 112 CH2_BLOCK, 113 CH3_BLOCK, 114 ANALOG_TOTAL, 115 POWER_ALL 116 }; 117 118 enum dp_irq_type { 119 DP_IRQ_TYPE_HP_CABLE_IN = BIT(0), 120 DP_IRQ_TYPE_HP_CABLE_OUT = BIT(1), 121 DP_IRQ_TYPE_HP_CHANGE = BIT(2), 122 DP_IRQ_TYPE_UNKNOWN = BIT(3), 123 }; 124 125 struct video_info { 126 char *name; 127 128 bool h_sync_polarity; 129 bool v_sync_polarity; 130 bool interlaced; 131 132 enum color_space color_space; 133 enum dynamic_range dynamic_range; 134 enum color_coefficient ycbcr_coeff; 135 enum color_depth color_depth; 136 137 int max_link_rate; 138 enum link_lane_count_type max_lane_count; 139 }; 140 141 struct link_train { 142 int eq_loop; 143 int cr_loop[4]; 144 145 u8 link_rate; 146 u8 lane_count; 147 u8 training_lane[4]; 148 149 enum link_training_state lt_state; 150 }; 151 152 struct analogix_dp_device { 153 struct drm_encoder *encoder; 154 struct device *dev; 155 struct drm_device *drm_dev; 156 struct drm_connector connector; 157 struct drm_bridge *bridge; 158 struct drm_dp_aux aux; 159 struct clk *clock; 160 unsigned int irq; 161 void __iomem *reg_base; 162 163 struct video_info video_info; 164 struct link_train link_train; 165 struct phy *phy; 166 int dpms_mode; 167 struct gpio_desc *hpd_gpiod; 168 bool force_hpd; 169 bool fast_train_enable; 170 bool psr_supported; 171 172 struct mutex panel_lock; 173 bool panel_is_modeset; 174 175 struct analogix_dp_plat_data *plat_data; 176 }; 177 178 /* analogix_dp_reg.c */ 179 void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable); 180 void analogix_dp_stop_video(struct analogix_dp_device *dp); 181 void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable); 182 void analogix_dp_init_analog_param(struct analogix_dp_device *dp); 183 void analogix_dp_init_interrupt(struct analogix_dp_device *dp); 184 void analogix_dp_reset(struct analogix_dp_device *dp); 185 void analogix_dp_swreset(struct analogix_dp_device *dp); 186 void analogix_dp_config_interrupt(struct analogix_dp_device *dp); 187 void analogix_dp_mute_hpd_interrupt(struct analogix_dp_device *dp); 188 void analogix_dp_unmute_hpd_interrupt(struct analogix_dp_device *dp); 189 int analogix_dp_wait_pll_locked(struct analogix_dp_device *dp); 190 void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable); 191 void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp, 192 enum analog_power_block block, 193 bool enable); 194 int analogix_dp_init_analog_func(struct analogix_dp_device *dp); 195 void analogix_dp_init_hpd(struct analogix_dp_device *dp); 196 void analogix_dp_force_hpd(struct analogix_dp_device *dp); 197 enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp); 198 void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp); 199 void analogix_dp_reset_aux(struct analogix_dp_device *dp); 200 void analogix_dp_init_aux(struct analogix_dp_device *dp); 201 int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp); 202 void analogix_dp_enable_sw_function(struct analogix_dp_device *dp); 203 void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype); 204 void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype); 205 void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count); 206 void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count); 207 void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, 208 bool enable); 209 void analogix_dp_set_training_pattern(struct analogix_dp_device *dp, 210 enum pattern_set pattern); 211 void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp); 212 u32 analogix_dp_get_lane_link_training(struct analogix_dp_device *dp, u8 lane); 213 void analogix_dp_reset_macro(struct analogix_dp_device *dp); 214 void analogix_dp_init_video(struct analogix_dp_device *dp); 215 216 void analogix_dp_set_video_color_format(struct analogix_dp_device *dp); 217 int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp); 218 void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp, 219 enum clock_recovery_m_value_type type, 220 u32 m_value, 221 u32 n_value); 222 void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type); 223 void analogix_dp_enable_video_master(struct analogix_dp_device *dp, 224 bool enable); 225 void analogix_dp_start_video(struct analogix_dp_device *dp); 226 int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp); 227 void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp); 228 void analogix_dp_enable_scrambling(struct analogix_dp_device *dp); 229 void analogix_dp_disable_scrambling(struct analogix_dp_device *dp); 230 void analogix_dp_enable_psr_crc(struct analogix_dp_device *dp); 231 int analogix_dp_send_psr_spd(struct analogix_dp_device *dp, 232 struct dp_sdp *vsc, bool blocking); 233 ssize_t analogix_dp_transfer(struct analogix_dp_device *dp, 234 struct drm_dp_aux_msg *msg); 235 236 #endif /* _ANALOGIX_DP_CORE_H */ 237