1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * intel_hdmi_audio.c - Intel HDMI audio driver 4 * 5 * Copyright (C) 2016 Intel Corp 6 * Authors: Sailaja Bandarupalli <sailaja.bandarupalli@intel.com> 7 * Ramesh Babu K V <ramesh.babu@intel.com> 8 * Vaibhav Agarwal <vaibhav.agarwal@intel.com> 9 * Jerome Anand <jerome.anand@intel.com> 10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 11 * 12 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 13 * ALSA driver for Intel HDMI audio 14 */ 15 16 #include <linux/types.h> 17 #include <linux/platform_device.h> 18 #include <linux/io.h> 19 #include <linux/slab.h> 20 #include <linux/module.h> 21 #include <linux/interrupt.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/dma-mapping.h> 24 #include <linux/delay.h> 25 #include <linux/string.h> 26 #include <sound/core.h> 27 #include <sound/asoundef.h> 28 #include <sound/pcm.h> 29 #include <sound/pcm_params.h> 30 #include <sound/initval.h> 31 #include <sound/control.h> 32 #include <sound/jack.h> 33 #include <drm/drm_edid.h> 34 #include <drm/drm_eld.h> 35 #include <drm/intel/intel_lpe_audio.h> 36 #include "intel_hdmi_audio.h" 37 38 #define INTEL_HDMI_AUDIO_SUSPEND_DELAY_MS 5000 39 40 #define for_each_pipe(card_ctx, pipe) \ 41 for ((pipe) = 0; (pipe) < (card_ctx)->num_pipes; (pipe)++) 42 #define for_each_port(card_ctx, port) \ 43 for ((port) = 0; (port) < (card_ctx)->num_ports; (port)++) 44 45 /*standard module options for ALSA. This module supports only one card*/ 46 static int hdmi_card_index = SNDRV_DEFAULT_IDX1; 47 static char *hdmi_card_id = SNDRV_DEFAULT_STR1; 48 static bool single_port; 49 50 module_param_named(index, hdmi_card_index, int, 0444); 51 MODULE_PARM_DESC(index, 52 "Index value for INTEL Intel HDMI Audio controller."); 53 module_param_named(id, hdmi_card_id, charp, 0444); 54 MODULE_PARM_DESC(id, 55 "ID string for INTEL Intel HDMI Audio controller."); 56 module_param(single_port, bool, 0444); 57 MODULE_PARM_DESC(single_port, 58 "Single-port mode (for compatibility)"); 59 60 /* 61 * ELD SA bits in the CEA Speaker Allocation data block 62 */ 63 static const int eld_speaker_allocation_bits[] = { 64 [0] = FL | FR, 65 [1] = LFE, 66 [2] = FC, 67 [3] = RL | RR, 68 [4] = RC, 69 [5] = FLC | FRC, 70 [6] = RLC | RRC, 71 /* the following are not defined in ELD yet */ 72 [7] = 0, 73 }; 74 75 /* 76 * This is an ordered list! 77 * 78 * The preceding ones have better chances to be selected by 79 * hdmi_channel_allocation(). 80 */ 81 static struct cea_channel_speaker_allocation channel_allocations[] = { 82 /* channel: 7 6 5 4 3 2 1 0 */ 83 { .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } }, 84 /* 2.1 */ 85 { .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } }, 86 /* Dolby Surround */ 87 { .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } }, 88 /* surround40 */ 89 { .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } }, 90 /* surround41 */ 91 { .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } }, 92 /* surround50 */ 93 { .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } }, 94 /* surround51 */ 95 { .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } }, 96 /* 6.1 */ 97 { .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } }, 98 /* surround71 */ 99 { .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } }, 100 101 { .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } }, 102 { .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } }, 103 { .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } }, 104 { .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } }, 105 { .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } }, 106 { .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } }, 107 { .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } }, 108 { .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } }, 109 { .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } }, 110 { .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } }, 111 { .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } }, 112 { .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } }, 113 { .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } }, 114 { .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } }, 115 { .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } }, 116 { .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } }, 117 { .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } }, 118 { .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } }, 119 { .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } }, 120 { .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } }, 121 { .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } }, 122 { .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } }, 123 { .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } }, 124 }; 125 126 static const struct channel_map_table map_tables[] = { 127 { SNDRV_CHMAP_FL, 0x00, FL }, 128 { SNDRV_CHMAP_FR, 0x01, FR }, 129 { SNDRV_CHMAP_RL, 0x04, RL }, 130 { SNDRV_CHMAP_RR, 0x05, RR }, 131 { SNDRV_CHMAP_LFE, 0x02, LFE }, 132 { SNDRV_CHMAP_FC, 0x03, FC }, 133 { SNDRV_CHMAP_RLC, 0x06, RLC }, 134 { SNDRV_CHMAP_RRC, 0x07, RRC }, 135 {} /* terminator */ 136 }; 137 138 /* hardware capability structure */ 139 static const struct snd_pcm_hardware had_pcm_hardware = { 140 .info = (SNDRV_PCM_INFO_INTERLEAVED | 141 SNDRV_PCM_INFO_MMAP | 142 SNDRV_PCM_INFO_MMAP_VALID | 143 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP), 144 .formats = (SNDRV_PCM_FMTBIT_S16_LE | 145 SNDRV_PCM_FMTBIT_S24_LE | 146 SNDRV_PCM_FMTBIT_S32_LE), 147 .rates = SNDRV_PCM_RATE_32000 | 148 SNDRV_PCM_RATE_44100 | 149 SNDRV_PCM_RATE_48000 | 150 SNDRV_PCM_RATE_88200 | 151 SNDRV_PCM_RATE_96000 | 152 SNDRV_PCM_RATE_176400 | 153 SNDRV_PCM_RATE_192000, 154 .rate_min = HAD_MIN_RATE, 155 .rate_max = HAD_MAX_RATE, 156 .channels_min = HAD_MIN_CHANNEL, 157 .channels_max = HAD_MAX_CHANNEL, 158 .buffer_bytes_max = HAD_MAX_BUFFER, 159 .period_bytes_min = HAD_MIN_PERIOD_BYTES, 160 .period_bytes_max = HAD_MAX_PERIOD_BYTES, 161 .periods_min = HAD_MIN_PERIODS, 162 .periods_max = HAD_MAX_PERIODS, 163 .fifo_size = HAD_FIFO_SIZE, 164 }; 165 166 /* Get the active PCM substream; 167 * Call had_substream_put() for unreferecing. 168 * Don't call this inside had_spinlock, as it takes by itself 169 */ 170 static struct snd_pcm_substream * 171 had_substream_get(struct snd_intelhad *intelhaddata) 172 { 173 struct snd_pcm_substream *substream; 174 unsigned long flags; 175 176 spin_lock_irqsave(&intelhaddata->had_spinlock, flags); 177 substream = intelhaddata->stream_info.substream; 178 if (substream) 179 intelhaddata->stream_info.substream_refcount++; 180 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags); 181 return substream; 182 } 183 184 /* Unref the active PCM substream; 185 * Don't call this inside had_spinlock, as it takes by itself 186 */ 187 static void had_substream_put(struct snd_intelhad *intelhaddata) 188 { 189 unsigned long flags; 190 191 spin_lock_irqsave(&intelhaddata->had_spinlock, flags); 192 intelhaddata->stream_info.substream_refcount--; 193 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags); 194 } 195 196 static u32 had_config_offset(int pipe) 197 { 198 switch (pipe) { 199 default: 200 case 0: 201 return AUDIO_HDMI_CONFIG_A; 202 case 1: 203 return AUDIO_HDMI_CONFIG_B; 204 case 2: 205 return AUDIO_HDMI_CONFIG_C; 206 } 207 } 208 209 /* Register access functions */ 210 static u32 had_read_register_raw(struct snd_intelhad_card *card_ctx, 211 int pipe, u32 reg) 212 { 213 return ioread32(card_ctx->mmio_start + had_config_offset(pipe) + reg); 214 } 215 216 static void had_write_register_raw(struct snd_intelhad_card *card_ctx, 217 int pipe, u32 reg, u32 val) 218 { 219 iowrite32(val, card_ctx->mmio_start + had_config_offset(pipe) + reg); 220 } 221 222 static void had_read_register(struct snd_intelhad *ctx, u32 reg, u32 *val) 223 { 224 if (!ctx->connected) 225 *val = 0; 226 else 227 *val = had_read_register_raw(ctx->card_ctx, ctx->pipe, reg); 228 } 229 230 static void had_write_register(struct snd_intelhad *ctx, u32 reg, u32 val) 231 { 232 if (ctx->connected) 233 had_write_register_raw(ctx->card_ctx, ctx->pipe, reg, val); 234 } 235 236 /* 237 * enable / disable audio configuration 238 * 239 * The normal read/modify should not directly be used on VLV2 for 240 * updating AUD_CONFIG register. 241 * This is because: 242 * Bit6 of AUD_CONFIG register is writeonly due to a silicon bug on VLV2 243 * HDMI IP. As a result a read-modify of AUD_CONFIG register will always 244 * clear bit6. AUD_CONFIG[6:4] represents the "channels" field of the 245 * register. This field should be 1xy binary for configuration with 6 or 246 * more channels. Read-modify of AUD_CONFIG (Eg. for enabling audio) 247 * causes the "channels" field to be updated as 0xy binary resulting in 248 * bad audio. The fix is to always write the AUD_CONFIG[6:4] with 249 * appropriate value when doing read-modify of AUD_CONFIG register. 250 */ 251 static void had_enable_audio(struct snd_intelhad *intelhaddata, 252 bool enable) 253 { 254 /* update the cached value */ 255 intelhaddata->aud_config.regx.aud_en = enable; 256 had_write_register(intelhaddata, AUD_CONFIG, 257 intelhaddata->aud_config.regval); 258 } 259 260 /* forcibly ACKs to both BUFFER_DONE and BUFFER_UNDERRUN interrupts */ 261 static void had_ack_irqs(struct snd_intelhad *ctx) 262 { 263 u32 status_reg; 264 265 if (!ctx->connected) 266 return; 267 had_read_register(ctx, AUD_HDMI_STATUS, &status_reg); 268 status_reg |= HDMI_AUDIO_BUFFER_DONE | HDMI_AUDIO_UNDERRUN; 269 had_write_register(ctx, AUD_HDMI_STATUS, status_reg); 270 had_read_register(ctx, AUD_HDMI_STATUS, &status_reg); 271 } 272 273 /* Reset buffer pointers */ 274 static void had_reset_audio(struct snd_intelhad *intelhaddata) 275 { 276 had_write_register(intelhaddata, AUD_HDMI_STATUS, 277 AUD_HDMI_STATUSG_MASK_FUNCRST); 278 had_write_register(intelhaddata, AUD_HDMI_STATUS, 0); 279 } 280 281 /* 282 * initialize audio channel status registers 283 * This function is called in the prepare callback 284 */ 285 static int had_prog_status_reg(struct snd_pcm_substream *substream, 286 struct snd_intelhad *intelhaddata) 287 { 288 union aud_ch_status_0 ch_stat0 = {.regval = 0}; 289 union aud_ch_status_1 ch_stat1 = {.regval = 0}; 290 291 ch_stat0.regx.lpcm_id = (intelhaddata->aes_bits & 292 IEC958_AES0_NONAUDIO) >> 1; 293 ch_stat0.regx.clk_acc = (intelhaddata->aes_bits & 294 IEC958_AES3_CON_CLOCK) >> 4; 295 296 switch (substream->runtime->rate) { 297 case AUD_SAMPLE_RATE_32: 298 ch_stat0.regx.samp_freq = CH_STATUS_MAP_32KHZ; 299 break; 300 301 case AUD_SAMPLE_RATE_44_1: 302 ch_stat0.regx.samp_freq = CH_STATUS_MAP_44KHZ; 303 break; 304 case AUD_SAMPLE_RATE_48: 305 ch_stat0.regx.samp_freq = CH_STATUS_MAP_48KHZ; 306 break; 307 case AUD_SAMPLE_RATE_88_2: 308 ch_stat0.regx.samp_freq = CH_STATUS_MAP_88KHZ; 309 break; 310 case AUD_SAMPLE_RATE_96: 311 ch_stat0.regx.samp_freq = CH_STATUS_MAP_96KHZ; 312 break; 313 case AUD_SAMPLE_RATE_176_4: 314 ch_stat0.regx.samp_freq = CH_STATUS_MAP_176KHZ; 315 break; 316 case AUD_SAMPLE_RATE_192: 317 ch_stat0.regx.samp_freq = CH_STATUS_MAP_192KHZ; 318 break; 319 320 default: 321 /* control should never come here */ 322 return -EINVAL; 323 } 324 325 had_write_register(intelhaddata, 326 AUD_CH_STATUS_0, ch_stat0.regval); 327 328 switch (substream->runtime->format) { 329 case SNDRV_PCM_FORMAT_S16_LE: 330 ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_20; 331 ch_stat1.regx.wrd_len = SMPL_WIDTH_16BITS; 332 break; 333 case SNDRV_PCM_FORMAT_S24_LE: 334 case SNDRV_PCM_FORMAT_S32_LE: 335 ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_24; 336 ch_stat1.regx.wrd_len = SMPL_WIDTH_24BITS; 337 break; 338 default: 339 return -EINVAL; 340 } 341 342 had_write_register(intelhaddata, 343 AUD_CH_STATUS_1, ch_stat1.regval); 344 return 0; 345 } 346 347 /* 348 * function to initialize audio 349 * registers and buffer configuration registers 350 * This function is called in the prepare callback 351 */ 352 static int had_init_audio_ctrl(struct snd_pcm_substream *substream, 353 struct snd_intelhad *intelhaddata) 354 { 355 union aud_cfg cfg_val = {.regval = 0}; 356 union aud_buf_config buf_cfg = {.regval = 0}; 357 u8 channels; 358 359 had_prog_status_reg(substream, intelhaddata); 360 361 buf_cfg.regx.audio_fifo_watermark = FIFO_THRESHOLD; 362 buf_cfg.regx.dma_fifo_watermark = DMA_FIFO_THRESHOLD; 363 buf_cfg.regx.aud_delay = 0; 364 had_write_register(intelhaddata, AUD_BUF_CONFIG, buf_cfg.regval); 365 366 channels = substream->runtime->channels; 367 cfg_val.regx.num_ch = channels - 2; 368 if (channels <= 2) 369 cfg_val.regx.layout = LAYOUT0; 370 else 371 cfg_val.regx.layout = LAYOUT1; 372 373 if (substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE) 374 cfg_val.regx.packet_mode = 1; 375 376 if (substream->runtime->format == SNDRV_PCM_FORMAT_S32_LE) 377 cfg_val.regx.left_align = 1; 378 379 cfg_val.regx.val_bit = 1; 380 381 /* fix up the DP bits */ 382 if (intelhaddata->dp_output) { 383 cfg_val.regx.dp_modei = 1; 384 cfg_val.regx.set = 1; 385 } 386 387 had_write_register(intelhaddata, AUD_CONFIG, cfg_val.regval); 388 intelhaddata->aud_config = cfg_val; 389 return 0; 390 } 391 392 /* 393 * Compute derived values in channel_allocations[]. 394 */ 395 static void init_channel_allocations(void) 396 { 397 int i, j; 398 struct cea_channel_speaker_allocation *p; 399 400 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { 401 p = channel_allocations + i; 402 p->channels = 0; 403 p->spk_mask = 0; 404 for (j = 0; j < ARRAY_SIZE(p->speakers); j++) 405 if (p->speakers[j]) { 406 p->channels++; 407 p->spk_mask |= p->speakers[j]; 408 } 409 } 410 } 411 412 /* 413 * The transformation takes two steps: 414 * 415 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask 416 * spk_mask => (channel_allocations[]) => ai->CA 417 * 418 * TODO: it could select the wrong CA from multiple candidates. 419 */ 420 static int had_channel_allocation(struct snd_intelhad *intelhaddata, 421 int channels) 422 { 423 int i; 424 int ca = 0; 425 int spk_mask = 0; 426 427 /* 428 * CA defaults to 0 for basic stereo audio 429 */ 430 if (channels <= 2) 431 return 0; 432 433 /* 434 * expand ELD's speaker allocation mask 435 * 436 * ELD tells the speaker mask in a compact(paired) form, 437 * expand ELD's notions to match the ones used by Audio InfoFrame. 438 */ 439 440 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) { 441 if (intelhaddata->eld[DRM_ELD_SPEAKER] & (1 << i)) 442 spk_mask |= eld_speaker_allocation_bits[i]; 443 } 444 445 /* search for the first working match in the CA table */ 446 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { 447 if (channels == channel_allocations[i].channels && 448 (spk_mask & channel_allocations[i].spk_mask) == 449 channel_allocations[i].spk_mask) { 450 ca = channel_allocations[i].ca_index; 451 break; 452 } 453 } 454 455 dev_dbg(intelhaddata->dev, "select CA 0x%x for %d\n", ca, channels); 456 457 return ca; 458 } 459 460 /* from speaker bit mask to ALSA API channel position */ 461 static int spk_to_chmap(int spk) 462 { 463 const struct channel_map_table *t = map_tables; 464 465 for (; t->map; t++) { 466 if (t->spk_mask == spk) 467 return t->map; 468 } 469 return 0; 470 } 471 472 static void had_build_channel_allocation_map(struct snd_intelhad *intelhaddata) 473 { 474 int i, c; 475 int spk_mask = 0; 476 struct snd_pcm_chmap_elem *chmap; 477 u8 eld_high, eld_high_mask = 0xF0; 478 u8 high_msb; 479 480 kfree(intelhaddata->chmap->chmap); 481 intelhaddata->chmap->chmap = NULL; 482 483 chmap = kzalloc(sizeof(*chmap), GFP_KERNEL); 484 if (!chmap) 485 return; 486 487 dev_dbg(intelhaddata->dev, "eld speaker = %x\n", 488 intelhaddata->eld[DRM_ELD_SPEAKER]); 489 490 /* WA: Fix the max channel supported to 8 */ 491 492 /* 493 * Sink may support more than 8 channels, if eld_high has more than 494 * one bit set. SOC supports max 8 channels. 495 * Refer eld_speaker_allocation_bits, for sink speaker allocation 496 */ 497 498 /* if 0x2F < eld < 0x4F fall back to 0x2f, else fall back to 0x4F */ 499 eld_high = intelhaddata->eld[DRM_ELD_SPEAKER] & eld_high_mask; 500 if ((eld_high & (eld_high-1)) && (eld_high > 0x1F)) { 501 /* eld_high & (eld_high-1): if more than 1 bit set */ 502 /* 0x1F: 7 channels */ 503 for (i = 1; i < 4; i++) { 504 high_msb = eld_high & (0x80 >> i); 505 if (high_msb) { 506 intelhaddata->eld[DRM_ELD_SPEAKER] &= 507 high_msb | 0xF; 508 break; 509 } 510 } 511 } 512 513 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) { 514 if (intelhaddata->eld[DRM_ELD_SPEAKER] & (1 << i)) 515 spk_mask |= eld_speaker_allocation_bits[i]; 516 } 517 518 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { 519 if (spk_mask == channel_allocations[i].spk_mask) { 520 for (c = 0; c < channel_allocations[i].channels; c++) { 521 chmap->map[c] = spk_to_chmap( 522 channel_allocations[i].speakers[ 523 (MAX_SPEAKERS - 1) - c]); 524 } 525 chmap->channels = channel_allocations[i].channels; 526 intelhaddata->chmap->chmap = chmap; 527 break; 528 } 529 } 530 if (i >= ARRAY_SIZE(channel_allocations)) 531 kfree(chmap); 532 } 533 534 /* 535 * ALSA API channel-map control callbacks 536 */ 537 static int had_chmap_ctl_info(struct snd_kcontrol *kcontrol, 538 struct snd_ctl_elem_info *uinfo) 539 { 540 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 541 uinfo->count = HAD_MAX_CHANNEL; 542 uinfo->value.integer.min = 0; 543 uinfo->value.integer.max = SNDRV_CHMAP_LAST; 544 return 0; 545 } 546 547 static int had_chmap_ctl_get(struct snd_kcontrol *kcontrol, 548 struct snd_ctl_elem_value *ucontrol) 549 { 550 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol); 551 struct snd_intelhad *intelhaddata = info->private_data; 552 int i; 553 const struct snd_pcm_chmap_elem *chmap; 554 555 memset(ucontrol->value.integer.value, 0, 556 sizeof(long) * HAD_MAX_CHANNEL); 557 mutex_lock(&intelhaddata->mutex); 558 if (!intelhaddata->chmap->chmap) { 559 mutex_unlock(&intelhaddata->mutex); 560 return 0; 561 } 562 563 chmap = intelhaddata->chmap->chmap; 564 for (i = 0; i < chmap->channels; i++) 565 ucontrol->value.integer.value[i] = chmap->map[i]; 566 mutex_unlock(&intelhaddata->mutex); 567 568 return 0; 569 } 570 571 static int had_register_chmap_ctls(struct snd_intelhad *intelhaddata, 572 struct snd_pcm *pcm) 573 { 574 int err; 575 576 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK, 577 NULL, 0, (unsigned long)intelhaddata, 578 &intelhaddata->chmap); 579 if (err < 0) 580 return err; 581 582 intelhaddata->chmap->private_data = intelhaddata; 583 intelhaddata->chmap->kctl->info = had_chmap_ctl_info; 584 intelhaddata->chmap->kctl->get = had_chmap_ctl_get; 585 intelhaddata->chmap->chmap = NULL; 586 return 0; 587 } 588 589 /* 590 * Initialize Data Island Packets registers 591 * This function is called in the prepare callback 592 */ 593 static void had_prog_dip(struct snd_pcm_substream *substream, 594 struct snd_intelhad *intelhaddata) 595 { 596 int i; 597 union aud_ctrl_st ctrl_state = {.regval = 0}; 598 union aud_info_frame2 frame2 = {.regval = 0}; 599 union aud_info_frame3 frame3 = {.regval = 0}; 600 u8 checksum = 0; 601 u32 info_frame; 602 int channels; 603 int ca; 604 605 channels = substream->runtime->channels; 606 607 had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval); 608 609 ca = had_channel_allocation(intelhaddata, channels); 610 if (intelhaddata->dp_output) { 611 info_frame = DP_INFO_FRAME_WORD1; 612 frame2.regval = (substream->runtime->channels - 1) | (ca << 24); 613 } else { 614 info_frame = HDMI_INFO_FRAME_WORD1; 615 frame2.regx.chnl_cnt = substream->runtime->channels - 1; 616 frame3.regx.chnl_alloc = ca; 617 618 /* Calculte the byte wide checksum for all valid DIP words */ 619 for (i = 0; i < BYTES_PER_WORD; i++) 620 checksum += (info_frame >> (i * 8)) & 0xff; 621 for (i = 0; i < BYTES_PER_WORD; i++) 622 checksum += (frame2.regval >> (i * 8)) & 0xff; 623 for (i = 0; i < BYTES_PER_WORD; i++) 624 checksum += (frame3.regval >> (i * 8)) & 0xff; 625 626 frame2.regx.chksum = -(checksum); 627 } 628 629 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, info_frame); 630 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame2.regval); 631 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame3.regval); 632 633 /* program remaining DIP words with zero */ 634 for (i = 0; i < HAD_MAX_DIP_WORDS-VALID_DIP_WORDS; i++) 635 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, 0x0); 636 637 ctrl_state.regx.dip_freq = 1; 638 ctrl_state.regx.dip_en_sta = 1; 639 had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval); 640 } 641 642 static int had_calculate_maud_value(u32 aud_samp_freq, u32 link_rate) 643 { 644 u32 maud_val; 645 646 /* Select maud according to DP 1.2 spec */ 647 if (link_rate == DP_2_7_GHZ) { 648 switch (aud_samp_freq) { 649 case AUD_SAMPLE_RATE_32: 650 maud_val = AUD_SAMPLE_RATE_32_DP_2_7_MAUD_VAL; 651 break; 652 653 case AUD_SAMPLE_RATE_44_1: 654 maud_val = AUD_SAMPLE_RATE_44_1_DP_2_7_MAUD_VAL; 655 break; 656 657 case AUD_SAMPLE_RATE_48: 658 maud_val = AUD_SAMPLE_RATE_48_DP_2_7_MAUD_VAL; 659 break; 660 661 case AUD_SAMPLE_RATE_88_2: 662 maud_val = AUD_SAMPLE_RATE_88_2_DP_2_7_MAUD_VAL; 663 break; 664 665 case AUD_SAMPLE_RATE_96: 666 maud_val = AUD_SAMPLE_RATE_96_DP_2_7_MAUD_VAL; 667 break; 668 669 case AUD_SAMPLE_RATE_176_4: 670 maud_val = AUD_SAMPLE_RATE_176_4_DP_2_7_MAUD_VAL; 671 break; 672 673 case HAD_MAX_RATE: 674 maud_val = HAD_MAX_RATE_DP_2_7_MAUD_VAL; 675 break; 676 677 default: 678 maud_val = -EINVAL; 679 break; 680 } 681 } else if (link_rate == DP_1_62_GHZ) { 682 switch (aud_samp_freq) { 683 case AUD_SAMPLE_RATE_32: 684 maud_val = AUD_SAMPLE_RATE_32_DP_1_62_MAUD_VAL; 685 break; 686 687 case AUD_SAMPLE_RATE_44_1: 688 maud_val = AUD_SAMPLE_RATE_44_1_DP_1_62_MAUD_VAL; 689 break; 690 691 case AUD_SAMPLE_RATE_48: 692 maud_val = AUD_SAMPLE_RATE_48_DP_1_62_MAUD_VAL; 693 break; 694 695 case AUD_SAMPLE_RATE_88_2: 696 maud_val = AUD_SAMPLE_RATE_88_2_DP_1_62_MAUD_VAL; 697 break; 698 699 case AUD_SAMPLE_RATE_96: 700 maud_val = AUD_SAMPLE_RATE_96_DP_1_62_MAUD_VAL; 701 break; 702 703 case AUD_SAMPLE_RATE_176_4: 704 maud_val = AUD_SAMPLE_RATE_176_4_DP_1_62_MAUD_VAL; 705 break; 706 707 case HAD_MAX_RATE: 708 maud_val = HAD_MAX_RATE_DP_1_62_MAUD_VAL; 709 break; 710 711 default: 712 maud_val = -EINVAL; 713 break; 714 } 715 } else 716 maud_val = -EINVAL; 717 718 return maud_val; 719 } 720 721 /* 722 * Program HDMI audio CTS value 723 * 724 * @aud_samp_freq: sampling frequency of audio data 725 * @tmds: sampling frequency of the display data 726 * @link_rate: DP link rate 727 * @n_param: N value, depends on aud_samp_freq 728 * @intelhaddata: substream private data 729 * 730 * Program CTS register based on the audio and display sampling frequency 731 */ 732 static void had_prog_cts(u32 aud_samp_freq, u32 tmds, u32 link_rate, 733 u32 n_param, struct snd_intelhad *intelhaddata) 734 { 735 u32 cts_val; 736 u64 dividend, divisor; 737 738 if (intelhaddata->dp_output) { 739 /* Substitute cts_val with Maud according to DP 1.2 spec*/ 740 cts_val = had_calculate_maud_value(aud_samp_freq, link_rate); 741 } else { 742 /* Calculate CTS according to HDMI 1.3a spec*/ 743 dividend = (u64)tmds * n_param*1000; 744 divisor = 128 * aud_samp_freq; 745 cts_val = div64_u64(dividend, divisor); 746 } 747 dev_dbg(intelhaddata->dev, "TMDS value=%d, N value=%d, CTS Value=%d\n", 748 tmds, n_param, cts_val); 749 had_write_register(intelhaddata, AUD_HDMI_CTS, (BIT(24) | cts_val)); 750 } 751 752 static int had_calculate_n_value(u32 aud_samp_freq) 753 { 754 int n_val; 755 756 /* Select N according to HDMI 1.3a spec*/ 757 switch (aud_samp_freq) { 758 case AUD_SAMPLE_RATE_32: 759 n_val = 4096; 760 break; 761 762 case AUD_SAMPLE_RATE_44_1: 763 n_val = 6272; 764 break; 765 766 case AUD_SAMPLE_RATE_48: 767 n_val = 6144; 768 break; 769 770 case AUD_SAMPLE_RATE_88_2: 771 n_val = 12544; 772 break; 773 774 case AUD_SAMPLE_RATE_96: 775 n_val = 12288; 776 break; 777 778 case AUD_SAMPLE_RATE_176_4: 779 n_val = 25088; 780 break; 781 782 case HAD_MAX_RATE: 783 n_val = 24576; 784 break; 785 786 default: 787 n_val = -EINVAL; 788 break; 789 } 790 return n_val; 791 } 792 793 /* 794 * Program HDMI audio N value 795 * 796 * @aud_samp_freq: sampling frequency of audio data 797 * @n_param: N value, depends on aud_samp_freq 798 * @intelhaddata: substream private data 799 * 800 * This function is called in the prepare callback. 801 * It programs based on the audio and display sampling frequency 802 */ 803 static int had_prog_n(u32 aud_samp_freq, u32 *n_param, 804 struct snd_intelhad *intelhaddata) 805 { 806 int n_val; 807 808 if (intelhaddata->dp_output) { 809 /* 810 * According to DP specs, Maud and Naud values hold 811 * a relationship, which is stated as: 812 * Maud/Naud = 512 * fs / f_LS_Clk 813 * where, fs is the sampling frequency of the audio stream 814 * and Naud is 32768 for Async clock. 815 */ 816 817 n_val = DP_NAUD_VAL; 818 } else 819 n_val = had_calculate_n_value(aud_samp_freq); 820 821 if (n_val < 0) 822 return n_val; 823 824 had_write_register(intelhaddata, AUD_N_ENABLE, (BIT(24) | n_val)); 825 *n_param = n_val; 826 return 0; 827 } 828 829 /* 830 * PCM ring buffer handling 831 * 832 * The hardware provides a ring buffer with the fixed 4 buffer descriptors 833 * (BDs). The driver maps these 4 BDs onto the PCM ring buffer. The mapping 834 * moves at each period elapsed. The below illustrates how it works: 835 * 836 * At time=0 837 * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1| 838 * BD | 0 | 1 | 2 | 3 | 839 * 840 * At time=1 (period elapsed) 841 * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1| 842 * BD | 1 | 2 | 3 | 0 | 843 * 844 * At time=2 (second period elapsed) 845 * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1| 846 * BD | 2 | 3 | 0 | 1 | 847 * 848 * The bd_head field points to the index of the BD to be read. It's also the 849 * position to be filled at next. The pcm_head and the pcm_filled fields 850 * point to the indices of the current position and of the next position to 851 * be filled, respectively. For PCM buffer there are both _head and _filled 852 * because they may be difference when nperiods > 4. For example, in the 853 * example above at t=1, bd_head=1 and pcm_head=1 while pcm_filled=5: 854 * 855 * pcm_head (=1) --v v-- pcm_filled (=5) 856 * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1| 857 * BD | 1 | 2 | 3 | 0 | 858 * bd_head (=1) --^ ^-- next to fill (= bd_head) 859 * 860 * For nperiods < 4, the remaining BDs out of 4 are marked as invalid, so that 861 * the hardware skips those BDs in the loop. 862 * 863 * An exceptional setup is the case with nperiods=1. Since we have to update 864 * BDs after finishing one BD processing, we'd need at least two BDs, where 865 * both BDs point to the same content, the same address, the same size of the 866 * whole PCM buffer. 867 */ 868 869 #define AUD_BUF_ADDR(x) (AUD_BUF_A_ADDR + (x) * HAD_REG_WIDTH) 870 #define AUD_BUF_LEN(x) (AUD_BUF_A_LENGTH + (x) * HAD_REG_WIDTH) 871 872 /* Set up a buffer descriptor at the "filled" position */ 873 static void had_prog_bd(struct snd_pcm_substream *substream, 874 struct snd_intelhad *intelhaddata) 875 { 876 int idx = intelhaddata->bd_head; 877 int ofs = intelhaddata->pcmbuf_filled * intelhaddata->period_bytes; 878 u32 addr = substream->runtime->dma_addr + ofs; 879 880 addr |= AUD_BUF_VALID; 881 if (!substream->runtime->no_period_wakeup) 882 addr |= AUD_BUF_INTR_EN; 883 had_write_register(intelhaddata, AUD_BUF_ADDR(idx), addr); 884 had_write_register(intelhaddata, AUD_BUF_LEN(idx), 885 intelhaddata->period_bytes); 886 887 /* advance the indices to the next */ 888 intelhaddata->bd_head++; 889 intelhaddata->bd_head %= intelhaddata->num_bds; 890 intelhaddata->pcmbuf_filled++; 891 intelhaddata->pcmbuf_filled %= substream->runtime->periods; 892 } 893 894 /* invalidate a buffer descriptor with the given index */ 895 static void had_invalidate_bd(struct snd_intelhad *intelhaddata, 896 int idx) 897 { 898 had_write_register(intelhaddata, AUD_BUF_ADDR(idx), 0); 899 had_write_register(intelhaddata, AUD_BUF_LEN(idx), 0); 900 } 901 902 /* Initial programming of ring buffer */ 903 static void had_init_ringbuf(struct snd_pcm_substream *substream, 904 struct snd_intelhad *intelhaddata) 905 { 906 struct snd_pcm_runtime *runtime = substream->runtime; 907 int i, num_periods; 908 909 num_periods = runtime->periods; 910 intelhaddata->num_bds = min(num_periods, HAD_NUM_OF_RING_BUFS); 911 /* set the minimum 2 BDs for num_periods=1 */ 912 intelhaddata->num_bds = max(intelhaddata->num_bds, 2U); 913 intelhaddata->period_bytes = 914 frames_to_bytes(runtime, runtime->period_size); 915 WARN_ON(intelhaddata->period_bytes & 0x3f); 916 917 intelhaddata->bd_head = 0; 918 intelhaddata->pcmbuf_head = 0; 919 intelhaddata->pcmbuf_filled = 0; 920 921 for (i = 0; i < HAD_NUM_OF_RING_BUFS; i++) { 922 if (i < intelhaddata->num_bds) 923 had_prog_bd(substream, intelhaddata); 924 else /* invalidate the rest */ 925 had_invalidate_bd(intelhaddata, i); 926 } 927 928 intelhaddata->bd_head = 0; /* reset at head again before starting */ 929 } 930 931 /* process a bd, advance to the next */ 932 static void had_advance_ringbuf(struct snd_pcm_substream *substream, 933 struct snd_intelhad *intelhaddata) 934 { 935 int num_periods = substream->runtime->periods; 936 937 /* reprogram the next buffer */ 938 had_prog_bd(substream, intelhaddata); 939 940 /* proceed to next */ 941 intelhaddata->pcmbuf_head++; 942 intelhaddata->pcmbuf_head %= num_periods; 943 } 944 945 /* process the current BD(s); 946 * returns the current PCM buffer byte position, or -EPIPE for underrun. 947 */ 948 static int had_process_ringbuf(struct snd_pcm_substream *substream, 949 struct snd_intelhad *intelhaddata) 950 { 951 int len, processed; 952 unsigned long flags; 953 954 processed = 0; 955 spin_lock_irqsave(&intelhaddata->had_spinlock, flags); 956 for (;;) { 957 /* get the remaining bytes on the buffer */ 958 had_read_register(intelhaddata, 959 AUD_BUF_LEN(intelhaddata->bd_head), 960 &len); 961 if (len < 0 || len > intelhaddata->period_bytes) { 962 dev_dbg(intelhaddata->dev, "Invalid buf length %d\n", 963 len); 964 len = -EPIPE; 965 goto out; 966 } 967 968 if (len > 0) /* OK, this is the current buffer */ 969 break; 970 971 /* len=0 => already empty, check the next buffer */ 972 if (++processed >= intelhaddata->num_bds) { 973 len = -EPIPE; /* all empty? - report underrun */ 974 goto out; 975 } 976 had_advance_ringbuf(substream, intelhaddata); 977 } 978 979 len = intelhaddata->period_bytes - len; 980 len += intelhaddata->period_bytes * intelhaddata->pcmbuf_head; 981 out: 982 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags); 983 return len; 984 } 985 986 /* called from irq handler */ 987 static void had_process_buffer_done(struct snd_intelhad *intelhaddata) 988 { 989 struct snd_pcm_substream *substream; 990 991 substream = had_substream_get(intelhaddata); 992 if (!substream) 993 return; /* no stream? - bail out */ 994 995 if (!intelhaddata->connected) { 996 snd_pcm_stop_xrun(substream); 997 goto out; /* disconnected? - bail out */ 998 } 999 1000 /* process or stop the stream */ 1001 if (had_process_ringbuf(substream, intelhaddata) < 0) 1002 snd_pcm_stop_xrun(substream); 1003 else 1004 snd_pcm_period_elapsed(substream); 1005 1006 out: 1007 had_substream_put(intelhaddata); 1008 } 1009 1010 /* 1011 * The interrupt status 'sticky' bits might not be cleared by 1012 * setting '1' to that bit once... 1013 */ 1014 static void wait_clear_underrun_bit(struct snd_intelhad *intelhaddata) 1015 { 1016 int i; 1017 u32 val; 1018 1019 for (i = 0; i < 100; i++) { 1020 /* clear bit30, 31 AUD_HDMI_STATUS */ 1021 had_read_register(intelhaddata, AUD_HDMI_STATUS, &val); 1022 if (!(val & AUD_HDMI_STATUS_MASK_UNDERRUN)) 1023 return; 1024 udelay(100); 1025 cond_resched(); 1026 had_write_register(intelhaddata, AUD_HDMI_STATUS, val); 1027 } 1028 dev_err(intelhaddata->dev, "Unable to clear UNDERRUN bits\n"); 1029 } 1030 1031 /* Perform some reset procedure after stopping the stream; 1032 * this is called from prepare or hw_free callbacks once after trigger STOP 1033 * or underrun has been processed in order to settle down the h/w state. 1034 */ 1035 static int had_pcm_sync_stop(struct snd_pcm_substream *substream) 1036 { 1037 struct snd_intelhad *intelhaddata = snd_pcm_substream_chip(substream); 1038 1039 if (!intelhaddata->connected) 1040 return 0; 1041 1042 /* Reset buffer pointers */ 1043 had_reset_audio(intelhaddata); 1044 wait_clear_underrun_bit(intelhaddata); 1045 return 0; 1046 } 1047 1048 /* called from irq handler */ 1049 static void had_process_buffer_underrun(struct snd_intelhad *intelhaddata) 1050 { 1051 struct snd_pcm_substream *substream; 1052 1053 /* Report UNDERRUN error to above layers */ 1054 substream = had_substream_get(intelhaddata); 1055 if (substream) { 1056 snd_pcm_stop_xrun(substream); 1057 had_substream_put(intelhaddata); 1058 } 1059 } 1060 1061 /* 1062 * ALSA PCM open callback 1063 */ 1064 static int had_pcm_open(struct snd_pcm_substream *substream) 1065 { 1066 struct snd_intelhad *intelhaddata; 1067 struct snd_pcm_runtime *runtime; 1068 int retval; 1069 1070 intelhaddata = snd_pcm_substream_chip(substream); 1071 runtime = substream->runtime; 1072 1073 retval = pm_runtime_resume_and_get(intelhaddata->dev); 1074 if (retval < 0) 1075 return retval; 1076 1077 /* set the runtime hw parameter with local snd_pcm_hardware struct */ 1078 runtime->hw = had_pcm_hardware; 1079 1080 retval = snd_pcm_hw_constraint_integer(runtime, 1081 SNDRV_PCM_HW_PARAM_PERIODS); 1082 if (retval < 0) 1083 goto error; 1084 1085 /* Make sure, that the period size is always aligned 1086 * 64byte boundary 1087 */ 1088 retval = snd_pcm_hw_constraint_step(substream->runtime, 0, 1089 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 64); 1090 if (retval < 0) 1091 goto error; 1092 1093 retval = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); 1094 if (retval < 0) 1095 goto error; 1096 1097 /* expose PCM substream */ 1098 spin_lock_irq(&intelhaddata->had_spinlock); 1099 intelhaddata->stream_info.substream = substream; 1100 intelhaddata->stream_info.substream_refcount++; 1101 spin_unlock_irq(&intelhaddata->had_spinlock); 1102 1103 return retval; 1104 error: 1105 pm_runtime_put_autosuspend(intelhaddata->dev); 1106 return retval; 1107 } 1108 1109 /* 1110 * ALSA PCM close callback 1111 */ 1112 static int had_pcm_close(struct snd_pcm_substream *substream) 1113 { 1114 struct snd_intelhad *intelhaddata; 1115 1116 intelhaddata = snd_pcm_substream_chip(substream); 1117 1118 /* unreference and sync with the pending PCM accesses */ 1119 spin_lock_irq(&intelhaddata->had_spinlock); 1120 intelhaddata->stream_info.substream = NULL; 1121 intelhaddata->stream_info.substream_refcount--; 1122 while (intelhaddata->stream_info.substream_refcount > 0) { 1123 spin_unlock_irq(&intelhaddata->had_spinlock); 1124 cpu_relax(); 1125 spin_lock_irq(&intelhaddata->had_spinlock); 1126 } 1127 spin_unlock_irq(&intelhaddata->had_spinlock); 1128 1129 pm_runtime_put_autosuspend(intelhaddata->dev); 1130 return 0; 1131 } 1132 1133 /* 1134 * ALSA PCM hw_params callback 1135 */ 1136 static int had_pcm_hw_params(struct snd_pcm_substream *substream, 1137 struct snd_pcm_hw_params *hw_params) 1138 { 1139 struct snd_intelhad *intelhaddata; 1140 int buf_size; 1141 1142 intelhaddata = snd_pcm_substream_chip(substream); 1143 buf_size = params_buffer_bytes(hw_params); 1144 dev_dbg(intelhaddata->dev, "%s:allocated memory = %d\n", 1145 __func__, buf_size); 1146 return 0; 1147 } 1148 1149 /* 1150 * ALSA PCM trigger callback 1151 */ 1152 static int had_pcm_trigger(struct snd_pcm_substream *substream, int cmd) 1153 { 1154 int retval = 0; 1155 struct snd_intelhad *intelhaddata; 1156 1157 intelhaddata = snd_pcm_substream_chip(substream); 1158 1159 spin_lock(&intelhaddata->had_spinlock); 1160 switch (cmd) { 1161 case SNDRV_PCM_TRIGGER_START: 1162 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1163 case SNDRV_PCM_TRIGGER_RESUME: 1164 /* Enable Audio */ 1165 had_ack_irqs(intelhaddata); /* FIXME: do we need this? */ 1166 had_enable_audio(intelhaddata, true); 1167 break; 1168 1169 case SNDRV_PCM_TRIGGER_STOP: 1170 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1171 /* Disable Audio */ 1172 had_enable_audio(intelhaddata, false); 1173 break; 1174 1175 default: 1176 retval = -EINVAL; 1177 } 1178 spin_unlock(&intelhaddata->had_spinlock); 1179 return retval; 1180 } 1181 1182 /* 1183 * ALSA PCM prepare callback 1184 */ 1185 static int had_pcm_prepare(struct snd_pcm_substream *substream) 1186 { 1187 int retval; 1188 u32 disp_samp_freq, n_param; 1189 u32 link_rate = 0; 1190 struct snd_intelhad *intelhaddata; 1191 struct snd_pcm_runtime *runtime; 1192 1193 intelhaddata = snd_pcm_substream_chip(substream); 1194 runtime = substream->runtime; 1195 1196 dev_dbg(intelhaddata->dev, "period_size=%d\n", 1197 (int)frames_to_bytes(runtime, runtime->period_size)); 1198 dev_dbg(intelhaddata->dev, "periods=%d\n", runtime->periods); 1199 dev_dbg(intelhaddata->dev, "buffer_size=%d\n", 1200 (int)snd_pcm_lib_buffer_bytes(substream)); 1201 dev_dbg(intelhaddata->dev, "rate=%d\n", runtime->rate); 1202 dev_dbg(intelhaddata->dev, "channels=%d\n", runtime->channels); 1203 1204 /* Get N value in KHz */ 1205 disp_samp_freq = intelhaddata->tmds_clock_speed; 1206 1207 retval = had_prog_n(substream->runtime->rate, &n_param, intelhaddata); 1208 if (retval) { 1209 dev_err(intelhaddata->dev, 1210 "programming N value failed %#x\n", retval); 1211 goto prep_end; 1212 } 1213 1214 if (intelhaddata->dp_output) 1215 link_rate = intelhaddata->link_rate; 1216 1217 had_prog_cts(substream->runtime->rate, disp_samp_freq, link_rate, 1218 n_param, intelhaddata); 1219 1220 had_prog_dip(substream, intelhaddata); 1221 1222 retval = had_init_audio_ctrl(substream, intelhaddata); 1223 1224 /* Prog buffer address */ 1225 had_init_ringbuf(substream, intelhaddata); 1226 1227 /* 1228 * Program channel mapping in following order: 1229 * FL, FR, C, LFE, RL, RR 1230 */ 1231 1232 had_write_register(intelhaddata, AUD_BUF_CH_SWAP, SWAP_LFE_CENTER); 1233 1234 prep_end: 1235 return retval; 1236 } 1237 1238 /* 1239 * ALSA PCM pointer callback 1240 */ 1241 static snd_pcm_uframes_t had_pcm_pointer(struct snd_pcm_substream *substream) 1242 { 1243 struct snd_intelhad *intelhaddata; 1244 int len; 1245 1246 intelhaddata = snd_pcm_substream_chip(substream); 1247 1248 if (!intelhaddata->connected) 1249 return SNDRV_PCM_POS_XRUN; 1250 1251 len = had_process_ringbuf(substream, intelhaddata); 1252 if (len < 0) 1253 return SNDRV_PCM_POS_XRUN; 1254 len = bytes_to_frames(substream->runtime, len); 1255 /* wrapping may happen when periods=1 */ 1256 len %= substream->runtime->buffer_size; 1257 return len; 1258 } 1259 1260 /* 1261 * ALSA PCM ops 1262 */ 1263 static const struct snd_pcm_ops had_pcm_ops = { 1264 .open = had_pcm_open, 1265 .close = had_pcm_close, 1266 .hw_params = had_pcm_hw_params, 1267 .prepare = had_pcm_prepare, 1268 .trigger = had_pcm_trigger, 1269 .sync_stop = had_pcm_sync_stop, 1270 .pointer = had_pcm_pointer, 1271 }; 1272 1273 /* process mode change of the running stream; called in mutex */ 1274 static int had_process_mode_change(struct snd_intelhad *intelhaddata) 1275 { 1276 struct snd_pcm_substream *substream; 1277 int retval = 0; 1278 u32 disp_samp_freq, n_param; 1279 u32 link_rate = 0; 1280 1281 substream = had_substream_get(intelhaddata); 1282 if (!substream) 1283 return 0; 1284 1285 /* Disable Audio */ 1286 had_enable_audio(intelhaddata, false); 1287 1288 /* Update CTS value */ 1289 disp_samp_freq = intelhaddata->tmds_clock_speed; 1290 1291 retval = had_prog_n(substream->runtime->rate, &n_param, intelhaddata); 1292 if (retval) { 1293 dev_err(intelhaddata->dev, 1294 "programming N value failed %#x\n", retval); 1295 goto out; 1296 } 1297 1298 if (intelhaddata->dp_output) 1299 link_rate = intelhaddata->link_rate; 1300 1301 had_prog_cts(substream->runtime->rate, disp_samp_freq, link_rate, 1302 n_param, intelhaddata); 1303 1304 /* Enable Audio */ 1305 had_enable_audio(intelhaddata, true); 1306 1307 out: 1308 had_substream_put(intelhaddata); 1309 return retval; 1310 } 1311 1312 /* process hot plug, called from wq with mutex locked */ 1313 static void had_process_hot_plug(struct snd_intelhad *intelhaddata) 1314 { 1315 struct snd_pcm_substream *substream; 1316 1317 spin_lock_irq(&intelhaddata->had_spinlock); 1318 if (intelhaddata->connected) { 1319 dev_dbg(intelhaddata->dev, "Device already connected\n"); 1320 spin_unlock_irq(&intelhaddata->had_spinlock); 1321 return; 1322 } 1323 1324 /* Disable Audio */ 1325 had_enable_audio(intelhaddata, false); 1326 1327 intelhaddata->connected = true; 1328 dev_dbg(intelhaddata->dev, 1329 "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_CONNECTED\n", 1330 __func__, __LINE__); 1331 spin_unlock_irq(&intelhaddata->had_spinlock); 1332 1333 had_build_channel_allocation_map(intelhaddata); 1334 1335 /* Report to above ALSA layer */ 1336 substream = had_substream_get(intelhaddata); 1337 if (substream) { 1338 snd_pcm_stop_xrun(substream); 1339 had_substream_put(intelhaddata); 1340 } 1341 1342 snd_jack_report(intelhaddata->jack, SND_JACK_AVOUT); 1343 } 1344 1345 /* process hot unplug, called from wq with mutex locked */ 1346 static void had_process_hot_unplug(struct snd_intelhad *intelhaddata) 1347 { 1348 struct snd_pcm_substream *substream; 1349 1350 spin_lock_irq(&intelhaddata->had_spinlock); 1351 if (!intelhaddata->connected) { 1352 dev_dbg(intelhaddata->dev, "Device already disconnected\n"); 1353 spin_unlock_irq(&intelhaddata->had_spinlock); 1354 return; 1355 1356 } 1357 1358 /* Disable Audio */ 1359 had_enable_audio(intelhaddata, false); 1360 1361 intelhaddata->connected = false; 1362 dev_dbg(intelhaddata->dev, 1363 "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_DISCONNECTED\n", 1364 __func__, __LINE__); 1365 spin_unlock_irq(&intelhaddata->had_spinlock); 1366 1367 kfree(intelhaddata->chmap->chmap); 1368 intelhaddata->chmap->chmap = NULL; 1369 1370 /* Report to above ALSA layer */ 1371 substream = had_substream_get(intelhaddata); 1372 if (substream) { 1373 snd_pcm_stop_xrun(substream); 1374 had_substream_put(intelhaddata); 1375 } 1376 1377 snd_jack_report(intelhaddata->jack, 0); 1378 } 1379 1380 /* 1381 * ALSA iec958 and ELD controls 1382 */ 1383 1384 static int had_iec958_info(struct snd_kcontrol *kcontrol, 1385 struct snd_ctl_elem_info *uinfo) 1386 { 1387 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1388 uinfo->count = 1; 1389 return 0; 1390 } 1391 1392 static int had_iec958_get(struct snd_kcontrol *kcontrol, 1393 struct snd_ctl_elem_value *ucontrol) 1394 { 1395 struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol); 1396 1397 mutex_lock(&intelhaddata->mutex); 1398 ucontrol->value.iec958.status[0] = (intelhaddata->aes_bits >> 0) & 0xff; 1399 ucontrol->value.iec958.status[1] = (intelhaddata->aes_bits >> 8) & 0xff; 1400 ucontrol->value.iec958.status[2] = 1401 (intelhaddata->aes_bits >> 16) & 0xff; 1402 ucontrol->value.iec958.status[3] = 1403 (intelhaddata->aes_bits >> 24) & 0xff; 1404 mutex_unlock(&intelhaddata->mutex); 1405 return 0; 1406 } 1407 1408 static int had_iec958_mask_get(struct snd_kcontrol *kcontrol, 1409 struct snd_ctl_elem_value *ucontrol) 1410 { 1411 ucontrol->value.iec958.status[0] = 0xff; 1412 ucontrol->value.iec958.status[1] = 0xff; 1413 ucontrol->value.iec958.status[2] = 0xff; 1414 ucontrol->value.iec958.status[3] = 0xff; 1415 return 0; 1416 } 1417 1418 static int had_iec958_put(struct snd_kcontrol *kcontrol, 1419 struct snd_ctl_elem_value *ucontrol) 1420 { 1421 unsigned int val; 1422 struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol); 1423 int changed = 0; 1424 1425 val = (ucontrol->value.iec958.status[0] << 0) | 1426 (ucontrol->value.iec958.status[1] << 8) | 1427 (ucontrol->value.iec958.status[2] << 16) | 1428 (ucontrol->value.iec958.status[3] << 24); 1429 mutex_lock(&intelhaddata->mutex); 1430 if (intelhaddata->aes_bits != val) { 1431 intelhaddata->aes_bits = val; 1432 changed = 1; 1433 } 1434 mutex_unlock(&intelhaddata->mutex); 1435 return changed; 1436 } 1437 1438 static int had_ctl_eld_info(struct snd_kcontrol *kcontrol, 1439 struct snd_ctl_elem_info *uinfo) 1440 { 1441 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 1442 uinfo->count = HDMI_MAX_ELD_BYTES; 1443 return 0; 1444 } 1445 1446 static int had_ctl_eld_get(struct snd_kcontrol *kcontrol, 1447 struct snd_ctl_elem_value *ucontrol) 1448 { 1449 struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol); 1450 1451 mutex_lock(&intelhaddata->mutex); 1452 memcpy(ucontrol->value.bytes.data, intelhaddata->eld, 1453 HDMI_MAX_ELD_BYTES); 1454 mutex_unlock(&intelhaddata->mutex); 1455 return 0; 1456 } 1457 1458 static const struct snd_kcontrol_new had_controls[] = { 1459 { 1460 .access = SNDRV_CTL_ELEM_ACCESS_READ, 1461 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1462 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK), 1463 .info = had_iec958_info, /* shared */ 1464 .get = had_iec958_mask_get, 1465 }, 1466 { 1467 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1468 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), 1469 .info = had_iec958_info, 1470 .get = had_iec958_get, 1471 .put = had_iec958_put, 1472 }, 1473 { 1474 .access = (SNDRV_CTL_ELEM_ACCESS_READ | 1475 SNDRV_CTL_ELEM_ACCESS_VOLATILE), 1476 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1477 .name = "ELD", 1478 .info = had_ctl_eld_info, 1479 .get = had_ctl_eld_get, 1480 }, 1481 }; 1482 1483 /* 1484 * audio interrupt handler 1485 */ 1486 static irqreturn_t display_pipe_interrupt_handler(int irq, void *dev_id) 1487 { 1488 struct snd_intelhad_card *card_ctx = dev_id; 1489 u32 audio_stat[3] = {}; 1490 int pipe, port; 1491 1492 for_each_pipe(card_ctx, pipe) { 1493 /* use raw register access to ack IRQs even while disconnected */ 1494 audio_stat[pipe] = had_read_register_raw(card_ctx, pipe, 1495 AUD_HDMI_STATUS) & 1496 (HDMI_AUDIO_UNDERRUN | HDMI_AUDIO_BUFFER_DONE); 1497 1498 if (audio_stat[pipe]) 1499 had_write_register_raw(card_ctx, pipe, 1500 AUD_HDMI_STATUS, audio_stat[pipe]); 1501 } 1502 1503 for_each_port(card_ctx, port) { 1504 struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port]; 1505 int pipe = ctx->pipe; 1506 1507 if (pipe < 0) 1508 continue; 1509 1510 if (audio_stat[pipe] & HDMI_AUDIO_BUFFER_DONE) 1511 had_process_buffer_done(ctx); 1512 if (audio_stat[pipe] & HDMI_AUDIO_UNDERRUN) 1513 had_process_buffer_underrun(ctx); 1514 } 1515 1516 return IRQ_HANDLED; 1517 } 1518 1519 /* 1520 * monitor plug/unplug notification from i915; just kick off the work 1521 */ 1522 static void notify_audio_lpe(struct platform_device *pdev, int port) 1523 { 1524 struct snd_intelhad_card *card_ctx = platform_get_drvdata(pdev); 1525 struct snd_intelhad *ctx; 1526 1527 ctx = &card_ctx->pcm_ctx[single_port ? 0 : port]; 1528 if (single_port) 1529 ctx->port = port; 1530 1531 schedule_work(&ctx->hdmi_audio_wq); 1532 } 1533 1534 /* the work to handle monitor hot plug/unplug */ 1535 static void had_audio_wq(struct work_struct *work) 1536 { 1537 struct snd_intelhad *ctx = 1538 container_of(work, struct snd_intelhad, hdmi_audio_wq); 1539 struct intel_hdmi_lpe_audio_pdata *pdata = ctx->dev->platform_data; 1540 struct intel_hdmi_lpe_audio_port_pdata *ppdata = &pdata->port[ctx->port]; 1541 int ret; 1542 1543 ret = pm_runtime_resume_and_get(ctx->dev); 1544 if (ret < 0) 1545 return; 1546 1547 mutex_lock(&ctx->mutex); 1548 if (ppdata->pipe < 0) { 1549 dev_dbg(ctx->dev, "%s: Event: HAD_NOTIFY_HOT_UNPLUG : port = %d\n", 1550 __func__, ctx->port); 1551 1552 memset(ctx->eld, 0, sizeof(ctx->eld)); /* clear the old ELD */ 1553 1554 ctx->dp_output = false; 1555 ctx->tmds_clock_speed = 0; 1556 ctx->link_rate = 0; 1557 1558 /* Shut down the stream */ 1559 had_process_hot_unplug(ctx); 1560 1561 ctx->pipe = -1; 1562 } else { 1563 dev_dbg(ctx->dev, "%s: HAD_NOTIFY_ELD : port = %d, tmds = %d\n", 1564 __func__, ctx->port, ppdata->ls_clock); 1565 1566 memcpy(ctx->eld, ppdata->eld, sizeof(ctx->eld)); 1567 1568 ctx->dp_output = ppdata->dp_output; 1569 if (ctx->dp_output) { 1570 ctx->tmds_clock_speed = 0; 1571 ctx->link_rate = ppdata->ls_clock; 1572 } else { 1573 ctx->tmds_clock_speed = ppdata->ls_clock; 1574 ctx->link_rate = 0; 1575 } 1576 1577 /* 1578 * Shut down the stream before we change 1579 * the pipe assignment for this pcm device 1580 */ 1581 had_process_hot_plug(ctx); 1582 1583 ctx->pipe = ppdata->pipe; 1584 1585 /* Restart the stream if necessary */ 1586 had_process_mode_change(ctx); 1587 } 1588 1589 mutex_unlock(&ctx->mutex); 1590 pm_runtime_put_autosuspend(ctx->dev); 1591 } 1592 1593 /* 1594 * Jack interface 1595 */ 1596 static int had_create_jack(struct snd_intelhad *ctx, 1597 struct snd_pcm *pcm) 1598 { 1599 char hdmi_str[32]; 1600 int err; 1601 1602 snprintf(hdmi_str, sizeof(hdmi_str), 1603 "HDMI/DP,pcm=%d", pcm->device); 1604 1605 err = snd_jack_new(ctx->card_ctx->card, hdmi_str, 1606 SND_JACK_AVOUT, &ctx->jack, 1607 true, false); 1608 if (err < 0) 1609 return err; 1610 ctx->jack->private_data = ctx; 1611 return 0; 1612 } 1613 1614 /* 1615 * PM callbacks 1616 */ 1617 1618 static int hdmi_lpe_audio_suspend(struct device *dev) 1619 { 1620 struct snd_intelhad_card *card_ctx = dev_get_drvdata(dev); 1621 1622 snd_power_change_state(card_ctx->card, SNDRV_CTL_POWER_D3hot); 1623 1624 return 0; 1625 } 1626 1627 static int hdmi_lpe_audio_resume(struct device *dev) 1628 { 1629 struct snd_intelhad_card *card_ctx = dev_get_drvdata(dev); 1630 1631 pm_runtime_mark_last_busy(dev); 1632 1633 snd_power_change_state(card_ctx->card, SNDRV_CTL_POWER_D0); 1634 1635 return 0; 1636 } 1637 1638 /* release resources */ 1639 static void hdmi_lpe_audio_free(struct snd_card *card) 1640 { 1641 struct snd_intelhad_card *card_ctx = card->private_data; 1642 struct intel_hdmi_lpe_audio_pdata *pdata = card_ctx->dev->platform_data; 1643 int port; 1644 1645 spin_lock_irq(&pdata->lpe_audio_slock); 1646 pdata->notify_audio_lpe = NULL; 1647 spin_unlock_irq(&pdata->lpe_audio_slock); 1648 1649 for_each_port(card_ctx, port) { 1650 struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port]; 1651 1652 cancel_work_sync(&ctx->hdmi_audio_wq); 1653 } 1654 } 1655 1656 /* 1657 * hdmi_lpe_audio_probe - start bridge with i915 1658 * 1659 * This function is called when the i915 driver creates the 1660 * hdmi-lpe-audio platform device. 1661 */ 1662 static int __hdmi_lpe_audio_probe(struct platform_device *pdev) 1663 { 1664 struct snd_card *card; 1665 struct snd_intelhad_card *card_ctx; 1666 struct snd_intelhad *ctx; 1667 struct snd_pcm *pcm; 1668 struct intel_hdmi_lpe_audio_pdata *pdata; 1669 int irq; 1670 struct resource *res_mmio; 1671 int port, ret; 1672 1673 pdata = pdev->dev.platform_data; 1674 if (!pdata) { 1675 dev_err(&pdev->dev, "%s: quit: pdata not allocated by i915!!\n", __func__); 1676 return -EINVAL; 1677 } 1678 1679 /* get resources */ 1680 irq = platform_get_irq(pdev, 0); 1681 if (irq < 0) 1682 return irq; 1683 1684 res_mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1685 if (!res_mmio) { 1686 dev_err(&pdev->dev, "Could not get IO_MEM resources\n"); 1687 return -ENXIO; 1688 } 1689 1690 /* create a card instance with ALSA framework */ 1691 ret = snd_devm_card_new(&pdev->dev, hdmi_card_index, hdmi_card_id, 1692 THIS_MODULE, sizeof(*card_ctx), &card); 1693 if (ret) 1694 return ret; 1695 1696 card_ctx = card->private_data; 1697 card_ctx->dev = &pdev->dev; 1698 card_ctx->card = card; 1699 strscpy(card->driver, INTEL_HAD); 1700 strscpy(card->shortname, "Intel HDMI/DP LPE Audio"); 1701 strscpy(card->longname, "Intel HDMI/DP LPE Audio"); 1702 1703 card_ctx->irq = -1; 1704 1705 card->private_free = hdmi_lpe_audio_free; 1706 1707 platform_set_drvdata(pdev, card_ctx); 1708 1709 card_ctx->num_pipes = pdata->num_pipes; 1710 card_ctx->num_ports = single_port ? 1 : pdata->num_ports; 1711 1712 for_each_port(card_ctx, port) { 1713 ctx = &card_ctx->pcm_ctx[port]; 1714 ctx->card_ctx = card_ctx; 1715 ctx->dev = card_ctx->dev; 1716 ctx->port = single_port ? -1 : port; 1717 ctx->pipe = -1; 1718 1719 spin_lock_init(&ctx->had_spinlock); 1720 mutex_init(&ctx->mutex); 1721 INIT_WORK(&ctx->hdmi_audio_wq, had_audio_wq); 1722 } 1723 1724 dev_dbg(&pdev->dev, "%s: mmio_start = 0x%x, mmio_end = 0x%x\n", 1725 __func__, (unsigned int)res_mmio->start, 1726 (unsigned int)res_mmio->end); 1727 1728 card_ctx->mmio_start = 1729 devm_ioremap(&pdev->dev, res_mmio->start, 1730 (size_t)(resource_size(res_mmio))); 1731 if (!card_ctx->mmio_start) { 1732 dev_err(&pdev->dev, "Could not get ioremap\n"); 1733 return -EACCES; 1734 } 1735 1736 /* setup interrupt handler */ 1737 ret = devm_request_irq(&pdev->dev, irq, display_pipe_interrupt_handler, 1738 0, pdev->name, card_ctx); 1739 if (ret < 0) { 1740 dev_err(&pdev->dev, "request_irq failed\n"); 1741 return ret; 1742 } 1743 1744 card_ctx->irq = irq; 1745 1746 /* only 32bit addressable */ 1747 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 1748 if (ret) 1749 return ret; 1750 1751 init_channel_allocations(); 1752 1753 card_ctx->num_pipes = pdata->num_pipes; 1754 card_ctx->num_ports = single_port ? 1 : pdata->num_ports; 1755 1756 for_each_port(card_ctx, port) { 1757 int i; 1758 1759 ctx = &card_ctx->pcm_ctx[port]; 1760 ret = snd_pcm_new(card, INTEL_HAD, port, MAX_PB_STREAMS, 1761 MAX_CAP_STREAMS, &pcm); 1762 if (ret) 1763 return ret; 1764 1765 /* setup private data which can be retrieved when required */ 1766 pcm->private_data = ctx; 1767 pcm->info_flags = 0; 1768 strscpy(pcm->name, card->shortname, sizeof(pcm->name)); 1769 /* setup the ops for playback */ 1770 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &had_pcm_ops); 1771 1772 /* allocate dma pages; 1773 * try to allocate 600k buffer as default which is large enough 1774 */ 1775 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV_WC, 1776 card->dev, HAD_DEFAULT_BUFFER, 1777 HAD_MAX_BUFFER); 1778 1779 /* create controls */ 1780 for (i = 0; i < ARRAY_SIZE(had_controls); i++) { 1781 struct snd_kcontrol *kctl; 1782 1783 kctl = snd_ctl_new1(&had_controls[i], ctx); 1784 if (!kctl) 1785 return -ENOMEM; 1786 1787 kctl->id.device = pcm->device; 1788 1789 ret = snd_ctl_add(card, kctl); 1790 if (ret < 0) 1791 return ret; 1792 } 1793 1794 /* Register channel map controls */ 1795 ret = had_register_chmap_ctls(ctx, pcm); 1796 if (ret < 0) 1797 return ret; 1798 1799 ret = had_create_jack(ctx, pcm); 1800 if (ret < 0) 1801 return ret; 1802 } 1803 1804 ret = snd_card_register(card); 1805 if (ret) 1806 return ret; 1807 1808 spin_lock_irq(&pdata->lpe_audio_slock); 1809 pdata->notify_audio_lpe = notify_audio_lpe; 1810 spin_unlock_irq(&pdata->lpe_audio_slock); 1811 1812 pm_runtime_set_autosuspend_delay(&pdev->dev, INTEL_HDMI_AUDIO_SUSPEND_DELAY_MS); 1813 pm_runtime_use_autosuspend(&pdev->dev); 1814 pm_runtime_enable(&pdev->dev); 1815 pm_runtime_mark_last_busy(&pdev->dev); 1816 pm_runtime_idle(&pdev->dev); 1817 1818 dev_dbg(&pdev->dev, "%s: handle pending notification\n", __func__); 1819 for_each_port(card_ctx, port) { 1820 struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port]; 1821 1822 schedule_work(&ctx->hdmi_audio_wq); 1823 } 1824 1825 return 0; 1826 } 1827 1828 static int hdmi_lpe_audio_probe(struct platform_device *pdev) 1829 { 1830 return snd_card_free_on_error(&pdev->dev, __hdmi_lpe_audio_probe(pdev)); 1831 } 1832 1833 static const struct dev_pm_ops hdmi_lpe_audio_pm = { 1834 SYSTEM_SLEEP_PM_OPS(hdmi_lpe_audio_suspend, hdmi_lpe_audio_resume) 1835 }; 1836 1837 static struct platform_driver hdmi_lpe_audio_driver = { 1838 .driver = { 1839 .name = "hdmi-lpe-audio", 1840 .pm = pm_ptr(&hdmi_lpe_audio_pm), 1841 }, 1842 .probe = hdmi_lpe_audio_probe, 1843 }; 1844 1845 module_platform_driver(hdmi_lpe_audio_driver); 1846 MODULE_ALIAS("platform:hdmi_lpe_audio"); 1847 1848 MODULE_AUTHOR("Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>"); 1849 MODULE_AUTHOR("Ramesh Babu K V <ramesh.babu@intel.com>"); 1850 MODULE_AUTHOR("Vaibhav Agarwal <vaibhav.agarwal@intel.com>"); 1851 MODULE_AUTHOR("Jerome Anand <jerome.anand@intel.com>"); 1852 MODULE_DESCRIPTION("Intel HDMI Audio driver"); 1853 MODULE_LICENSE("GPL v2"); 1854