1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright(c) 2020, Analogix Semiconductor. All rights reserved. 4 * 5 */ 6 7 #ifndef __ANX7625_H__ 8 #define __ANX7625_H__ 9 10 #define ANX7625_DRV_VERSION "0.1.04" 11 12 /* Loading OCM re-trying times */ 13 #define OCM_LOADING_TIME 10 14 15 /********* ANX7625 Register **********/ 16 #define TX_P0_ADDR 0x70 17 #define TX_P1_ADDR 0x7A 18 #define TX_P2_ADDR 0x72 19 20 #define RX_P0_ADDR 0x7e 21 #define RX_P1_ADDR 0x84 22 #define RX_P2_ADDR 0x54 23 24 #define RSVD_00_ADDR 0x00 25 #define RSVD_D1_ADDR 0xD1 26 #define RSVD_60_ADDR 0x60 27 #define RSVD_39_ADDR 0x39 28 #define RSVD_7F_ADDR 0x7F 29 30 #define TCPC_INTERFACE_ADDR 0x58 31 32 /* Clock frequency in Hz */ 33 #define XTAL_FRQ (27 * 1000000) 34 35 #define POST_DIVIDER_MIN 1 36 #define POST_DIVIDER_MAX 16 37 #define PLL_OUT_FREQ_MIN 520000000UL 38 #define PLL_OUT_FREQ_MAX 730000000UL 39 #define PLL_OUT_FREQ_ABS_MIN 300000000UL 40 #define PLL_OUT_FREQ_ABS_MAX 800000000UL 41 #define MAX_UNSIGNED_24BIT 16777215UL 42 43 /***************************************************************/ 44 /* Register definition of device address 0x58 */ 45 46 #define PRODUCT_ID_L 0x02 47 #define PRODUCT_ID_H 0x03 48 49 #define INTR_ALERT_1 0xCC 50 #define INTR_SOFTWARE_INT BIT(3) 51 #define INTR_RECEIVED_MSG BIT(5) 52 53 #define SYSTEM_STSTUS 0x45 54 #define INTERFACE_CHANGE_INT_MASK 0x43 55 #define INTERFACE_CHANGE_INT 0x44 56 #define VCONN_STATUS BIT(2) 57 #define VBUS_STATUS BIT(3) 58 #define CC_STATUS BIT(4) 59 #define DATA_ROLE_STATUS BIT(5) 60 #define HPD_STATUS BIT(7) 61 62 #define NEW_CC_STATUS 0x46 63 #define CC1_RD BIT(0) 64 #define CC1_RA BIT(1) 65 #define CC1_RP (BIT(2) | BIT(3)) 66 #define CC2_RD BIT(4) 67 #define CC2_RA BIT(5) 68 #define CC2_RP (BIT(6) | BIT(7)) 69 70 #define CMD_SEND_BUF 0xC0 71 #define CMD_RECV_BUF 0xE0 72 73 /******** END of I2C Address 0x58 ********/ 74 75 /***************************************************************/ 76 /* Register definition of device address 0x70 */ 77 #define TX_HDCP_CTRL0 0x01 78 #define STORE_AN BIT(7) 79 #define RX_REPEATER BIT(6) 80 #define RE_AUTHEN BIT(5) 81 #define SW_AUTH_OK BIT(4) 82 #define HARD_AUTH_EN BIT(3) 83 #define ENC_EN BIT(2) 84 #define BKSV_SRM_PASS BIT(1) 85 #define KSVLIST_VLD BIT(0) 86 87 #define SP_TX_WAIT_R0_TIME 0x40 88 #define SP_TX_WAIT_KSVR_TIME 0x42 89 #define SP_TX_SYS_CTRL1_REG 0x80 90 #define HDCP2TX_FW_EN BIT(4) 91 92 #define SP_TX_LINK_BW_SET_REG 0xA0 93 #define SP_TX_LANE_COUNT_SET_REG 0xA1 94 95 #define M_VID_0 0xC0 96 #define M_VID_1 0xC1 97 #define M_VID_2 0xC2 98 #define N_VID_0 0xC3 99 #define N_VID_1 0xC4 100 #define N_VID_2 0xC5 101 102 #define KEY_START_ADDR 0x9000 103 #define KEY_RESERVED 416 104 105 #define HDCP14KEY_START_ADDR (KEY_START_ADDR + KEY_RESERVED) 106 #define HDCP14KEY_SIZE 624 107 108 /***************************************************************/ 109 /* Register definition of device address 0x72 */ 110 #define AUX_RST 0x04 111 #define RST_CTRL2 0x07 112 113 #define SP_TX_TOTAL_LINE_STA_L 0x24 114 #define SP_TX_TOTAL_LINE_STA_H 0x25 115 #define SP_TX_ACT_LINE_STA_L 0x26 116 #define SP_TX_ACT_LINE_STA_H 0x27 117 #define SP_TX_V_F_PORCH_STA 0x28 118 #define SP_TX_V_SYNC_STA 0x29 119 #define SP_TX_V_B_PORCH_STA 0x2A 120 #define SP_TX_TOTAL_PIXEL_STA_L 0x2B 121 #define SP_TX_TOTAL_PIXEL_STA_H 0x2C 122 #define SP_TX_ACT_PIXEL_STA_L 0x2D 123 #define SP_TX_ACT_PIXEL_STA_H 0x2E 124 #define SP_TX_H_F_PORCH_STA_L 0x2F 125 #define SP_TX_H_F_PORCH_STA_H 0x30 126 #define SP_TX_H_SYNC_STA_L 0x31 127 #define SP_TX_H_SYNC_STA_H 0x32 128 #define SP_TX_H_B_PORCH_STA_L 0x33 129 #define SP_TX_H_B_PORCH_STA_H 0x34 130 131 #define SP_TX_VID_CTRL 0x84 132 #define SP_TX_BPC_MASK 0xE0 133 #define SP_TX_BPC_6 0x00 134 #define SP_TX_BPC_8 0x20 135 #define SP_TX_BPC_10 0x40 136 #define SP_TX_BPC_12 0x60 137 138 #define VIDEO_BIT_MATRIX_12 0x4c 139 140 #define AUDIO_CHANNEL_STATUS_1 0xd0 141 #define AUDIO_CHANNEL_STATUS_2 0xd1 142 #define AUDIO_CHANNEL_STATUS_3 0xd2 143 #define AUDIO_CHANNEL_STATUS_4 0xd3 144 #define AUDIO_CHANNEL_STATUS_5 0xd4 145 #define AUDIO_CHANNEL_STATUS_6 0xd5 146 #define TDM_SLAVE_MODE 0x10 147 #define I2S_SLAVE_MODE 0x08 148 #define AUDIO_LAYOUT 0x01 149 150 #define HPD_DET_TIMER_BIT0_7 0xea 151 #define HPD_DET_TIMER_BIT8_15 0xeb 152 #define HPD_DET_TIMER_BIT16_23 0xec 153 /* HPD debounce time 2ms for 27M clock */ 154 #define HPD_TIME 54000 155 156 #define AUDIO_CONTROL_REGISTER 0xe6 157 #define TDM_TIMING_MODE 0x08 158 159 #define I2C_ADDR_72_DPTX 0x72 160 161 #define HP_MIN 8 162 #define HBLANKING_MIN 80 163 #define SYNC_LEN_DEF 32 164 #define HFP_HBP_DEF ((HBLANKING_MIN - SYNC_LEN_DEF) / 2) 165 #define VIDEO_CONTROL_0 0x08 166 167 #define ACTIVE_LINES_L 0x14 168 #define ACTIVE_LINES_H 0x15 /* Bit[7:6] are reserved */ 169 #define VERTICAL_FRONT_PORCH 0x16 170 #define VERTICAL_SYNC_WIDTH 0x17 171 #define VERTICAL_BACK_PORCH 0x18 172 173 #define HORIZONTAL_TOTAL_PIXELS_L 0x19 174 #define HORIZONTAL_TOTAL_PIXELS_H 0x1A /* Bit[7:6] are reserved */ 175 #define HORIZONTAL_ACTIVE_PIXELS_L 0x1B 176 #define HORIZONTAL_ACTIVE_PIXELS_H 0x1C /* Bit[7:6] are reserved */ 177 #define HORIZONTAL_FRONT_PORCH_L 0x1D 178 #define HORIZONTAL_FRONT_PORCH_H 0x1E /* Bit[7:4] are reserved */ 179 #define HORIZONTAL_SYNC_WIDTH_L 0x1F 180 #define HORIZONTAL_SYNC_WIDTH_H 0x20 /* Bit[7:4] are reserved */ 181 #define HORIZONTAL_BACK_PORCH_L 0x21 182 #define HORIZONTAL_BACK_PORCH_H 0x22 /* Bit[7:4] are reserved */ 183 184 /******** END of I2C Address 0x72 *********/ 185 186 /***************************************************************/ 187 /* Register definition of device address 0x7a */ 188 #define DP_TX_SWING_REG_CNT 0x14 189 #define DP_TX_LANE0_SWING_REG0 0x00 190 #define DP_TX_LANE1_SWING_REG0 0x14 191 /******** END of I2C Address 0x7a *********/ 192 193 /***************************************************************/ 194 /* Register definition of device address 0x7e */ 195 196 #define I2C_ADDR_7E_FLASH_CONTROLLER 0x7E 197 198 #define R_BOOT_RETRY 0x00 199 #define R_RAM_ADDR_H 0x01 200 #define R_RAM_ADDR_L 0x02 201 #define R_RAM_LEN_H 0x03 202 #define R_RAM_LEN_L 0x04 203 #define FLASH_LOAD_STA 0x05 204 #define FLASH_LOAD_STA_CHK BIT(7) 205 206 #define R_RAM_CTRL 0x05 207 /* bit positions */ 208 #define FLASH_DONE BIT(7) 209 #define BOOT_LOAD_DONE BIT(6) 210 #define CRC_OK BIT(5) 211 #define LOAD_DONE BIT(4) 212 #define O_RW_DONE BIT(3) 213 #define FUSE_BUSY BIT(2) 214 #define DECRYPT_EN BIT(1) 215 #define LOAD_START BIT(0) 216 217 #define FLASH_ADDR_HIGH 0x0F 218 #define FLASH_ADDR_LOW 0x10 219 #define FLASH_LEN_HIGH 0x31 220 #define FLASH_LEN_LOW 0x32 221 #define R_FLASH_RW_CTRL 0x33 222 /* bit positions */ 223 #define READ_DELAY_SELECT BIT(7) 224 #define GENERAL_INSTRUCTION_EN BIT(6) 225 #define FLASH_ERASE_EN BIT(5) 226 #define RDID_READ_EN BIT(4) 227 #define REMS_READ_EN BIT(3) 228 #define WRITE_STATUS_EN BIT(2) 229 #define FLASH_READ BIT(1) 230 #define FLASH_WRITE BIT(0) 231 232 #define FLASH_BUF_BASE_ADDR 0x60 233 #define FLASH_BUF_LEN 0x20 234 235 #define XTAL_FRQ_SEL 0x3F 236 /* bit field positions */ 237 #define XTAL_FRQ_SEL_POS 5 238 /* bit field values */ 239 #define XTAL_FRQ_19M2 (0 << XTAL_FRQ_SEL_POS) 240 #define XTAL_FRQ_27M (4 << XTAL_FRQ_SEL_POS) 241 242 #define R_DSC_CTRL_0 0x40 243 #define READ_STATUS_EN 7 244 #define CLK_1MEG_RB 6 /* 1MHz clock reset; 0=reset, 0=reset release */ 245 #define DSC_BIST_DONE 1 /* Bit[5:1]: 1=DSC MBIST pass */ 246 #define DSC_EN 0x01 /* 1=DSC enabled, 0=DSC disabled */ 247 248 #define OCM_FW_VERSION 0x31 249 #define OCM_FW_REVERSION 0x32 250 251 #define AP_AUX_ADDR_7_0 0x11 252 #define AP_AUX_ADDR_15_8 0x12 253 #define AP_AUX_ADDR_19_16 0x13 254 255 /* Bit[0:3] AUX status, bit 4 op_en, bit 5 address only */ 256 #define AP_AUX_CTRL_STATUS 0x14 257 #define AP_AUX_CTRL_OP_EN 0x10 258 #define AP_AUX_CTRL_ADDRONLY 0x20 259 260 #define AP_AUX_BUFF_START 0x15 261 #define PIXEL_CLOCK_L 0x25 262 #define PIXEL_CLOCK_H 0x26 263 264 #define AP_AUX_COMMAND 0x27 /* com+len */ 265 #define LENGTH_SHIFT 4 266 #define DPCD_CMD(len, cmd) ((((len) - 1) << LENGTH_SHIFT) | (cmd)) 267 268 /* Bit 0&1: 3D video structure */ 269 /* 0x01: frame packing, 0x02:Line alternative, 0x03:Side-by-side(full) */ 270 #define AP_AV_STATUS 0x28 271 #define AP_VIDEO_CHG BIT(2) 272 #define AP_AUDIO_CHG BIT(3) 273 #define AP_MIPI_MUTE BIT(4) /* 1:MIPI input mute, 0: ummute */ 274 #define AP_MIPI_RX_EN BIT(5) /* 1: MIPI RX input in 0: no RX in */ 275 #define AP_DISABLE_PD BIT(6) 276 #define AP_DISABLE_DISPLAY BIT(7) 277 278 #define GPIO_CTRL_2 0x49 279 #define HPD_SOURCE BIT(6) 280 281 /***************************************************************/ 282 /* Register definition of device address 0x84 */ 283 #define MIPI_PHY_CONTROL_3 0x03 284 #define MIPI_HS_PWD_CLK 7 285 #define MIPI_HS_RT_CLK 6 286 #define MIPI_PD_CLK 5 287 #define MIPI_CLK_RT_MANUAL_PD_EN 4 288 #define MIPI_CLK_HS_MANUAL_PD_EN 3 289 #define MIPI_CLK_DET_DET_BYPASS 2 290 #define MIPI_CLK_MISS_CTRL 1 291 #define MIPI_PD_LPTX_CH_MANUAL_PD_EN 0 292 293 #define MIPI_LANE_CTRL_0 0x05 294 #define MIPI_TIME_HS_PRPR 0x08 295 296 /* 297 * After MIPI RX protocol layer received video frames, 298 * Protocol layer starts to reconstruct video stream from PHY 299 */ 300 #define MIPI_VIDEO_STABLE_CNT 0x0A 301 302 #define MIPI_LANE_CTRL_10 0x0F 303 #define MIPI_DIGITAL_ADJ_1 0x1B 304 #define IVO_MID 0x26CF 305 306 #define MIPI_PLL_M_NUM_23_16 0x1E 307 #define MIPI_PLL_M_NUM_15_8 0x1F 308 #define MIPI_PLL_M_NUM_7_0 0x20 309 #define MIPI_PLL_N_NUM_23_16 0x21 310 #define MIPI_PLL_N_NUM_15_8 0x22 311 #define MIPI_PLL_N_NUM_7_0 0x23 312 313 #define MIPI_DIGITAL_PLL_6 0x2A 314 /* Bit[7:6]: VCO band control, only effective */ 315 #define MIPI_M_NUM_READY 0x10 316 #define MIPI_N_NUM_READY 0x08 317 #define STABLE_INTEGER_CNT_EN 0x04 318 #define MIPI_PLL_TEST_BIT 0 319 /* Bit[1:0]: test point output select - */ 320 /* 00: VCO power, 01: dvdd_pdt, 10: dvdd, 11: vcox */ 321 322 #define MIPI_DIGITAL_PLL_7 0x2B 323 #define MIPI_PLL_FORCE_N_EN 7 324 #define MIPI_PLL_FORCE_BAND_EN 6 325 326 #define MIPI_PLL_VCO_TUNE_REG 4 327 /* Bit[5:4]: VCO metal capacitance - */ 328 /* 00: +20% fast, 01: +10% fast (default), 10: typical, 11: -10% slow */ 329 #define MIPI_PLL_VCO_TUNE_REG_VAL 0x30 330 331 #define MIPI_PLL_PLL_LDO_BIT 2 332 /* Bit[3:2]: vco_v2i power - */ 333 /* 00: 1.40V, 01: 1.45V (default), 10: 1.50V, 11: 1.55V */ 334 #define MIPI_PLL_RESET_N 0x02 335 #define MIPI_FRQ_FORCE_NDET 0 336 337 #define MIPI_ALERT_CLR_0 0x2D 338 #define HS_link_error_clear 7 339 /* This bit itself is S/C, and it clears 0x84:0x31[7] */ 340 341 #define MIPI_ALERT_OUT_0 0x31 342 #define check_sum_err_hs_sync 7 343 /* This bit is cleared by 0x84:0x2D[7] */ 344 345 #define MIPI_DIGITAL_PLL_8 0x33 346 #define MIPI_POST_DIV_VAL 4 347 /* N means divided by (n+1), n = 0~15 */ 348 #define MIPI_EN_LOCK_FRZ 3 349 #define MIPI_FRQ_COUNTER_RST 2 350 #define MIPI_FRQ_SET_REG_8 1 351 /* Bit 0 is reserved */ 352 353 #define MIPI_DIGITAL_PLL_9 0x34 354 355 #define MIPI_DIGITAL_PLL_16 0x3B 356 #define MIPI_FRQ_FREEZE_NDET 7 357 #define MIPI_FRQ_REG_SET_ENABLE 6 358 #define MIPI_REG_FORCE_SEL_EN 5 359 #define MIPI_REG_SEL_DIV_REG 4 360 #define MIPI_REG_FORCE_PRE_DIV_EN 3 361 /* Bit 2 is reserved */ 362 #define MIPI_FREF_D_IND 1 363 #define REF_CLK_27000KHZ 1 364 #define REF_CLK_19200KHZ 0 365 #define MIPI_REG_PLL_PLL_TEST_ENABLE 0 366 367 #define MIPI_DIGITAL_PLL_18 0x3D 368 #define FRQ_COUNT_RB_SEL 7 369 #define REG_FORCE_POST_DIV_EN 6 370 #define MIPI_DPI_SELECT 5 371 #define SELECT_DSI 1 372 #define SELECT_DPI 0 373 #define REG_BAUD_DIV_RATIO 0 374 375 #define H_BLANK_L 0x3E 376 /* For DSC only */ 377 #define H_BLANK_H 0x3F 378 /* For DSC only; note: bit[7:6] are reserved */ 379 #define MIPI_SWAP 0x4A 380 #define MIPI_SWAP_CH0 7 381 #define MIPI_SWAP_CH1 6 382 #define MIPI_SWAP_CH2 5 383 #define MIPI_SWAP_CH3 4 384 #define MIPI_SWAP_CLK 3 385 /* Bit[2:0] are reserved */ 386 387 /******** END of I2C Address 0x84 *********/ 388 389 /* DPCD regs */ 390 #define DPCD_DPCD_REV 0x00 391 #define DPCD_MAX_LINK_RATE 0x01 392 #define DPCD_MAX_LANE_COUNT 0x02 393 394 /********* ANX7625 Register End **********/ 395 396 /***************** Display *****************/ 397 enum audio_fs { 398 AUDIO_FS_441K = 0x00, 399 AUDIO_FS_48K = 0x02, 400 AUDIO_FS_32K = 0x03, 401 AUDIO_FS_882K = 0x08, 402 AUDIO_FS_96K = 0x0a, 403 AUDIO_FS_1764K = 0x0c, 404 AUDIO_FS_192K = 0x0e 405 }; 406 407 enum audio_wd_len { 408 AUDIO_W_LEN_16_20MAX = 0x02, 409 AUDIO_W_LEN_18_20MAX = 0x04, 410 AUDIO_W_LEN_17_20MAX = 0x0c, 411 AUDIO_W_LEN_19_20MAX = 0x08, 412 AUDIO_W_LEN_20_20MAX = 0x0a, 413 AUDIO_W_LEN_20_24MAX = 0x03, 414 AUDIO_W_LEN_22_24MAX = 0x05, 415 AUDIO_W_LEN_21_24MAX = 0x0d, 416 AUDIO_W_LEN_23_24MAX = 0x09, 417 AUDIO_W_LEN_24_24MAX = 0x0b 418 }; 419 420 #define I2S_CH_2 0x01 421 #define TDM_CH_4 0x03 422 #define TDM_CH_6 0x05 423 #define TDM_CH_8 0x07 424 425 #define MAX_DPCD_BUFFER_SIZE 16 426 427 #define ONE_BLOCK_SIZE 128 428 #define FOUR_BLOCK_SIZE (128 * 4) 429 430 #define MAX_EDID_BLOCK 3 431 #define EDID_TRY_CNT 3 432 #define SUPPORT_PIXEL_CLOCK 300000 433 434 /***************** Display End *****************/ 435 436 #define MAX_LANES_SUPPORT 4 437 438 struct anx7625_platform_data { 439 struct gpio_desc *gpio_p_on; 440 struct gpio_desc *gpio_reset; 441 struct regulator_bulk_data supplies[3]; 442 struct drm_bridge *panel_bridge; 443 int intp_irq; 444 int is_dpi; 445 int mipi_lanes; 446 int audio_en; 447 int dp_lane0_swing_reg_cnt; 448 u8 lane0_reg_data[DP_TX_SWING_REG_CNT]; 449 int dp_lane1_swing_reg_cnt; 450 u8 lane1_reg_data[DP_TX_SWING_REG_CNT]; 451 u32 low_power_mode; 452 struct device_node *mipi_host_node; 453 }; 454 455 struct anx7625_i2c_client { 456 struct i2c_client *tx_p0_client; 457 struct i2c_client *tx_p1_client; 458 struct i2c_client *tx_p2_client; 459 struct i2c_client *rx_p0_client; 460 struct i2c_client *rx_p1_client; 461 struct i2c_client *rx_p2_client; 462 struct i2c_client *tcpc_client; 463 }; 464 465 struct typec_port; 466 struct usb_role_switch; 467 468 #define MAX_BUF_LEN 30 469 struct fw_msg { 470 u8 msg_len; 471 u8 msg_type; 472 u8 buf[MAX_BUF_LEN]; 473 } __packed; 474 #define HEADER_LEN 2 475 476 struct anx7625_data { 477 struct anx7625_platform_data pdata; 478 struct platform_device *audio_pdev; 479 struct typec_port *typec_port; 480 struct usb_role_switch *role_sw; 481 int typec_data_role; 482 int hpd_status; 483 int hpd_high_cnt; 484 int dp_en; 485 int hdcp_cp; 486 /* Lock for work queue */ 487 struct mutex lock; 488 struct device *dev; 489 struct anx7625_i2c_client i2c; 490 struct i2c_client *last_client; 491 struct timer_list hdcp_timer; 492 const struct drm_edid *cached_drm_edid; 493 struct device *codec_dev; 494 hdmi_codec_plugged_cb plugged_cb; 495 struct work_struct work; 496 struct workqueue_struct *workqueue; 497 struct delayed_work hdcp_work; 498 struct workqueue_struct *hdcp_workqueue; 499 /* Lock for hdcp work queue */ 500 struct mutex hdcp_wq_lock; 501 /* Lock for aux transfer and disable */ 502 struct mutex aux_lock; 503 char edid_block; 504 struct display_timing dt; 505 u8 display_timing_valid; 506 struct drm_bridge bridge; 507 u8 bridge_attached; 508 struct drm_connector *connector; 509 struct mipi_dsi_device *dsi; 510 struct drm_dp_aux aux; 511 struct fw_msg send_msg; 512 }; 513 514 #endif /* __ANX7625_H__ */ 515