1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #ifndef DC_TYPES_H_ 26 #define DC_TYPES_H_ 27 28 /* AND EdidUtility only needs a portion 29 * of this file, including the rest only 30 * causes additional issues. 31 */ 32 #include "os_types.h" 33 #include "fixed31_32.h" 34 #include "irq_types.h" 35 #include "dc_ddc_types.h" 36 #include "dc_dp_types.h" 37 #include "dc_hdmi_types.h" 38 #include "dc_hw_types.h" 39 #include "dal_types.h" 40 #include "grph_object_defs.h" 41 #include "grph_object_ctrl_defs.h" 42 43 #include "dm_cp_psp.h" 44 45 /* forward declarations */ 46 struct dc_plane_state; 47 struct dc_stream_state; 48 struct dc_link; 49 struct dc_sink; 50 struct dal; 51 struct dc_dmub_srv; 52 53 /******************************** 54 * Environment definitions 55 ********************************/ 56 enum dce_environment { 57 DCE_ENV_PRODUCTION_DRV = 0, 58 /* Emulation on FPGA, in "Maximus" System. 59 * This environment enforces that *only* DC registers accessed. 60 * (access to non-DC registers will hang FPGA) */ 61 DCE_ENV_FPGA_MAXIMUS, 62 /* Emulation on real HW or on FPGA. Used by Diagnostics, enforces 63 * requirements of Diagnostics team. */ 64 DCE_ENV_DIAG, 65 /* 66 * Guest VM system, DC HW may exist but is not virtualized and 67 * should not be used. SW support for VDI only. 68 */ 69 DCE_ENV_VIRTUAL_HW 70 }; 71 72 struct dc_perf_trace { 73 unsigned long read_count; 74 unsigned long write_count; 75 unsigned long last_entry_read; 76 unsigned long last_entry_write; 77 }; 78 79 #define NUM_PIXEL_FORMATS 10 80 81 enum tiling_mode { 82 TILING_MODE_INVALID, 83 TILING_MODE_LINEAR, 84 TILING_MODE_TILED, 85 TILING_MODE_COUNT 86 }; 87 88 enum view_3d_format { 89 VIEW_3D_FORMAT_NONE = 0, 90 VIEW_3D_FORMAT_FRAME_SEQUENTIAL, 91 VIEW_3D_FORMAT_SIDE_BY_SIDE, 92 VIEW_3D_FORMAT_TOP_AND_BOTTOM, 93 VIEW_3D_FORMAT_COUNT, 94 VIEW_3D_FORMAT_FIRST = VIEW_3D_FORMAT_FRAME_SEQUENTIAL 95 }; 96 97 enum plane_stereo_format { 98 PLANE_STEREO_FORMAT_NONE = 0, 99 PLANE_STEREO_FORMAT_SIDE_BY_SIDE = 1, 100 PLANE_STEREO_FORMAT_TOP_AND_BOTTOM = 2, 101 PLANE_STEREO_FORMAT_FRAME_ALTERNATE = 3, 102 PLANE_STEREO_FORMAT_ROW_INTERLEAVED = 5, 103 PLANE_STEREO_FORMAT_COLUMN_INTERLEAVED = 6, 104 PLANE_STEREO_FORMAT_CHECKER_BOARD = 7 105 }; 106 107 /* TODO: Find way to calculate number of bits 108 * Please increase if pixel_format enum increases 109 * num from PIXEL_FORMAT_INDEX8 to PIXEL_FORMAT_444BPP32 110 */ 111 112 enum dc_edid_connector_type { 113 DC_EDID_CONNECTOR_UNKNOWN = 0, 114 DC_EDID_CONNECTOR_ANALOG = 1, 115 DC_EDID_CONNECTOR_DIGITAL = 10, 116 DC_EDID_CONNECTOR_DVI = 11, 117 DC_EDID_CONNECTOR_HDMIA = 12, 118 DC_EDID_CONNECTOR_MDDI = 14, 119 DC_EDID_CONNECTOR_DISPLAYPORT = 15 120 }; 121 122 enum dc_edid_status { 123 EDID_OK, 124 EDID_BAD_INPUT, 125 EDID_NO_RESPONSE, 126 EDID_BAD_CHECKSUM, 127 EDID_THE_SAME, 128 EDID_FALL_BACK, 129 EDID_PARTIAL_VALID, 130 }; 131 132 enum act_return_status { 133 ACT_SUCCESS, 134 ACT_LINK_LOST, 135 ACT_FAILED 136 }; 137 138 /* audio capability from EDID*/ 139 struct dc_cea_audio_mode { 140 uint8_t format_code; /* ucData[0] [6:3]*/ 141 uint8_t channel_count; /* ucData[0] [2:0]*/ 142 uint8_t sample_rate; /* ucData[1]*/ 143 union { 144 uint8_t sample_size; /* for LPCM*/ 145 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/ 146 uint8_t max_bit_rate; 147 uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/ 148 }; 149 }; 150 151 struct dc_edid { 152 uint32_t length; 153 uint8_t raw_edid[DC_MAX_EDID_BUFFER_SIZE]; 154 }; 155 156 /* When speaker location data block is not available, DEFAULT_SPEAKER_LOCATION 157 * is used. In this case we assume speaker location are: front left, front 158 * right and front center. */ 159 #define DEFAULT_SPEAKER_LOCATION 5 160 161 #define DC_MAX_AUDIO_DESC_COUNT 16 162 163 #define AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 20 164 165 struct dc_panel_patch { 166 unsigned int dppowerup_delay; 167 unsigned int extra_t12_ms; 168 unsigned int extra_delay_backlight_off; 169 unsigned int extra_t7_ms; 170 unsigned int skip_scdc_overwrite; 171 unsigned int delay_ignore_msa; 172 unsigned int disable_fec; 173 unsigned int extra_t3_ms; 174 unsigned int max_dsc_target_bpp_limit; 175 unsigned int embedded_tiled_slave; 176 unsigned int disable_fams; 177 unsigned int skip_avmute; 178 unsigned int skip_audio_sab_check; 179 unsigned int mst_start_top_delay; 180 unsigned int remove_sink_ext_caps; 181 unsigned int disable_colorimetry; 182 uint8_t blankstream_before_otg_off; 183 bool oled_optimize_display_on; 184 unsigned int force_mst_blocked_discovery; 185 unsigned int wait_after_dpcd_poweroff_ms; 186 }; 187 188 /** 189 * struct dc_edid_caps - Capabilities read from EDID. 190 * @analog: Whether the monitor is analog. Used by DVI-I handling. 191 */ 192 struct dc_edid_caps { 193 /* sink identification */ 194 uint16_t manufacturer_id; 195 uint16_t product_id; 196 uint32_t serial_number; 197 uint8_t manufacture_week; 198 uint8_t manufacture_year; 199 uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS]; 200 201 /* audio caps */ 202 uint8_t speaker_flags; 203 uint32_t audio_mode_count; 204 struct dc_cea_audio_mode audio_modes[DC_MAX_AUDIO_DESC_COUNT]; 205 uint32_t audio_latency; 206 uint32_t video_latency; 207 208 uint8_t qs_bit; 209 uint8_t qy_bit; 210 211 uint32_t max_tmds_clk_mhz; 212 213 /*HDMI 2.0 caps*/ 214 bool lte_340mcsc_scramble; 215 216 bool edid_hdmi; 217 bool hdr_supported; 218 bool rr_capable; 219 bool scdc_present; 220 bool analog; 221 222 struct dc_panel_patch panel_patch; 223 }; 224 225 struct dc_mode_flags { 226 /* note: part of refresh rate flag*/ 227 uint32_t INTERLACE :1; 228 /* native display timing*/ 229 uint32_t NATIVE :1; 230 /* preferred is the recommended mode, one per display */ 231 uint32_t PREFERRED :1; 232 /* true if this mode should use reduced blanking timings 233 *_not_ related to the Reduced Blanking adjustment*/ 234 uint32_t REDUCED_BLANKING :1; 235 /* note: part of refreshrate flag*/ 236 uint32_t VIDEO_OPTIMIZED_RATE :1; 237 /* should be reported to upper layers as mode_flags*/ 238 uint32_t PACKED_PIXEL_FORMAT :1; 239 /*< preferred view*/ 240 uint32_t PREFERRED_VIEW :1; 241 /* this timing should be used only in tiled mode*/ 242 uint32_t TILED_MODE :1; 243 uint32_t DSE_MODE :1; 244 /* Refresh rate divider when Miracast sink is using a 245 different rate than the output display device 246 Must be zero for wired displays and non-zero for 247 Miracast displays*/ 248 uint32_t MIRACAST_REFRESH_DIVIDER; 249 }; 250 251 252 enum dc_timing_source { 253 TIMING_SOURCE_UNDEFINED, 254 255 /* explicitly specifed by user, most important*/ 256 TIMING_SOURCE_USER_FORCED, 257 TIMING_SOURCE_USER_OVERRIDE, 258 TIMING_SOURCE_CUSTOM, 259 TIMING_SOURCE_EXPLICIT, 260 261 /* explicitly specified by the display device, more important*/ 262 TIMING_SOURCE_EDID_CEA_SVD_3D, 263 TIMING_SOURCE_EDID_CEA_SVD_PREFERRED, 264 TIMING_SOURCE_EDID_CEA_SVD_420, 265 TIMING_SOURCE_EDID_DETAILED, 266 TIMING_SOURCE_EDID_ESTABLISHED, 267 TIMING_SOURCE_EDID_STANDARD, 268 TIMING_SOURCE_EDID_CEA_SVD, 269 TIMING_SOURCE_EDID_CVT_3BYTE, 270 TIMING_SOURCE_EDID_4BYTE, 271 TIMING_SOURCE_EDID_CEA_DISPLAYID_VTDB, 272 TIMING_SOURCE_EDID_CEA_RID, 273 TIMING_SOURCE_EDID_DISPLAYID_TYPE5, 274 TIMING_SOURCE_VBIOS, 275 TIMING_SOURCE_CV, 276 TIMING_SOURCE_TV, 277 TIMING_SOURCE_HDMI_VIC, 278 TIMING_SOURCE_CEA_VIC, 279 280 /* implicitly specified by display device, still safe but less important*/ 281 TIMING_SOURCE_DEFAULT, 282 283 /* only used for custom base modes */ 284 TIMING_SOURCE_CUSTOM_BASE, 285 286 /* these timing might not work, least important*/ 287 TIMING_SOURCE_RANGELIMIT, 288 TIMING_SOURCE_OS_FORCED, 289 TIMING_SOURCE_IMPLICIT, 290 291 /* only used by default mode list*/ 292 TIMING_SOURCE_BASICMODE, 293 294 TIMING_SOURCE_COUNT 295 }; 296 297 298 struct stereo_3d_features { 299 bool supported ; 300 bool allTimings ; 301 bool cloneMode ; 302 bool scaling ; 303 bool singleFrameSWPacked; 304 }; 305 306 enum dc_timing_support_method { 307 TIMING_SUPPORT_METHOD_UNDEFINED, 308 TIMING_SUPPORT_METHOD_EXPLICIT, 309 TIMING_SUPPORT_METHOD_IMPLICIT, 310 TIMING_SUPPORT_METHOD_NATIVE 311 }; 312 313 struct dc_mode_info { 314 uint32_t pixel_width; 315 uint32_t pixel_height; 316 uint32_t field_rate; 317 /* Vertical refresh rate for progressive modes. 318 * Field rate for interlaced modes.*/ 319 320 enum dc_timing_standard timing_standard; 321 enum dc_timing_source timing_source; 322 struct dc_mode_flags flags; 323 }; 324 325 enum dc_power_state { 326 DC_POWER_STATE_ON = 1, 327 DC_POWER_STATE_STANDBY, 328 DC_POWER_STATE_SUSPEND, 329 DC_POWER_STATE_OFF 330 }; 331 332 /* DC PowerStates */ 333 enum dc_video_power_state { 334 DC_VIDEO_POWER_UNSPECIFIED = 0, 335 DC_VIDEO_POWER_ON = 1, 336 DC_VIDEO_POWER_STANDBY, 337 DC_VIDEO_POWER_SUSPEND, 338 DC_VIDEO_POWER_OFF, 339 DC_VIDEO_POWER_HIBERNATE, 340 DC_VIDEO_POWER_SHUTDOWN, 341 DC_VIDEO_POWER_ULPS, /* BACO or Ultra-Light-Power-State */ 342 DC_VIDEO_POWER_AFTER_RESET, 343 DC_VIDEO_POWER_MAXIMUM 344 }; 345 346 enum dc_acpi_cm_power_state { 347 DC_ACPI_CM_POWER_STATE_D0 = 1, 348 DC_ACPI_CM_POWER_STATE_D1 = 2, 349 DC_ACPI_CM_POWER_STATE_D2 = 4, 350 DC_ACPI_CM_POWER_STATE_D3 = 8 351 }; 352 353 enum dc_connection_type { 354 dc_connection_none, 355 dc_connection_single, 356 dc_connection_mst_branch, 357 dc_connection_sst_branch, 358 dc_connection_analog_load 359 }; 360 361 struct dc_csc_adjustments { 362 struct fixed31_32 contrast; 363 struct fixed31_32 saturation; 364 struct fixed31_32 brightness; 365 struct fixed31_32 hue; 366 }; 367 368 /* Scaling format */ 369 enum scaling_transformation { 370 SCALING_TRANSFORMATION_UNINITIALIZED, 371 SCALING_TRANSFORMATION_IDENTITY = 0x0001, 372 SCALING_TRANSFORMATION_CENTER_TIMING = 0x0002, 373 SCALING_TRANSFORMATION_FULL_SCREEN_SCALE = 0x0004, 374 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE = 0x0008, 375 SCALING_TRANSFORMATION_DAL_DECIDE = 0x0010, 376 SCALING_TRANSFORMATION_INVALID = 0x80000000, 377 378 /* Flag the first and last */ 379 SCALING_TRANSFORMATION_BEGING = SCALING_TRANSFORMATION_IDENTITY, 380 SCALING_TRANSFORMATION_END = 381 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE 382 }; 383 384 enum display_content_type { 385 DISPLAY_CONTENT_TYPE_NO_DATA = 0, 386 DISPLAY_CONTENT_TYPE_GRAPHICS = 1, 387 DISPLAY_CONTENT_TYPE_PHOTO = 2, 388 DISPLAY_CONTENT_TYPE_CINEMA = 4, 389 DISPLAY_CONTENT_TYPE_GAME = 8 390 }; 391 392 enum cm_gamut_adjust_type { 393 CM_GAMUT_ADJUST_TYPE_BYPASS = 0, 394 CM_GAMUT_ADJUST_TYPE_HW, /* without adjustments */ 395 CM_GAMUT_ADJUST_TYPE_SW /* use adjustments */ 396 }; 397 398 struct cm_grph_csc_adjustment { 399 struct fixed31_32 temperature_matrix[12]; 400 enum cm_gamut_adjust_type gamut_adjust_type; 401 enum cm_gamut_coef_format gamut_coef_format; 402 }; 403 404 /* writeback */ 405 struct dwb_stereo_params { 406 bool stereo_enabled; /* false: normal mode, true: 3D stereo */ 407 enum dwb_stereo_type stereo_type; /* indicates stereo format */ 408 bool stereo_polarity; /* indicates left eye or right eye comes first in stereo mode */ 409 enum dwb_stereo_eye_select stereo_eye_select; /* indicate which eye should be captured */ 410 }; 411 412 struct dc_dwb_cnv_params { 413 unsigned int src_width; /* input active width */ 414 unsigned int src_height; /* input active height (half-active height in interlaced mode) */ 415 unsigned int crop_width; /* cropped window width at cnv output */ 416 bool crop_en; /* window cropping enable in cnv */ 417 unsigned int crop_height; /* cropped window height at cnv output */ 418 unsigned int crop_x; /* cropped window start x value at cnv output */ 419 unsigned int crop_y; /* cropped window start y value at cnv output */ 420 enum dwb_cnv_out_bpc cnv_out_bpc; /* cnv output pixel depth - 8bpc or 10bpc */ 421 enum dwb_out_format fc_out_format; /* dwb output pixel format - 2101010 or 16161616 and ARGB or RGBA */ 422 enum dwb_out_denorm out_denorm_mode;/* dwb output denormalization mode */ 423 unsigned int out_max_pix_val;/* pixel values greater than out_max_pix_val are clamped to out_max_pix_val */ 424 unsigned int out_min_pix_val;/* pixel values less than out_min_pix_val are clamped to out_min_pix_val */ 425 }; 426 427 struct dc_dwb_params { 428 unsigned int dwbscl_black_color; /* must be in FP1.5.10 */ 429 unsigned int hdr_mult; /* must be in FP1.6.12 */ 430 struct cm_grph_csc_adjustment csc_params; 431 struct dwb_stereo_params stereo_params; 432 struct dc_dwb_cnv_params cnv_params; /* CNV source size and cropping window parameters */ 433 unsigned int dest_width; /* Destination width */ 434 unsigned int dest_height; /* Destination height */ 435 enum dwb_scaler_mode out_format; /* default = YUV420 - TODO: limit this to 0 and 1 on dcn3 */ 436 enum dwb_output_depth output_depth; /* output pixel depth - 8bpc or 10bpc */ 437 enum dwb_capture_rate capture_rate; /* controls the frame capture rate */ 438 struct scaling_taps scaler_taps; /* Scaling taps */ 439 enum dwb_subsample_position subsample_position; 440 const struct dc_transfer_func *out_transfer_func; 441 }; 442 443 /* audio*/ 444 445 union audio_sample_rates { 446 struct sample_rates { 447 uint8_t RATE_32:1; 448 uint8_t RATE_44_1:1; 449 uint8_t RATE_48:1; 450 uint8_t RATE_88_2:1; 451 uint8_t RATE_96:1; 452 uint8_t RATE_176_4:1; 453 uint8_t RATE_192:1; 454 } rate; 455 456 uint8_t all; 457 }; 458 459 struct audio_speaker_flags { 460 uint32_t FL_FR:1; 461 uint32_t LFE:1; 462 uint32_t FC:1; 463 uint32_t RL_RR:1; 464 uint32_t RC:1; 465 uint32_t FLC_FRC:1; 466 uint32_t RLC_RRC:1; 467 uint32_t SUPPORT_AI:1; 468 }; 469 470 struct audio_speaker_info { 471 uint32_t ALLSPEAKERS:7; 472 uint32_t SUPPORT_AI:1; 473 }; 474 475 476 struct audio_info_flags { 477 478 union { 479 480 struct audio_speaker_flags speaker_flags; 481 struct audio_speaker_info info; 482 483 uint8_t all; 484 }; 485 }; 486 487 enum audio_format_code { 488 AUDIO_FORMAT_CODE_FIRST = 1, 489 AUDIO_FORMAT_CODE_LINEARPCM = AUDIO_FORMAT_CODE_FIRST, 490 491 AUDIO_FORMAT_CODE_AC3, 492 /*Layers 1 & 2 */ 493 AUDIO_FORMAT_CODE_MPEG1, 494 /*MPEG1 Layer 3 */ 495 AUDIO_FORMAT_CODE_MP3, 496 /*multichannel */ 497 AUDIO_FORMAT_CODE_MPEG2, 498 AUDIO_FORMAT_CODE_AAC, 499 AUDIO_FORMAT_CODE_DTS, 500 AUDIO_FORMAT_CODE_ATRAC, 501 AUDIO_FORMAT_CODE_1BITAUDIO, 502 AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS, 503 AUDIO_FORMAT_CODE_DTS_HD, 504 AUDIO_FORMAT_CODE_MAT_MLP, 505 AUDIO_FORMAT_CODE_DST, 506 AUDIO_FORMAT_CODE_WMAPRO, 507 AUDIO_FORMAT_CODE_LAST, 508 AUDIO_FORMAT_CODE_COUNT = 509 AUDIO_FORMAT_CODE_LAST - AUDIO_FORMAT_CODE_FIRST 510 }; 511 512 struct audio_mode { 513 /* ucData[0] [6:3] */ 514 enum audio_format_code format_code; 515 /* ucData[0] [2:0] */ 516 uint8_t channel_count; 517 /* ucData[1] */ 518 union audio_sample_rates sample_rates; 519 union { 520 /* for LPCM */ 521 uint8_t sample_size; 522 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz) */ 523 uint8_t max_bit_rate; 524 /* for Audio Formats 9-15 */ 525 uint8_t vendor_specific; 526 }; 527 }; 528 529 struct audio_info { 530 struct audio_info_flags flags; 531 uint32_t video_latency; 532 uint32_t audio_latency; 533 uint32_t display_index; 534 uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS]; 535 uint32_t manufacture_id; 536 uint32_t product_id; 537 /* PortID used for ContainerID when defined */ 538 uint32_t port_id[2]; 539 uint32_t mode_count; 540 /* this field must be last in this struct */ 541 struct audio_mode modes[DC_MAX_AUDIO_DESC_COUNT]; 542 }; 543 struct audio_check { 544 unsigned int audio_packet_type; 545 unsigned int max_audiosample_rate; 546 unsigned int acat; 547 }; 548 enum dc_infoframe_type { 549 DC_HDMI_INFOFRAME_TYPE_VENDOR = 0x81, 550 DC_HDMI_INFOFRAME_TYPE_AVI = 0x82, 551 DC_HDMI_INFOFRAME_TYPE_SPD = 0x83, 552 DC_HDMI_INFOFRAME_TYPE_AUDIO = 0x84, 553 DC_DP_INFOFRAME_TYPE_PPS = 0x10, 554 }; 555 556 struct dc_info_packet { 557 bool valid; 558 uint8_t hb0; 559 uint8_t hb1; 560 uint8_t hb2; 561 uint8_t hb3; 562 uint8_t sb[32]; 563 }; 564 565 struct dc_info_packet_128 { 566 bool valid; 567 uint8_t hb0; 568 uint8_t hb1; 569 uint8_t hb2; 570 uint8_t hb3; 571 uint8_t sb[128]; 572 }; 573 574 struct dc_edid_read_policy { 575 uint32_t max_retry_count; 576 uint32_t delay_time_ms; 577 uint32_t ignore_checksum; 578 }; 579 580 #define DC_PLANE_UPDATE_TIMES_MAX 10 581 582 struct dc_plane_flip_time { 583 unsigned int time_elapsed_in_us[DC_PLANE_UPDATE_TIMES_MAX]; 584 unsigned int index; 585 unsigned int prev_update_time_in_us; 586 }; 587 588 enum dc_alpm_mode { 589 DC_ALPM_AUXWAKE = 0, 590 DC_ALPM_AUXLESS = 1, 591 DC_ALPM_UNSUPPORTED = 0xF, 592 }; 593 594 enum dc_psr_state { 595 PSR_STATE0 = 0x0, 596 PSR_STATE1, 597 PSR_STATE1a, 598 PSR_STATE2, 599 PSR_STATE2a, 600 PSR_STATE2b, 601 PSR_STATE3, 602 PSR_STATE3Init, 603 PSR_STATE4, 604 PSR_STATE4a, 605 PSR_STATE4b, 606 PSR_STATE4c, 607 PSR_STATE4d, 608 PSR_STATE4_FULL_FRAME, 609 PSR_STATE4a_FULL_FRAME, 610 PSR_STATE4b_FULL_FRAME, 611 PSR_STATE4c_FULL_FRAME, 612 PSR_STATE4_FULL_FRAME_POWERUP, 613 PSR_STATE4_FULL_FRAME_HW_LOCK, 614 PSR_STATE5, 615 PSR_STATE5a, 616 PSR_STATE5b, 617 PSR_STATE5c, 618 PSR_STATE_HWLOCK_MGR, 619 PSR_STATE_POLLVUPDATE, 620 PSR_STATE_RELEASE_HWLOCK_MGR_FULL_FRAME, 621 PSR_STATE_INVALID = 0xFF 622 }; 623 624 struct psr_config { 625 unsigned char psr_version; 626 unsigned int psr_rfb_setup_time; 627 bool psr_exit_link_training_required; 628 bool psr_frame_capture_indication_req; 629 unsigned int psr_sdp_transmit_line_num_deadline; 630 bool allow_smu_optimizations; 631 bool allow_multi_disp_optimizations; 632 /* Panel self refresh 2 selective update granularity required */ 633 bool su_granularity_required; 634 /* psr2 selective update y granularity capability */ 635 uint8_t su_y_granularity; 636 unsigned int line_time_in_us; 637 uint8_t rate_control_caps; 638 uint16_t dsc_slice_height; 639 bool os_request_force_ffu; 640 }; 641 642 union dmcu_psr_level { 643 struct { 644 unsigned int SKIP_CRC:1; 645 unsigned int SKIP_DP_VID_STREAM_DISABLE:1; 646 unsigned int SKIP_PHY_POWER_DOWN:1; 647 unsigned int SKIP_AUX_ACK_CHECK:1; 648 unsigned int SKIP_CRTC_DISABLE:1; 649 unsigned int SKIP_AUX_RFB_CAPTURE_CHECK:1; 650 unsigned int SKIP_SMU_NOTIFICATION:1; 651 unsigned int SKIP_AUTO_STATE_ADVANCE:1; 652 unsigned int DISABLE_PSR_ENTRY_ABORT:1; 653 unsigned int SKIP_SINGLE_OTG_DISABLE:1; 654 unsigned int DISABLE_ALPM:1; 655 unsigned int ALPM_DEFAULT_PD_MODE:1; 656 unsigned int RESERVED:20; 657 } bits; 658 unsigned int u32all; 659 }; 660 661 enum physical_phy_id { 662 PHYLD_0, 663 PHYLD_1, 664 PHYLD_2, 665 PHYLD_3, 666 PHYLD_4, 667 PHYLD_5, 668 PHYLD_6, 669 PHYLD_7, 670 PHYLD_8, 671 PHYLD_9, 672 PHYLD_COUNT, 673 PHYLD_UNKNOWN = (-1L) 674 }; 675 676 enum phy_type { 677 PHY_TYPE_UNKNOWN = 1, 678 PHY_TYPE_PCIE_PHY = 2, 679 PHY_TYPE_UNIPHY = 3, 680 }; 681 682 struct psr_context { 683 /* ddc line */ 684 enum channel_id channel; 685 /* Transmitter id */ 686 enum transmitter transmitterId; 687 /* Engine Id is used for Dig Be source select */ 688 enum engine_id engineId; 689 /* Controller Id used for Dig Fe source select */ 690 enum controller_id controllerId; 691 /* Pcie or Uniphy */ 692 enum phy_type phyType; 693 /* Physical PHY Id used by SMU interpretation */ 694 enum physical_phy_id smuPhyId; 695 /* Vertical total pixels from crtc timing. 696 * This is used for static screen detection. 697 * ie. If we want to detect half a frame, 698 * we use this to determine the hyst lines. 699 */ 700 unsigned int crtcTimingVerticalTotal; 701 /* PSR supported from panel capabilities and 702 * current display configuration 703 */ 704 bool psrSupportedDisplayConfig; 705 /* Whether fast link training is supported by the panel */ 706 bool psrExitLinkTrainingRequired; 707 /* If RFB setup time is greater than the total VBLANK time, 708 * it is not possible for the sink to capture the video frame 709 * in the same frame the SDP is sent. In this case, 710 * the frame capture indication bit should be set and an extra 711 * static frame should be transmitted to the sink. 712 */ 713 bool psrFrameCaptureIndicationReq; 714 /* Set the last possible line SDP may be transmitted without violating 715 * the RFB setup time or entering the active video frame. 716 */ 717 unsigned int sdpTransmitLineNumDeadline; 718 /* The VSync rate in Hz used to calculate the 719 * step size for smooth brightness feature 720 */ 721 unsigned int vsync_rate_hz; 722 unsigned int skipPsrWaitForPllLock; 723 unsigned int numberOfControllers; 724 /* Unused, for future use. To indicate that first changed frame from 725 * state3 shouldn't result in psr_inactive, but rather to perform 726 * an automatic single frame rfb_update. 727 */ 728 bool rfb_update_auto_en; 729 /* Number of frame before entering static screen */ 730 unsigned int timehyst_frames; 731 /* Partial frames before entering static screen */ 732 unsigned int hyst_lines; 733 /* # of repeated AUX transaction attempts to make before 734 * indicating failure to the driver 735 */ 736 unsigned int aux_repeats; 737 /* Controls hw blocks to power down during PSR active state */ 738 union dmcu_psr_level psr_level; 739 /* Controls additional delay after remote frame capture before 740 * continuing powerd own 741 */ 742 unsigned int frame_delay; 743 bool allow_smu_optimizations; 744 bool allow_multi_disp_optimizations; 745 /* Panel self refresh 2 selective update granularity required */ 746 bool su_granularity_required; 747 /* psr2 selective update y granularity capability */ 748 uint8_t su_y_granularity; 749 unsigned int line_time_in_us; 750 uint8_t rate_control_caps; 751 uint16_t dsc_slice_height; 752 bool os_request_force_ffu; 753 }; 754 755 struct colorspace_transform { 756 struct fixed31_32 matrix[12]; 757 bool enable_remap; 758 }; 759 760 enum i2c_mot_mode { 761 I2C_MOT_UNDEF, 762 I2C_MOT_TRUE, 763 I2C_MOT_FALSE 764 }; 765 766 struct AsicStateEx { 767 unsigned int memoryClock; 768 unsigned int displayClock; 769 unsigned int engineClock; 770 unsigned int maxSupportedDppClock; 771 unsigned int dppClock; 772 unsigned int socClock; 773 unsigned int dcfClockDeepSleep; 774 unsigned int fClock; 775 unsigned int phyClock; 776 }; 777 778 779 enum dc_clock_type { 780 DC_CLOCK_TYPE_DISPCLK = 0, 781 DC_CLOCK_TYPE_DPPCLK = 1, 782 }; 783 784 struct dc_clock_config { 785 uint32_t max_clock_khz; 786 uint32_t min_clock_khz; 787 uint32_t bw_requirequired_clock_khz; 788 uint32_t current_clock_khz;/*current clock in use*/ 789 }; 790 791 struct hw_asic_id { 792 uint32_t chip_id; 793 uint32_t chip_family; 794 uint32_t pci_revision_id; 795 uint32_t hw_internal_rev; 796 uint32_t vram_type; 797 uint32_t vram_width; 798 uint32_t feature_flags; 799 uint32_t fake_paths_num; 800 void *atombios_base_address; 801 }; 802 803 struct dc_context { 804 struct dc *dc; 805 806 void *driver_context; /* e.g. amdgpu_device */ 807 struct dal_logger *logger; 808 struct dc_perf_trace *perf_trace; 809 void *cgs_device; 810 811 enum dce_environment dce_environment; 812 struct hw_asic_id asic_id; 813 814 /* todo: below should probably move to dc. to facilitate removal 815 * of AS we will store these here 816 */ 817 enum dce_version dce_version; 818 struct dc_bios *dc_bios; 819 bool created_bios; 820 struct gpio_service *gpio_service; 821 uint32_t dc_sink_id_count; 822 uint32_t dc_stream_id_count; 823 uint32_t dc_edp_id_count; 824 uint64_t fbc_gpu_addr; 825 struct dc_dmub_srv *dmub_srv; 826 struct cp_psp cp_psp; 827 uint32_t *dcn_reg_offsets; 828 uint32_t *nbio_reg_offsets; 829 uint32_t *clk_reg_offsets; 830 }; 831 832 /* DSC DPCD capabilities */ 833 union dsc_slice_caps1 { 834 struct { 835 uint8_t NUM_SLICES_1 : 1; 836 uint8_t NUM_SLICES_2 : 1; 837 uint8_t RESERVED : 1; 838 uint8_t NUM_SLICES_4 : 1; 839 uint8_t NUM_SLICES_6 : 1; 840 uint8_t NUM_SLICES_8 : 1; 841 uint8_t NUM_SLICES_10 : 1; 842 uint8_t NUM_SLICES_12 : 1; 843 } bits; 844 uint8_t raw; 845 }; 846 847 union dsc_slice_caps2 { 848 struct { 849 uint8_t NUM_SLICES_16 : 1; 850 uint8_t NUM_SLICES_20 : 1; 851 uint8_t NUM_SLICES_24 : 1; 852 uint8_t RESERVED : 5; 853 } bits; 854 uint8_t raw; 855 }; 856 857 union dsc_color_formats { 858 struct { 859 uint8_t RGB : 1; 860 uint8_t YCBCR_444 : 1; 861 uint8_t YCBCR_SIMPLE_422 : 1; 862 uint8_t YCBCR_NATIVE_422 : 1; 863 uint8_t YCBCR_NATIVE_420 : 1; 864 uint8_t RESERVED : 3; 865 } bits; 866 uint8_t raw; 867 }; 868 869 union dsc_color_depth { 870 struct { 871 uint8_t RESERVED1 : 1; 872 uint8_t COLOR_DEPTH_8_BPC : 1; 873 uint8_t COLOR_DEPTH_10_BPC : 1; 874 uint8_t COLOR_DEPTH_12_BPC : 1; 875 uint8_t RESERVED2 : 3; 876 } bits; 877 uint8_t raw; 878 }; 879 880 struct dsc_dec_dpcd_caps { 881 bool is_dsc_supported; 882 uint8_t dsc_version; 883 int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */ 884 union dsc_slice_caps1 slice_caps1; 885 union dsc_slice_caps2 slice_caps2; 886 int32_t lb_bit_depth; 887 bool is_block_pred_supported; 888 int32_t edp_max_bits_per_pixel; /* Valid only in eDP */ 889 union dsc_color_formats color_formats; 890 union dsc_color_depth color_depth; 891 int32_t throughput_mode_0_mps; /* In MPs */ 892 int32_t throughput_mode_1_mps; /* In MPs */ 893 int32_t max_slice_width; 894 uint32_t bpp_increment_div; /* bpp increment divisor, e.g. if 16, it's 1/16th of a bit */ 895 896 /* Extended DSC caps */ 897 uint32_t branch_overall_throughput_0_mps; /* In MPs */ 898 uint32_t branch_overall_throughput_1_mps; /* In MPs */ 899 uint32_t branch_max_line_width; 900 bool is_dp; /* Decoded format */ 901 }; 902 903 struct hblank_expansion_dpcd_caps { 904 bool expansion_supported; 905 bool reduction_supported; 906 bool buffer_unit_bytes; /* True: buffer size in bytes. False: buffer size in pixels*/ 907 bool buffer_per_port; /* True: buffer size per port. False: buffer size per lane*/ 908 uint32_t buffer_size; /* Add 1 to value and multiply by 32 */ 909 }; 910 911 struct dc_golden_table { 912 uint16_t dc_golden_table_ver; 913 uint32_t aux_dphy_rx_control0_val; 914 uint32_t aux_dphy_tx_control_val; 915 uint32_t aux_dphy_rx_control1_val; 916 uint32_t dc_gpio_aux_ctrl_0_val; 917 uint32_t dc_gpio_aux_ctrl_1_val; 918 uint32_t dc_gpio_aux_ctrl_2_val; 919 uint32_t dc_gpio_aux_ctrl_3_val; 920 uint32_t dc_gpio_aux_ctrl_4_val; 921 uint32_t dc_gpio_aux_ctrl_5_val; 922 }; 923 924 enum dc_gpu_mem_alloc_type { 925 DC_MEM_ALLOC_TYPE_GART, 926 DC_MEM_ALLOC_TYPE_FRAME_BUFFER, 927 DC_MEM_ALLOC_TYPE_INVISIBLE_FRAME_BUFFER, 928 DC_MEM_ALLOC_TYPE_AGP 929 }; 930 931 enum dc_link_encoding_format { 932 DC_LINK_ENCODING_UNSPECIFIED = 0, 933 DC_LINK_ENCODING_DP_8b_10b, 934 DC_LINK_ENCODING_DP_128b_132b, 935 DC_LINK_ENCODING_HDMI_TMDS, 936 DC_LINK_ENCODING_HDMI_FRL 937 }; 938 939 enum dc_psr_version { 940 DC_PSR_VERSION_1 = 0, 941 DC_PSR_VERSION_SU_1 = 1, 942 DC_PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 943 }; 944 945 enum dc_replay_version { 946 DC_FREESYNC_REPLAY = 0, 947 DC_VESA_PANEL_REPLAY = 1, 948 DC_REPLAY_VERSION_UNSUPPORTED = 0XFF, 949 }; 950 951 /* Possible values of display_endpoint_id.endpoint */ 952 enum display_endpoint_type { 953 DISPLAY_ENDPOINT_PHY = 0, /* Physical connector. */ 954 DISPLAY_ENDPOINT_USB4_DPIA, /* USB4 DisplayPort tunnel. */ 955 DISPLAY_ENDPOINT_UNKNOWN = -1 956 }; 957 958 /* Extends graphics_object_id with an additional member 'ep_type' for 959 * distinguishing between physical endpoints (with entries in BIOS connector table) and 960 * logical endpoints. 961 */ 962 struct display_endpoint_id { 963 struct graphics_object_id link_id; 964 enum display_endpoint_type ep_type; 965 }; 966 967 enum dc_panel_type { 968 PANEL_TYPE_NONE = 0, // UNKONWN, not determined yet 969 PANEL_TYPE_LCD = 1, 970 PANEL_TYPE_OLED = 2, 971 PANEL_TYPE_MINILED = 3, 972 }; 973 974 enum backlight_control_type { 975 BACKLIGHT_CONTROL_PWM = 0, 976 BACKLIGHT_CONTROL_VESA_AUX = 1, 977 BACKLIGHT_CONTROL_AMD_AUX = 2, 978 }; 979 980 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 981 #define MAX_CRC_WINDOW_NUM 2 982 983 struct otg_phy_mux { 984 uint8_t phy_output_num; 985 uint8_t otg_output_num; 986 }; 987 988 struct crc_window { 989 struct rect rect; 990 bool enable; 991 }; 992 #endif 993 994 enum dc_detect_reason { 995 DETECT_REASON_BOOT, 996 DETECT_REASON_RESUMEFROMS3S4, 997 DETECT_REASON_HPD, 998 DETECT_REASON_HPDRX, 999 DETECT_REASON_FALLBACK, 1000 DETECT_REASON_RETRAIN, 1001 DETECT_REASON_TDR, 1002 }; 1003 1004 struct dc_link_status { 1005 bool link_active; 1006 struct dpcd_caps *dpcd_caps; 1007 }; 1008 1009 union hdcp_rx_caps { 1010 struct { 1011 uint8_t version; 1012 uint8_t reserved; 1013 struct { 1014 uint8_t repeater : 1; 1015 uint8_t hdcp_capable : 1; 1016 uint8_t reserved : 6; 1017 } byte0; 1018 } fields; 1019 uint8_t raw[3]; 1020 }; 1021 1022 union hdcp_bcaps { 1023 struct { 1024 uint8_t HDCP_CAPABLE:1; 1025 uint8_t REPEATER:1; 1026 uint8_t RESERVED:6; 1027 } bits; 1028 uint8_t raw; 1029 }; 1030 1031 struct hdcp_caps { 1032 union hdcp_rx_caps rx_caps; 1033 union hdcp_bcaps bcaps; 1034 }; 1035 1036 /* DP MST stream allocation (payload bandwidth number) */ 1037 struct link_mst_stream_allocation { 1038 /* DIG front */ 1039 const struct stream_encoder *stream_enc; 1040 /* HPO DP Stream Encoder */ 1041 const struct hpo_dp_stream_encoder *hpo_dp_stream_enc; 1042 /* associate DRM payload table with DC stream encoder */ 1043 uint8_t vcp_id; 1044 /* number of slots required for the DP stream in transport packet */ 1045 uint8_t slot_count; 1046 }; 1047 1048 #define MAX_CONTROLLER_NUM 6 1049 1050 /* DP MST stream allocation table */ 1051 struct link_mst_stream_allocation_table { 1052 /* number of DP video streams */ 1053 int stream_count; 1054 /* array of stream allocations */ 1055 struct link_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM]; 1056 }; 1057 1058 /* PSR feature flags */ 1059 struct psr_settings { 1060 bool psr_feature_enabled; // PSR is supported by sink 1061 bool psr_allow_active; // PSR is currently active 1062 enum dc_psr_version psr_version; // Internal PSR version, determined based on DPCD 1063 bool psr_vtotal_control_support; // Vtotal control is supported by sink 1064 unsigned long long psr_dirty_rects_change_timestamp_ns; // for delay of enabling PSR-SU 1065 1066 /* These parameters are calculated in Driver, 1067 * based on display timing and Sink capabilities. 1068 * If VBLANK region is too small and Sink takes a long time 1069 * to set up RFB, it may take an extra frame to enter PSR state. 1070 */ 1071 bool psr_frame_capture_indication_req; 1072 unsigned int psr_sdp_transmit_line_num_deadline; 1073 uint8_t force_ffu_mode; 1074 unsigned int psr_power_opt; 1075 1076 /** 1077 * Some panels cannot handle idle pattern during PSR entry. 1078 * To power down phy before disable stream to avoid sending 1079 * idle pattern. 1080 */ 1081 uint8_t power_down_phy_before_disable_stream; 1082 }; 1083 1084 enum replay_coasting_vtotal_type { 1085 PR_COASTING_TYPE_NOM = 0, 1086 PR_COASTING_TYPE_STATIC, 1087 PR_COASTING_TYPE_FULL_SCREEN_VIDEO, 1088 PR_COASTING_TYPE_TEST_HARNESS, 1089 PR_COASTING_TYPE_VIDEO_CONFERENCING_V2, 1090 PR_COASTING_TYPE_NUM, 1091 }; 1092 1093 enum replay_link_off_frame_count_level { 1094 PR_LINK_OFF_FRAME_COUNT_FAIL = 0x0, 1095 PR_LINK_OFF_FRAME_COUNT_GOOD = 0x2, 1096 PR_LINK_OFF_FRAME_COUNT_BEST = 0x6, 1097 }; 1098 1099 /* 1100 * This is general Interface for Replay to 1101 * set an 32 bit variable to dmub 1102 * The Message_type indicates which variable 1103 * passed to DMUB. 1104 */ 1105 enum replay_FW_Message_type { 1106 Replay_Msg_Not_Support = -1, 1107 Replay_Set_Timing_Sync_Supported, 1108 Replay_Set_Residency_Frameupdate_Timer, 1109 Replay_Set_Pseudo_VTotal, 1110 Replay_Disabled_Adaptive_Sync_SDP, 1111 Replay_Set_General_Cmd, 1112 }; 1113 1114 union replay_error_status { 1115 struct { 1116 unsigned int STATE_TRANSITION_ERROR :1; 1117 unsigned int LINK_CRC_ERROR :1; 1118 unsigned int DESYNC_ERROR :1; 1119 unsigned int RESERVED_3 :1; 1120 unsigned int LOW_RR_INCORRECT_VTOTAL :1; 1121 unsigned int NO_DOUBLED_RR :1; 1122 unsigned int RESERVED_6_7 :2; 1123 } bits; 1124 unsigned char raw; 1125 }; 1126 1127 union replay_low_refresh_rate_enable_options { 1128 struct { 1129 //BIT[0-3]: Replay Low Hz Support control 1130 unsigned int ENABLE_LOW_RR_SUPPORT :1; 1131 unsigned int SKIP_ASIC_CHECK :1; 1132 unsigned int RESERVED_2_3 :2; 1133 //BIT[4-15]: Replay Low Hz Enable Scenarios 1134 unsigned int ENABLE_STATIC_SCREEN :1; 1135 unsigned int ENABLE_FULL_SCREEN_VIDEO :1; 1136 unsigned int ENABLE_GENERAL_UI :1; 1137 unsigned int RESERVED_7_15 :9; 1138 //BIT[16-31]: Replay Low Hz Enable Check 1139 unsigned int ENABLE_STATIC_FLICKER_CHECK :1; 1140 unsigned int RESERVED_17_31 :15; 1141 } bits; 1142 unsigned int raw; 1143 }; 1144 1145 union replay_optimization { 1146 struct { 1147 //BIT[0-3]: Replay Teams Optimization 1148 unsigned int TEAMS_OPTIMIZATION_VER_1 :1; 1149 unsigned int TEAMS_OPTIMIZATION_VER_2 :1; 1150 unsigned int RESERVED_2_3 :2; 1151 } bits; 1152 1153 unsigned int raw; 1154 }; 1155 1156 struct replay_config { 1157 /* Replay version */ 1158 enum dc_replay_version replay_version; 1159 /* Replay feature is supported */ 1160 bool replay_supported; 1161 /* Replay caps support DPCD & EDID caps*/ 1162 bool replay_cap_support; 1163 /* Power opt flags that are supported */ 1164 unsigned int replay_power_opt_supported; 1165 /* SMU optimization is supported */ 1166 bool replay_smu_opt_supported; 1167 /* Replay enablement option */ 1168 unsigned int replay_enable_option; 1169 /* Replay debug flags */ 1170 uint32_t debug_flags; 1171 /* Replay sync is supported */ 1172 bool replay_timing_sync_supported; 1173 /* Replay Disable desync error check. */ 1174 bool force_disable_desync_error_check; 1175 /* Replay Received Desync Error HPD. */ 1176 bool received_desync_error_hpd; 1177 /* Replay feature is supported long vblank */ 1178 bool replay_support_fast_resync_in_ultra_sleep_mode; 1179 /* Replay error status */ 1180 union replay_error_status replay_error_status; 1181 /* Replay Low Hz enable Options */ 1182 union replay_low_refresh_rate_enable_options low_rr_enable_options; 1183 /* Replay coasting vtotal is within low refresh rate range. */ 1184 bool low_rr_activated; 1185 /* Replay low refresh rate supported*/ 1186 bool low_rr_supported; 1187 /* Replay Video Conferencing Optimization Enabled */ 1188 bool replay_video_conferencing_optimization_enabled; 1189 /* Replay alpm mode */ 1190 enum dc_alpm_mode alpm_mode; 1191 /* Replay full screen only */ 1192 bool os_request_force_ffu; 1193 /* Replay optimization */ 1194 union replay_optimization replay_optimization; 1195 /* Replay sub feature Frame Skipping is supported */ 1196 bool frame_skip_supported; 1197 }; 1198 1199 /* Replay feature flags*/ 1200 struct replay_settings { 1201 /* Replay configuration */ 1202 struct replay_config config; 1203 /* Replay feature is ready for activating */ 1204 bool replay_feature_enabled; 1205 /* Replay is currently active */ 1206 bool replay_allow_active; 1207 /* Replay is currently active */ 1208 bool replay_allow_long_vblank; 1209 /* Power opt flags that are activated currently */ 1210 unsigned int replay_power_opt_active; 1211 /* SMU optimization is enabled */ 1212 bool replay_smu_opt_enable; 1213 /* Current Coasting vtotal */ 1214 uint32_t coasting_vtotal; 1215 /* Coasting vtotal table */ 1216 uint32_t coasting_vtotal_table[PR_COASTING_TYPE_NUM]; 1217 /* Defer Update Coasting vtotal table */ 1218 uint32_t defer_update_coasting_vtotal_table[PR_COASTING_TYPE_NUM]; 1219 /* Skip frame number table */ 1220 uint32_t frame_skip_number_table[PR_COASTING_TYPE_NUM]; 1221 /* Defer skip frame number table */ 1222 uint32_t defer_frame_skip_number_table[PR_COASTING_TYPE_NUM]; 1223 /* Maximum link off frame count */ 1224 uint32_t link_off_frame_count; 1225 /* Replay pseudo vtotal for low refresh rate*/ 1226 uint16_t low_rr_full_screen_video_pseudo_vtotal; 1227 /* Replay last pseudo vtotal set to DMUB */ 1228 uint16_t last_pseudo_vtotal; 1229 /* Replay desync error */ 1230 uint32_t replay_desync_error_fail_count; 1231 /* The frame skip number dal send to DMUB */ 1232 uint16_t frame_skip_number; 1233 /* Current Panel Replay event */ 1234 uint32_t replay_events; 1235 }; 1236 1237 /* To split out "global" and "per-panel" config settings. 1238 * Add a struct dc_panel_config under dc_link 1239 */ 1240 struct dc_panel_config { 1241 /* extra panel power sequence parameters */ 1242 struct pps { 1243 unsigned int extra_t3_ms; 1244 unsigned int extra_t7_ms; 1245 unsigned int extra_delay_backlight_off; 1246 unsigned int extra_post_t7_ms; 1247 unsigned int extra_pre_t11_ms; 1248 unsigned int extra_t12_ms; 1249 unsigned int extra_post_OUI_ms; 1250 } pps; 1251 /* nit brightness */ 1252 struct nits_brightness { 1253 unsigned int peak; /* nits */ 1254 unsigned int max_avg; /* nits */ 1255 unsigned int min; /* 1/10000 nits */ 1256 unsigned int max_nonboost_brightness_millinits; 1257 unsigned int min_brightness_millinits; 1258 } nits_brightness; 1259 /* PSR */ 1260 struct psr { 1261 bool disable_psr; 1262 bool disallow_psrsu; 1263 bool disallow_replay; 1264 bool rc_disable; 1265 bool rc_allow_static_screen; 1266 bool rc_allow_fullscreen_VPB; 1267 bool read_psrcap_again; 1268 unsigned int replay_enable_option; 1269 } psr; 1270 /* ABM */ 1271 struct varib { 1272 unsigned int varibright_feature_enable; 1273 unsigned int def_varibright_level; 1274 unsigned int abm_config_setting; 1275 } varib; 1276 /* edp DSC */ 1277 struct dsc { 1278 bool disable_dsc_edp; 1279 unsigned int force_dsc_edp_policy; 1280 } dsc; 1281 /* eDP ILR */ 1282 struct ilr { 1283 bool optimize_edp_link_rate; /* eDP ILR */ 1284 } ilr; 1285 }; 1286 1287 #define MAX_SINKS_PER_LINK 4 1288 1289 /* 1290 * USB4 DPIA BW ALLOCATION STRUCTS 1291 */ 1292 struct dc_dpia_bw_alloc { 1293 int remote_sink_req_bw[MAX_SINKS_PER_LINK]; // BW requested by remote sinks 1294 int link_verified_bw; // The Verified BW that link can allocated and use that has been verified already 1295 int link_max_bw; // The Max BW that link can require/support 1296 int allocated_bw; // The Actual Allocated BW for this DPIA 1297 int estimated_bw; // The estimated available BW for this DPIA 1298 int bw_granularity; // BW Granularity 1299 int dp_overhead; // DP overhead in dp tunneling 1300 bool bw_alloc_enabled; // The BW Alloc Mode Support is turned ON for all 3: DP-Tx & Dpia & CM 1301 uint8_t nrd_max_lane_count; // Non-reduced max lane count 1302 uint8_t nrd_max_link_rate; // Non-reduced max link rate 1303 }; 1304 1305 enum dc_hpd_enable_select { 1306 HPD_EN_FOR_ALL_EDP = 0, 1307 HPD_EN_FOR_PRIMARY_EDP_ONLY, 1308 HPD_EN_FOR_SECONDARY_EDP_ONLY, 1309 }; 1310 1311 enum dc_cm2_shaper_3dlut_setting { 1312 DC_CM2_SHAPER_3DLUT_SETTING_BYPASS_ALL, 1313 DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER, 1314 /* Bypassing Shaper will always bypass 3DLUT */ 1315 DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER_3DLUT 1316 }; 1317 1318 enum dc_cm2_gpu_mem_layout { 1319 DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_RGB, 1320 DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_BGR, 1321 DC_CM2_GPU_MEM_LAYOUT_1D_PACKED_LINEAR 1322 }; 1323 1324 enum dc_cm2_gpu_mem_pixel_component_order { 1325 DC_CM2_GPU_MEM_PIXEL_COMPONENT_ORDER_RGBA, 1326 }; 1327 1328 enum dc_cm2_gpu_mem_format { 1329 DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12MSB, 1330 DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12LSB, 1331 DC_CM2_GPU_MEM_FORMAT_16161616_FLOAT_FP1_5_10 1332 }; 1333 1334 struct dc_cm2_gpu_mem_format_parameters { 1335 enum dc_cm2_gpu_mem_format format; 1336 union { 1337 struct { 1338 /* bias & scale for float only */ 1339 uint16_t bias; 1340 uint16_t scale; 1341 } float_params; 1342 }; 1343 }; 1344 1345 enum dc_cm2_gpu_mem_size { 1346 DC_CM2_GPU_MEM_SIZE_171717, 1347 DC_CM2_GPU_MEM_SIZE_TRANSFORMED, 1348 }; 1349 1350 struct dc_cm2_gpu_mem_parameters { 1351 struct dc_plane_address addr; 1352 enum dc_cm2_gpu_mem_layout layout; 1353 struct dc_cm2_gpu_mem_format_parameters format_params; 1354 enum dc_cm2_gpu_mem_pixel_component_order component_order; 1355 enum dc_cm2_gpu_mem_size size; 1356 uint16_t bit_depth; 1357 }; 1358 1359 enum dc_cm2_transfer_func_source { 1360 DC_CM2_TRANSFER_FUNC_SOURCE_SYSMEM, 1361 DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM 1362 }; 1363 1364 struct dc_cm2_component_settings { 1365 enum dc_cm2_shaper_3dlut_setting shaper_3dlut_setting; 1366 bool lut1d_enable; 1367 }; 1368 1369 /* 1370 * All pointers in this struct must remain valid for as long as the 3DLUTs are used 1371 */ 1372 struct dc_cm2_func_luts { 1373 const struct dc_transfer_func *shaper; 1374 struct { 1375 enum dc_cm2_transfer_func_source lut3d_src; 1376 union { 1377 const struct dc_3dlut *lut3d_func; 1378 struct dc_cm2_gpu_mem_parameters gpu_mem_params; 1379 }; 1380 bool rmcm_3dlut_shaper_select; 1381 bool mpc_3dlut_enable; 1382 bool rmcm_3dlut_enable; 1383 bool mpc_mcm_post_blend; 1384 uint8_t rmcm_tmz; 1385 } lut3d_data; 1386 const struct dc_transfer_func *lut1d_func; 1387 }; 1388 1389 struct dc_cm2_parameters { 1390 struct dc_cm2_component_settings component_settings; 1391 struct dc_cm2_func_luts cm2_luts; 1392 }; 1393 1394 enum mall_stream_type { 1395 SUBVP_NONE, // subvp not in use 1396 SUBVP_MAIN, // subvp in use, this stream is main stream 1397 SUBVP_PHANTOM, // subvp in use, this stream is a phantom stream 1398 }; 1399 1400 enum dc_power_source_type { 1401 DC_POWER_SOURCE_AC, // wall power 1402 DC_POWER_SOURCE_DC, // battery power 1403 }; 1404 1405 struct dc_state_create_params { 1406 enum dc_power_source_type power_source; 1407 }; 1408 1409 struct dc_commit_streams_params { 1410 struct dc_stream_state **streams; 1411 uint8_t stream_count; 1412 enum dc_power_source_type power_source; 1413 }; 1414 1415 struct set_backlight_level_params { 1416 /* backlight in pwm */ 1417 uint32_t backlight_pwm_u16_16; 1418 /* brightness ramping */ 1419 uint32_t frame_ramp; 1420 /* backlight control type 1421 * 0: PWM backlight control 1422 * 1: VESA AUX backlight control 1423 * 2: AMD AUX backlight control 1424 */ 1425 enum backlight_control_type control_type; 1426 /* backlight in millinits */ 1427 uint32_t backlight_millinits; 1428 /* transition time in ms */ 1429 uint32_t transition_time_in_ms; 1430 /* minimum luminance in nits */ 1431 uint32_t min_luminance; 1432 /* maximum luminance in nits */ 1433 uint32_t max_luminance; 1434 /* minimum backlight in pwm */ 1435 uint32_t min_backlight_pwm; 1436 /* maximum backlight in pwm */ 1437 uint32_t max_backlight_pwm; 1438 /* AUX HW instance */ 1439 uint8_t aux_inst; 1440 }; 1441 1442 enum dc_validate_mode { 1443 /* validate the mode and program HW */ 1444 DC_VALIDATE_MODE_AND_PROGRAMMING = 0, 1445 /* only validate the mode */ 1446 DC_VALIDATE_MODE_ONLY = 1, 1447 /* validate the mode and get the max state (voltage level) */ 1448 DC_VALIDATE_MODE_AND_STATE_INDEX = 2, 1449 }; 1450 1451 struct dc_validation_dpia_set { 1452 const struct dc_link *link; 1453 const struct dc_tunnel_settings *tunnel_settings; 1454 uint32_t required_bw; 1455 }; 1456 1457 #endif /* DC_TYPES_H_ */ 1458