1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * PCI Express Hot Plug Controller Driver
4 *
5 * Copyright (C) 1995,2001 Compaq Computer Corporation
6 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
7 * Copyright (C) 2001 IBM Corp.
8 * Copyright (C) 2003-2004 Intel Corporation
9 *
10 * All rights reserved.
11 *
12 * Send feedback to <greg@kroah.com>, <kristen.c.accardi@intel.com>
13 *
14 */
15 #ifndef _PCIEHP_H
16 #define _PCIEHP_H
17
18 #include <linux/types.h>
19 #include <linux/pci.h>
20 #include <linux/pci_hotplug.h>
21 #include <linux/delay.h>
22 #include <linux/mutex.h>
23 #include <linux/rwsem.h>
24 #include <linux/workqueue.h>
25
26 #include "../pcie/portdrv.h"
27
28 extern bool pciehp_poll_mode;
29 extern int pciehp_poll_time;
30
31 /*
32 * Set CONFIG_DYNAMIC_DEBUG=y and boot with 'dyndbg="file pciehp* +p"' to
33 * enable debug messages.
34 */
35 #define ctrl_dbg(ctrl, format, arg...) \
36 pci_dbg(ctrl->pcie->port, format, ## arg)
37 #define ctrl_err(ctrl, format, arg...) \
38 pci_err(ctrl->pcie->port, format, ## arg)
39 #define ctrl_info(ctrl, format, arg...) \
40 pci_info(ctrl->pcie->port, format, ## arg)
41 #define ctrl_warn(ctrl, format, arg...) \
42 pci_warn(ctrl->pcie->port, format, ## arg)
43
44 #define SLOT_NAME_SIZE 10
45
46 /**
47 * struct controller - PCIe hotplug controller
48 * @pcie: pointer to the controller's PCIe port service device
49 * @dsn: cached copy of Device Serial Number of Function 0 in the hotplug slot
50 * (PCIe r6.2 sec 7.9.3); used to determine whether a hotplugged device
51 * was replaced with a different one during system sleep
52 * @slot_cap: cached copy of the Slot Capabilities register
53 * @inband_presence_disabled: In-Band Presence Detect Disable supported by
54 * controller and disabled per spec recommendation (PCIe r5.0, appendix I
55 * implementation note)
56 * @slot_ctrl: cached copy of the Slot Control register
57 * @ctrl_lock: serializes writes to the Slot Control register
58 * @cmd_started: jiffies when the Slot Control register was last written;
59 * the next write is allowed 1 second later, absent a Command Completed
60 * interrupt (PCIe r4.0, sec 6.7.3.2)
61 * @cmd_busy: flag set on Slot Control register write, cleared by IRQ handler
62 * on reception of a Command Completed event
63 * @queue: wait queue to wake up on reception of a Command Completed event,
64 * used for synchronous writes to the Slot Control register
65 * @pending_events: used by the IRQ handler to save events retrieved from the
66 * Slot Status register for later consumption by the IRQ thread
67 * @notification_enabled: whether the IRQ was requested successfully
68 * @power_fault_detected: whether a power fault was detected by the hardware
69 * that has not yet been cleared by the user
70 * @poll_thread: thread to poll for slot events if no IRQ is available,
71 * enabled with pciehp_poll_mode module parameter
72 * @state: current state machine position
73 * @state_lock: protects reads and writes of @state;
74 * protects scheduling, execution and cancellation of @button_work
75 * @button_work: work item to turn the slot on or off after 5 seconds
76 * in response to an Attention Button press
77 * @hotplug_slot: structure registered with the PCI hotplug core
78 * @reset_lock: prevents access to the Data Link Layer Link Active bit in the
79 * Link Status register and to the Presence Detect State bit in the Slot
80 * Status register during a slot reset which may cause them to flap
81 * @depth: Number of additional hotplug ports in the path to the root bus,
82 * used as lock subclass for @reset_lock
83 * @ist_running: flag to keep user request waiting while IRQ thread is running
84 * @request_result: result of last user request submitted to the IRQ thread
85 * @requester: wait queue to wake up on completion of user request,
86 * used for synchronous slot enable/disable request via sysfs
87 *
88 * PCIe hotplug has a 1:1 relationship between controller and slot, hence
89 * unlike other drivers, the two aren't represented by separate structures.
90 */
91 struct controller {
92 struct pcie_device *pcie;
93 u64 dsn;
94
95 u32 slot_cap; /* capabilities and quirks */
96 unsigned int inband_presence_disabled:1;
97
98 u16 slot_ctrl; /* control register access */
99 struct mutex ctrl_lock;
100 unsigned long cmd_started;
101 unsigned int cmd_busy:1;
102 wait_queue_head_t queue;
103
104 atomic_t pending_events; /* event handling */
105 unsigned int notification_enabled:1;
106 unsigned int power_fault_detected;
107 struct task_struct *poll_thread;
108
109 u8 state; /* state machine */
110 struct mutex state_lock;
111 struct delayed_work button_work;
112
113 struct hotplug_slot hotplug_slot; /* hotplug core interface */
114 struct rw_semaphore reset_lock;
115 unsigned int depth;
116 unsigned int ist_running;
117 int request_result;
118 wait_queue_head_t requester;
119 };
120
121 /**
122 * DOC: Slot state
123 *
124 * @OFF_STATE: slot is powered off, no subordinate devices are enumerated
125 * @BLINKINGON_STATE: slot will be powered on after the 5 second delay,
126 * Power Indicator is blinking
127 * @BLINKINGOFF_STATE: slot will be powered off after the 5 second delay,
128 * Power Indicator is blinking
129 * @POWERON_STATE: slot is currently powering on
130 * @POWEROFF_STATE: slot is currently powering off
131 * @ON_STATE: slot is powered on, subordinate devices have been enumerated
132 */
133 #define OFF_STATE 0
134 #define BLINKINGON_STATE 1
135 #define BLINKINGOFF_STATE 2
136 #define POWERON_STATE 3
137 #define POWEROFF_STATE 4
138 #define ON_STATE 5
139
140 /**
141 * DOC: Flags to request an action from the IRQ thread
142 *
143 * These are stored together with events read from the Slot Status register,
144 * hence must be greater than its 16-bit width.
145 *
146 * %DISABLE_SLOT: Disable the slot in response to a user request via sysfs or
147 * an Attention Button press after the 5 second delay
148 * %RERUN_ISR: Used by the IRQ handler to inform the IRQ thread that the
149 * hotplug port was inaccessible when the interrupt occurred, requiring
150 * that the IRQ handler is rerun by the IRQ thread after it has made the
151 * hotplug port accessible by runtime resuming its parents to D0
152 */
153 #define DISABLE_SLOT (1 << 16)
154 #define RERUN_ISR (1 << 17)
155
156 #define ATTN_BUTTN(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_ABP)
157 #define POWER_CTRL(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_PCP)
158 #define MRL_SENS(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_MRLSP)
159 #define ATTN_LED(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_AIP)
160 #define PWR_LED(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_PIP)
161 #define NO_CMD_CMPL(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_NCCS)
162 #define PSN(ctrl) (((ctrl)->slot_cap & PCI_EXP_SLTCAP_PSN) >> 19)
163
164 void pciehp_request(struct controller *ctrl, int action);
165 void pciehp_handle_button_press(struct controller *ctrl);
166 void pciehp_handle_disable_request(struct controller *ctrl);
167 void pciehp_handle_presence_or_link_change(struct controller *ctrl, u32 events);
168 int pciehp_configure_device(struct controller *ctrl);
169 void pciehp_unconfigure_device(struct controller *ctrl, bool presence);
170 void pciehp_queue_pushbutton_work(struct work_struct *work);
171 struct controller *pcie_init(struct pcie_device *dev);
172 int pcie_init_notification(struct controller *ctrl);
173 void pcie_shutdown_notification(struct controller *ctrl);
174 void pcie_clear_hotplug_events(struct controller *ctrl);
175 void pcie_enable_interrupt(struct controller *ctrl);
176 void pcie_disable_interrupt(struct controller *ctrl);
177 int pciehp_power_on_slot(struct controller *ctrl);
178 void pciehp_power_off_slot(struct controller *ctrl);
179 void pciehp_get_power_status(struct controller *ctrl, u8 *status);
180
181 #define INDICATOR_NOOP -1 /* Leave indicator unchanged */
182 void pciehp_set_indicators(struct controller *ctrl, int pwr, int attn);
183
184 void pciehp_get_latch_status(struct controller *ctrl, u8 *status);
185 int pciehp_query_power_fault(struct controller *ctrl);
186 int pciehp_card_present(struct controller *ctrl);
187 int pciehp_card_present_or_link_active(struct controller *ctrl);
188 int pciehp_check_link_status(struct controller *ctrl);
189 int pciehp_check_link_active(struct controller *ctrl);
190 void pciehp_release_ctrl(struct controller *ctrl);
191
192 int pciehp_sysfs_enable_slot(struct hotplug_slot *hotplug_slot);
193 int pciehp_sysfs_disable_slot(struct hotplug_slot *hotplug_slot);
194 int pciehp_reset_slot(struct hotplug_slot *hotplug_slot, bool probe);
195 int pciehp_get_attention_status(struct hotplug_slot *hotplug_slot, u8 *status);
196 int pciehp_set_raw_indicator_status(struct hotplug_slot *h_slot, u8 status);
197 int pciehp_get_raw_indicator_status(struct hotplug_slot *h_slot, u8 *status);
198
199 int pciehp_slot_reset(struct pcie_device *dev);
200
slot_name(struct controller * ctrl)201 static inline const char *slot_name(struct controller *ctrl)
202 {
203 return hotplug_slot_name(&ctrl->hotplug_slot);
204 }
205
to_ctrl(struct hotplug_slot * hotplug_slot)206 static inline struct controller *to_ctrl(struct hotplug_slot *hotplug_slot)
207 {
208 return container_of(hotplug_slot, struct controller, hotplug_slot);
209 }
210
211 #endif /* _PCIEHP_H */
212