1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include <linux/types.h>
8 #include <linux/bitops.h>
9 #include <linux/bitfield.h>
10
11 #include "debug.h"
12 #include "core.h"
13 #include "ce.h"
14 #include "hw.h"
15 #include "mhi.h"
16 #include "dp_rx.h"
17
18 static const guid_t wcn7850_uuid = GUID_INIT(0xf634f534, 0x6147, 0x11ec,
19 0x90, 0xd6, 0x02, 0x42,
20 0xac, 0x12, 0x00, 0x03);
21
ath12k_hw_qcn9274_mac_from_pdev_id(int pdev_idx)22 static u8 ath12k_hw_qcn9274_mac_from_pdev_id(int pdev_idx)
23 {
24 return pdev_idx;
25 }
26
ath12k_hw_mac_id_to_pdev_id_qcn9274(const struct ath12k_hw_params * hw,int mac_id)27 static int ath12k_hw_mac_id_to_pdev_id_qcn9274(const struct ath12k_hw_params *hw,
28 int mac_id)
29 {
30 return mac_id;
31 }
32
ath12k_hw_mac_id_to_srng_id_qcn9274(const struct ath12k_hw_params * hw,int mac_id)33 static int ath12k_hw_mac_id_to_srng_id_qcn9274(const struct ath12k_hw_params *hw,
34 int mac_id)
35 {
36 return 0;
37 }
38
ath12k_hw_get_ring_selector_qcn9274(struct sk_buff * skb)39 static u8 ath12k_hw_get_ring_selector_qcn9274(struct sk_buff *skb)
40 {
41 return smp_processor_id();
42 }
43
ath12k_dp_srng_is_comp_ring_qcn9274(int ring_num)44 static bool ath12k_dp_srng_is_comp_ring_qcn9274(int ring_num)
45 {
46 if (ring_num < 3 || ring_num == 4)
47 return true;
48
49 return false;
50 }
51
ath12k_hw_mac_id_to_pdev_id_wcn7850(const struct ath12k_hw_params * hw,int mac_id)52 static int ath12k_hw_mac_id_to_pdev_id_wcn7850(const struct ath12k_hw_params *hw,
53 int mac_id)
54 {
55 return 0;
56 }
57
ath12k_hw_mac_id_to_srng_id_wcn7850(const struct ath12k_hw_params * hw,int mac_id)58 static int ath12k_hw_mac_id_to_srng_id_wcn7850(const struct ath12k_hw_params *hw,
59 int mac_id)
60 {
61 return mac_id;
62 }
63
ath12k_hw_get_ring_selector_wcn7850(struct sk_buff * skb)64 static u8 ath12k_hw_get_ring_selector_wcn7850(struct sk_buff *skb)
65 {
66 return skb_get_queue_mapping(skb);
67 }
68
ath12k_dp_srng_is_comp_ring_wcn7850(int ring_num)69 static bool ath12k_dp_srng_is_comp_ring_wcn7850(int ring_num)
70 {
71 if (ring_num == 0 || ring_num == 2 || ring_num == 4)
72 return true;
73
74 return false;
75 }
76
77 static const struct ath12k_hw_ops qcn9274_ops = {
78 .get_hw_mac_from_pdev_id = ath12k_hw_qcn9274_mac_from_pdev_id,
79 .mac_id_to_pdev_id = ath12k_hw_mac_id_to_pdev_id_qcn9274,
80 .mac_id_to_srng_id = ath12k_hw_mac_id_to_srng_id_qcn9274,
81 .rxdma_ring_sel_config = ath12k_dp_rxdma_ring_sel_config_qcn9274,
82 .get_ring_selector = ath12k_hw_get_ring_selector_qcn9274,
83 .dp_srng_is_tx_comp_ring = ath12k_dp_srng_is_comp_ring_qcn9274,
84 };
85
86 static const struct ath12k_hw_ops wcn7850_ops = {
87 .get_hw_mac_from_pdev_id = ath12k_hw_qcn9274_mac_from_pdev_id,
88 .mac_id_to_pdev_id = ath12k_hw_mac_id_to_pdev_id_wcn7850,
89 .mac_id_to_srng_id = ath12k_hw_mac_id_to_srng_id_wcn7850,
90 .rxdma_ring_sel_config = ath12k_dp_rxdma_ring_sel_config_wcn7850,
91 .get_ring_selector = ath12k_hw_get_ring_selector_wcn7850,
92 .dp_srng_is_tx_comp_ring = ath12k_dp_srng_is_comp_ring_wcn7850,
93 };
94
95 #define ATH12K_TX_RING_MASK_0 0x1
96 #define ATH12K_TX_RING_MASK_1 0x2
97 #define ATH12K_TX_RING_MASK_2 0x4
98 #define ATH12K_TX_RING_MASK_3 0x8
99 #define ATH12K_TX_RING_MASK_4 0x10
100
101 #define ATH12K_RX_RING_MASK_0 0x1
102 #define ATH12K_RX_RING_MASK_1 0x2
103 #define ATH12K_RX_RING_MASK_2 0x4
104 #define ATH12K_RX_RING_MASK_3 0x8
105
106 #define ATH12K_RX_ERR_RING_MASK_0 0x1
107
108 #define ATH12K_RX_WBM_REL_RING_MASK_0 0x1
109
110 #define ATH12K_REO_STATUS_RING_MASK_0 0x1
111
112 #define ATH12K_HOST2RXDMA_RING_MASK_0 0x1
113
114 #define ATH12K_RX_MON_RING_MASK_0 0x1
115 #define ATH12K_RX_MON_RING_MASK_1 0x2
116 #define ATH12K_RX_MON_RING_MASK_2 0x4
117
118 #define ATH12K_TX_MON_RING_MASK_0 0x1
119 #define ATH12K_TX_MON_RING_MASK_1 0x2
120
121 /* Target firmware's Copy Engine configuration. */
122 static const struct ce_pipe_config ath12k_target_ce_config_wlan_qcn9274[] = {
123 /* CE0: host->target HTC control and raw streams */
124 {
125 .pipenum = __cpu_to_le32(0),
126 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
127 .nentries = __cpu_to_le32(32),
128 .nbytes_max = __cpu_to_le32(2048),
129 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
130 .reserved = __cpu_to_le32(0),
131 },
132
133 /* CE1: target->host HTT + HTC control */
134 {
135 .pipenum = __cpu_to_le32(1),
136 .pipedir = __cpu_to_le32(PIPEDIR_IN),
137 .nentries = __cpu_to_le32(32),
138 .nbytes_max = __cpu_to_le32(2048),
139 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
140 .reserved = __cpu_to_le32(0),
141 },
142
143 /* CE2: target->host WMI */
144 {
145 .pipenum = __cpu_to_le32(2),
146 .pipedir = __cpu_to_le32(PIPEDIR_IN),
147 .nentries = __cpu_to_le32(32),
148 .nbytes_max = __cpu_to_le32(2048),
149 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
150 .reserved = __cpu_to_le32(0),
151 },
152
153 /* CE3: host->target WMI (mac0) */
154 {
155 .pipenum = __cpu_to_le32(3),
156 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
157 .nentries = __cpu_to_le32(32),
158 .nbytes_max = __cpu_to_le32(2048),
159 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
160 .reserved = __cpu_to_le32(0),
161 },
162
163 /* CE4: host->target HTT */
164 {
165 .pipenum = __cpu_to_le32(4),
166 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
167 .nentries = __cpu_to_le32(256),
168 .nbytes_max = __cpu_to_le32(256),
169 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
170 .reserved = __cpu_to_le32(0),
171 },
172
173 /* CE5: target->host Pktlog */
174 {
175 .pipenum = __cpu_to_le32(5),
176 .pipedir = __cpu_to_le32(PIPEDIR_IN),
177 .nentries = __cpu_to_le32(32),
178 .nbytes_max = __cpu_to_le32(2048),
179 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
180 .reserved = __cpu_to_le32(0),
181 },
182
183 /* CE6: Reserved for target autonomous hif_memcpy */
184 {
185 .pipenum = __cpu_to_le32(6),
186 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
187 .nentries = __cpu_to_le32(32),
188 .nbytes_max = __cpu_to_le32(16384),
189 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
190 .reserved = __cpu_to_le32(0),
191 },
192
193 /* CE7: host->target WMI (mac1) */
194 {
195 .pipenum = __cpu_to_le32(7),
196 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
197 .nentries = __cpu_to_le32(32),
198 .nbytes_max = __cpu_to_le32(2048),
199 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
200 .reserved = __cpu_to_le32(0),
201 },
202
203 /* CE8: Reserved for target autonomous hif_memcpy */
204 {
205 .pipenum = __cpu_to_le32(8),
206 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
207 .nentries = __cpu_to_le32(32),
208 .nbytes_max = __cpu_to_le32(16384),
209 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
210 .reserved = __cpu_to_le32(0),
211 },
212
213 /* CE9, 10 and 11: Reserved for MHI */
214
215 /* CE12: Target CV prefetch */
216 {
217 .pipenum = __cpu_to_le32(12),
218 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
219 .nentries = __cpu_to_le32(32),
220 .nbytes_max = __cpu_to_le32(2048),
221 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
222 .reserved = __cpu_to_le32(0),
223 },
224
225 /* CE13: Target CV prefetch */
226 {
227 .pipenum = __cpu_to_le32(13),
228 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
229 .nentries = __cpu_to_le32(32),
230 .nbytes_max = __cpu_to_le32(2048),
231 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
232 .reserved = __cpu_to_le32(0),
233 },
234
235 /* CE14: WMI logging/CFR/Spectral/Radar */
236 {
237 .pipenum = __cpu_to_le32(14),
238 .pipedir = __cpu_to_le32(PIPEDIR_IN),
239 .nentries = __cpu_to_le32(32),
240 .nbytes_max = __cpu_to_le32(2048),
241 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
242 .reserved = __cpu_to_le32(0),
243 },
244
245 /* CE15: Reserved */
246 };
247
248 /* Target firmware's Copy Engine configuration. */
249 static const struct ce_pipe_config ath12k_target_ce_config_wlan_wcn7850[] = {
250 /* CE0: host->target HTC control and raw streams */
251 {
252 .pipenum = __cpu_to_le32(0),
253 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
254 .nentries = __cpu_to_le32(32),
255 .nbytes_max = __cpu_to_le32(2048),
256 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
257 .reserved = __cpu_to_le32(0),
258 },
259
260 /* CE1: target->host HTT + HTC control */
261 {
262 .pipenum = __cpu_to_le32(1),
263 .pipedir = __cpu_to_le32(PIPEDIR_IN),
264 .nentries = __cpu_to_le32(32),
265 .nbytes_max = __cpu_to_le32(2048),
266 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
267 .reserved = __cpu_to_le32(0),
268 },
269
270 /* CE2: target->host WMI */
271 {
272 .pipenum = __cpu_to_le32(2),
273 .pipedir = __cpu_to_le32(PIPEDIR_IN),
274 .nentries = __cpu_to_le32(32),
275 .nbytes_max = __cpu_to_le32(2048),
276 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
277 .reserved = __cpu_to_le32(0),
278 },
279
280 /* CE3: host->target WMI */
281 {
282 .pipenum = __cpu_to_le32(3),
283 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
284 .nentries = __cpu_to_le32(32),
285 .nbytes_max = __cpu_to_le32(2048),
286 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
287 .reserved = __cpu_to_le32(0),
288 },
289
290 /* CE4: host->target HTT */
291 {
292 .pipenum = __cpu_to_le32(4),
293 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
294 .nentries = __cpu_to_le32(256),
295 .nbytes_max = __cpu_to_le32(256),
296 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
297 .reserved = __cpu_to_le32(0),
298 },
299
300 /* CE5: target->host Pktlog */
301 {
302 .pipenum = __cpu_to_le32(5),
303 .pipedir = __cpu_to_le32(PIPEDIR_IN),
304 .nentries = __cpu_to_le32(32),
305 .nbytes_max = __cpu_to_le32(2048),
306 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
307 .reserved = __cpu_to_le32(0),
308 },
309
310 /* CE6: Reserved for target autonomous hif_memcpy */
311 {
312 .pipenum = __cpu_to_le32(6),
313 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
314 .nentries = __cpu_to_le32(32),
315 .nbytes_max = __cpu_to_le32(16384),
316 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
317 .reserved = __cpu_to_le32(0),
318 },
319
320 /* CE7 used only by Host */
321 {
322 .pipenum = __cpu_to_le32(7),
323 .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H),
324 .nentries = __cpu_to_le32(0),
325 .nbytes_max = __cpu_to_le32(0),
326 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
327 .reserved = __cpu_to_le32(0),
328 },
329
330 /* CE8 target->host used only by IPA */
331 {
332 .pipenum = __cpu_to_le32(8),
333 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
334 .nentries = __cpu_to_le32(32),
335 .nbytes_max = __cpu_to_le32(16384),
336 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
337 .reserved = __cpu_to_le32(0),
338 },
339 /* CE 9, 10, 11 are used by MHI driver */
340 };
341
342 /* Map from service/endpoint to Copy Engine.
343 * This table is derived from the CE_PCI TABLE, above.
344 * It is passed to the Target at startup for use by firmware.
345 */
346 static const struct service_to_pipe ath12k_target_service_to_ce_map_wlan_qcn9274[] = {
347 {
348 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VO),
349 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
350 __cpu_to_le32(3),
351 },
352 {
353 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VO),
354 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
355 __cpu_to_le32(2),
356 },
357 {
358 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BK),
359 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
360 __cpu_to_le32(3),
361 },
362 {
363 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BK),
364 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
365 __cpu_to_le32(2),
366 },
367 {
368 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BE),
369 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
370 __cpu_to_le32(3),
371 },
372 {
373 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BE),
374 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
375 __cpu_to_le32(2),
376 },
377 {
378 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VI),
379 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
380 __cpu_to_le32(3),
381 },
382 {
383 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VI),
384 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
385 __cpu_to_le32(2),
386 },
387 {
388 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL),
389 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
390 __cpu_to_le32(3),
391 },
392 {
393 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL),
394 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
395 __cpu_to_le32(2),
396 },
397 {
398 __cpu_to_le32(ATH12K_HTC_SVC_ID_RSVD_CTRL),
399 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
400 __cpu_to_le32(0),
401 },
402 {
403 __cpu_to_le32(ATH12K_HTC_SVC_ID_RSVD_CTRL),
404 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
405 __cpu_to_le32(1),
406 },
407 {
408 __cpu_to_le32(ATH12K_HTC_SVC_ID_TEST_RAW_STREAMS),
409 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
410 __cpu_to_le32(0),
411 },
412 {
413 __cpu_to_le32(ATH12K_HTC_SVC_ID_TEST_RAW_STREAMS),
414 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
415 __cpu_to_le32(1),
416 },
417 {
418 __cpu_to_le32(ATH12K_HTC_SVC_ID_HTT_DATA_MSG),
419 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
420 __cpu_to_le32(4),
421 },
422 {
423 __cpu_to_le32(ATH12K_HTC_SVC_ID_HTT_DATA_MSG),
424 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
425 __cpu_to_le32(1),
426 },
427 {
428 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL_MAC1),
429 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
430 __cpu_to_le32(7),
431 },
432 {
433 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL_MAC1),
434 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
435 __cpu_to_le32(2),
436 },
437 {
438 __cpu_to_le32(ATH12K_HTC_SVC_ID_PKT_LOG),
439 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
440 __cpu_to_le32(5),
441 },
442 {
443 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL_DIAG),
444 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
445 __cpu_to_le32(14),
446 },
447
448 /* (Additions here) */
449
450 { /* must be last */
451 __cpu_to_le32(0),
452 __cpu_to_le32(0),
453 __cpu_to_le32(0),
454 },
455 };
456
457 static const struct service_to_pipe ath12k_target_service_to_ce_map_wlan_wcn7850[] = {
458 {
459 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VO),
460 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
461 __cpu_to_le32(3),
462 },
463 {
464 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VO),
465 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
466 __cpu_to_le32(2),
467 },
468 {
469 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BK),
470 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
471 __cpu_to_le32(3),
472 },
473 {
474 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BK),
475 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
476 __cpu_to_le32(2),
477 },
478 {
479 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BE),
480 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
481 __cpu_to_le32(3),
482 },
483 {
484 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BE),
485 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
486 __cpu_to_le32(2),
487 },
488 {
489 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VI),
490 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
491 __cpu_to_le32(3),
492 },
493 {
494 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VI),
495 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
496 __cpu_to_le32(2),
497 },
498 {
499 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL),
500 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
501 __cpu_to_le32(3),
502 },
503 {
504 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL),
505 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
506 __cpu_to_le32(2),
507 },
508 {
509 __cpu_to_le32(ATH12K_HTC_SVC_ID_RSVD_CTRL),
510 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
511 __cpu_to_le32(0),
512 },
513 {
514 __cpu_to_le32(ATH12K_HTC_SVC_ID_RSVD_CTRL),
515 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
516 __cpu_to_le32(2),
517 },
518 {
519 __cpu_to_le32(ATH12K_HTC_SVC_ID_HTT_DATA_MSG),
520 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
521 __cpu_to_le32(4),
522 },
523 {
524 __cpu_to_le32(ATH12K_HTC_SVC_ID_HTT_DATA_MSG),
525 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
526 __cpu_to_le32(1),
527 },
528
529 /* (Additions here) */
530
531 { /* must be last */
532 __cpu_to_le32(0),
533 __cpu_to_le32(0),
534 __cpu_to_le32(0),
535 },
536 };
537
538 static const struct ath12k_hw_ring_mask ath12k_hw_ring_mask_qcn9274 = {
539 .tx = {
540 ATH12K_TX_RING_MASK_0,
541 ATH12K_TX_RING_MASK_1,
542 ATH12K_TX_RING_MASK_2,
543 ATH12K_TX_RING_MASK_3,
544 },
545 .rx_mon_dest = {
546 0, 0, 0, 0,
547 0, 0, 0, 0,
548 ATH12K_RX_MON_RING_MASK_0,
549 ATH12K_RX_MON_RING_MASK_1,
550 ATH12K_RX_MON_RING_MASK_2,
551 },
552 .rx = {
553 0, 0, 0, 0,
554 ATH12K_RX_RING_MASK_0,
555 ATH12K_RX_RING_MASK_1,
556 ATH12K_RX_RING_MASK_2,
557 ATH12K_RX_RING_MASK_3,
558 },
559 .rx_err = {
560 0, 0, 0,
561 ATH12K_RX_ERR_RING_MASK_0,
562 },
563 .rx_wbm_rel = {
564 0, 0, 0,
565 ATH12K_RX_WBM_REL_RING_MASK_0,
566 },
567 .reo_status = {
568 0, 0, 0,
569 ATH12K_REO_STATUS_RING_MASK_0,
570 },
571 .host2rxdma = {
572 0, 0, 0,
573 ATH12K_HOST2RXDMA_RING_MASK_0,
574 },
575 .tx_mon_dest = {
576 0, 0, 0,
577 },
578 };
579
580 static const struct ath12k_hw_ring_mask ath12k_hw_ring_mask_wcn7850 = {
581 .tx = {
582 ATH12K_TX_RING_MASK_0,
583 ATH12K_TX_RING_MASK_1,
584 ATH12K_TX_RING_MASK_2,
585 },
586 .rx_mon_dest = {
587 },
588 .rx = {
589 0, 0, 0,
590 ATH12K_RX_RING_MASK_0,
591 ATH12K_RX_RING_MASK_1,
592 ATH12K_RX_RING_MASK_2,
593 ATH12K_RX_RING_MASK_3,
594 },
595 .rx_err = {
596 ATH12K_RX_ERR_RING_MASK_0,
597 },
598 .rx_wbm_rel = {
599 ATH12K_RX_WBM_REL_RING_MASK_0,
600 },
601 .reo_status = {
602 ATH12K_REO_STATUS_RING_MASK_0,
603 },
604 .host2rxdma = {
605 },
606 .tx_mon_dest = {
607 },
608 };
609
610 static const struct ath12k_hw_regs qcn9274_v1_regs = {
611 /* SW2TCL(x) R0 ring configuration address */
612 .hal_tcl1_ring_id = 0x00000908,
613 .hal_tcl1_ring_misc = 0x00000910,
614 .hal_tcl1_ring_tp_addr_lsb = 0x0000091c,
615 .hal_tcl1_ring_tp_addr_msb = 0x00000920,
616 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000930,
617 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000934,
618 .hal_tcl1_ring_msi1_base_lsb = 0x00000948,
619 .hal_tcl1_ring_msi1_base_msb = 0x0000094c,
620 .hal_tcl1_ring_msi1_data = 0x00000950,
621 .hal_tcl_ring_base_lsb = 0x00000b58,
622
623 /* TCL STATUS ring address */
624 .hal_tcl_status_ring_base_lsb = 0x00000d38,
625
626 .hal_wbm_idle_ring_base_lsb = 0x00000d0c,
627 .hal_wbm_idle_ring_misc_addr = 0x00000d1c,
628 .hal_wbm_r0_idle_list_cntl_addr = 0x00000210,
629 .hal_wbm_r0_idle_list_size_addr = 0x00000214,
630 .hal_wbm_scattered_ring_base_lsb = 0x00000220,
631 .hal_wbm_scattered_ring_base_msb = 0x00000224,
632 .hal_wbm_scattered_desc_head_info_ix0 = 0x00000230,
633 .hal_wbm_scattered_desc_head_info_ix1 = 0x00000234,
634 .hal_wbm_scattered_desc_tail_info_ix0 = 0x00000240,
635 .hal_wbm_scattered_desc_tail_info_ix1 = 0x00000244,
636 .hal_wbm_scattered_desc_ptr_hp_addr = 0x0000024c,
637
638 .hal_wbm_sw_release_ring_base_lsb = 0x0000034c,
639 .hal_wbm_sw1_release_ring_base_lsb = 0x000003c4,
640 .hal_wbm0_release_ring_base_lsb = 0x00000dd8,
641 .hal_wbm1_release_ring_base_lsb = 0x00000e50,
642
643 /* PCIe base address */
644 .pcie_qserdes_sysclk_en_sel = 0x01e0c0a8,
645 .pcie_pcs_osc_dtct_config_base = 0x01e0d45c,
646
647 /* PPE release ring address */
648 .hal_ppe_rel_ring_base = 0x0000043c,
649
650 /* REO DEST ring address */
651 .hal_reo2_ring_base = 0x0000055c,
652 .hal_reo1_misc_ctrl_addr = 0x00000b7c,
653 .hal_reo1_sw_cookie_cfg0 = 0x00000050,
654 .hal_reo1_sw_cookie_cfg1 = 0x00000054,
655 .hal_reo1_qdesc_lut_base0 = 0x00000058,
656 .hal_reo1_qdesc_lut_base1 = 0x0000005c,
657 .hal_reo1_ring_base_lsb = 0x000004e4,
658 .hal_reo1_ring_base_msb = 0x000004e8,
659 .hal_reo1_ring_id = 0x000004ec,
660 .hal_reo1_ring_misc = 0x000004f4,
661 .hal_reo1_ring_hp_addr_lsb = 0x000004f8,
662 .hal_reo1_ring_hp_addr_msb = 0x000004fc,
663 .hal_reo1_ring_producer_int_setup = 0x00000508,
664 .hal_reo1_ring_msi1_base_lsb = 0x0000052C,
665 .hal_reo1_ring_msi1_base_msb = 0x00000530,
666 .hal_reo1_ring_msi1_data = 0x00000534,
667 .hal_reo1_aging_thres_ix0 = 0x00000b08,
668 .hal_reo1_aging_thres_ix1 = 0x00000b0c,
669 .hal_reo1_aging_thres_ix2 = 0x00000b10,
670 .hal_reo1_aging_thres_ix3 = 0x00000b14,
671
672 /* REO Exception ring address */
673 .hal_reo2_sw0_ring_base = 0x000008a4,
674
675 /* REO Reinject ring address */
676 .hal_sw2reo_ring_base = 0x00000304,
677 .hal_sw2reo1_ring_base = 0x0000037c,
678
679 /* REO cmd ring address */
680 .hal_reo_cmd_ring_base = 0x0000028c,
681
682 /* REO status ring address */
683 .hal_reo_status_ring_base = 0x00000a84,
684 };
685
686 static const struct ath12k_hw_regs qcn9274_v2_regs = {
687 /* SW2TCL(x) R0 ring configuration address */
688 .hal_tcl1_ring_id = 0x00000908,
689 .hal_tcl1_ring_misc = 0x00000910,
690 .hal_tcl1_ring_tp_addr_lsb = 0x0000091c,
691 .hal_tcl1_ring_tp_addr_msb = 0x00000920,
692 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000930,
693 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000934,
694 .hal_tcl1_ring_msi1_base_lsb = 0x00000948,
695 .hal_tcl1_ring_msi1_base_msb = 0x0000094c,
696 .hal_tcl1_ring_msi1_data = 0x00000950,
697 .hal_tcl_ring_base_lsb = 0x00000b58,
698
699 /* TCL STATUS ring address */
700 .hal_tcl_status_ring_base_lsb = 0x00000d38,
701
702 /* WBM idle link ring address */
703 .hal_wbm_idle_ring_base_lsb = 0x00000d3c,
704 .hal_wbm_idle_ring_misc_addr = 0x00000d4c,
705 .hal_wbm_r0_idle_list_cntl_addr = 0x00000240,
706 .hal_wbm_r0_idle_list_size_addr = 0x00000244,
707 .hal_wbm_scattered_ring_base_lsb = 0x00000250,
708 .hal_wbm_scattered_ring_base_msb = 0x00000254,
709 .hal_wbm_scattered_desc_head_info_ix0 = 0x00000260,
710 .hal_wbm_scattered_desc_head_info_ix1 = 0x00000264,
711 .hal_wbm_scattered_desc_tail_info_ix0 = 0x00000270,
712 .hal_wbm_scattered_desc_tail_info_ix1 = 0x00000274,
713 .hal_wbm_scattered_desc_ptr_hp_addr = 0x0000027c,
714
715 /* SW2WBM release ring address */
716 .hal_wbm_sw_release_ring_base_lsb = 0x0000037c,
717 .hal_wbm_sw1_release_ring_base_lsb = 0x000003f4,
718
719 /* WBM2SW release ring address */
720 .hal_wbm0_release_ring_base_lsb = 0x00000e08,
721 .hal_wbm1_release_ring_base_lsb = 0x00000e80,
722
723 /* PCIe base address */
724 .pcie_qserdes_sysclk_en_sel = 0x01e0c0a8,
725 .pcie_pcs_osc_dtct_config_base = 0x01e0d45c,
726
727 /* PPE release ring address */
728 .hal_ppe_rel_ring_base = 0x0000046c,
729
730 /* REO DEST ring address */
731 .hal_reo2_ring_base = 0x00000578,
732 .hal_reo1_misc_ctrl_addr = 0x00000b9c,
733 .hal_reo1_sw_cookie_cfg0 = 0x0000006c,
734 .hal_reo1_sw_cookie_cfg1 = 0x00000070,
735 .hal_reo1_qdesc_lut_base0 = 0x00000074,
736 .hal_reo1_qdesc_lut_base1 = 0x00000078,
737 .hal_reo1_ring_base_lsb = 0x00000500,
738 .hal_reo1_ring_base_msb = 0x00000504,
739 .hal_reo1_ring_id = 0x00000508,
740 .hal_reo1_ring_misc = 0x00000510,
741 .hal_reo1_ring_hp_addr_lsb = 0x00000514,
742 .hal_reo1_ring_hp_addr_msb = 0x00000518,
743 .hal_reo1_ring_producer_int_setup = 0x00000524,
744 .hal_reo1_ring_msi1_base_lsb = 0x00000548,
745 .hal_reo1_ring_msi1_base_msb = 0x0000054C,
746 .hal_reo1_ring_msi1_data = 0x00000550,
747 .hal_reo1_aging_thres_ix0 = 0x00000B28,
748 .hal_reo1_aging_thres_ix1 = 0x00000B2C,
749 .hal_reo1_aging_thres_ix2 = 0x00000B30,
750 .hal_reo1_aging_thres_ix3 = 0x00000B34,
751
752 /* REO Exception ring address */
753 .hal_reo2_sw0_ring_base = 0x000008c0,
754
755 /* REO Reinject ring address */
756 .hal_sw2reo_ring_base = 0x00000320,
757 .hal_sw2reo1_ring_base = 0x00000398,
758
759 /* REO cmd ring address */
760 .hal_reo_cmd_ring_base = 0x000002A8,
761
762 /* REO status ring address */
763 .hal_reo_status_ring_base = 0x00000aa0,
764 };
765
766 static const struct ath12k_hw_regs wcn7850_regs = {
767 /* SW2TCL(x) R0 ring configuration address */
768 .hal_tcl1_ring_id = 0x00000908,
769 .hal_tcl1_ring_misc = 0x00000910,
770 .hal_tcl1_ring_tp_addr_lsb = 0x0000091c,
771 .hal_tcl1_ring_tp_addr_msb = 0x00000920,
772 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000930,
773 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000934,
774 .hal_tcl1_ring_msi1_base_lsb = 0x00000948,
775 .hal_tcl1_ring_msi1_base_msb = 0x0000094c,
776 .hal_tcl1_ring_msi1_data = 0x00000950,
777 .hal_tcl_ring_base_lsb = 0x00000b58,
778
779 /* TCL STATUS ring address */
780 .hal_tcl_status_ring_base_lsb = 0x00000d38,
781
782 .hal_wbm_idle_ring_base_lsb = 0x00000d3c,
783 .hal_wbm_idle_ring_misc_addr = 0x00000d4c,
784 .hal_wbm_r0_idle_list_cntl_addr = 0x00000240,
785 .hal_wbm_r0_idle_list_size_addr = 0x00000244,
786 .hal_wbm_scattered_ring_base_lsb = 0x00000250,
787 .hal_wbm_scattered_ring_base_msb = 0x00000254,
788 .hal_wbm_scattered_desc_head_info_ix0 = 0x00000260,
789 .hal_wbm_scattered_desc_head_info_ix1 = 0x00000264,
790 .hal_wbm_scattered_desc_tail_info_ix0 = 0x00000270,
791 .hal_wbm_scattered_desc_tail_info_ix1 = 0x00000274,
792 .hal_wbm_scattered_desc_ptr_hp_addr = 0x00000027c,
793
794 .hal_wbm_sw_release_ring_base_lsb = 0x0000037c,
795 .hal_wbm_sw1_release_ring_base_lsb = 0x00000284,
796 .hal_wbm0_release_ring_base_lsb = 0x00000e08,
797 .hal_wbm1_release_ring_base_lsb = 0x00000e80,
798
799 /* PCIe base address */
800 .pcie_qserdes_sysclk_en_sel = 0x01e0e0a8,
801 .pcie_pcs_osc_dtct_config_base = 0x01e0f45c,
802
803 /* PPE release ring address */
804 .hal_ppe_rel_ring_base = 0x0000043c,
805
806 /* REO DEST ring address */
807 .hal_reo2_ring_base = 0x0000055c,
808 .hal_reo1_misc_ctrl_addr = 0x00000b7c,
809 .hal_reo1_sw_cookie_cfg0 = 0x00000050,
810 .hal_reo1_sw_cookie_cfg1 = 0x00000054,
811 .hal_reo1_qdesc_lut_base0 = 0x00000058,
812 .hal_reo1_qdesc_lut_base1 = 0x0000005c,
813 .hal_reo1_ring_base_lsb = 0x000004e4,
814 .hal_reo1_ring_base_msb = 0x000004e8,
815 .hal_reo1_ring_id = 0x000004ec,
816 .hal_reo1_ring_misc = 0x000004f4,
817 .hal_reo1_ring_hp_addr_lsb = 0x000004f8,
818 .hal_reo1_ring_hp_addr_msb = 0x000004fc,
819 .hal_reo1_ring_producer_int_setup = 0x00000508,
820 .hal_reo1_ring_msi1_base_lsb = 0x0000052C,
821 .hal_reo1_ring_msi1_base_msb = 0x00000530,
822 .hal_reo1_ring_msi1_data = 0x00000534,
823 .hal_reo1_aging_thres_ix0 = 0x00000b08,
824 .hal_reo1_aging_thres_ix1 = 0x00000b0c,
825 .hal_reo1_aging_thres_ix2 = 0x00000b10,
826 .hal_reo1_aging_thres_ix3 = 0x00000b14,
827
828 /* REO Exception ring address */
829 .hal_reo2_sw0_ring_base = 0x000008a4,
830
831 /* REO Reinject ring address */
832 .hal_sw2reo_ring_base = 0x00000304,
833 .hal_sw2reo1_ring_base = 0x0000037c,
834
835 /* REO cmd ring address */
836 .hal_reo_cmd_ring_base = 0x0000028c,
837
838 /* REO status ring address */
839 .hal_reo_status_ring_base = 0x00000a84,
840 };
841
842 static const struct ath12k_hw_hal_params ath12k_hw_hal_params_qcn9274 = {
843 .rx_buf_rbm = HAL_RX_BUF_RBM_SW3_BM,
844 .wbm2sw_cc_enable = HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW0_EN |
845 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW1_EN |
846 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW2_EN |
847 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW3_EN |
848 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW4_EN,
849 };
850
851 static const struct ath12k_hw_hal_params ath12k_hw_hal_params_wcn7850 = {
852 .rx_buf_rbm = HAL_RX_BUF_RBM_SW1_BM,
853 .wbm2sw_cc_enable = HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW0_EN |
854 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW2_EN |
855 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW3_EN |
856 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW4_EN,
857 };
858
859 static const struct ath12k_hw_params ath12k_hw_params[] = {
860 {
861 .name = "qcn9274 hw1.0",
862 .hw_rev = ATH12K_HW_QCN9274_HW10,
863 .fw = {
864 .dir = "QCN9274/hw1.0",
865 .board_size = 256 * 1024,
866 .cal_offset = 128 * 1024,
867 },
868 .max_radios = 1,
869 .single_pdev_only = false,
870 .qmi_service_ins_id = ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9274,
871 .internal_sleep_clock = false,
872
873 .hw_ops = &qcn9274_ops,
874 .ring_mask = &ath12k_hw_ring_mask_qcn9274,
875 .regs = &qcn9274_v1_regs,
876
877 .host_ce_config = ath12k_host_ce_config_qcn9274,
878 .ce_count = 16,
879 .target_ce_config = ath12k_target_ce_config_wlan_qcn9274,
880 .target_ce_count = 12,
881 .svc_to_ce_map = ath12k_target_service_to_ce_map_wlan_qcn9274,
882 .svc_to_ce_map_len = 18,
883
884 .hal_params = &ath12k_hw_hal_params_qcn9274,
885
886 .rxdma1_enable = false,
887 .num_rxdma_per_pdev = 1,
888 .num_rxdma_dst_ring = 0,
889 .rx_mac_buf_ring = false,
890 .vdev_start_delay = false,
891
892 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
893 BIT(NL80211_IFTYPE_AP) |
894 BIT(NL80211_IFTYPE_MESH_POINT) |
895 BIT(NL80211_IFTYPE_AP_VLAN),
896 .supports_monitor = false,
897
898 .idle_ps = false,
899 .download_calib = true,
900 .supports_suspend = false,
901 .tcl_ring_retry = true,
902 .reoq_lut_support = false,
903 .supports_shadow_regs = false,
904
905 .num_tcl_banks = 48,
906 .max_tx_ring = 4,
907
908 .mhi_config = &ath12k_mhi_config_qcn9274,
909
910 .wmi_init = ath12k_wmi_init_qcn9274,
911
912 .hal_ops = &hal_qcn9274_ops,
913
914 .qmi_cnss_feature_bitmap = BIT(CNSS_QDSS_CFG_MISS_V01),
915
916 .rfkill_pin = 0,
917 .rfkill_cfg = 0,
918 .rfkill_on_level = 0,
919
920 .rddm_size = 0x600000,
921
922 .def_num_link = 0,
923 .max_mlo_peer = 256,
924
925 .otp_board_id_register = QCN9274_QFPROM_RAW_RFA_PDET_ROW13_LSB,
926
927 .supports_sta_ps = false,
928
929 .acpi_guid = NULL,
930 .supports_dynamic_smps_6ghz = true,
931
932 .iova_mask = 0,
933
934 .supports_aspm = false,
935 },
936 {
937 .name = "wcn7850 hw2.0",
938 .hw_rev = ATH12K_HW_WCN7850_HW20,
939
940 .fw = {
941 .dir = "WCN7850/hw2.0",
942 .board_size = 256 * 1024,
943 .cal_offset = 256 * 1024,
944 },
945
946 .max_radios = 1,
947 .single_pdev_only = true,
948 .qmi_service_ins_id = ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_WCN7850,
949 .internal_sleep_clock = true,
950
951 .hw_ops = &wcn7850_ops,
952 .ring_mask = &ath12k_hw_ring_mask_wcn7850,
953 .regs = &wcn7850_regs,
954
955 .host_ce_config = ath12k_host_ce_config_wcn7850,
956 .ce_count = 9,
957 .target_ce_config = ath12k_target_ce_config_wlan_wcn7850,
958 .target_ce_count = 9,
959 .svc_to_ce_map = ath12k_target_service_to_ce_map_wlan_wcn7850,
960 .svc_to_ce_map_len = 14,
961
962 .hal_params = &ath12k_hw_hal_params_wcn7850,
963
964 .rxdma1_enable = false,
965 .num_rxdma_per_pdev = 2,
966 .num_rxdma_dst_ring = 1,
967 .rx_mac_buf_ring = true,
968 .vdev_start_delay = true,
969
970 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
971 BIT(NL80211_IFTYPE_AP) |
972 BIT(NL80211_IFTYPE_P2P_DEVICE) |
973 BIT(NL80211_IFTYPE_P2P_CLIENT) |
974 BIT(NL80211_IFTYPE_P2P_GO),
975 .supports_monitor = false,
976
977 .idle_ps = true,
978 .download_calib = false,
979 .supports_suspend = true,
980 .tcl_ring_retry = false,
981 .reoq_lut_support = false,
982 .supports_shadow_regs = true,
983
984 .num_tcl_banks = 7,
985 .max_tx_ring = 3,
986
987 .mhi_config = &ath12k_mhi_config_wcn7850,
988
989 .wmi_init = ath12k_wmi_init_wcn7850,
990
991 .hal_ops = &hal_wcn7850_ops,
992
993 .qmi_cnss_feature_bitmap = BIT(CNSS_QDSS_CFG_MISS_V01) |
994 BIT(CNSS_PCIE_PERST_NO_PULL_V01),
995
996 .rfkill_pin = 48,
997 .rfkill_cfg = 0,
998 .rfkill_on_level = 1,
999
1000 .rddm_size = 0x780000,
1001
1002 .def_num_link = 2,
1003 .max_mlo_peer = 32,
1004
1005 .otp_board_id_register = 0,
1006
1007 .supports_sta_ps = true,
1008
1009 .acpi_guid = &wcn7850_uuid,
1010 .supports_dynamic_smps_6ghz = false,
1011
1012 .iova_mask = ATH12K_PCIE_MAX_PAYLOAD_SIZE - 1,
1013
1014 .supports_aspm = true,
1015 },
1016 {
1017 .name = "qcn9274 hw2.0",
1018 .hw_rev = ATH12K_HW_QCN9274_HW20,
1019 .fw = {
1020 .dir = "QCN9274/hw2.0",
1021 .board_size = 256 * 1024,
1022 .cal_offset = 128 * 1024,
1023 },
1024 .max_radios = 2,
1025 .single_pdev_only = false,
1026 .qmi_service_ins_id = ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9274,
1027 .internal_sleep_clock = false,
1028
1029 .hw_ops = &qcn9274_ops,
1030 .ring_mask = &ath12k_hw_ring_mask_qcn9274,
1031 .regs = &qcn9274_v2_regs,
1032
1033 .host_ce_config = ath12k_host_ce_config_qcn9274,
1034 .ce_count = 16,
1035 .target_ce_config = ath12k_target_ce_config_wlan_qcn9274,
1036 .target_ce_count = 12,
1037 .svc_to_ce_map = ath12k_target_service_to_ce_map_wlan_qcn9274,
1038 .svc_to_ce_map_len = 18,
1039
1040 .hal_params = &ath12k_hw_hal_params_qcn9274,
1041
1042 .rxdma1_enable = true,
1043 .num_rxdma_per_pdev = 1,
1044 .num_rxdma_dst_ring = 0,
1045 .rx_mac_buf_ring = false,
1046 .vdev_start_delay = false,
1047
1048 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
1049 BIT(NL80211_IFTYPE_AP) |
1050 BIT(NL80211_IFTYPE_MESH_POINT) |
1051 BIT(NL80211_IFTYPE_AP_VLAN),
1052 .supports_monitor = false,
1053
1054 .idle_ps = false,
1055 .download_calib = true,
1056 .supports_suspend = false,
1057 .tcl_ring_retry = true,
1058 .reoq_lut_support = false,
1059 .supports_shadow_regs = false,
1060
1061 .num_tcl_banks = 48,
1062 .max_tx_ring = 4,
1063
1064 .mhi_config = &ath12k_mhi_config_qcn9274,
1065
1066 .wmi_init = ath12k_wmi_init_qcn9274,
1067
1068 .hal_ops = &hal_qcn9274_ops,
1069
1070 .qmi_cnss_feature_bitmap = BIT(CNSS_QDSS_CFG_MISS_V01),
1071
1072 .rfkill_pin = 0,
1073 .rfkill_cfg = 0,
1074 .rfkill_on_level = 0,
1075
1076 .rddm_size = 0x600000,
1077
1078 .def_num_link = 0,
1079 .max_mlo_peer = 256,
1080
1081 .otp_board_id_register = QCN9274_QFPROM_RAW_RFA_PDET_ROW13_LSB,
1082
1083 .supports_sta_ps = false,
1084
1085 .acpi_guid = NULL,
1086 .supports_dynamic_smps_6ghz = true,
1087
1088 .iova_mask = 0,
1089
1090 .supports_aspm = false,
1091 },
1092 };
1093
ath12k_hw_init(struct ath12k_base * ab)1094 int ath12k_hw_init(struct ath12k_base *ab)
1095 {
1096 const struct ath12k_hw_params *hw_params = NULL;
1097 int i;
1098
1099 for (i = 0; i < ARRAY_SIZE(ath12k_hw_params); i++) {
1100 hw_params = &ath12k_hw_params[i];
1101
1102 if (hw_params->hw_rev == ab->hw_rev)
1103 break;
1104 }
1105
1106 if (i == ARRAY_SIZE(ath12k_hw_params)) {
1107 ath12k_err(ab, "Unsupported hardware version: 0x%x\n", ab->hw_rev);
1108 return -EINVAL;
1109 }
1110
1111 ab->hw_params = hw_params;
1112
1113 ath12k_info(ab, "Hardware name: %s\n", ab->hw_params->name);
1114
1115 return 0;
1116 }
1117