1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 #define AT803X_SPECIFIC_FUNCTION_CONTROL 0x10 4 #define AT803X_SFC_ASSERT_CRS BIT(11) 5 #define AT803X_SFC_FORCE_LINK BIT(10) 6 #define AT803X_SFC_MDI_CROSSOVER_MODE_M GENMASK(6, 5) 7 #define AT803X_SFC_AUTOMATIC_CROSSOVER 0x3 8 #define AT803X_SFC_MANUAL_MDIX 0x1 9 #define AT803X_SFC_MANUAL_MDI 0x0 10 #define AT803X_SFC_SQE_TEST BIT(2) 11 #define AT803X_SFC_POLARITY_REVERSAL BIT(1) 12 #define AT803X_SFC_DISABLE_JABBER BIT(0) 13 14 #define AT803X_SPECIFIC_STATUS 0x11 15 #define AT803X_SS_SPEED_MASK GENMASK(15, 14) 16 #define AT803X_SS_SPEED_1000 2 17 #define AT803X_SS_SPEED_100 1 18 #define AT803X_SS_SPEED_10 0 19 #define AT803X_SS_DUPLEX BIT(13) 20 #define AT803X_SS_SPEED_DUPLEX_RESOLVED BIT(11) 21 #define AT803X_SS_MDIX BIT(6) 22 23 #define QCA808X_SS_SPEED_MASK GENMASK(9, 7) 24 #define QCA808X_SS_SPEED_2500 4 25 26 #define AT803X_INTR_ENABLE 0x12 27 #define AT803X_INTR_ENABLE_AUTONEG_ERR BIT(15) 28 #define AT803X_INTR_ENABLE_SPEED_CHANGED BIT(14) 29 #define AT803X_INTR_ENABLE_DUPLEX_CHANGED BIT(13) 30 #define AT803X_INTR_ENABLE_PAGE_RECEIVED BIT(12) 31 #define AT803X_INTR_ENABLE_LINK_FAIL BIT(11) 32 #define AT803X_INTR_ENABLE_LINK_SUCCESS BIT(10) 33 #define AT803X_INTR_ENABLE_LINK_FAIL_BX BIT(8) 34 #define AT803X_INTR_ENABLE_LINK_SUCCESS_BX BIT(7) 35 #define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE BIT(5) 36 #define AT803X_INTR_ENABLE_POLARITY_CHANGED BIT(1) 37 #define AT803X_INTR_ENABLE_WOL BIT(0) 38 39 #define AT803X_INTR_STATUS 0x13 40 41 #define AT803X_SMART_SPEED 0x14 42 #define AT803X_SMART_SPEED_ENABLE BIT(5) 43 #define AT803X_SMART_SPEED_RETRY_LIMIT_MASK GENMASK(4, 2) 44 #define AT803X_SMART_SPEED_BYPASS_TIMER BIT(1) 45 46 #define AT803X_CDT 0x16 47 #define AT803X_CDT_MDI_PAIR_MASK GENMASK(9, 8) 48 #define AT803X_CDT_ENABLE_TEST BIT(0) 49 #define AT803X_CDT_STATUS 0x1c 50 #define AT803X_CDT_STATUS_STAT_NORMAL 0 51 #define AT803X_CDT_STATUS_STAT_SHORT 1 52 #define AT803X_CDT_STATUS_STAT_OPEN 2 53 #define AT803X_CDT_STATUS_STAT_FAIL 3 54 #define AT803X_CDT_STATUS_STAT_MASK GENMASK(9, 8) 55 #define AT803X_CDT_STATUS_DELTA_TIME_MASK GENMASK(7, 0) 56 57 #define QCA808X_CDT_ENABLE_TEST BIT(15) 58 #define QCA808X_CDT_INTER_CHECK_DIS BIT(13) 59 #define QCA808X_CDT_STATUS BIT(11) 60 #define QCA808X_CDT_LENGTH_UNIT BIT(10) 61 62 #define QCA808X_MMD3_CDT_STATUS 0x8064 63 #define QCA808X_MMD3_CDT_DIAG_PAIR_A 0x8065 64 #define QCA808X_MMD3_CDT_DIAG_PAIR_B 0x8066 65 #define QCA808X_MMD3_CDT_DIAG_PAIR_C 0x8067 66 #define QCA808X_MMD3_CDT_DIAG_PAIR_D 0x8068 67 #define QCA808X_CDT_DIAG_LENGTH_SAME_SHORT GENMASK(15, 8) 68 #define QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT GENMASK(7, 0) 69 70 #define QCA808X_CDT_CODE_PAIR_A GENMASK(15, 12) 71 #define QCA808X_CDT_CODE_PAIR_B GENMASK(11, 8) 72 #define QCA808X_CDT_CODE_PAIR_C GENMASK(7, 4) 73 #define QCA808X_CDT_CODE_PAIR_D GENMASK(3, 0) 74 75 #define QCA808X_CDT_STATUS_STAT_TYPE GENMASK(1, 0) 76 #define QCA808X_CDT_STATUS_STAT_FAIL FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 0) 77 #define QCA808X_CDT_STATUS_STAT_NORMAL FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 1) 78 #define QCA808X_CDT_STATUS_STAT_SAME_OPEN FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 2) 79 #define QCA808X_CDT_STATUS_STAT_SAME_SHORT FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 3) 80 81 #define QCA808X_CDT_STATUS_STAT_MDI GENMASK(3, 2) 82 #define QCA808X_CDT_STATUS_STAT_MDI1 FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 1) 83 #define QCA808X_CDT_STATUS_STAT_MDI2 FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 2) 84 #define QCA808X_CDT_STATUS_STAT_MDI3 FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 3) 85 86 /* NORMAL are MDI with type set to 0 */ 87 #define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL QCA808X_CDT_STATUS_STAT_MDI1 88 #define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN (QCA808X_CDT_STATUS_STAT_SAME_OPEN |\ 89 QCA808X_CDT_STATUS_STAT_MDI1) 90 #define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT (QCA808X_CDT_STATUS_STAT_SAME_SHORT |\ 91 QCA808X_CDT_STATUS_STAT_MDI1) 92 #define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL QCA808X_CDT_STATUS_STAT_MDI2 93 #define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN (QCA808X_CDT_STATUS_STAT_SAME_OPEN |\ 94 QCA808X_CDT_STATUS_STAT_MDI2) 95 #define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT (QCA808X_CDT_STATUS_STAT_SAME_SHORT |\ 96 QCA808X_CDT_STATUS_STAT_MDI2) 97 #define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL QCA808X_CDT_STATUS_STAT_MDI3 98 #define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN (QCA808X_CDT_STATUS_STAT_SAME_OPEN |\ 99 QCA808X_CDT_STATUS_STAT_MDI3) 100 #define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT (QCA808X_CDT_STATUS_STAT_SAME_SHORT |\ 101 QCA808X_CDT_STATUS_STAT_MDI3) 102 103 /* Added for reference of existence but should be handled by wait_for_completion already */ 104 #define QCA808X_CDT_STATUS_STAT_BUSY (BIT(1) | BIT(3)) 105 106 #define QCA808X_MMD7_LED_GLOBAL 0x8073 107 #define QCA808X_LED_BLINK_1 GENMASK(11, 6) 108 #define QCA808X_LED_BLINK_2 GENMASK(5, 0) 109 /* Values are the same for both BLINK_1 and BLINK_2 */ 110 #define QCA808X_LED_BLINK_FREQ_MASK GENMASK(5, 3) 111 #define QCA808X_LED_BLINK_FREQ_2HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x0) 112 #define QCA808X_LED_BLINK_FREQ_4HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x1) 113 #define QCA808X_LED_BLINK_FREQ_8HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x2) 114 #define QCA808X_LED_BLINK_FREQ_16HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x3) 115 #define QCA808X_LED_BLINK_FREQ_32HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x4) 116 #define QCA808X_LED_BLINK_FREQ_64HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x5) 117 #define QCA808X_LED_BLINK_FREQ_128HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x6) 118 #define QCA808X_LED_BLINK_FREQ_256HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x7) 119 #define QCA808X_LED_BLINK_DUTY_MASK GENMASK(2, 0) 120 #define QCA808X_LED_BLINK_DUTY_50_50 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x0) 121 #define QCA808X_LED_BLINK_DUTY_75_25 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x1) 122 #define QCA808X_LED_BLINK_DUTY_25_75 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x2) 123 #define QCA808X_LED_BLINK_DUTY_33_67 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x3) 124 #define QCA808X_LED_BLINK_DUTY_67_33 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x4) 125 #define QCA808X_LED_BLINK_DUTY_17_83 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x5) 126 #define QCA808X_LED_BLINK_DUTY_83_17 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x6) 127 #define QCA808X_LED_BLINK_DUTY_8_92 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x7) 128 129 /* LED hw control pattern is the same for every LED */ 130 #define QCA808X_LED_PATTERN_MASK GENMASK(15, 0) 131 #define QCA808X_LED_SPEED2500_ON BIT(15) 132 #define QCA808X_LED_SPEED2500_BLINK BIT(14) 133 /* Follow blink trigger even if duplex or speed condition doesn't match */ 134 #define QCA808X_LED_BLINK_CHECK_BYPASS BIT(13) 135 #define QCA808X_LED_FULL_DUPLEX_ON BIT(12) 136 #define QCA808X_LED_HALF_DUPLEX_ON BIT(11) 137 #define QCA808X_LED_TX_BLINK BIT(10) 138 #define QCA808X_LED_RX_BLINK BIT(9) 139 #define QCA808X_LED_TX_ON_10MS BIT(8) 140 #define QCA808X_LED_RX_ON_10MS BIT(7) 141 #define QCA808X_LED_SPEED1000_ON BIT(6) 142 #define QCA808X_LED_SPEED100_ON BIT(5) 143 #define QCA808X_LED_SPEED10_ON BIT(4) 144 #define QCA808X_LED_COLLISION_BLINK BIT(3) 145 #define QCA808X_LED_SPEED1000_BLINK BIT(2) 146 #define QCA808X_LED_SPEED100_BLINK BIT(1) 147 #define QCA808X_LED_SPEED10_BLINK BIT(0) 148 149 /* LED force ctrl is the same for every LED 150 * No documentation exist for this, not even internal one 151 * with NDA as QCOM gives only info about configuring 152 * hw control pattern rules and doesn't indicate any way 153 * to force the LED to specific mode. 154 * These define comes from reverse and testing and maybe 155 * lack of some info or some info are not entirely correct. 156 * For the basic LED control and hw control these finding 157 * are enough to support LED control in all the required APIs. 158 * 159 * On doing some comparison with implementation with qca807x, 160 * it was found that it's 1:1 equal to it and confirms all the 161 * reverse done. It was also found further specification with the 162 * force mode and the blink modes. 163 */ 164 #define QCA808X_LED_FORCE_EN BIT(15) 165 #define QCA808X_LED_FORCE_MODE_MASK GENMASK(14, 13) 166 #define QCA808X_LED_FORCE_BLINK_1 FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x3) 167 #define QCA808X_LED_FORCE_BLINK_2 FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x2) 168 #define QCA808X_LED_FORCE_ON FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x1) 169 #define QCA808X_LED_FORCE_OFF FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x0) 170 171 #define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C 172 #define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B 173 #define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A 174 175 #define AT803X_PHY_MMD3_WOL_CTRL 0x8012 176 #define AT803X_WOL_EN BIT(5) 177 178 #define AT803X_DEBUG_ADDR 0x1D 179 #define AT803X_DEBUG_DATA 0x1E 180 181 #define AT803X_DEBUG_ANALOG_TEST_CTRL 0x00 182 #define QCA8327_DEBUG_MANU_CTRL_EN BIT(2) 183 #define QCA8337_DEBUG_MANU_CTRL_EN GENMASK(3, 2) 184 #define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15) 185 186 #define AT803X_DEBUG_SYSTEM_CTRL_MODE 0x05 187 #define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8) 188 189 #define AT803X_DEBUG_REG_HIB_CTRL 0x0b 190 #define AT803X_DEBUG_HIB_CTRL_SEL_RST_80U BIT(10) 191 #define AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE BIT(13) 192 #define AT803X_DEBUG_HIB_CTRL_PS_HIB_EN BIT(15) 193 194 #define AT803X_DEFAULT_DOWNSHIFT 5 195 #define AT803X_MIN_DOWNSHIFT 2 196 #define AT803X_MAX_DOWNSHIFT 9 197 198 enum stat_access_type { 199 PHY, 200 MMD 201 }; 202 203 struct at803x_hw_stat { 204 const char *string; 205 u8 reg; 206 u32 mask; 207 enum stat_access_type access_type; 208 }; 209 210 struct at803x_ss_mask { 211 u16 speed_mask; 212 u8 speed_shift; 213 }; 214 215 int at803x_debug_reg_read(struct phy_device *phydev, u16 reg); 216 int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg, 217 u16 clear, u16 set); 218 int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data); 219 int at803x_set_wol(struct phy_device *phydev, 220 struct ethtool_wolinfo *wol); 221 int at8031_set_wol(struct phy_device *phydev, 222 struct ethtool_wolinfo *wol); 223 void at803x_get_wol(struct phy_device *phydev, 224 struct ethtool_wolinfo *wol); 225 int at803x_ack_interrupt(struct phy_device *phydev); 226 int at803x_config_intr(struct phy_device *phydev); 227 irqreturn_t at803x_handle_interrupt(struct phy_device *phydev); 228 int at803x_read_specific_status(struct phy_device *phydev, 229 struct at803x_ss_mask ss_mask); 230 int at803x_config_mdix(struct phy_device *phydev, u8 ctrl); 231 int at803x_prepare_config_aneg(struct phy_device *phydev); 232 int at803x_read_status(struct phy_device *phydev); 233 int at803x_get_tunable(struct phy_device *phydev, 234 struct ethtool_tunable *tuna, void *data); 235 int at803x_set_tunable(struct phy_device *phydev, 236 struct ethtool_tunable *tuna, const void *data); 237 int at803x_cdt_fault_length(int dt); 238 int at803x_cdt_start(struct phy_device *phydev, u32 cdt_start); 239 int at803x_cdt_wait_for_completion(struct phy_device *phydev, 240 u32 cdt_en); 241 int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finished); 242 int qca808x_led_reg_hw_control_enable(struct phy_device *phydev, u16 reg); 243 bool qca808x_led_reg_hw_control_status(struct phy_device *phydev, u16 reg); 244 int qca808x_led_reg_brightness_set(struct phy_device *phydev, 245 u16 reg, enum led_brightness value); 246 int qca808x_led_reg_blink_set(struct phy_device *phydev, u16 reg, 247 unsigned long *delay_on, 248 unsigned long *delay_off); 249