1 /* SPDX-License-Identifier: MIT */ 2 3 #ifndef __AST_REG_H__ 4 #define __AST_REG_H__ 5 6 #include <linux/bits.h> 7 8 /* 9 * Modesetting 10 */ 11 12 #define AST_IO_MM_OFFSET (0x380) 13 #define AST_IO_MM_LENGTH (128) 14 15 #define AST_IO_VGAARI_W (0x40) 16 17 #define AST_IO_VGAMR_W (0x42) 18 #define AST_IO_VGAMR_R (0x4c) 19 #define AST_IO_VGAMR_IOSEL BIT(0) 20 21 #define AST_IO_VGAER (0x43) 22 #define AST_IO_VGAER_VGA_ENABLE BIT(0) 23 24 #define AST_IO_VGASRI (0x44) 25 #define AST_IO_VGASR1_SD BIT(5) 26 #define AST_IO_VGADRR (0x47) 27 #define AST_IO_VGADWR (0x48) 28 #define AST_IO_VGAPDR (0x49) 29 #define AST_IO_VGAGRI (0x4E) 30 31 #define AST_IO_VGACRI (0x54) 32 #define AST_IO_VGACR17_SYNC_ENABLE BIT(7) /* called "Hardware reset" in docs */ 33 #define AST_IO_VGACR80_PASSWORD (0xa8) 34 35 #define AST_IO_VGACR8C_NEW_MODE_MASK GENMASK(3, 0) 36 #define AST_IO_VGACR8C_NEW_MODE_EGA (0x00) 37 #define AST_IO_VGACR8C_NEW_MODE_VGA (0x01) 38 #define AST_IO_VGACR8C_NEW_MODE_15_BPP (0x02) 39 #define AST_IO_VGACR8C_NEW_MODE_16_BPP (0x03) 40 #define AST_IO_VGACR8C_NEW_MODE_32_BPP (0x04) 41 #define AST_IO_VGACR8C_NEW_MODE_CGA (0x0f) 42 #define AST_IO_VGACR8C_NEW_MODE_TEXT (0x0e) 43 #define AST_IO_VGACR8C_CUR_MODE_MASK GENMASK(7, 4) 44 #define AST_IO_VGACR8C_CUR_MODE_EGA (0x00) 45 #define AST_IO_VGACR8C_CUR_MODE_VGA (0x10) 46 #define AST_IO_VGACR8C_CUR_MODE_15_BPP (0x20) 47 #define AST_IO_VGACR8C_CUR_MODE_16_BPP (0x30) 48 #define AST_IO_VGACR8C_CUR_MODE_32_BPP (0x40) 49 #define AST_IO_VGACR8C_CUR_MODE_CGA (0xf0) 50 #define AST_IO_VGACR8C_CUR_MODE_TEXT (0xe0) 51 52 #define AST_IO_VGACR91_PASSWORD (0xa8) 53 #define AST_IO_VGACR99_VGAMEM_RSRV_MASK GENMASK(1, 0) 54 55 #define AST_IO_VGACRA0_MEMORY_CHAIN4_MODE BIT(6) 56 #define AST_IO_VGACRA0_LINEAR_EXT_ACCESS BIT(5) 57 #define AST_IO_VGACRA0_SEGMENTED_EXT_ACCESS BIT(4) 58 59 #define AST_IO_VGACRA1_VGAIO_DISABLED BIT(1) 60 #define AST_IO_VGACRA1_MMIO_ENABLED BIT(2) 61 62 #define AST_IO_VGACRA3_DVO_ENABLED BIT(7) 63 #define AST_IO_VGACRA3_32_BPP BIT(3) 64 #define AST_IO_VGACRA3_16_BPP BIT(2) 65 #define AST_IO_VGACRA3_15_BPP BIT(1) 66 #define AST_IO_VGACRA3_256_COLORS BIT(0) 67 68 #define AST_IO_VGACRA8_GAMMA_CORRECTION_ENABLED BIT(1) 69 #define AST_IO_VGACRAA_VGAMEM_SIZE_MASK GENMASK(1, 0) 70 #define AST_IO_VGACRB6_HSYNC_OFF BIT(0) 71 #define AST_IO_VGACRB6_VSYNC_OFF BIT(1) 72 #define AST_IO_VGACRCB_HWC_16BPP BIT(0) /* set: ARGB4444, cleared: 2bpp palette */ 73 #define AST_IO_VGACRCB_HWC_ENABLED BIT(1) 74 75 /* mirrors SCU100[7:0] */ 76 #define AST_IO_VGACRD0_VRAM_INIT_STATUS_MASK GENMASK(7, 6) 77 #define AST_IO_VGACRD0_VRAM_INIT_BY_BMC BIT(7) 78 #define AST_IO_VGACRD0_VRAM_INIT_READY BIT(6) 79 #define AST_IO_VGACRD0_IKVM_WIDESCREEN BIT(0) 80 81 #define AST_IO_VGACRD1_MCU_FW_EXECUTING BIT(5) 82 /* Display Transmitter Type */ 83 #define AST_IO_VGACRD1_TX_TYPE_MASK GENMASK(3, 1) 84 #define AST_IO_VGACRD1_NO_TX 0x00 85 #define AST_IO_VGACRD1_TX_ITE66121_VBIOS 0x02 86 #define AST_IO_VGACRD1_TX_SIL164_VBIOS 0x04 87 #define AST_IO_VGACRD1_TX_CH7003_VBIOS 0x06 88 #define AST_IO_VGACRD1_TX_DP501_VBIOS 0x08 89 #define AST_IO_VGACRD1_TX_ANX9807_VBIOS 0x0a 90 #define AST_IO_VGACRD1_TX_FW_EMBEDDED_FW 0x0c /* special case of DP501 */ 91 #define AST_IO_VGACRD1_TX_ASTDP 0x0e 92 #define AST_IO_VGACRD1_SUPPORTS_WUXGA BIT(0) 93 94 /* 95 * AST DisplayPort 96 */ 97 #define AST_IO_VGACRD7_EDID_VALID_FLAG BIT(0) 98 #define AST_IO_VGACRDC_LINK_SUCCESS BIT(0) 99 #define AST_IO_VGACRDF_HPD BIT(0) 100 #define AST_IO_VGACRDF_DP_VIDEO_ENABLE BIT(4) /* mirrors AST_IO_VGACRE3_DP_VIDEO_ENABLE */ 101 #define AST_IO_VGACRE0_24BPP BIT(5) /* 18 bpp, if unset */ 102 #define AST_IO_VGACRE3_DP_VIDEO_ENABLE BIT(0) 103 #define AST_IO_VGACRE3_DP_PHY_SLEEP BIT(4) 104 #define AST_IO_VGACRE5_EDID_READ_DONE BIT(0) 105 106 #define AST_IO_VGAIR1_R (0x5A) 107 #define AST_IO_VGAIR1_VREFRESH BIT(3) 108 109 /* 110 * P-Bus to AHB Bridge (0x00000000 - 0x0001ffff) 111 */ 112 113 #define AST_REG_P2A_BASE (0x00000000) 114 #define AST_REG_P2A(__offset) (AST_REG_P2A_BASE + (__offset)) 115 #define AST_REG_P2A_ADDR(__addr) AST_REG_P2A(0x10000 + ((__addr) & GENMASK(15, 0))) 116 #define AST_REG_P2A00 AST_REG_P2A(0xf000) 117 #define AST_REG_P2A00_PROTECTION_KEY (0x01) 118 #define AST_REG_P2A04 AST_REG_P2A(0xf004) 119 #define AST_REG_P2A04_BASE_MASK GENMASK(31, 16) 120 121 /* 122 * AHB Controller (0x1e600000 - 0x1e61ffff) 123 */ 124 125 #define AST_REG_AHBC_BASE (0x1e600000) 126 #define AST_REG_AHBC(__offset) (AST_REG_AHBC_BASE + (__offset)) 127 #define AST_REG_AHBC00 AST_REG_AHBC(0x00) 128 #define AST_REG_AHBC00_PROTECT_KEY (0xaeed1a03) 129 #define AST_REG_AHBC84 AST_REG_AHBC(0x84) 130 #define AST_REG_AHBC88 AST_REG_AHBC(0x88) 131 132 /* 133 * SDRAM Memory Controller (0x1e6e0000 - 0x1e6e0fff) 134 */ 135 136 #define AST_REG_MCR_BASE (0x1e6e0000) 137 #define AST_REG_MCR(__offset) (AST_REG_MCR_BASE + (__offset)) 138 #define AST_REG_MCR00 AST_REG_MCR(0x00) 139 #define AST_REG_MCR00_PROTECTION_KEY (0xfc600309) 140 #define AST_REG_MCR04 AST_REG_MCR(0x04) 141 #define AST_REG_MCR08 AST_REG_MCR(0x08) 142 #define AST_REG_MCR0C AST_REG_MCR(0x0c) 143 #define AST_REG_MCR10 AST_REG_MCR(0x10) 144 #define AST_REG_MCR14 AST_REG_MCR(0x14) 145 #define AST_REG_MCR18 AST_REG_MCR(0x18) 146 #define AST_REG_MCR1C AST_REG_MCR(0x1c) 147 #define AST_REG_MCR20 AST_REG_MCR(0x20) 148 #define AST_REG_MCR24 AST_REG_MCR(0x24) 149 #define AST_REG_MCR28 AST_REG_MCR(0x28) 150 #define AST_REG_MCR2C AST_REG_MCR(0x2C) 151 #define AST_REG_MCR30 AST_REG_MCR(0x30) 152 #define AST_REG_MCR34 AST_REG_MCR(0x34) 153 #define AST_REG_MCR38 AST_REG_MCR(0x38) 154 #define AST_REG_MCR3C AST_REG_MCR(0x3c) 155 #define AST_REG_MCR40 AST_REG_MCR(0x40) 156 #define AST_REG_MCR44 AST_REG_MCR(0x44) 157 #define AST_REG_MCR48 AST_REG_MCR(0x48) 158 #define AST_REG_MCR4C AST_REG_MCR(0x4C) 159 #define AST_REG_MCR50 AST_REG_MCR(0x50) 160 #define AST_REG_MCR54 AST_REG_MCR(0x54) 161 #define AST_REG_MCR58 AST_REG_MCR(0x58) 162 #define AST_REG_MCR5C AST_REG_MCR(0x5c) 163 #define AST_REG_MCR60 AST_REG_MCR(0x60) 164 #define AST_REG_MCR64 AST_REG_MCR(0x64) 165 #define AST_REG_MCR68 AST_REG_MCR(0x68) 166 #define AST_REG_MCR6C AST_REG_MCR(0x6c) 167 #define AST_REG_MCR70 AST_REG_MCR(0x70) 168 #define AST_REG_MCR74 AST_REG_MCR(0x74) 169 #define AST_REG_MCR78 AST_REG_MCR(0x78) 170 #define AST_REG_MCR7C AST_REG_MCR(0x7c) 171 #define AST_REG_MCR80 AST_REG_MCR(0x80) 172 #define AST_REG_MCR84 AST_REG_MCR(0x84) 173 #define AST_REG_MCR88 AST_REG_MCR(0x88) 174 #define AST_REG_MCR8C AST_REG_MCR(0x8c) 175 #define AST_REG_MCR100 AST_REG_MCR(0x100) 176 #define AST_REG_MCR108 AST_REG_MCR(0x108) 177 #define AST_REG_MCR120 AST_REG_MCR(0x120) 178 #define AST_REG_MCR140 AST_REG_MCR(0x140) 179 #define AST_REG_MCR200 AST_REG_MCR(0x200) 180 #define AST_REG_MCR204 AST_REG_MCR(0x204) 181 #define AST_REG_MCR208 AST_REG_MCR(0x208) 182 #define AST_REG_MCR20C AST_REG_MCR(0x20C) 183 #define AST_REG_MCR210 AST_REG_MCR(0x210) 184 #define AST_REG_MCR214 AST_REG_MCR(0x214) 185 #define AST_REG_MCR218 AST_REG_MCR(0x218) 186 #define AST_REG_MCR220 AST_REG_MCR(0x220) 187 #define AST_REG_MCR228 AST_REG_MCR(0x228) 188 #define AST_REG_MCR230 AST_REG_MCR(0x230) 189 #define AST_REG_MCR2A8 AST_REG_MCR(0x2a8) 190 #define AST_REG_MCR2B0 AST_REG_MCR(0x2b0) 191 #define AST_REG_MCR240 AST_REG_MCR(0x240) 192 #define AST_REG_MCR244 AST_REG_MCR(0x244) 193 #define AST_REG_MCR248 AST_REG_MCR(0x248) 194 #define AST_REG_MCR24C AST_REG_MCR(0x24c) 195 #define AST_REG_MCR290 AST_REG_MCR(0x290) 196 #define AST_REG_MCR2C0 AST_REG_MCR(0x2c0) 197 #define AST_REG_MCR2C4 AST_REG_MCR(0x2c4) 198 #define AST_REG_MCR2C8 AST_REG_MCR(0x2c8) 199 #define AST_REG_MCR2CC AST_REG_MCR(0x2cc) 200 #define AST_REG_MCR2E0 AST_REG_MCR(0x2e0) 201 #define AST_REG_MCR2E4 AST_REG_MCR(0x2e4) 202 #define AST_REG_MCR2E8 AST_REG_MCR(0x2e8) 203 #define AST_REG_MCR2EC AST_REG_MCR(0x2ec) 204 #define AST_REG_MCR2F0 AST_REG_MCR(0x2f0) 205 #define AST_REG_MCR2F4 AST_REG_MCR(0x2f4) 206 #define AST_REG_MCR2F8 AST_REG_MCR(0x2f8) 207 #define AST_REG_MCR300 AST_REG_MCR(0x300) 208 #define AST_REG_MCR3D0 AST_REG_MCR(0x3d0) 209 210 /* 211 * System Control Unit (0x1e6e2000 - 0x1e6e2fff) 212 */ 213 214 #define AST_REG_SCU_BASE (0x1e6e2000) 215 #define AST_REG_SCU(__offset) (AST_REG_SCU_BASE + (__offset)) 216 #define AST_REG_SCU000 AST_REG_SCU(0x000) 217 #define AST_REG_SCU000_PROTECTION_KEY (0x1688a8a8) 218 #define AST_REG_SCU008 AST_REG_SCU(0x008) 219 #define AST_REG_SCU00C AST_REG_SCU(0x00c) 220 #define AST_REG_SCU020 AST_REG_SCU(0x020) 221 #define AST_REG_SCU02C AST_REG_SCU(0x02c) 222 #define AST_REG_SCU040 AST_REG_SCU(0x040) 223 #define AST_REG_SCU070 AST_REG_SCU(0x070) 224 #define AST_REG_SCU07C AST_REG_SCU(0x07c) 225 #define AST_REG_SCU07C_CHIP_BONDING_MASK GENMASK(15, 8) 226 #define AST_REG_SCU084 AST_REG_SCU(0x084) 227 #define AST_REG_SCU088 AST_REG_SCU(0x088) 228 #define AST_REG_SCU08C AST_REG_SCU(0x08c) 229 #define AST_REG_SCU090 AST_REG_SCU(0x090) 230 #define AST_REG_SCU094 AST_REG_SCU(0x094) 231 #define AST_REG_SCU0A4 AST_REG_SCU(0x0a4) 232 #define AST_REG_SCU0A8 AST_REG_SCU(0x0a8) 233 #define AST_REG_SCU100 AST_REG_SCU(0x100) 234 #define AST_REG_SCU104 AST_REG_SCU(0x104) 235 #define AST_REG_SCU160 AST_REG_SCU(0x160) 236 237 /* 238 * AHB-to-P Bus Bridge (0x1e720000 - 0x1e73ffff) 239 */ 240 241 #define AST_REG_A2P_BASE (0x1e720000) 242 #define AST_REG_A2P(__offset) (AST_REG_A2P_BASE + (__offset)) 243 #define AST_REG_A2P58 AST_REG_A2P(0x58) 244 245 /* 246 * Watchdog timer (0x1e785000 - 0x1e785fff) 247 */ 248 249 #define AST_REG_WDT_BASE(__n) (0x1e785000 + (__n) * 0x40) 250 #define AST_REG_WDT(__n, __offset) (AST_REG_WDT_BASE((__n)) + (__offset)) 251 #define AST_REG_WDT04(__n) AST_REG_WDT((__n), 0x04) 252 #define AST_REG_WDT08(__n) AST_REG_WDT((__n), 0x08) 253 #define AST_REG_WDT0C(__n) AST_REG_WDT((__n), 0x0c) 254 #define AST_REG_WDT14(__n) AST_REG_WDT((__n), 0x14) 255 #define AST_REG_WDT1C(__n) AST_REG_WDT((__n), 0x1c) 256 #define AST_REG_WDT2C(__n) AST_REG_WDT((__n), 0x2c) 257 258 /* 259 * SDRAM (0x80000000 - 0xffffffff) 260 */ 261 262 #define AST_SDRAM_BASE (0x80000000) 263 #define AST_SDRAM(__offset) (AST_SDRAM_BASE + (__offset)) 264 265 #endif 266