xref: /linux/drivers/gpu/drm/ast/ast_reg.h (revision 3fd6c59042dbba50391e30862beac979491145fe)
1 /* SPDX-License-Identifier: MIT */
2 
3 #ifndef __AST_REG_H__
4 #define __AST_REG_H__
5 
6 #include <linux/bits.h>
7 
8 /*
9  * Modesetting
10  */
11 
12 #define AST_IO_MM_OFFSET		(0x380)
13 #define AST_IO_MM_LENGTH		(128)
14 
15 #define AST_IO_VGAARI_W			(0x40)
16 
17 #define AST_IO_VGAMR_W			(0x42)
18 #define AST_IO_VGAMR_R			(0x4c)
19 #define AST_IO_VGAMR_IOSEL		BIT(0)
20 
21 #define AST_IO_VGAER			(0x43)
22 #define AST_IO_VGAER_VGA_ENABLE		BIT(0)
23 
24 #define AST_IO_VGASRI			(0x44)
25 #define AST_IO_VGASR1_SD		BIT(5)
26 #define AST_IO_VGADRR			(0x47)
27 #define AST_IO_VGADWR			(0x48)
28 #define AST_IO_VGAPDR		        (0x49)
29 #define AST_IO_VGAGRI			(0x4E)
30 
31 #define AST_IO_VGACRI			(0x54)
32 #define AST_IO_VGACR80_PASSWORD		(0xa8)
33 #define AST_IO_VGACRA1_VGAIO_DISABLED	BIT(1)
34 #define AST_IO_VGACRA1_MMIO_ENABLED	BIT(2)
35 #define AST_IO_VGACRB6_HSYNC_OFF	BIT(0)
36 #define AST_IO_VGACRB6_VSYNC_OFF	BIT(1)
37 #define AST_IO_VGACRCB_HWC_16BPP	BIT(0) /* set: ARGB4444, cleared: 2bpp palette */
38 #define AST_IO_VGACRCB_HWC_ENABLED	BIT(1)
39 
40 #define AST_IO_VGACRD1_MCU_FW_EXECUTING		BIT(5)
41 /* Display Transmitter Type */
42 #define AST_IO_VGACRD1_TX_TYPE_MASK		GENMASK(3, 1)
43 #define AST_IO_VGACRD1_NO_TX			0x00
44 #define AST_IO_VGACRD1_TX_ITE66121_VBIOS	0x02
45 #define AST_IO_VGACRD1_TX_SIL164_VBIOS		0x04
46 #define AST_IO_VGACRD1_TX_CH7003_VBIOS		0x06
47 #define AST_IO_VGACRD1_TX_DP501_VBIOS		0x08
48 #define AST_IO_VGACRD1_TX_ANX9807_VBIOS		0x0a
49 #define AST_IO_VGACRD1_TX_FW_EMBEDDED_FW	0x0c /* special case of DP501 */
50 #define AST_IO_VGACRD1_TX_ASTDP			0x0e
51 
52 #define AST_IO_VGACRD7_EDID_VALID_FLAG	BIT(0)
53 #define AST_IO_VGACRDC_LINK_SUCCESS	BIT(0)
54 #define AST_IO_VGACRDF_HPD		BIT(0)
55 #define AST_IO_VGACRDF_DP_VIDEO_ENABLE	BIT(4) /* mirrors AST_IO_VGACRE3_DP_VIDEO_ENABLE */
56 #define AST_IO_VGACRE3_DP_VIDEO_ENABLE	BIT(0)
57 #define AST_IO_VGACRE3_DP_PHY_SLEEP	BIT(4)
58 #define AST_IO_VGACRE5_EDID_READ_DONE	BIT(0)
59 
60 #define AST_IO_VGAIR1_R			(0x5A)
61 #define AST_IO_VGAIR1_VREFRESH		BIT(3)
62 
63 
64 #define AST_VRAM_INIT_STATUS_MASK	GENMASK(7, 6)
65 //#define AST_VRAM_INIT_BY_BMC		BIT(7)
66 //#define AST_VRAM_INIT_READY		BIT(6)
67 
68 /*
69  * AST DisplayPort
70  */
71 
72 /*
73  * ASTDP setmode registers:
74  * CRE0[7:0]: MISC0 ((0x00: 18-bpp) or (0x20: 24-bpp)
75  * CRE1[7:0]: MISC1 (default: 0x00)
76  * CRE2[7:0]: video format index (0x00 ~ 0x20 or 0x40 ~ 0x50)
77  */
78 #define ASTDP_MISC0_24bpp		BIT(5)
79 #define ASTDP_MISC1			0
80 #define ASTDP_AND_CLEAR_MASK		0x00
81 
82 #endif
83