1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * mt2701-reg.h -- Mediatek 2701 audio driver reg definition 4 * 5 * Copyright (c) 2016 MediaTek Inc. 6 * Author: Garlic Tseng <garlic.tseng@mediatek.com> 7 */ 8 9 #ifndef _MT2701_REG_H_ 10 #define _MT2701_REG_H_ 11 12 #define AUDIO_TOP_CON0 0x0000 13 #define AUDIO_TOP_CON3 0x000c 14 #define AUDIO_TOP_CON4 0x0010 15 #define AUDIO_TOP_CON5 0x0014 16 #define AFE_DAIBT_CON0 0x001c 17 #define AFE_MRGIF_CON 0x003c 18 #define AFE_HDMI_OUT_CON0 0x0370 19 #define AFE_HDMI_OUT_BASE 0x0374 20 #define AFE_HDMI_OUT_CUR 0x0378 21 #define AFE_HDMI_OUT_END 0x037c 22 #define AFE_HDMI_CONN0 0x0390 23 #define AFE_8CH_I2S_OUT_CON 0x0394 24 #define ASMI_TIMING_CON1 0x0100 25 #define ASMO_TIMING_CON1 0x0104 26 #define PWR1_ASM_CON1 0x0108 27 #define ASYS_TOP_CON 0x0600 28 #define ASYS_I2SIN1_CON 0x0604 29 #define ASYS_I2SIN2_CON 0x0608 30 #define ASYS_I2SIN3_CON 0x060c 31 #define ASYS_I2SIN4_CON 0x0610 32 #define ASYS_I2SIN5_CON 0x0614 33 #define ASYS_I2SO1_CON 0x061C 34 #define ASYS_I2SO2_CON 0x0620 35 #define ASYS_I2SO3_CON 0x0624 36 #define ASYS_I2SO4_CON 0x0628 37 #define ASYS_I2SO5_CON 0x062c 38 #define PWR2_TOP_CON 0x0634 39 #define AFE_CONN0 0x06c0 40 #define AFE_CONN1 0x06c4 41 #define AFE_CONN2 0x06c8 42 #define AFE_CONN3 0x06cc 43 #define AFE_CONN14 0x06f8 44 #define AFE_CONN15 0x06fc 45 #define AFE_CONN16 0x0700 46 #define AFE_CONN17 0x0704 47 #define AFE_CONN18 0x0708 48 #define AFE_CONN19 0x070c 49 #define AFE_CONN20 0x0710 50 #define AFE_CONN21 0x0714 51 #define AFE_CONN22 0x0718 52 #define AFE_CONN23 0x071c 53 #define AFE_CONN24 0x0720 54 #define AFE_CONN41 0x0764 55 #define ASYS_IRQ1_CON 0x0780 56 #define ASYS_IRQ2_CON 0x0784 57 #define ASYS_IRQ3_CON 0x0788 58 #define ASYS_IRQ_CLR 0x07c0 59 #define ASYS_IRQ_STATUS 0x07c4 60 #define PWR2_ASM_CON1 0x1070 61 #define AFE_DAC_CON0 0x1200 62 #define AFE_DAC_CON1 0x1204 63 #define AFE_DAC_CON2 0x1208 64 #define AFE_DAC_CON3 0x120c 65 #define AFE_DAC_CON4 0x1210 66 #define AFE_MEMIF_HD_CON1 0x121c 67 #define AFE_MEMIF_PBUF_SIZE 0x1238 68 #define AFE_MEMIF_HD_CON0 0x123c 69 #define AFE_DL1_BASE 0x1240 70 #define AFE_DL1_CUR 0x1244 71 #define AFE_DL2_BASE 0x1250 72 #define AFE_DL2_CUR 0x1254 73 #define AFE_DL3_BASE 0x1260 74 #define AFE_DL3_CUR 0x1264 75 #define AFE_DL4_BASE 0x1270 76 #define AFE_DL4_CUR 0x1274 77 #define AFE_DL5_BASE 0x1280 78 #define AFE_DL5_CUR 0x1284 79 #define AFE_DLMCH_BASE 0x12a0 80 #define AFE_DLMCH_CUR 0x12a4 81 #define AFE_ARB1_BASE 0x12b0 82 #define AFE_ARB1_CUR 0x12b4 83 #define AFE_VUL_BASE 0x1300 84 #define AFE_VUL_CUR 0x130c 85 #define AFE_UL2_BASE 0x1310 86 #define AFE_UL2_END 0x1318 87 #define AFE_UL2_CUR 0x131c 88 #define AFE_UL3_BASE 0x1320 89 #define AFE_UL3_END 0x1328 90 #define AFE_UL3_CUR 0x132c 91 #define AFE_UL4_BASE 0x1330 92 #define AFE_UL4_END 0x1338 93 #define AFE_UL4_CUR 0x133c 94 #define AFE_UL5_BASE 0x1340 95 #define AFE_UL5_END 0x1348 96 #define AFE_UL5_CUR 0x134c 97 #define AFE_DAI_BASE 0x1370 98 #define AFE_DAI_CUR 0x137c 99 100 /* AFE_DAIBT_CON0 (0x001c) */ 101 #define AFE_DAIBT_CON0_DAIBT_EN (0x1 << 0) 102 #define AFE_DAIBT_CON0_BT_FUNC_EN (0x1 << 1) 103 #define AFE_DAIBT_CON0_BT_FUNC_RDY (0x1 << 3) 104 #define AFE_DAIBT_CON0_BT_WIDE_MODE_EN (0x1 << 9) 105 #define AFE_DAIBT_CON0_MRG_USE (0x1 << 12) 106 107 /* PWR1_ASM_CON1 (0x0108) */ 108 #define PWR1_ASM_CON1_INIT_VAL (0x492) 109 110 /* AFE_MRGIF_CON (0x003c) */ 111 #define AFE_MRGIF_CON_MRG_EN (0x1 << 0) 112 #define AFE_MRGIF_CON_MRG_I2S_EN (0x1 << 16) 113 #define AFE_MRGIF_CON_I2S_MODE_MASK (0xf << 20) 114 #define AFE_MRGIF_CON_I2S_MODE_32K (0x4 << 20) 115 116 /* ASYS_TOP_CON (0x0600) */ 117 #define ASYS_TOP_CON_ASYS_TIMING_ON (0x3 << 0) 118 119 /* PWR2_ASM_CON1 (0x1070) */ 120 #define PWR2_ASM_CON1_INIT_VAL (0x492492) 121 122 /* AFE_DAC_CON0 (0x1200) */ 123 #define AFE_DAC_CON0_AFE_ON (0x1 << 0) 124 125 /* AFE_MEMIF_PBUF_SIZE (0x1238) */ 126 #define AFE_MEMIF_PBUF_SIZE_DLM_MASK (0x1 << 29) 127 #define AFE_MEMIF_PBUF_SIZE_PAIR_INTERLEAVE (0x0 << 29) 128 #define AFE_MEMIF_PBUF_SIZE_FULL_INTERLEAVE (0x1 << 29) 129 #define DLMCH_BIT_WIDTH_MASK (0x1 << 28) 130 #define AFE_MEMIF_PBUF_SIZE_DLM_CH_MASK (0xf << 24) 131 #define AFE_MEMIF_PBUF_SIZE_DLM_CH(x) ((x) << 24) 132 #define AFE_MEMIF_PBUF_SIZE_DLM_BYTE_MASK (0x3 << 12) 133 #define AFE_MEMIF_PBUF_SIZE_DLM_32BYTES (0x1 << 12) 134 135 /* AUDIO_TOP_CON3 (0x000c) -- HDMI BCK divider */ 136 #define AUDIO_TOP_CON3_HDMI_BCK_DIV_MASK (0x3f << 8) 137 #define AUDIO_TOP_CON3_HDMI_BCK_DIV(x) (((x) & 0x3f) << 8) 138 139 /* AFE_HDMI_OUT_CON0 (0x0370) */ 140 #define AFE_HDMI_OUT_CON0_OUT_ON (0x1 << 0) 141 #define AFE_HDMI_OUT_CON0_BIT_WIDTH_MASK (0x1 << 1) 142 #define AFE_HDMI_OUT_CON0_BIT_WIDTH_16 (0x0 << 1) 143 #define AFE_HDMI_OUT_CON0_BIT_WIDTH_32 (0x1 << 1) 144 #define AFE_HDMI_OUT_CON0_CH_NUM_MASK (0xf << 4) 145 #define AFE_HDMI_OUT_CON0_CH_NUM(x) (((x) & 0xf) << 4) 146 147 /* AFE_8CH_I2S_OUT_CON (0x0394) -- on-SoC 8-channel I2S that feeds HDMI TX */ 148 #define AFE_8CH_I2S_OUT_CON_EN (0x1 << 0) 149 #define AFE_8CH_I2S_OUT_CON_BCK_INV (0x1 << 1) 150 #define AFE_8CH_I2S_OUT_CON_LRCK_INV (0x1 << 2) 151 #define AFE_8CH_I2S_OUT_CON_I2S_DELAY (0x1 << 3) 152 #define AFE_8CH_I2S_OUT_CON_WLEN_MASK (0x3 << 4) 153 #define AFE_8CH_I2S_OUT_CON_WLEN_16BIT (0x1 << 4) 154 #define AFE_8CH_I2S_OUT_CON_WLEN_24BIT (0x2 << 4) 155 #define AFE_8CH_I2S_OUT_CON_WLEN_32BIT (0x3 << 4) 156 157 /* I2S in/out register bit control */ 158 #define ASYS_I2S_CON_FS (0x1f << 8) 159 #define ASYS_I2S_CON_FS_SET(x) ((x) << 8) 160 #define ASYS_I2S_CON_RESET (0x1 << 30) 161 #define ASYS_I2S_CON_I2S_EN (0x1 << 0) 162 #define ASYS_I2S_CON_ONE_HEART_MODE (0x1 << 16) 163 #define ASYS_I2S_CON_I2S_COUPLE_MODE (0x1 << 17) 164 /* 0:EIAJ 1:I2S */ 165 #define ASYS_I2S_CON_I2S_MODE (0x1 << 3) 166 #define ASYS_I2S_CON_WIDE_MODE (0x1 << 1) 167 #define ASYS_I2S_CON_WIDE_MODE_SET(x) ((x) << 1) 168 #define ASYS_I2S_IN_PHASE_FIX (0x1 << 31) 169 170 #endif 171