1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * AMD Platform Management Framework Driver 4 * 5 * Copyright (c) 2022, Advanced Micro Devices, Inc. 6 * All Rights Reserved. 7 * 8 * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> 9 */ 10 11 #ifndef PMF_H 12 #define PMF_H 13 14 #include <linux/acpi.h> 15 #include <linux/amd-pmf-io.h> 16 #include <linux/circ_buf.h> 17 #include <linux/input.h> 18 #include <linux/mutex_types.h> 19 #include <linux/platform_device.h> 20 #include <linux/platform_profile.h> 21 22 #define POLICY_BUF_MAX_SZ 0x4b000 23 #define POLICY_SIGN_COOKIE 0x31535024 24 #define POLICY_COOKIE_OFFSET 0x10 25 26 /* List of supported CPU ids */ 27 #define AMD_CPU_ID_RMB 0x14b5 28 #define AMD_CPU_ID_PS 0x14e8 29 #define PCI_DEVICE_ID_AMD_1AH_M20H_ROOT 0x1507 30 #define PCI_DEVICE_ID_AMD_1AH_M60H_ROOT 0x1122 31 32 struct cookie_header { 33 u32 sign; 34 u32 length; 35 } __packed; 36 37 /* APMF Functions */ 38 #define APMF_FUNC_VERIFY_INTERFACE 0 39 #define APMF_FUNC_GET_SYS_PARAMS 1 40 #define APMF_FUNC_SBIOS_REQUESTS 2 41 #define APMF_FUNC_SBIOS_HEARTBEAT 4 42 #define APMF_FUNC_AUTO_MODE 5 43 #define APMF_FUNC_SET_FAN_IDX 7 44 #define APMF_FUNC_OS_POWER_SLIDER_UPDATE 8 45 #define APMF_FUNC_STATIC_SLIDER_GRANULAR 9 46 #define APMF_FUNC_DYN_SLIDER_AC 11 47 #define APMF_FUNC_DYN_SLIDER_DC 12 48 #define APMF_FUNC_NOTIFY_SMART_PC_UPDATES 14 49 #define APMF_FUNC_SBIOS_HEARTBEAT_V2 16 50 51 /* Message Definitions */ 52 #define SET_SPL 0x03 /* SPL: Sustained Power Limit */ 53 #define SET_SPPT 0x05 /* SPPT: Slow Package Power Tracking */ 54 #define SET_FPPT 0x07 /* FPPT: Fast Package Power Tracking */ 55 #define GET_SPL 0x0B 56 #define GET_SPPT 0x0D 57 #define GET_FPPT 0x0F 58 #define SET_DRAM_ADDR_HIGH 0x14 59 #define SET_DRAM_ADDR_LOW 0x15 60 #define SET_TRANSFER_TABLE 0x16 61 #define SET_STT_MIN_LIMIT 0x18 /* STT: Skin Temperature Tracking */ 62 #define SET_STT_LIMIT_APU 0x19 63 #define SET_STT_LIMIT_HS2 0x1A 64 #define SET_SPPT_APU_ONLY 0x1D 65 #define GET_SPPT_APU_ONLY 0x1E 66 #define GET_STT_MIN_LIMIT 0x1F 67 #define GET_STT_LIMIT_APU 0x20 68 #define GET_STT_LIMIT_HS2 0x21 69 #define SET_P3T 0x23 /* P3T: Peak Package Power Limit */ 70 #define SET_PMF_PPT 0x25 71 #define SET_PMF_PPT_APU_ONLY 0x26 72 73 /* OS slider update notification */ 74 #define DC_BEST_PERF 0 75 #define DC_BETTER_PERF 1 76 #define DC_BATTERY_SAVER 3 77 #define AC_BEST_PERF 4 78 #define AC_BETTER_PERF 5 79 #define AC_BETTER_BATTERY 6 80 81 /* Fan Index for Auto Mode */ 82 #define FAN_INDEX_AUTO 0xFFFFFFFF 83 84 #define ARG_NONE 0 85 #define AVG_SAMPLE_SIZE 3 86 87 /* Policy Actions */ 88 #define PMF_POLICY_SPL 2 89 #define PMF_POLICY_SPPT 3 90 #define PMF_POLICY_FPPT 4 91 #define PMF_POLICY_SPPT_APU_ONLY 5 92 #define PMF_POLICY_STT_MIN 6 93 #define PMF_POLICY_STT_SKINTEMP_APU 7 94 #define PMF_POLICY_STT_SKINTEMP_HS2 8 95 #define PMF_POLICY_SYSTEM_STATE 9 96 #define PMF_POLICY_BIOS_OUTPUT_1 10 97 #define PMF_POLICY_BIOS_OUTPUT_2 11 98 #define PMF_POLICY_P3T 38 99 #define PMF_POLICY_PMF_PPT 54 100 #define PMF_POLICY_PMF_PPT_APU_ONLY 55 101 #define PMF_POLICY_BIOS_OUTPUT_3 57 102 #define PMF_POLICY_BIOS_OUTPUT_4 58 103 #define PMF_POLICY_BIOS_OUTPUT_5 59 104 #define PMF_POLICY_BIOS_OUTPUT_6 60 105 #define PMF_POLICY_BIOS_OUTPUT_7 61 106 #define PMF_POLICY_BIOS_OUTPUT_8 62 107 #define PMF_POLICY_BIOS_OUTPUT_9 63 108 #define PMF_POLICY_BIOS_OUTPUT_10 64 109 110 /* TA macros */ 111 #define PMF_TA_IF_VERSION_MAJOR 1 112 #define TA_PMF_ACTION_MAX 32 113 #define TA_PMF_UNDO_MAX 8 114 #define TA_OUTPUT_RESERVED_MEM 922 115 #define MAX_OPERATION_PARAMS 4 116 117 #define TA_ERROR_CRYPTO_INVALID_PARAM 0x20002 118 #define TA_ERROR_CRYPTO_BIN_TOO_LARGE 0x2000d 119 120 #define PMF_IF_V1 1 121 #define PMF_IF_V2 2 122 123 #define APTS_MAX_STATES 16 124 #define CUSTOM_BIOS_INPUT_BITS GENMASK(16, 7) 125 #define BIOS_INPUTS_MAX 10 126 #define CUSTOM_BIOS_INPUT_RING_ENTRIES 64 /* Must be power of two for CIRC_* macros */ 127 128 /* amd_pmf_send_cmd() set/get */ 129 #define SET_CMD false 130 #define GET_CMD true 131 132 #define METRICS_TABLE_ID 7 133 134 typedef void (*apmf_event_handler_t)(acpi_handle handle, u32 event, void *data); 135 136 static const uuid_t amd_pmf_ta_uuid[] __used = { UUID_INIT(0xd9b39bf2, 0x66bd, 0x4154, 0xaf, 0xb8, 137 0x8a, 0xcc, 0x2b, 0x2b, 0x60, 0xd6), 138 UUID_INIT(0x6fd93b77, 0x3fb8, 0x524d, 0xb1, 0x2d, 139 0xc5, 0x29, 0xb1, 0x3d, 0x85, 0x43), 140 }; 141 142 /* APTS PMF BIOS Interface */ 143 struct amd_pmf_apts_output { 144 u16 table_version; 145 u32 fan_table_idx; 146 u32 pmf_ppt; 147 u32 ppt_pmf_apu_only; 148 u32 stt_min_limit; 149 u8 stt_skin_temp_limit_apu; 150 u8 stt_skin_temp_limit_hs2; 151 } __packed; 152 153 struct amd_pmf_apts_granular_output { 154 u16 size; 155 struct amd_pmf_apts_output val; 156 } __packed; 157 158 struct amd_pmf_apts_granular { 159 u16 size; 160 struct amd_pmf_apts_output val[APTS_MAX_STATES]; 161 }; 162 163 struct sbios_hb_event_v2 { 164 u16 size; 165 u8 load; 166 u8 unload; 167 u8 suspend; 168 u8 resume; 169 } __packed; 170 171 enum sbios_hb_v2 { 172 ON_LOAD, 173 ON_UNLOAD, 174 ON_SUSPEND, 175 ON_RESUME, 176 }; 177 178 /* AMD PMF BIOS interfaces */ 179 struct apmf_verify_interface { 180 u16 size; 181 u16 version; 182 u32 notification_mask; 183 u32 supported_functions; 184 } __packed; 185 186 struct apmf_system_params { 187 u16 size; 188 u32 valid_mask; 189 u32 flags; 190 u8 command_code; 191 u32 heartbeat_int; 192 } __packed; 193 194 struct apmf_sbios_req { 195 u16 size; 196 u32 pending_req; 197 u8 rsd; 198 u8 cql_event; 199 u8 amt_event; 200 u32 fppt; 201 u32 sppt; 202 u32 fppt_apu_only; 203 u32 spl; 204 u32 stt_min_limit; 205 u8 skin_temp_apu; 206 u8 skin_temp_hs2; 207 } __packed; 208 209 /* As per APMF spec 1.3 */ 210 struct apmf_sbios_req_v1 { 211 u16 size; 212 u32 pending_req; 213 u8 rsvd; 214 u8 cql_event; 215 u8 amt_event; 216 u32 fppt; 217 u32 sppt; 218 u32 sppt_apu_only; 219 u32 spl; 220 u32 stt_min_limit; 221 u8 skin_temp_apu; 222 u8 skin_temp_hs2; 223 u8 enable_cnqf; 224 u32 custom_policy[BIOS_INPUTS_MAX]; 225 } __packed; 226 227 struct apmf_sbios_req_v2 { 228 u16 size; 229 u32 pending_req; 230 u8 rsd; 231 u32 ppt_pmf; 232 u32 ppt_pmf_apu_only; 233 u32 stt_min_limit; 234 u8 skin_temp_apu; 235 u8 skin_temp_hs2; 236 u32 custom_policy[BIOS_INPUTS_MAX]; 237 } __packed; 238 239 struct apmf_fan_idx { 240 u16 size; 241 u8 fan_ctl_mode; 242 u32 fan_ctl_idx; 243 } __packed; 244 245 struct smu_pmf_metrics_v2 { 246 u16 core_frequency[16]; /* MHz */ 247 u16 core_power[16]; /* mW */ 248 u16 core_temp[16]; /* centi-C */ 249 u16 gfx_temp; /* centi-C */ 250 u16 soc_temp; /* centi-C */ 251 u16 stapm_opn_limit; /* mW */ 252 u16 stapm_cur_limit; /* mW */ 253 u16 infra_cpu_maxfreq; /* MHz */ 254 u16 infra_gfx_maxfreq; /* MHz */ 255 u16 skin_temp; /* centi-C */ 256 u16 gfxclk_freq; /* MHz */ 257 u16 fclk_freq; /* MHz */ 258 u16 gfx_activity; /* GFX busy % [0-100] */ 259 u16 socclk_freq; /* MHz */ 260 u16 vclk_freq; /* MHz */ 261 u16 vcn_activity; /* VCN busy % [0-100] */ 262 u16 vpeclk_freq; /* MHz */ 263 u16 npuclk_freq; /* MHz */ 264 u16 npu_busy[8]; /* NPU busy % [0-100] */ 265 u16 dram_reads; /* MB/sec */ 266 u16 dram_writes; /* MB/sec */ 267 u16 core_c0residency[16]; /* C0 residency % [0-100] */ 268 u16 npu_power; /* mW */ 269 u32 apu_power; /* mW */ 270 u32 gfx_power; /* mW */ 271 u32 dgpu_power; /* mW */ 272 u32 socket_power; /* mW */ 273 u32 all_core_power; /* mW */ 274 u32 filter_alpha_value; /* time constant [us] */ 275 u32 metrics_counter; 276 u16 memclk_freq; /* MHz */ 277 u16 mpnpuclk_freq; /* MHz */ 278 u16 npu_reads; /* MB/sec */ 279 u16 npu_writes; /* MB/sec */ 280 u32 throttle_residency_prochot; 281 u32 throttle_residency_spl; 282 u32 throttle_residency_fppt; 283 u32 throttle_residency_sppt; 284 u32 throttle_residency_thm_core; 285 u32 throttle_residency_thm_gfx; 286 u32 throttle_residency_thm_soc; 287 u16 psys; 288 u16 spare1; 289 u32 spare[6]; 290 } __packed; 291 292 struct smu_pmf_metrics { 293 u16 gfxclk_freq; /* in MHz */ 294 u16 socclk_freq; /* in MHz */ 295 u16 vclk_freq; /* in MHz */ 296 u16 dclk_freq; /* in MHz */ 297 u16 memclk_freq; /* in MHz */ 298 u16 spare; 299 u16 gfx_activity; /* in Centi */ 300 u16 uvd_activity; /* in Centi */ 301 u16 voltage[2]; /* in mV */ 302 u16 currents[2]; /* in mA */ 303 u16 power[2];/* in mW */ 304 u16 core_freq[8]; /* in MHz */ 305 u16 core_power[8]; /* in mW */ 306 u16 core_temp[8]; /* in centi-Celsius */ 307 u16 l3_freq; /* in MHz */ 308 u16 l3_temp; /* in centi-Celsius */ 309 u16 gfx_temp; /* in centi-Celsius */ 310 u16 soc_temp; /* in centi-Celsius */ 311 u16 throttler_status; 312 u16 current_socketpower; /* in mW */ 313 u16 stapm_orig_limit; /* in W */ 314 u16 stapm_cur_limit; /* in W */ 315 u32 apu_power; /* in mW */ 316 u32 dgpu_power; /* in mW */ 317 u16 vdd_tdc_val; /* in mA */ 318 u16 soc_tdc_val; /* in mA */ 319 u16 vdd_edc_val; /* in mA */ 320 u16 soc_edcv_al; /* in mA */ 321 u16 infra_cpu_maxfreq; /* in MHz */ 322 u16 infra_gfx_maxfreq; /* in MHz */ 323 u16 skin_temp; /* in centi-Celsius */ 324 u16 device_state; 325 u16 curtemp; /* in centi-Celsius */ 326 u16 filter_alpha_value; 327 u16 avg_gfx_clkfrequency; 328 u16 avg_fclk_frequency; 329 u16 avg_gfx_activity; 330 u16 avg_socclk_frequency; 331 u16 avg_vclk_frequency; 332 u16 avg_vcn_activity; 333 u16 avg_dram_reads; 334 u16 avg_dram_writes; 335 u16 avg_socket_power; 336 u16 avg_core_power[2]; 337 u16 avg_core_c0residency[16]; 338 u16 spare1; 339 u32 metrics_counter; 340 } __packed; 341 342 enum amd_stt_skin_temp { 343 STT_TEMP_APU, 344 STT_TEMP_HS2, 345 STT_TEMP_COUNT, 346 }; 347 348 enum amd_slider_op { 349 SLIDER_OP_GET, 350 SLIDER_OP_SET, 351 }; 352 353 enum power_source { 354 POWER_SOURCE_AC, 355 POWER_SOURCE_DC, 356 POWER_SOURCE_MAX, 357 }; 358 359 enum power_modes { 360 POWER_MODE_PERFORMANCE, 361 POWER_MODE_BALANCED_POWER, 362 POWER_MODE_POWER_SAVER, 363 POWER_MODE_MAX, 364 }; 365 366 enum power_modes_v2 { 367 POWER_MODE_BEST_PERFORMANCE, 368 POWER_MODE_BALANCED, 369 POWER_MODE_BEST_POWER_EFFICIENCY, 370 POWER_MODE_ENERGY_SAVE, 371 POWER_MODE_V2_MAX, 372 }; 373 374 struct pmf_bios_inputs_prev { 375 u32 custom_bios_inputs[BIOS_INPUTS_MAX]; 376 }; 377 378 /** 379 * struct pmf_bios_input_entry - Snapshot of custom BIOS input event 380 * @val: Array of custom BIOS input values 381 * @preq: Pending request value associated with this event 382 */ 383 struct pmf_bios_input_entry { 384 u32 val[BIOS_INPUTS_MAX]; 385 u32 preq; 386 }; 387 388 struct pmf_cbi_ring_buffer { 389 struct pmf_bios_input_entry data[CUSTOM_BIOS_INPUT_RING_ENTRIES]; 390 int head; 391 int tail; 392 }; 393 394 struct amd_pmf_dev { 395 void __iomem *regbase; 396 void __iomem *smu_virt_addr; 397 void *buf; 398 u32 base_addr; 399 u32 cpu_id; 400 struct device *dev; 401 struct mutex lock; /* protects the PMF interface */ 402 u32 supported_func; 403 enum platform_profile_option current_profile; 404 struct device *ppdev; /* platform profile class device */ 405 struct dentry *dbgfs_dir; 406 int hb_interval; /* SBIOS heartbeat interval */ 407 struct delayed_work heart_beat; 408 struct smu_pmf_metrics m_table; 409 struct smu_pmf_metrics_v2 m_table_v2; 410 struct delayed_work work_buffer; 411 ktime_t start_time; 412 int socket_power_history[AVG_SAMPLE_SIZE]; 413 int socket_power_history_idx; 414 bool amt_enabled; 415 struct mutex update_mutex; /* protects race between ACPI handler and metrics thread */ 416 bool cnqf_enabled; 417 bool cnqf_supported; 418 struct notifier_block pwr_src_notifier; 419 /* Smart PC solution builder */ 420 struct dentry *esbin; 421 unsigned char *policy_buf; 422 resource_size_t policy_sz; 423 struct tee_context *tee_ctx; 424 struct tee_shm *fw_shm_pool; 425 u32 session_id; 426 void *shbuf; 427 struct delayed_work pb_work; 428 struct pmf_action_table *prev_data; 429 resource_size_t policy_addr; 430 void __iomem *policy_base; 431 bool smart_pc_enabled; 432 u16 pmf_if_version; 433 struct input_dev *pmf_idev; 434 size_t mtable_size; 435 struct resource *res; 436 struct apmf_sbios_req_v2 req; /* To get custom bios pending request */ 437 struct mutex cb_mutex; 438 u32 notifications; 439 struct apmf_sbios_req_v1 req1; 440 struct pmf_bios_inputs_prev cb_prev; /* To preserve custom BIOS inputs */ 441 bool cb_flag; /* To handle first custom BIOS input */ 442 struct pmf_cbi_ring_buffer cbi_buf; 443 struct mutex cbi_mutex; /* Protects ring buffer access */ 444 struct mutex metrics_mutex; 445 }; 446 447 struct apmf_sps_prop_granular_v2 { 448 u8 power_states[POWER_SOURCE_MAX][POWER_MODE_V2_MAX]; 449 } __packed; 450 451 struct apmf_sps_prop_granular { 452 u32 fppt; 453 u32 sppt; 454 u32 sppt_apu_only; 455 u32 spl; 456 u32 stt_min; 457 u8 stt_skin_temp[STT_TEMP_COUNT]; 458 u32 fan_id; 459 } __packed; 460 461 /* Static Slider */ 462 struct apmf_static_slider_granular_output { 463 u16 size; 464 struct apmf_sps_prop_granular prop[POWER_SOURCE_MAX * POWER_MODE_MAX]; 465 } __packed; 466 467 struct amd_pmf_static_slider_granular { 468 u16 size; 469 struct apmf_sps_prop_granular prop[POWER_SOURCE_MAX][POWER_MODE_MAX]; 470 }; 471 472 struct apmf_static_slider_granular_output_v2 { 473 u16 size; 474 struct apmf_sps_prop_granular_v2 sps_idx; 475 } __packed; 476 477 struct amd_pmf_static_slider_granular_v2 { 478 u16 size; 479 struct apmf_sps_prop_granular_v2 sps_idx; 480 }; 481 482 struct os_power_slider { 483 u16 size; 484 u8 slider_event; 485 } __packed; 486 487 struct amd_pmf_notify_smart_pc_update { 488 u16 size; 489 u32 pending_req; 490 u32 custom_bios[BIOS_INPUTS_MAX]; 491 } __packed; 492 493 struct fan_table_control { 494 bool manual; 495 unsigned long fan_id; 496 }; 497 498 struct power_table_control { 499 u32 spl; 500 u32 sppt; 501 u32 fppt; 502 u32 sppt_apu_only; 503 u32 stt_min; 504 u32 stt_skin_temp[STT_TEMP_COUNT]; 505 u32 reserved[16]; 506 }; 507 508 /* Auto Mode Layer */ 509 enum auto_mode_transition_priority { 510 AUTO_TRANSITION_TO_PERFORMANCE, /* Any other mode to Performance Mode */ 511 AUTO_TRANSITION_FROM_QUIET_TO_BALANCE, /* Quiet Mode to Balance Mode */ 512 AUTO_TRANSITION_TO_QUIET, /* Any other mode to Quiet Mode */ 513 AUTO_TRANSITION_FROM_PERFORMANCE_TO_BALANCE, /* Performance Mode to Balance Mode */ 514 AUTO_TRANSITION_MAX, 515 }; 516 517 enum auto_mode_mode { 518 AUTO_QUIET, 519 AUTO_BALANCE, 520 AUTO_PERFORMANCE_ON_LAP, 521 AUTO_PERFORMANCE, 522 AUTO_MODE_MAX, 523 }; 524 525 struct auto_mode_trans_params { 526 u32 time_constant; /* minimum time required to switch to next mode */ 527 u32 power_delta; /* delta power to shift mode */ 528 u32 power_threshold; 529 u32 timer; /* elapsed time. if timer > TimeThreshold, it will move to next mode */ 530 u32 applied; 531 enum auto_mode_mode target_mode; 532 u32 shifting_up; 533 }; 534 535 struct auto_mode_mode_settings { 536 struct power_table_control power_control; 537 struct fan_table_control fan_control; 538 u32 power_floor; 539 }; 540 541 struct auto_mode_mode_config { 542 struct auto_mode_trans_params transition[AUTO_TRANSITION_MAX]; 543 struct auto_mode_mode_settings mode_set[AUTO_MODE_MAX]; 544 enum auto_mode_mode current_mode; 545 }; 546 547 struct apmf_auto_mode { 548 u16 size; 549 /* time constant */ 550 u32 balanced_to_perf; 551 u32 perf_to_balanced; 552 u32 quiet_to_balanced; 553 u32 balanced_to_quiet; 554 /* power floor */ 555 u32 pfloor_perf; 556 u32 pfloor_balanced; 557 u32 pfloor_quiet; 558 /* Power delta for mode change */ 559 u32 pd_balanced_to_perf; 560 u32 pd_perf_to_balanced; 561 u32 pd_quiet_to_balanced; 562 u32 pd_balanced_to_quiet; 563 /* skin temperature limits */ 564 u8 stt_apu_perf_on_lap; /* CQL ON */ 565 u8 stt_hs2_perf_on_lap; /* CQL ON */ 566 u8 stt_apu_perf; 567 u8 stt_hs2_perf; 568 u8 stt_apu_balanced; 569 u8 stt_hs2_balanced; 570 u8 stt_apu_quiet; 571 u8 stt_hs2_quiet; 572 u32 stt_min_limit_perf_on_lap; /* CQL ON */ 573 u32 stt_min_limit_perf; 574 u32 stt_min_limit_balanced; 575 u32 stt_min_limit_quiet; 576 /* SPL based */ 577 u32 fppt_perf_on_lap; /* CQL ON */ 578 u32 sppt_perf_on_lap; /* CQL ON */ 579 u32 spl_perf_on_lap; /* CQL ON */ 580 u32 sppt_apu_only_perf_on_lap; /* CQL ON */ 581 u32 fppt_perf; 582 u32 sppt_perf; 583 u32 spl_perf; 584 u32 sppt_apu_only_perf; 585 u32 fppt_balanced; 586 u32 sppt_balanced; 587 u32 spl_balanced; 588 u32 sppt_apu_only_balanced; 589 u32 fppt_quiet; 590 u32 sppt_quiet; 591 u32 spl_quiet; 592 u32 sppt_apu_only_quiet; 593 /* Fan ID */ 594 u32 fan_id_perf; 595 u32 fan_id_balanced; 596 u32 fan_id_quiet; 597 } __packed; 598 599 /* CnQF Layer */ 600 enum cnqf_trans_priority { 601 CNQF_TRANSITION_TO_TURBO, /* Any other mode to Turbo Mode */ 602 CNQF_TRANSITION_FROM_BALANCE_TO_PERFORMANCE, /* quiet/balance to Performance Mode */ 603 CNQF_TRANSITION_FROM_QUIET_TO_BALANCE, /* Quiet Mode to Balance Mode */ 604 CNQF_TRANSITION_TO_QUIET, /* Any other mode to Quiet Mode */ 605 CNQF_TRANSITION_FROM_PERFORMANCE_TO_BALANCE, /* Performance/Turbo to Balance Mode */ 606 CNQF_TRANSITION_FROM_TURBO_TO_PERFORMANCE, /* Turbo mode to Performance Mode */ 607 CNQF_TRANSITION_MAX, 608 }; 609 610 enum cnqf_mode { 611 CNQF_MODE_QUIET, 612 CNQF_MODE_BALANCE, 613 CNQF_MODE_PERFORMANCE, 614 CNQF_MODE_TURBO, 615 CNQF_MODE_MAX, 616 }; 617 618 enum apmf_cnqf_pos { 619 APMF_CNQF_TURBO, 620 APMF_CNQF_PERFORMANCE, 621 APMF_CNQF_BALANCE, 622 APMF_CNQF_QUIET, 623 APMF_CNQF_MAX, 624 }; 625 626 struct cnqf_mode_settings { 627 struct power_table_control power_control; 628 struct fan_table_control fan_control; 629 u32 power_floor; 630 }; 631 632 struct cnqf_tran_params { 633 u32 time_constant; /* minimum time required to switch to next mode */ 634 u32 power_threshold; 635 u32 timer; /* elapsed time. if timer > timethreshold, it will move to next mode */ 636 u32 total_power; 637 u32 count; 638 bool priority; 639 bool shifting_up; 640 enum cnqf_mode target_mode; 641 }; 642 643 struct cnqf_config { 644 struct cnqf_tran_params trans_param[POWER_SOURCE_MAX][CNQF_TRANSITION_MAX]; 645 struct cnqf_mode_settings mode_set[POWER_SOURCE_MAX][CNQF_MODE_MAX]; 646 struct power_table_control defaults; 647 enum cnqf_mode current_mode; 648 u32 power_src; 649 u32 avg_power; 650 }; 651 652 struct apmf_cnqf_power_set { 653 u32 pfloor; 654 u32 fppt; 655 u32 sppt; 656 u32 sppt_apu_only; 657 u32 spl; 658 u32 stt_min_limit; 659 u8 stt_skintemp[STT_TEMP_COUNT]; 660 u32 fan_id; 661 } __packed; 662 663 struct apmf_dyn_slider_output { 664 u16 size; 665 u16 flags; 666 u32 t_perf_to_turbo; 667 u32 t_balanced_to_perf; 668 u32 t_quiet_to_balanced; 669 u32 t_balanced_to_quiet; 670 u32 t_perf_to_balanced; 671 u32 t_turbo_to_perf; 672 struct apmf_cnqf_power_set ps[APMF_CNQF_MAX]; 673 } __packed; 674 675 /* Smart PC - TA internals */ 676 enum system_state { 677 SYSTEM_STATE_S0i3, 678 SYSTEM_STATE_S4, 679 SYSTEM_STATE_SCREEN_LOCK, 680 SYSTEM_STATE_MAX, 681 }; 682 683 enum ta_slider { 684 TA_BEST_BATTERY, 685 TA_BETTER_BATTERY, 686 TA_BETTER_PERFORMANCE, 687 TA_BEST_PERFORMANCE, 688 TA_MAX, 689 }; 690 691 struct amd_pmf_pb_bitmap { 692 const char *name; 693 u32 bit_mask; 694 }; 695 696 static const struct amd_pmf_pb_bitmap custom_bios_inputs[] __used = { 697 {"NOTIFY_CUSTOM_BIOS_INPUT1", BIT(5)}, 698 {"NOTIFY_CUSTOM_BIOS_INPUT2", BIT(6)}, 699 {"NOTIFY_CUSTOM_BIOS_INPUT3", BIT(7)}, 700 {"NOTIFY_CUSTOM_BIOS_INPUT4", BIT(8)}, 701 {"NOTIFY_CUSTOM_BIOS_INPUT5", BIT(9)}, 702 {"NOTIFY_CUSTOM_BIOS_INPUT6", BIT(10)}, 703 {"NOTIFY_CUSTOM_BIOS_INPUT7", BIT(11)}, 704 {"NOTIFY_CUSTOM_BIOS_INPUT8", BIT(12)}, 705 {"NOTIFY_CUSTOM_BIOS_INPUT9", BIT(13)}, 706 {"NOTIFY_CUSTOM_BIOS_INPUT10", BIT(14)}, 707 }; 708 709 static const struct amd_pmf_pb_bitmap custom_bios_inputs_v1[] __used = { 710 {"NOTIFY_CUSTOM_BIOS_INPUT1", BIT(7)}, 711 {"NOTIFY_CUSTOM_BIOS_INPUT2", BIT(8)}, 712 {"NOTIFY_CUSTOM_BIOS_INPUT3", BIT(9)}, 713 {"NOTIFY_CUSTOM_BIOS_INPUT4", BIT(10)}, 714 {"NOTIFY_CUSTOM_BIOS_INPUT5", BIT(11)}, 715 {"NOTIFY_CUSTOM_BIOS_INPUT6", BIT(12)}, 716 {"NOTIFY_CUSTOM_BIOS_INPUT7", BIT(13)}, 717 {"NOTIFY_CUSTOM_BIOS_INPUT8", BIT(14)}, 718 {"NOTIFY_CUSTOM_BIOS_INPUT9", BIT(15)}, 719 {"NOTIFY_CUSTOM_BIOS_INPUT10", BIT(16)}, 720 }; 721 722 enum platform_type { 723 PTYPE_UNKNOWN = 0, 724 LID_CLOSE, 725 CLAMSHELL, 726 FLAT, 727 TENT, 728 STAND, 729 TABLET, 730 BOOK, 731 PRESENTATION, 732 PULL_FWD, 733 PTYPE_INVALID = 0xf, 734 }; 735 736 /* Command ids for TA communication */ 737 enum ta_pmf_command { 738 TA_PMF_COMMAND_POLICY_BUILDER_INITIALIZE, 739 TA_PMF_COMMAND_POLICY_BUILDER_ENACT_POLICIES, 740 }; 741 742 enum ta_pmf_error_type { 743 TA_PMF_TYPE_SUCCESS, 744 TA_PMF_ERROR_TYPE_GENERIC, 745 TA_PMF_ERROR_TYPE_CRYPTO, 746 TA_PMF_ERROR_TYPE_CRYPTO_VALIDATE, 747 TA_PMF_ERROR_TYPE_CRYPTO_VERIFY_OEM, 748 TA_PMF_ERROR_TYPE_POLICY_BUILDER, 749 TA_PMF_ERROR_TYPE_PB_CONVERT, 750 TA_PMF_ERROR_TYPE_PB_SETUP, 751 TA_PMF_ERROR_TYPE_PB_ENACT, 752 TA_PMF_ERROR_TYPE_ASD_GET_DEVICE_INFO, 753 TA_PMF_ERROR_TYPE_ASD_GET_DEVICE_PCIE_INFO, 754 TA_PMF_ERROR_TYPE_SYS_DRV_FW_VALIDATION, 755 TA_PMF_ERROR_TYPE_MAX, 756 }; 757 758 struct pmf_action_table { 759 enum system_state system_state; 760 u32 spl; /* in mW */ 761 u32 sppt; /* in mW */ 762 u32 sppt_apuonly; /* in mW */ 763 u32 fppt; /* in mW */ 764 u32 stt_minlimit; /* in mW */ 765 u32 stt_skintemp_apu; /* in C */ 766 u32 stt_skintemp_hs2; /* in C */ 767 u32 p3t_limit; /* in mW */ 768 u32 pmf_ppt; /* in mW */ 769 u32 pmf_ppt_apu_only; /* in mW */ 770 }; 771 772 /* Input conditions */ 773 struct ta_pmf_condition_info { 774 u32 power_source; 775 u32 bat_percentage; 776 u32 power_slider; 777 u32 lid_state; 778 bool user_present; 779 u32 bios_input_1[2]; 780 u32 monitor_count; 781 u32 rsvd2[2]; 782 u32 bat_design; 783 u32 full_charge_capacity; 784 int drain_rate; 785 bool user_engaged; 786 u32 device_state; 787 u32 socket_power; 788 u32 skin_temperature; 789 u32 rsvd3[2]; 790 u32 platform_type; 791 u32 rsvd3_1[2]; 792 u32 ambient_light; 793 u32 length; 794 u32 avg_c0residency; 795 u32 max_c0residency; 796 u32 s0i3_entry; 797 u32 gfx_busy; 798 u32 rsvd4[7]; 799 bool camera_state; 800 u32 workload_type; 801 u32 display_type; 802 u32 display_state; 803 u32 rsvd5_1[17]; 804 u32 bios_input_2[8]; 805 u32 rsvd5[125]; 806 }; 807 808 struct ta_pmf_load_policy_table { 809 u32 table_size; 810 u8 table[POLICY_BUF_MAX_SZ]; 811 }; 812 813 /* TA initialization params */ 814 struct ta_pmf_init_table { 815 u32 frequency; /* SMU sampling frequency */ 816 bool validate; 817 bool sku_check; 818 bool metadata_macrocheck; 819 struct ta_pmf_load_policy_table policies_table; 820 }; 821 822 /* Everything the TA needs to Enact Policies */ 823 struct ta_pmf_enact_table { 824 struct ta_pmf_condition_info ev_info; 825 u32 name; 826 }; 827 828 struct ta_pmf_action { 829 u32 action_index; 830 u32 value; 831 u32 spl_arg; 832 }; 833 834 /* Output actions from TA */ 835 struct ta_pmf_enact_result { 836 u32 actions_count; 837 struct ta_pmf_action actions_list[TA_PMF_ACTION_MAX]; 838 u32 undo_count; 839 struct ta_pmf_action undo_list[TA_PMF_UNDO_MAX]; 840 }; 841 842 union ta_pmf_input { 843 struct ta_pmf_enact_table enact_table; 844 struct ta_pmf_init_table init_table; 845 }; 846 847 union ta_pmf_output { 848 struct ta_pmf_enact_result policy_apply_table; 849 u32 rsvd[TA_OUTPUT_RESERVED_MEM]; 850 }; 851 852 struct ta_pmf_shared_memory { 853 int command_id; 854 int resp_id; 855 u32 pmf_result; 856 u32 if_version; 857 union ta_pmf_output pmf_output; 858 union ta_pmf_input pmf_input; 859 }; 860 861 /* Core Layer */ 862 int apmf_acpi_init(struct amd_pmf_dev *pmf_dev); 863 void apmf_acpi_deinit(struct amd_pmf_dev *pmf_dev); 864 int is_apmf_func_supported(struct amd_pmf_dev *pdev, unsigned long index); 865 int amd_pmf_send_cmd(struct amd_pmf_dev *dev, u8 message, bool get, u32 arg, u32 *data); 866 int amd_pmf_init_metrics_table(struct amd_pmf_dev *dev); 867 int amd_pmf_get_power_source(void); 868 int apmf_install_handler(struct amd_pmf_dev *pmf_dev); 869 int apmf_os_power_slider_update(struct amd_pmf_dev *dev, u8 flag); 870 int amd_pmf_set_dram_addr(struct amd_pmf_dev *dev, bool alloc_buffer); 871 int amd_pmf_notify_sbios_heartbeat_event_v2(struct amd_pmf_dev *dev, u8 flag); 872 u32 fixp_q88_fromint(u32 val); 873 int is_apmf_bios_input_notifications_supported(struct amd_pmf_dev *pdev); 874 875 /* SPS Layer */ 876 int amd_pmf_get_pprof_modes(struct amd_pmf_dev *pmf); 877 void amd_pmf_update_slider(struct amd_pmf_dev *dev, bool op, int idx, 878 struct amd_pmf_static_slider_granular *table); 879 int amd_pmf_init_sps(struct amd_pmf_dev *dev); 880 int apmf_get_static_slider_granular(struct amd_pmf_dev *pdev, 881 struct apmf_static_slider_granular_output *output); 882 bool is_pprof_balanced(struct amd_pmf_dev *pmf); 883 int amd_pmf_power_slider_update_event(struct amd_pmf_dev *dev); 884 const char *amd_pmf_source_as_str(unsigned int state); 885 886 const char *amd_pmf_source_as_str(unsigned int state); 887 888 int apmf_update_fan_idx(struct amd_pmf_dev *pdev, bool manual, u32 idx); 889 int amd_pmf_set_sps_power_limits(struct amd_pmf_dev *pmf); 890 int apmf_get_static_slider_granular_v2(struct amd_pmf_dev *dev, 891 struct apmf_static_slider_granular_output_v2 *data); 892 int apts_get_static_slider_granular_v2(struct amd_pmf_dev *pdev, 893 struct amd_pmf_apts_granular_output *data, u32 apts_idx); 894 895 /* Auto Mode Layer */ 896 int apmf_get_auto_mode_def(struct amd_pmf_dev *pdev, struct apmf_auto_mode *data); 897 void amd_pmf_init_auto_mode(struct amd_pmf_dev *dev); 898 void amd_pmf_deinit_auto_mode(struct amd_pmf_dev *dev); 899 void amd_pmf_trans_automode(struct amd_pmf_dev *dev, int socket_power, ktime_t time_elapsed_ms); 900 int apmf_get_sbios_requests(struct amd_pmf_dev *pdev, struct apmf_sbios_req *req); 901 int apmf_get_sbios_requests_v1(struct amd_pmf_dev *pdev, struct apmf_sbios_req_v1 *req); 902 int apmf_get_sbios_requests_v2(struct amd_pmf_dev *pdev, struct apmf_sbios_req_v2 *req); 903 904 void amd_pmf_update_2_cql(struct amd_pmf_dev *dev, bool is_cql_event); 905 int amd_pmf_reset_amt(struct amd_pmf_dev *dev); 906 void amd_pmf_handle_amt(struct amd_pmf_dev *dev); 907 908 /* CnQF Layer */ 909 int apmf_get_dyn_slider_def_ac(struct amd_pmf_dev *pdev, struct apmf_dyn_slider_output *data); 910 int apmf_get_dyn_slider_def_dc(struct amd_pmf_dev *pdev, struct apmf_dyn_slider_output *data); 911 int amd_pmf_init_cnqf(struct amd_pmf_dev *dev); 912 void amd_pmf_deinit_cnqf(struct amd_pmf_dev *dev); 913 int amd_pmf_trans_cnqf(struct amd_pmf_dev *dev, int socket_power, ktime_t time_lapsed_ms); 914 extern const struct attribute_group cnqf_feature_attribute_group; 915 916 /* Smart PC builder Layer */ 917 int amd_pmf_init_smart_pc(struct amd_pmf_dev *dev); 918 void amd_pmf_deinit_smart_pc(struct amd_pmf_dev *dev); 919 int apmf_check_smart_pc(struct amd_pmf_dev *pmf_dev); 920 int amd_pmf_smartpc_apply_bios_output(struct amd_pmf_dev *dev, u32 val, u32 preq, u32 idx); 921 922 /* Smart PC - TA interfaces */ 923 void amd_pmf_populate_ta_inputs(struct amd_pmf_dev *dev, struct ta_pmf_enact_table *in); 924 void amd_pmf_dump_ta_inputs(struct amd_pmf_dev *dev, struct ta_pmf_enact_table *in); 925 int amd_pmf_invoke_cmd_enact(struct amd_pmf_dev *dev); 926 927 int amd_pmf_tee_init(struct amd_pmf_dev *dev, const uuid_t *uuid); 928 void amd_pmf_tee_deinit(struct amd_pmf_dev *dev); 929 int amd_pmf_start_policy_engine(struct amd_pmf_dev *dev); 930 931 #endif /* PMF_H */ 932