1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 /* 3 * Copyright (c) 2024 Amlogic, Inc. All rights reserved. 4 * Author: Xianwei Zhao <xianwei.zhao@amlogic.com> 5 */ 6 7 #include <linux/err.h> 8 #include <linux/gpio/driver.h> 9 #include <linux/init.h> 10 #include <linux/io.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/of_address.h> 14 #include <linux/platform_device.h> 15 #include <linux/regmap.h> 16 #include <linux/seq_file.h> 17 #include <linux/slab.h> 18 #include <linux/string_helpers.h> 19 20 #include <linux/pinctrl/consumer.h> 21 #include <linux/pinctrl/pinconf.h> 22 #include <linux/pinctrl/pinctrl.h> 23 #include <linux/pinctrl/pinmux.h> 24 #include <dt-bindings/pinctrl/amlogic,pinctrl.h> 25 26 #include "../core.h" 27 #include "../pinctrl-utils.h" 28 #include "../pinconf.h" 29 30 #define gpio_chip_to_bank(chip) \ 31 container_of(chip, struct aml_gpio_bank, gpio_chip) 32 33 #define AML_REG_PULLEN 0 34 #define AML_REG_PULL 1 35 #define AML_REG_DIR 2 36 #define AML_REG_OUT 3 37 #define AML_REG_IN 4 38 #define AML_REG_DS 5 39 #define AML_NUM_REG 6 40 41 enum aml_pinconf_drv { 42 PINCONF_DRV_500UA, 43 PINCONF_DRV_2500UA, 44 PINCONF_DRV_3000UA, 45 PINCONF_DRV_4000UA, 46 }; 47 48 struct aml_pio_control { 49 u32 gpio_offset; 50 u32 reg_offset[AML_NUM_REG]; 51 u32 bit_offset[AML_NUM_REG]; 52 }; 53 54 /* 55 * partial bank(subordinate) pins mux config use other bank(main) mux registgers 56 * m_bank_id: the main bank which pin_id from 0, but register bit not from bit 0 57 * m_bit_offs: bit offset the main bank mux register 58 * s_bit_offs: start bit that subordinate bank use mux register 59 * sid: start pin_id of subordinate bank 60 * eid: end pin_id of subordinate bank 61 * next: subordinate bank reused multiple other bank groups. 62 */ 63 struct multi_mux { 64 unsigned int m_bank_id; 65 unsigned int m_bit_offs; 66 unsigned int s_bit_offs; 67 unsigned int sid; 68 unsigned int eid; 69 const struct multi_mux *next; 70 }; 71 72 struct aml_pctl_data { 73 unsigned int number; 74 const struct multi_mux *p_mux; 75 }; 76 77 struct aml_pmx_func { 78 const char *name; 79 const char **groups; 80 unsigned int ngroups; 81 }; 82 83 struct aml_pctl_group { 84 const char *name; 85 unsigned int npins; 86 unsigned int *pins; 87 unsigned int *func; 88 }; 89 90 struct aml_gpio_bank { 91 struct gpio_chip gpio_chip; 92 struct aml_pio_control pc; 93 u32 bank_id; 94 u32 mux_bit_offs; 95 unsigned int pin_base; 96 struct regmap *reg_mux; 97 struct regmap *reg_gpio; 98 struct regmap *reg_ds; 99 const struct multi_mux *p_mux; 100 }; 101 102 struct aml_pinctrl { 103 struct device *dev; 104 struct pinctrl_dev *pctl; 105 struct aml_gpio_bank *banks; 106 int nbanks; 107 struct aml_pmx_func *functions; 108 int nfunctions; 109 struct aml_pctl_group *groups; 110 int ngroups; 111 112 const struct aml_pctl_data *data; 113 }; 114 115 static const unsigned int aml_bit_strides[AML_NUM_REG] = { 116 1, 1, 1, 1, 1, 2 117 }; 118 119 static const unsigned int aml_def_regoffs[AML_NUM_REG] = { 120 3, 4, 2, 1, 0, 7 121 }; 122 123 static const char *aml_bank_name[31] = { 124 "GPIOA", "GPIOB", "GPIOC", "GPIOD", "GPIOE", "GPIOF", "GPIOG", 125 "GPIOH", "GPIOI", "GPIOJ", "GPIOK", "GPIOL", "GPIOM", "GPION", 126 "GPIOO", "GPIOP", "GPIOQ", "GPIOR", "GPIOS", "GPIOT", "GPIOU", 127 "GPIOV", "GPIOW", "GPIOX", "GPIOY", "GPIOZ", "GPIODV", "GPIOAO", 128 "GPIOCC", "TEST_N", "ANALOG" 129 }; 130 131 static const struct multi_mux multi_mux_a9[] = { 132 { 133 .m_bank_id = AMLOGIC_GPIO_C, 134 .m_bit_offs = 4, 135 .s_bit_offs = 0, 136 .sid = (AMLOGIC_GPIO_D << 8) + 16, 137 .eid = (AMLOGIC_GPIO_D << 8) + 16, 138 .next = &multi_mux_a9[1], 139 }, { 140 .m_bank_id = AMLOGIC_GPIO_AO, 141 .m_bit_offs = 0, 142 .s_bit_offs = 52, 143 .sid = (AMLOGIC_GPIO_D << 8) + 17, 144 .eid = (AMLOGIC_GPIO_D << 8) + 17, 145 .next = NULL, 146 }, { 147 .m_bank_id = AMLOGIC_GPIO_A, 148 .m_bit_offs = 0, 149 .s_bit_offs = 80, 150 .sid = (AMLOGIC_GPIO_Y << 8) + 8, 151 .eid = (AMLOGIC_GPIO_Y << 8) + 9, 152 .next = NULL, 153 }, { 154 .m_bank_id = AMLOGIC_GPIO_CC, 155 .m_bit_offs = 24, 156 .s_bit_offs = 0, 157 .sid = (AMLOGIC_GPIO_X << 8) + 16, 158 .eid = (AMLOGIC_GPIO_X << 8) + 17, 159 .next = NULL, 160 }, 161 }; 162 163 static const struct aml_pctl_data a9_priv_data = { 164 .number = ARRAY_SIZE(multi_mux_a9), 165 .p_mux = multi_mux_a9, 166 }; 167 168 static const struct multi_mux multi_mux_s7[] = { 169 { 170 .m_bank_id = AMLOGIC_GPIO_CC, 171 .m_bit_offs = 24, 172 .s_bit_offs = 0, 173 .sid = (AMLOGIC_GPIO_X << 8) + 16, 174 .eid = (AMLOGIC_GPIO_X << 8) + 19, 175 .next = NULL, 176 }, 177 }; 178 179 static const struct aml_pctl_data s7_priv_data = { 180 .number = ARRAY_SIZE(multi_mux_s7), 181 .p_mux = multi_mux_s7, 182 }; 183 184 static const struct multi_mux multi_mux_s6[] = { 185 { 186 .m_bank_id = AMLOGIC_GPIO_CC, 187 .m_bit_offs = 24, 188 .s_bit_offs = 0, 189 .sid = (AMLOGIC_GPIO_X << 8) + 16, 190 .eid = (AMLOGIC_GPIO_X << 8) + 19, 191 .next = NULL, 192 }, { 193 .m_bank_id = AMLOGIC_GPIO_F, 194 .m_bit_offs = 4, 195 .s_bit_offs = 0, 196 .sid = (AMLOGIC_GPIO_D << 8) + 6, 197 .eid = (AMLOGIC_GPIO_D << 8) + 6, 198 .next = NULL, 199 }, 200 }; 201 202 static const struct aml_pctl_data s6_priv_data = { 203 .number = ARRAY_SIZE(multi_mux_s6), 204 .p_mux = multi_mux_s6, 205 }; 206 207 static int aml_pmx_calc_reg_and_offset(struct pinctrl_gpio_range *range, 208 unsigned int pin, unsigned int *reg, 209 unsigned int *offset) 210 { 211 unsigned int shift; 212 213 shift = ((pin - range->pin_base) << 2) + *offset; 214 *reg = (shift / 32) * 4; 215 *offset = shift % 32; 216 217 return 0; 218 } 219 220 static int aml_pctl_set_function(struct aml_pinctrl *info, 221 struct pinctrl_gpio_range *range, 222 int pin_id, int func) 223 { 224 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); 225 unsigned int shift; 226 int reg; 227 int i, loop_count; 228 unsigned int offset = bank->mux_bit_offs; 229 const struct multi_mux *p_mux; 230 231 /* peculiar mux reg set */ 232 loop_count = 10; 233 p_mux = bank->p_mux; 234 while (p_mux && loop_count) { 235 if (pin_id >= p_mux->sid && pin_id <= p_mux->eid) { 236 bank = NULL; 237 for (i = 0; i < info->nbanks; i++) { 238 if (info->banks[i].bank_id == p_mux->m_bank_id) { 239 bank = &info->banks[i]; 240 break; 241 } 242 } 243 244 if (!bank || !bank->reg_mux) 245 return -EINVAL; 246 247 shift = ((pin_id - p_mux->sid) << 2) + p_mux->s_bit_offs; 248 reg = (shift / 32) * 4; 249 offset = shift % 32; 250 return regmap_update_bits(bank->reg_mux, reg, 251 0xf << offset, (func & 0xf) << offset); 252 } 253 p_mux = p_mux->next; 254 loop_count--; 255 } 256 257 /* normal mux reg set */ 258 if (!bank->reg_mux) 259 return 0; 260 261 aml_pmx_calc_reg_and_offset(range, pin_id, ®, &offset); 262 return regmap_update_bits(bank->reg_mux, reg, 263 0xf << offset, (func & 0xf) << offset); 264 } 265 266 static int aml_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 267 { 268 struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 269 270 return info->nfunctions; 271 } 272 273 static const char *aml_pmx_get_fname(struct pinctrl_dev *pctldev, 274 unsigned int selector) 275 { 276 struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 277 278 return info->functions[selector].name; 279 } 280 281 static int aml_pmx_get_groups(struct pinctrl_dev *pctldev, 282 unsigned int selector, 283 const char * const **grps, 284 unsigned * const ngrps) 285 { 286 struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 287 288 *grps = info->functions[selector].groups; 289 *ngrps = info->functions[selector].ngroups; 290 291 return 0; 292 } 293 294 static int aml_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned int fselector, 295 unsigned int group_id) 296 { 297 struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 298 struct aml_pctl_group *group = &info->groups[group_id]; 299 struct pinctrl_gpio_range *range; 300 int i; 301 302 for (i = 0; i < group->npins; i++) { 303 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, group->pins[i]); 304 aml_pctl_set_function(info, range, group->pins[i], group->func[i]); 305 } 306 307 return 0; 308 } 309 310 static int aml_pmx_request_gpio(struct pinctrl_dev *pctldev, 311 struct pinctrl_gpio_range *range, 312 unsigned int pin) 313 { 314 struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 315 316 return aml_pctl_set_function(info, range, pin, 0); 317 } 318 319 static const struct pinmux_ops aml_pmx_ops = { 320 .set_mux = aml_pmx_set_mux, 321 .get_functions_count = aml_pmx_get_funcs_count, 322 .get_function_name = aml_pmx_get_fname, 323 .get_function_groups = aml_pmx_get_groups, 324 .gpio_request_enable = aml_pmx_request_gpio, 325 }; 326 327 static int aml_calc_reg_and_bit(struct pinctrl_gpio_range *range, 328 unsigned int pin, 329 unsigned int reg_type, 330 unsigned int *reg, unsigned int *bit) 331 { 332 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); 333 334 *bit = (pin - range->pin_base) * aml_bit_strides[reg_type] 335 + bank->pc.bit_offset[reg_type]; 336 *reg = (bank->pc.reg_offset[reg_type] + (*bit / 32)) * 4; 337 *bit &= 0x1f; 338 339 return 0; 340 } 341 342 static int aml_pinconf_get_pull(struct aml_pinctrl *info, unsigned int pin) 343 { 344 struct pinctrl_gpio_range *range = 345 pinctrl_find_gpio_range_from_pin_nolock(info->pctl, pin); 346 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); 347 unsigned int reg, bit, val; 348 int ret, conf; 349 350 aml_calc_reg_and_bit(range, pin, AML_REG_PULLEN, ®, &bit); 351 352 ret = regmap_read(bank->reg_gpio, reg, &val); 353 if (ret) 354 return ret; 355 356 if (!(val & BIT(bit))) { 357 conf = PIN_CONFIG_BIAS_DISABLE; 358 } else { 359 aml_calc_reg_and_bit(range, pin, AML_REG_PULL, ®, &bit); 360 361 ret = regmap_read(bank->reg_gpio, reg, &val); 362 if (ret) 363 return ret; 364 365 if (val & BIT(bit)) 366 conf = PIN_CONFIG_BIAS_PULL_UP; 367 else 368 conf = PIN_CONFIG_BIAS_PULL_DOWN; 369 } 370 371 return conf; 372 } 373 374 static int aml_pinconf_get_drive_strength(struct aml_pinctrl *info, 375 unsigned int pin, 376 u16 *drive_strength_ua) 377 { 378 struct pinctrl_gpio_range *range = 379 pinctrl_find_gpio_range_from_pin_nolock(info->pctl, pin); 380 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); 381 unsigned int reg, bit; 382 unsigned int val; 383 int ret; 384 385 if (!bank->reg_ds) 386 return -EOPNOTSUPP; 387 388 aml_calc_reg_and_bit(range, pin, AML_REG_DS, ®, &bit); 389 ret = regmap_read(bank->reg_ds, reg, &val); 390 if (ret) 391 return ret; 392 393 switch ((val >> bit) & 0x3) { 394 case PINCONF_DRV_500UA: 395 *drive_strength_ua = 500; 396 break; 397 case PINCONF_DRV_2500UA: 398 *drive_strength_ua = 2500; 399 break; 400 case PINCONF_DRV_3000UA: 401 *drive_strength_ua = 3000; 402 break; 403 case PINCONF_DRV_4000UA: 404 *drive_strength_ua = 4000; 405 break; 406 default: 407 return -EINVAL; 408 } 409 410 return 0; 411 } 412 413 static int aml_pinconf_get_gpio_bit(struct aml_pinctrl *info, 414 unsigned int pin, 415 unsigned int reg_type) 416 { 417 struct pinctrl_gpio_range *range = 418 pinctrl_find_gpio_range_from_pin_nolock(info->pctl, pin); 419 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); 420 unsigned int reg, bit, val; 421 int ret; 422 423 aml_calc_reg_and_bit(range, pin, reg_type, ®, &bit); 424 ret = regmap_read(bank->reg_gpio, reg, &val); 425 if (ret) 426 return ret; 427 428 return BIT(bit) & val ? 1 : 0; 429 } 430 431 static int aml_pinconf_get_output(struct aml_pinctrl *info, 432 unsigned int pin) 433 { 434 int ret = aml_pinconf_get_gpio_bit(info, pin, AML_REG_DIR); 435 436 if (ret < 0) 437 return ret; 438 439 return !ret; 440 } 441 442 static int aml_pinconf_get_drive(struct aml_pinctrl *info, 443 unsigned int pin) 444 { 445 return aml_pinconf_get_gpio_bit(info, pin, AML_REG_OUT); 446 } 447 448 static int aml_pinconf_get(struct pinctrl_dev *pcdev, unsigned int pin, 449 unsigned long *config) 450 { 451 struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pcdev); 452 enum pin_config_param param = pinconf_to_config_param(*config); 453 u16 arg; 454 int ret; 455 456 switch (param) { 457 case PIN_CONFIG_BIAS_DISABLE: 458 case PIN_CONFIG_BIAS_PULL_DOWN: 459 case PIN_CONFIG_BIAS_PULL_UP: 460 if (aml_pinconf_get_pull(info, pin) == param) 461 arg = 1; 462 else 463 return -EINVAL; 464 break; 465 case PIN_CONFIG_DRIVE_STRENGTH_UA: 466 ret = aml_pinconf_get_drive_strength(info, pin, &arg); 467 if (ret) 468 return ret; 469 break; 470 case PIN_CONFIG_OUTPUT_ENABLE: 471 ret = aml_pinconf_get_output(info, pin); 472 if (ret <= 0) 473 return -EINVAL; 474 arg = 1; 475 break; 476 case PIN_CONFIG_LEVEL: 477 ret = aml_pinconf_get_output(info, pin); 478 if (ret <= 0) 479 return -EINVAL; 480 481 ret = aml_pinconf_get_drive(info, pin); 482 if (ret < 0) 483 return -EINVAL; 484 485 arg = ret; 486 break; 487 488 default: 489 return -ENOTSUPP; 490 } 491 492 *config = pinconf_to_config_packed(param, arg); 493 dev_dbg(info->dev, "pinconf for pin %u is %lu\n", pin, *config); 494 495 return 0; 496 } 497 498 static int aml_pinconf_disable_bias(struct aml_pinctrl *info, 499 unsigned int pin) 500 { 501 struct pinctrl_gpio_range *range = 502 pinctrl_find_gpio_range_from_pin_nolock(info->pctl, pin); 503 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); 504 unsigned int reg, bit = 0; 505 506 aml_calc_reg_and_bit(range, pin, AML_REG_PULLEN, ®, &bit); 507 508 return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), 0); 509 } 510 511 static int aml_pinconf_enable_bias(struct aml_pinctrl *info, unsigned int pin, 512 bool pull_up) 513 { 514 struct pinctrl_gpio_range *range = 515 pinctrl_find_gpio_range_from_pin_nolock(info->pctl, pin); 516 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); 517 unsigned int reg, bit, val = 0; 518 int ret; 519 520 aml_calc_reg_and_bit(range, pin, AML_REG_PULL, ®, &bit); 521 if (pull_up) 522 val = BIT(bit); 523 524 ret = regmap_update_bits(bank->reg_gpio, reg, BIT(bit), val); 525 if (ret) 526 return ret; 527 528 aml_calc_reg_and_bit(range, pin, AML_REG_PULLEN, ®, &bit); 529 return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), BIT(bit)); 530 } 531 532 static int aml_pinconf_set_drive_strength(struct aml_pinctrl *info, 533 unsigned int pin, 534 u16 drive_strength_ua) 535 { 536 struct pinctrl_gpio_range *range = 537 pinctrl_find_gpio_range_from_pin_nolock(info->pctl, pin); 538 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); 539 unsigned int reg, bit, ds_val; 540 541 if (!bank->reg_ds) { 542 dev_err(info->dev, "drive-strength not supported\n"); 543 return -EOPNOTSUPP; 544 } 545 546 aml_calc_reg_and_bit(range, pin, AML_REG_DS, ®, &bit); 547 548 if (drive_strength_ua <= 500) { 549 ds_val = PINCONF_DRV_500UA; 550 } else if (drive_strength_ua <= 2500) { 551 ds_val = PINCONF_DRV_2500UA; 552 } else if (drive_strength_ua <= 3000) { 553 ds_val = PINCONF_DRV_3000UA; 554 } else if (drive_strength_ua <= 4000) { 555 ds_val = PINCONF_DRV_4000UA; 556 } else { 557 dev_warn_once(info->dev, 558 "pin %u: invalid drive-strength : %d , default to 4mA\n", 559 pin, drive_strength_ua); 560 ds_val = PINCONF_DRV_4000UA; 561 } 562 563 return regmap_update_bits(bank->reg_ds, reg, 0x3 << bit, ds_val << bit); 564 } 565 566 static int aml_pinconf_set_gpio_bit(struct aml_pinctrl *info, 567 unsigned int pin, 568 unsigned int reg_type, 569 bool arg) 570 { 571 struct pinctrl_gpio_range *range = 572 pinctrl_find_gpio_range_from_pin_nolock(info->pctl, pin); 573 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); 574 unsigned int reg, bit; 575 576 aml_calc_reg_and_bit(range, pin, reg_type, ®, &bit); 577 return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), 578 arg ? BIT(bit) : 0); 579 } 580 581 static int aml_pinconf_set_output(struct aml_pinctrl *info, 582 unsigned int pin, 583 bool out) 584 { 585 return aml_pinconf_set_gpio_bit(info, pin, AML_REG_DIR, !out); 586 } 587 588 static int aml_pinconf_set_drive(struct aml_pinctrl *info, 589 unsigned int pin, 590 bool high) 591 { 592 return aml_pinconf_set_gpio_bit(info, pin, AML_REG_OUT, high); 593 } 594 595 static int aml_pinconf_set_output_drive(struct aml_pinctrl *info, 596 unsigned int pin, 597 bool high) 598 { 599 int ret; 600 601 ret = aml_pinconf_set_drive(info, pin, high); 602 if (ret) 603 return ret; 604 605 return aml_pinconf_set_output(info, pin, true); 606 } 607 608 static int aml_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin, 609 unsigned long *configs, unsigned int num_configs) 610 { 611 struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pcdev); 612 enum pin_config_param param; 613 unsigned int arg = 0; 614 int i, ret; 615 616 for (i = 0; i < num_configs; i++) { 617 param = pinconf_to_config_param(configs[i]); 618 619 switch (param) { 620 case PIN_CONFIG_DRIVE_STRENGTH_UA: 621 case PIN_CONFIG_OUTPUT_ENABLE: 622 case PIN_CONFIG_LEVEL: 623 arg = pinconf_to_config_argument(configs[i]); 624 break; 625 626 default: 627 break; 628 } 629 630 switch (param) { 631 case PIN_CONFIG_BIAS_DISABLE: 632 ret = aml_pinconf_disable_bias(info, pin); 633 break; 634 case PIN_CONFIG_BIAS_PULL_UP: 635 ret = aml_pinconf_enable_bias(info, pin, true); 636 break; 637 case PIN_CONFIG_BIAS_PULL_DOWN: 638 ret = aml_pinconf_enable_bias(info, pin, false); 639 break; 640 case PIN_CONFIG_DRIVE_STRENGTH_UA: 641 ret = aml_pinconf_set_drive_strength(info, pin, arg); 642 break; 643 case PIN_CONFIG_OUTPUT_ENABLE: 644 ret = aml_pinconf_set_output(info, pin, arg); 645 break; 646 case PIN_CONFIG_LEVEL: 647 ret = aml_pinconf_set_output_drive(info, pin, arg); 648 break; 649 default: 650 ret = -ENOTSUPP; 651 } 652 653 if (ret) 654 return ret; 655 } 656 657 return 0; 658 } 659 660 static int aml_pinconf_group_set(struct pinctrl_dev *pcdev, 661 unsigned int num_group, 662 unsigned long *configs, 663 unsigned int num_configs) 664 { 665 struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pcdev); 666 int i; 667 668 for (i = 0; i < info->groups[num_group].npins; i++) { 669 aml_pinconf_set(pcdev, info->groups[num_group].pins[i], configs, 670 num_configs); 671 } 672 673 return 0; 674 } 675 676 static int aml_pinconf_group_get(struct pinctrl_dev *pcdev, 677 unsigned int group, unsigned long *config) 678 { 679 return -EOPNOTSUPP; 680 } 681 682 static const struct pinconf_ops aml_pinconf_ops = { 683 .pin_config_get = aml_pinconf_get, 684 .pin_config_set = aml_pinconf_set, 685 .pin_config_group_get = aml_pinconf_group_get, 686 .pin_config_group_set = aml_pinconf_group_set, 687 .is_generic = true, 688 }; 689 690 static int aml_get_groups_count(struct pinctrl_dev *pctldev) 691 { 692 struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 693 694 return info->ngroups; 695 } 696 697 static const char *aml_get_group_name(struct pinctrl_dev *pctldev, 698 unsigned int selector) 699 { 700 struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 701 702 return info->groups[selector].name; 703 } 704 705 static int aml_get_group_pins(struct pinctrl_dev *pctldev, 706 unsigned int selector, const unsigned int **pins, 707 unsigned int *npins) 708 { 709 struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 710 711 if (selector >= info->ngroups) 712 return -EINVAL; 713 714 *pins = info->groups[selector].pins; 715 *npins = info->groups[selector].npins; 716 717 return 0; 718 } 719 720 static void aml_pin_dbg_show(struct pinctrl_dev *pcdev, struct seq_file *s, 721 unsigned int offset) 722 { 723 seq_printf(s, " %s", dev_name(pcdev->dev)); 724 } 725 726 static int aml_dt_node_to_map_pinmux(struct pinctrl_dev *pctldev, 727 struct device_node *np, 728 struct pinctrl_map **map, 729 unsigned int *num_maps) 730 { 731 struct device *dev = pctldev->dev; 732 unsigned long *configs = NULL; 733 unsigned int num_configs = 0; 734 struct property *prop; 735 unsigned int reserved_maps; 736 int reserve; 737 int ret; 738 739 prop = of_find_property(np, "pinmux", NULL); 740 if (!prop) { 741 dev_info(dev, "Missing pinmux property\n"); 742 return -ENOENT; 743 } 744 745 struct device_node *pnode __free(device_node) = of_get_parent(np); 746 if (!pnode) { 747 dev_info(dev, "Missing function node\n"); 748 return -EINVAL; 749 } 750 751 reserved_maps = 0; 752 *map = NULL; 753 *num_maps = 0; 754 755 ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, 756 &num_configs); 757 if (ret < 0) { 758 dev_err(dev, "%pOF: could not parse node property\n", np); 759 return ret; 760 } 761 762 reserve = 1; 763 if (num_configs) 764 reserve++; 765 766 ret = pinctrl_utils_reserve_map(pctldev, map, &reserved_maps, 767 num_maps, reserve); 768 if (ret < 0) 769 goto exit; 770 771 ret = pinctrl_utils_add_map_mux(pctldev, map, 772 &reserved_maps, num_maps, np->name, 773 pnode->name); 774 if (ret < 0) 775 goto exit; 776 777 if (num_configs) { 778 ret = pinctrl_utils_add_map_configs(pctldev, map, &reserved_maps, 779 num_maps, np->name, configs, 780 num_configs, PIN_MAP_TYPE_CONFIGS_GROUP); 781 if (ret < 0) 782 goto exit; 783 } 784 785 exit: 786 kfree(configs); 787 if (ret) 788 pinctrl_utils_free_map(pctldev, *map, *num_maps); 789 790 return ret; 791 } 792 793 static const struct pinctrl_ops aml_pctrl_ops = { 794 .get_groups_count = aml_get_groups_count, 795 .get_group_name = aml_get_group_name, 796 .get_group_pins = aml_get_group_pins, 797 .dt_node_to_map = aml_dt_node_to_map_pinmux, 798 .dt_free_map = pinconf_generic_dt_free_map, 799 .pin_dbg_show = aml_pin_dbg_show, 800 }; 801 802 static int aml_pctl_parse_functions(struct device_node *np, 803 struct aml_pinctrl *info, u32 index, 804 int *grp_index) 805 { 806 struct device *dev = info->dev; 807 struct aml_pmx_func *func; 808 struct aml_pctl_group *grp; 809 int ret, i; 810 811 func = &info->functions[index]; 812 func->name = np->name; 813 func->ngroups = of_get_child_count(np); 814 if (func->ngroups == 0) 815 return dev_err_probe(dev, -EINVAL, "No groups defined\n"); 816 817 func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL); 818 if (!func->groups) 819 return -ENOMEM; 820 821 i = 0; 822 for_each_child_of_node_scoped(np, child) { 823 func->groups[i++] = child->name; 824 grp = &info->groups[*grp_index]; 825 grp->name = child->name; 826 *grp_index += 1; 827 ret = pinconf_generic_parse_dt_pinmux(child, dev, &grp->pins, 828 &grp->func, &grp->npins); 829 if (ret) { 830 dev_err(dev, "function :%s, groups:%s fail\n", func->name, child->name); 831 return ret; 832 } 833 } 834 dev_dbg(dev, "Function[%d\t name:%s,\tgroups:%d]\n", index, func->name, func->ngroups); 835 836 return 0; 837 } 838 839 static u32 aml_bank_pins(struct device_node *np) 840 { 841 struct of_phandle_args of_args; 842 843 if (of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 844 0, &of_args)) 845 return 0; 846 847 of_node_put(of_args.np); 848 return of_args.args[2]; 849 } 850 851 static int aml_bank_number(struct device_node *np) 852 { 853 struct of_phandle_args of_args; 854 855 if (of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 856 0, &of_args)) 857 return -EINVAL; 858 859 of_node_put(of_args.np); 860 return of_args.args[1] >> 8; 861 } 862 863 static unsigned int aml_count_pins(struct device_node *np) 864 { 865 struct device_node *child; 866 unsigned int pins = 0; 867 868 for_each_child_of_node(np, child) { 869 if (of_property_read_bool(child, "gpio-controller")) 870 pins += aml_bank_pins(child); 871 } 872 873 return pins; 874 } 875 876 /* 877 * A pinctrl device contains two types of nodes. The one named GPIO 878 * bank which includes gpio-controller property. The other one named 879 * function which includes one or more pin groups. The pin group 880 * include pinmux property(global index in pinctrl dev, and mux vlaue 881 * in mux reg) and pin configuration properties. 882 */ 883 static void aml_pctl_dt_child_count(struct aml_pinctrl *info, 884 struct device_node *np) 885 { 886 struct device_node *child; 887 888 for_each_child_of_node(np, child) { 889 if (of_property_read_bool(child, "gpio-controller")) { 890 info->nbanks++; 891 } else { 892 info->nfunctions++; 893 info->ngroups += of_get_child_count(child); 894 } 895 } 896 } 897 898 static struct regmap *aml_map_resource(struct device *dev, unsigned int id, 899 struct device_node *node, char *name) 900 { 901 struct resource res; 902 void __iomem *base; 903 int i; 904 905 struct regmap_config aml_regmap_config = { 906 .reg_bits = 32, 907 .val_bits = 32, 908 .reg_stride = 4, 909 }; 910 911 i = of_property_match_string(node, "reg-names", name); 912 if (i < 0) 913 return NULL; 914 if (of_address_to_resource(node, i, &res)) 915 return NULL; 916 base = devm_ioremap_resource(dev, &res); 917 if (IS_ERR(base)) 918 return ERR_CAST(base); 919 920 aml_regmap_config.max_register = resource_size(&res) - 4; 921 aml_regmap_config.name = devm_kasprintf(dev, GFP_KERNEL, 922 "%s-%s", aml_bank_name[id], name); 923 if (!aml_regmap_config.name) 924 return ERR_PTR(-ENOMEM); 925 926 return devm_regmap_init_mmio(dev, base, &aml_regmap_config); 927 } 928 929 static inline int aml_gpio_calc_reg_and_bit(struct aml_gpio_bank *bank, 930 unsigned int reg_type, 931 unsigned int gpio, 932 unsigned int *reg, 933 unsigned int *bit) 934 { 935 *bit = gpio * aml_bit_strides[reg_type] + bank->pc.bit_offset[reg_type]; 936 *reg = (bank->pc.reg_offset[reg_type] + (*bit / 32)) * 4; 937 *bit &= 0x1f; 938 939 return 0; 940 } 941 942 static int aml_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio) 943 { 944 struct aml_gpio_bank *bank = gpiochip_get_data(chip); 945 unsigned int bit, reg, val; 946 int ret; 947 948 aml_gpio_calc_reg_and_bit(bank, AML_REG_DIR, gpio, ®, &bit); 949 950 ret = regmap_read(bank->reg_gpio, reg, &val); 951 if (ret) 952 return ret; 953 954 return BIT(bit) & val ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT; 955 } 956 957 static int aml_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio) 958 { 959 struct aml_gpio_bank *bank = gpiochip_get_data(chip); 960 unsigned int bit, reg; 961 962 aml_gpio_calc_reg_and_bit(bank, AML_REG_DIR, gpio, ®, &bit); 963 964 return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), BIT(bit)); 965 } 966 967 static int aml_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio, 968 int value) 969 { 970 struct aml_gpio_bank *bank = gpiochip_get_data(chip); 971 unsigned int bit, reg; 972 int ret; 973 974 aml_gpio_calc_reg_and_bit(bank, AML_REG_OUT, gpio, ®, &bit); 975 ret = regmap_update_bits(bank->reg_gpio, reg, BIT(bit), 976 value ? BIT(bit) : 0); 977 if (ret < 0) 978 return ret; 979 980 aml_gpio_calc_reg_and_bit(bank, AML_REG_DIR, gpio, ®, &bit); 981 return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), 0); 982 } 983 984 static int aml_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value) 985 { 986 struct aml_gpio_bank *bank = gpiochip_get_data(chip); 987 unsigned int bit, reg; 988 989 aml_gpio_calc_reg_and_bit(bank, AML_REG_OUT, gpio, ®, &bit); 990 991 return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), 992 value ? BIT(bit) : 0); 993 } 994 995 static int aml_gpio_get(struct gpio_chip *chip, unsigned int gpio) 996 { 997 struct aml_gpio_bank *bank = gpiochip_get_data(chip); 998 unsigned int reg, bit, val; 999 1000 aml_gpio_calc_reg_and_bit(bank, AML_REG_IN, gpio, ®, &bit); 1001 regmap_read(bank->reg_gpio, reg, &val); 1002 1003 return !!(val & BIT(bit)); 1004 } 1005 1006 static const struct gpio_chip aml_gpio_template = { 1007 .request = gpiochip_generic_request, 1008 .free = gpiochip_generic_free, 1009 .set_config = gpiochip_generic_config, 1010 .set = aml_gpio_set, 1011 .get = aml_gpio_get, 1012 .direction_input = aml_gpio_direction_input, 1013 .direction_output = aml_gpio_direction_output, 1014 .get_direction = aml_gpio_get_direction, 1015 .can_sleep = true, 1016 }; 1017 1018 static void init_bank_register_bit(struct aml_pinctrl *info, 1019 struct aml_gpio_bank *bank) 1020 { 1021 const struct aml_pctl_data *data = info->data; 1022 const struct multi_mux *p_mux; 1023 int i; 1024 1025 for (i = 0; i < AML_NUM_REG; i++) { 1026 bank->pc.reg_offset[i] = aml_def_regoffs[i]; 1027 bank->pc.bit_offset[i] = 0; 1028 } 1029 1030 bank->mux_bit_offs = 0; 1031 1032 if (data) { 1033 for (i = 0; i < data->number; i++) { 1034 p_mux = &data->p_mux[i]; 1035 if (bank->bank_id == p_mux->m_bank_id) { 1036 bank->mux_bit_offs = p_mux->m_bit_offs; 1037 break; 1038 } 1039 if (p_mux->sid >> 8 == bank->bank_id) { 1040 bank->p_mux = p_mux; 1041 break; 1042 } 1043 } 1044 } 1045 } 1046 1047 static int aml_gpiolib_register_bank(struct aml_pinctrl *info, 1048 int bank_nr, struct device_node *np) 1049 { 1050 struct aml_gpio_bank *bank = &info->banks[bank_nr]; 1051 struct device *dev = info->dev; 1052 int ret = 0; 1053 1054 ret = aml_bank_number(np); 1055 if (ret < 0) { 1056 dev_err(dev, "get num=%d bank identity fail\n", bank_nr); 1057 return -EINVAL; 1058 } 1059 bank->bank_id = ret; 1060 1061 bank->reg_mux = aml_map_resource(dev, bank->bank_id, np, "mux"); 1062 if (IS_ERR_OR_NULL(bank->reg_mux)) { 1063 if (bank->bank_id == AMLOGIC_GPIO_TEST_N || 1064 bank->bank_id == AMLOGIC_GPIO_ANALOG) 1065 bank->reg_mux = NULL; 1066 else 1067 return dev_err_probe(dev, bank->reg_mux ? PTR_ERR(bank->reg_mux) : -ENOENT, 1068 "mux registers not found\n"); 1069 } 1070 1071 bank->reg_gpio = aml_map_resource(dev, bank->bank_id, np, "gpio"); 1072 if (IS_ERR_OR_NULL(bank->reg_gpio)) 1073 return dev_err_probe(dev, bank->reg_gpio ? PTR_ERR(bank->reg_gpio) : -ENOENT, 1074 "gpio registers not found\n"); 1075 1076 bank->reg_ds = aml_map_resource(dev, bank->bank_id, np, "ds"); 1077 if (IS_ERR_OR_NULL(bank->reg_ds)) { 1078 dev_dbg(info->dev, "ds registers not found - skipping\n"); 1079 bank->reg_ds = bank->reg_gpio; 1080 } 1081 1082 bank->gpio_chip = aml_gpio_template; 1083 bank->gpio_chip.base = -1; 1084 bank->gpio_chip.ngpio = aml_bank_pins(np); 1085 bank->gpio_chip.fwnode = of_fwnode_handle(np); 1086 bank->gpio_chip.parent = dev; 1087 1088 init_bank_register_bit(info, bank); 1089 bank->gpio_chip.label = aml_bank_name[bank->bank_id]; 1090 1091 bank->pin_base = bank->bank_id << 8; 1092 1093 return 0; 1094 } 1095 1096 static int aml_pctl_probe_dt(struct platform_device *pdev, 1097 struct pinctrl_desc *pctl_desc, 1098 struct aml_pinctrl *info) 1099 { 1100 struct device *dev = &pdev->dev; 1101 struct pinctrl_pin_desc *pdesc; 1102 struct device_node *np = dev->of_node; 1103 int grp_index = 0; 1104 int i = 0, j = 0, k = 0, bank; 1105 int ret = 0; 1106 1107 aml_pctl_dt_child_count(info, np); 1108 if (!info->nbanks) 1109 return dev_err_probe(dev, -EINVAL, "you need at least one gpio bank\n"); 1110 1111 dev_dbg(dev, "nbanks = %d\n", info->nbanks); 1112 dev_dbg(dev, "nfunctions = %d\n", info->nfunctions); 1113 dev_dbg(dev, "ngroups = %d\n", info->ngroups); 1114 1115 info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL); 1116 1117 info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL); 1118 1119 info->banks = devm_kcalloc(dev, info->nbanks, sizeof(*info->banks), GFP_KERNEL); 1120 1121 if (!info->functions || !info->groups || !info->banks) 1122 return -ENOMEM; 1123 1124 info->data = (struct aml_pctl_data *)of_device_get_match_data(dev); 1125 1126 pctl_desc->npins = aml_count_pins(np); 1127 1128 pdesc = devm_kcalloc(dev, pctl_desc->npins, sizeof(*pdesc), GFP_KERNEL); 1129 if (!pdesc) 1130 return -ENOMEM; 1131 1132 pctl_desc->pins = pdesc; 1133 1134 bank = 0; 1135 for_each_child_of_node_scoped(np, child) { 1136 if (of_property_read_bool(child, "gpio-controller")) { 1137 const char *bank_name = NULL; 1138 char **pin_names; 1139 1140 ret = aml_gpiolib_register_bank(info, bank, child); 1141 if (ret) 1142 return ret; 1143 1144 k = info->banks[bank].pin_base; 1145 bank_name = info->banks[bank].gpio_chip.label; 1146 1147 pin_names = devm_kasprintf_strarray(dev, bank_name, 1148 info->banks[bank].gpio_chip.ngpio); 1149 if (IS_ERR(pin_names)) 1150 return PTR_ERR(pin_names); 1151 1152 for (j = 0; j < info->banks[bank].gpio_chip.ngpio; j++, k++) { 1153 pdesc->number = k; 1154 pdesc->name = pin_names[j]; 1155 pdesc++; 1156 } 1157 bank++; 1158 } else { 1159 ret = aml_pctl_parse_functions(child, info, 1160 i++, &grp_index); 1161 if (ret) 1162 return ret; 1163 } 1164 } 1165 1166 return 0; 1167 } 1168 1169 static int aml_pctl_probe(struct platform_device *pdev) 1170 { 1171 struct device *dev = &pdev->dev; 1172 struct aml_pinctrl *info; 1173 struct pinctrl_desc *pctl_desc; 1174 int ret, i; 1175 1176 pctl_desc = devm_kzalloc(dev, sizeof(*pctl_desc), GFP_KERNEL); 1177 if (!pctl_desc) 1178 return -ENOMEM; 1179 1180 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); 1181 if (!info) 1182 return -ENOMEM; 1183 1184 info->dev = dev; 1185 platform_set_drvdata(pdev, info); 1186 ret = aml_pctl_probe_dt(pdev, pctl_desc, info); 1187 if (ret) 1188 return ret; 1189 1190 pctl_desc->owner = THIS_MODULE; 1191 pctl_desc->pctlops = &aml_pctrl_ops; 1192 pctl_desc->pmxops = &aml_pmx_ops; 1193 pctl_desc->confops = &aml_pinconf_ops; 1194 pctl_desc->name = dev_name(dev); 1195 1196 info->pctl = devm_pinctrl_register(dev, pctl_desc, info); 1197 if (IS_ERR(info->pctl)) 1198 return dev_err_probe(dev, PTR_ERR(info->pctl), "Failed pinctrl registration\n"); 1199 1200 for (i = 0; i < info->nbanks; i++) { 1201 ret = gpiochip_add_data(&info->banks[i].gpio_chip, &info->banks[i]); 1202 if (ret) 1203 return dev_err_probe(dev, ret, "Failed to add gpiochip(%d)!\n", i); 1204 } 1205 1206 return 0; 1207 } 1208 1209 static const struct of_device_id aml_pctl_of_match[] = { 1210 { .compatible = "amlogic,pinctrl-a4", }, 1211 { .compatible = "amlogic,pinctrl-a9", .data = &a9_priv_data, }, 1212 { .compatible = "amlogic,pinctrl-s7", .data = &s7_priv_data, }, 1213 { .compatible = "amlogic,pinctrl-s6", .data = &s6_priv_data, }, 1214 { /* sentinel */ } 1215 }; 1216 MODULE_DEVICE_TABLE(of, aml_pctl_of_match); 1217 1218 static struct platform_driver aml_pctl_driver = { 1219 .driver = { 1220 .name = "amlogic-pinctrl", 1221 .of_match_table = aml_pctl_of_match, 1222 }, 1223 .probe = aml_pctl_probe, 1224 }; 1225 module_platform_driver(aml_pctl_driver); 1226 1227 MODULE_AUTHOR("Xianwei Zhao <xianwei.zhao@amlogic.com>"); 1228 MODULE_DESCRIPTION("Pin controller and GPIO driver for Amlogic SoC"); 1229 MODULE_LICENSE("Dual BSD/GPL"); 1230