1 /* SPDX-License-Identifier: MIT */
2 /*
3 * Copyright (C) 2015-2020 Advanced Micro Devices, Inc. All rights reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27 #ifndef __AMDGPU_DM_H__
28 #define __AMDGPU_DM_H__
29
30 #include <drm/display/drm_dp_mst_helper.h>
31 #include <drm/drm_atomic.h>
32 #include <drm/drm_connector.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_plane.h>
35 #include "link_service_types.h"
36 #include <drm/drm_writeback.h>
37
38 /*
39 * This file contains the definition for amdgpu_display_manager
40 * and its API for amdgpu driver's use.
41 * This component provides all the display related functionality
42 * and this is the only component that calls DAL API.
43 * The API contained here intended for amdgpu driver use.
44 * The API that is called directly from KMS framework is located
45 * in amdgpu_dm_kms.h file
46 */
47
48 #define AMDGPU_DM_MAX_CRTC 6
49
50 #define AMDGPU_DM_MAX_NUM_EDP 2
51
52 #define AMDGPU_DMUB_NOTIFICATION_MAX 8
53
54 enum amd_vsdb_panel_type {
55 AMD_VSDB_PANEL_TYPE_DEFAULT = 0,
56 AMD_VSDB_PANEL_TYPE_MINILED,
57 AMD_VSDB_PANEL_TYPE_OLED,
58 AMD_VSDB_PANEL_TYPE_RESERVED,
59 };
60
61 #define AMDGPU_HDR_MULT_DEFAULT (0x100000000LL)
62
63 /*
64 * Maximum HDMI HPD debounce delay in milliseconds
65 */
66 #define AMDGPU_DM_MAX_HDMI_HPD_DEBOUNCE_MS 5000
67 /*
68 #include "include/amdgpu_dal_power_if.h"
69 #include "amdgpu_dm_irq.h"
70 */
71
72 #include "irq_types.h"
73 #include "signal_types.h"
74 #include "amdgpu_dm_crc.h"
75 #include "mod_info_packet.h"
76 struct aux_payload;
77 struct set_config_cmd_payload;
78 enum aux_return_code_type;
79 enum set_config_status;
80
81 /* Forward declarations */
82 struct amdgpu_device;
83 struct amdgpu_crtc;
84 struct drm_device;
85 struct dc;
86 struct amdgpu_bo;
87 struct dmub_srv;
88 struct dc_plane_state;
89 struct dmub_notification;
90 struct dmub_cmd_fused_request;
91
92 struct common_irq_params {
93 struct amdgpu_device *adev;
94 enum dc_irq_source irq_src;
95 atomic64_t previous_timestamp;
96 };
97
98 /**
99 * struct dm_compressor_info - Buffer info used by frame buffer compression
100 * @cpu_addr: MMIO cpu addr
101 * @bo_ptr: Pointer to the buffer object
102 * @gpu_addr: MMIO gpu addr
103 */
104 struct dm_compressor_info {
105 void *cpu_addr;
106 struct amdgpu_bo *bo_ptr;
107 uint64_t gpu_addr;
108 };
109
110 /**
111 * struct dm_boot_time_crc_info - Buffer info used by boot time CRC
112 * @cpu_addr: MMIO cpu addr
113 * @bo_ptr: Pointer to the buffer object
114 * @gpu_addr: MMIO gpu addr
115 * @size: Size of the buffer
116 */
117 struct dm_boot_time_crc_info {
118 void *cpu_addr;
119 struct amdgpu_bo *bo_ptr;
120 uint64_t gpu_addr;
121 uint32_t size;
122 };
123
124 typedef void (*dmub_notify_interrupt_callback_t)(struct amdgpu_device *adev, struct dmub_notification *notify);
125
126 /**
127 * struct dmub_hpd_work - Handle time consuming work in low priority outbox IRQ
128 *
129 * @handle_hpd_work: Work to be executed in a separate thread to handle hpd_low_irq
130 * @dmub_notify: notification for callback function
131 * @adev: amdgpu_device pointer
132 */
133 struct dmub_hpd_work {
134 struct work_struct handle_hpd_work;
135 struct dmub_notification *dmub_notify;
136 struct amdgpu_device *adev;
137 };
138
139 /**
140 * struct vblank_control_work - Work data for vblank control
141 * @work: Kernel work data for the work event
142 * @dm: amdgpu display manager device
143 * @acrtc: amdgpu CRTC instance for which the event has occurred
144 * @stream: DC stream for which the event has occurred
145 * @enable: true if enabling vblank
146 */
147 struct vblank_control_work {
148 struct work_struct work;
149 struct amdgpu_display_manager *dm;
150 struct amdgpu_crtc *acrtc;
151 struct dc_stream_state *stream;
152 bool enable;
153 };
154
155 /**
156 * struct idle_workqueue - Work data for periodic action in idle
157 * @work: Kernel work data for the work event
158 * @dm: amdgpu display manager device
159 * @enable: true if idle worker is enabled
160 * @running: true if idle worker is running
161 */
162 struct idle_workqueue {
163 struct work_struct work;
164 struct amdgpu_display_manager *dm;
165 bool enable;
166 bool running;
167 };
168
169 /**
170 * struct vupdate_offload_work - Work data for offloading task from vupdate handler
171 * @work: Kernel work data for the work event
172 * @adev: amdgpu_device back pointer
173 * @stream: DC stream associated with the crtc
174 * @adjust: DC CRTC timing adjust to be applied to the crtc
175 */
176 struct vupdate_offload_work {
177 struct work_struct work;
178 struct amdgpu_device *adev;
179 struct dc_stream_state *stream;
180 struct dc_crtc_timing_adjust *adjust;
181 };
182
183 #define MAX_LUMINANCE_DATA_POINTS 99
184
185 /**
186 * struct amdgpu_dm_luminance_data - Custom luminance data
187 * @luminance: Luminance in percent
188 * @input_signal: Input signal in range 0-255
189 */
190 struct amdgpu_dm_luminance_data {
191 u8 luminance;
192 u8 input_signal;
193 } __packed;
194
195 /**
196 * struct amdgpu_dm_backlight_caps - Information about backlight
197 *
198 * Describe the backlight support for ACPI or eDP AUX.
199 */
200 struct amdgpu_dm_backlight_caps {
201 /**
202 * @ext_caps: Keep the data struct with all the information about the
203 * display support for HDR.
204 */
205 union dpcd_sink_ext_caps *ext_caps;
206 /**
207 * @aux_min_input_signal: Min brightness value supported by the display
208 */
209 u32 aux_min_input_signal;
210 /**
211 * @aux_max_input_signal: Max brightness value supported by the display
212 * in nits.
213 */
214 u32 aux_max_input_signal;
215 /**
216 * @min_input_signal: minimum possible input in range 0-255.
217 */
218 int min_input_signal;
219 /**
220 * @max_input_signal: maximum possible input in range 0-255.
221 */
222 int max_input_signal;
223 /**
224 * @caps_valid: true if these values are from the ACPI interface.
225 */
226 bool caps_valid;
227 /**
228 * @aux_support: Describes if the display supports AUX backlight.
229 */
230 bool aux_support;
231 /**
232 * @brightness_mask: After deriving brightness, OR it with this mask.
233 * Workaround for panels with issues with certain brightness values.
234 */
235 u32 brightness_mask;
236 /**
237 * @ac_level: the default brightness if booted on AC
238 */
239 u8 ac_level;
240 /**
241 * @dc_level: the default brightness if booted on DC
242 */
243 u8 dc_level;
244 /**
245 * @data_points: the number of custom luminance data points
246 */
247 u8 data_points;
248 /**
249 * @luminance_data: custom luminance data
250 */
251 struct amdgpu_dm_luminance_data luminance_data[MAX_LUMINANCE_DATA_POINTS];
252 };
253
254 /**
255 * struct dal_allocation - Tracks mapped FB memory for SMU communication
256 * @list: list of dal allocations
257 * @bo: GPU buffer object
258 * @cpu_ptr: CPU virtual address of the GPU buffer object
259 * @gpu_addr: GPU virtual address of the GPU buffer object
260 */
261 struct dal_allocation {
262 struct list_head list;
263 struct amdgpu_bo *bo;
264 void *cpu_ptr;
265 u64 gpu_addr;
266 };
267
268 /**
269 * struct hpd_rx_irq_offload_work_queue - Work queue to handle hpd_rx_irq
270 * offload work
271 */
272 struct hpd_rx_irq_offload_work_queue {
273 /**
274 * @wq: workqueue structure to queue offload work.
275 */
276 struct workqueue_struct *wq;
277 /**
278 * @offload_lock: To protect fields of offload work queue.
279 */
280 spinlock_t offload_lock;
281 /**
282 * @is_handling_link_loss: Used to prevent inserting link loss event when
283 * we're handling link loss
284 */
285 bool is_handling_link_loss;
286 /**
287 * @is_handling_mst_msg_rdy_event: Used to prevent inserting mst message
288 * ready event when we're already handling mst message ready event
289 */
290 bool is_handling_mst_msg_rdy_event;
291 /**
292 * @aconnector: The aconnector that this work queue is attached to
293 */
294 struct amdgpu_dm_connector *aconnector;
295 };
296
297 /**
298 * struct hpd_rx_irq_offload_work - hpd_rx_irq offload work structure
299 */
300 struct hpd_rx_irq_offload_work {
301 /**
302 * @work: offload work
303 */
304 struct work_struct work;
305 /**
306 * @data: reference irq data which is used while handling offload work
307 */
308 union hpd_irq_data data;
309 /**
310 * @offload_wq: offload work queue that this work is queued to
311 */
312 struct hpd_rx_irq_offload_work_queue *offload_wq;
313 /**
314 * @adev: amdgpu_device pointer
315 */
316 struct amdgpu_device *adev;
317 };
318
319 /**
320 * struct amdgpu_display_manager - Central amdgpu display manager device
321 *
322 * @dc: Display Core control structure
323 * @adev: AMDGPU base driver structure
324 * @ddev: DRM base driver structure
325 * @display_indexes_num: Max number of display streams supported
326 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables
327 * @irq_wq: Dedicated high-priority unbound workqueue for deferred IRQ work
328 * @vmin_vmax_wq: Dedicated unbound workqueue for deferred vmin/vmax updates
329 * @backlight_dev: Backlight control device
330 * @backlight_link: Link on which to control backlight
331 * @backlight_caps: Capabilities of the backlight device
332 * @freesync_module: Module handling freesync calculations
333 * @hdcp_workqueue: AMDGPU content protection queue
334 * @fw_dmcu: Reference to DMCU firmware
335 * @dmcu_fw_version: Version of the DMCU firmware
336 * @soc_bounding_box: SOC bounding box values provided by gpu_info FW
337 * @cached_state: Caches device atomic state for suspend/resume
338 * @cached_dc_state: Cached state of content streams
339 * @compressor: Frame buffer compression buffer. See &struct dm_compressor_info
340 * @force_timing_sync: set via debugfs. When set, indicates that all connected
341 * displays will be forced to synchronize.
342 * @dmcub_trace_event_en: enable dmcub trace events
343 * @dmub_outbox_params: DMUB Outbox parameters
344 * @num_of_edps: number of backlight eDPs
345 * @disable_hpd_irq: disables all HPD and HPD RX interrupt handling in the
346 * driver when true
347 * @dmub_aux_transfer_done: struct completion used to indicate when DMUB
348 * transfers are done
349 * @delayed_hpd_wq: work queue used to delay DMUB HPD work
350 */
351 struct amdgpu_display_manager {
352
353 struct dc *dc;
354
355 /**
356 * @dmub_srv:
357 *
358 * DMUB service, used for controlling the DMUB on hardware
359 * that supports it. The pointer to the dmub_srv will be
360 * NULL on hardware that does not support it.
361 */
362 struct dmub_srv *dmub_srv;
363
364 /**
365 * @dmub_notify:
366 *
367 * Notification from DMUB.
368 */
369
370 struct dmub_notification *dmub_notify;
371
372 /**
373 * @dmub_callback:
374 *
375 * Callback functions to handle notification from DMUB.
376 */
377
378 dmub_notify_interrupt_callback_t dmub_callback[AMDGPU_DMUB_NOTIFICATION_MAX];
379
380 /**
381 * @dmub_thread_offload:
382 *
383 * Flag to indicate if callback is offload.
384 */
385
386 bool dmub_thread_offload[AMDGPU_DMUB_NOTIFICATION_MAX];
387
388 /**
389 * @dmub_fb_info:
390 *
391 * Framebuffer regions for the DMUB.
392 */
393 struct dmub_srv_fb_info *dmub_fb_info;
394
395 /**
396 * @dmub_fw:
397 *
398 * DMUB firmware, required on hardware that has DMUB support.
399 */
400 const struct firmware *dmub_fw;
401
402 /**
403 * @dmub_bo:
404 *
405 * Buffer object for the DMUB.
406 */
407 struct amdgpu_bo *dmub_bo;
408
409 /**
410 * @dmub_bo_gpu_addr:
411 *
412 * GPU virtual address for the DMUB buffer object.
413 */
414 u64 dmub_bo_gpu_addr;
415
416 /**
417 * @dmub_bo_cpu_addr:
418 *
419 * CPU address for the DMUB buffer object.
420 */
421 void *dmub_bo_cpu_addr;
422
423 /**
424 * @dmcub_fw_version:
425 *
426 * DMCUB firmware version.
427 */
428 uint32_t dmcub_fw_version;
429
430 /**
431 * @fw_inst_size:
432 *
433 * Size of the firmware instruction buffer.
434 */
435 uint32_t fw_inst_size;
436
437 /**
438 * @cgs_device:
439 *
440 * The Common Graphics Services device. It provides an interface for
441 * accessing registers.
442 */
443 struct cgs_device *cgs_device;
444
445 struct amdgpu_device *adev;
446 struct drm_device *ddev;
447 u16 display_indexes_num;
448
449 /**
450 * @atomic_obj:
451 *
452 * In combination with &dm_atomic_state it helps manage
453 * global atomic state that doesn't map cleanly into existing
454 * drm resources, like &dc_context.
455 */
456 struct drm_private_obj atomic_obj;
457
458 /**
459 * @dc_lock:
460 *
461 * Guards access to DC functions that can issue register write
462 * sequences.
463 */
464 struct mutex dc_lock;
465
466 /**
467 * @dmub_lock:
468 *
469 * Guards access to DMUB command submission.
470 */
471 spinlock_t dmub_lock;
472
473 /**
474 * @audio_lock:
475 *
476 * Guards access to audio instance changes.
477 */
478 struct mutex audio_lock;
479
480 /**
481 * @audio_component:
482 *
483 * Used to notify ELD changes to sound driver.
484 */
485 struct drm_audio_component *audio_component;
486
487 /**
488 * @audio_registered:
489 *
490 * True if the audio component has been registered
491 * successfully, false otherwise.
492 */
493 bool audio_registered;
494
495 /**
496 * @irq_handler_list_low_tab:
497 *
498 * Low priority IRQ handler table.
499 *
500 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ
501 * source. Low priority IRQ handlers are deferred to a workqueue to be
502 * processed. Hence, they can sleep.
503 *
504 * Note that handlers are called in the same order as they were
505 * registered (FIFO).
506 */
507 struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER];
508
509 /**
510 * @irq_handler_list_high_tab:
511 *
512 * High priority IRQ handler table.
513 *
514 * It is a n*m table, same as &irq_handler_list_low_tab. However,
515 * handlers in this table are not deferred and are called immediately.
516 */
517 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER];
518
519 /**
520 * @pflip_params:
521 *
522 * Page flip IRQ parameters, passed to registered handlers when
523 * triggered.
524 */
525 struct common_irq_params
526 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1];
527
528 /**
529 * @vblank_params:
530 *
531 * Vertical blanking IRQ parameters, passed to registered handlers when
532 * triggered.
533 */
534 struct common_irq_params
535 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1];
536
537 /**
538 * @vline0_params:
539 *
540 * OTG vertical interrupt0 IRQ parameters, passed to registered
541 * handlers when triggered.
542 */
543 struct common_irq_params
544 vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1];
545
546 /**
547 * @vupdate_params:
548 *
549 * Vertical update IRQ parameters, passed to registered handlers when
550 * triggered.
551 */
552 struct common_irq_params
553 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1];
554
555 /**
556 * @irq_reg_lock:
557 *
558 * Serializes the read-modify-writes of the HW interrupt control
559 * registers. Several interrupt sources share one register - e.g. the
560 * enable and clear bits of both VSTARTUP (vblank) and VUPDATE_NO_LOCK
561 * live in OTG_GLOBAL_SYNC_STATUS. Therefore, enabling one source must
562 * not race with acking another. Held only across amdgpu_dm_irq_set()
563 * and amdgpu_dm_irq_ack().
564 */
565 spinlock_t irq_reg_lock;
566
567 /**
568 * @dmub_trace_params:
569 *
570 * DMUB trace event IRQ parameters, passed to registered handlers when
571 * triggered.
572 */
573 struct common_irq_params
574 dmub_trace_params[1];
575
576 struct common_irq_params
577 dmub_outbox_params[1];
578
579 spinlock_t irq_handler_list_table_lock;
580 struct workqueue_struct *irq_wq;
581 struct workqueue_struct *vmin_vmax_wq;
582
583 struct backlight_device *backlight_dev[AMDGPU_DM_MAX_NUM_EDP];
584
585 const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP];
586
587 uint8_t num_of_edps;
588
589 struct amdgpu_dm_backlight_caps backlight_caps[AMDGPU_DM_MAX_NUM_EDP];
590
591 struct mod_freesync *freesync_module;
592 struct mod_power *power_module;
593 struct hdcp_workqueue *hdcp_workqueue;
594
595 /**
596 * @vblank_control_workqueue:
597 *
598 * Deferred work for vblank control events.
599 */
600 struct workqueue_struct *vblank_control_workqueue;
601
602 /**
603 * @idle_workqueue:
604 *
605 * Periodic work for idle events.
606 */
607 struct idle_workqueue *idle_workqueue;
608
609 struct drm_atomic_commit *cached_state;
610 struct dc_state *cached_dc_state;
611
612 struct dm_compressor_info compressor;
613
614 const struct firmware *fw_dmcu;
615 uint32_t dmcu_fw_version;
616 /**
617 * @soc_bounding_box:
618 *
619 * gpu_info FW provided soc bounding box struct or 0 if not
620 * available in FW
621 */
622 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
623
624 /**
625 * @active_vblank_irq_count:
626 *
627 * number of currently active vblank irqs
628 */
629 uint32_t active_vblank_irq_count;
630
631 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
632 /**
633 * @secure_display_ctx:
634 *
635 * Store secure display relevant info. e.g. the ROI information
636 * , the work_struct to command dmub, etc.
637 */
638 struct secure_display_context secure_display_ctx;
639 #endif
640 /**
641 * @hpd_rx_offload_wq:
642 *
643 * Work queue to offload works of hpd_rx_irq
644 */
645 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq;
646 /**
647 * @mst_encoders:
648 *
649 * fake encoders used for DP MST.
650 */
651 struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC];
652 bool force_timing_sync;
653 bool disable_hpd_irq;
654 bool dmcub_trace_event_en;
655 /**
656 * @da_list:
657 *
658 * DAL fb memory allocation list, for communication with SMU.
659 */
660 struct list_head da_list;
661 struct completion dmub_aux_transfer_done;
662 struct workqueue_struct *delayed_hpd_wq;
663
664 /**
665 * @brightness:
666 *
667 * cached backlight values.
668 */
669 u32 brightness[AMDGPU_DM_MAX_NUM_EDP];
670 /**
671 * @actual_brightness:
672 *
673 * last successfully applied backlight values.
674 */
675 u32 actual_brightness[AMDGPU_DM_MAX_NUM_EDP];
676
677 /**
678 * @aux_hpd_discon_quirk:
679 *
680 * quirk for hpd discon while aux is on-going.
681 * occurred on certain intel platform
682 */
683 bool aux_hpd_discon_quirk;
684
685 /**
686 * @edp0_on_dp1_quirk:
687 *
688 * quirk for platforms that put edp0 on DP1.
689 */
690 bool edp0_on_dp1_quirk;
691
692 /**
693 * @dpia_aux_lock:
694 *
695 * Guards access to DPIA AUX
696 */
697 struct mutex dpia_aux_lock;
698
699 /**
700 * @bb_from_dmub:
701 *
702 * Bounding box data read from dmub during early initialization for DCN4+
703 * Data is stored as a byte array that should be casted to the appropriate bb struct
704 */
705 void *bb_from_dmub;
706
707 /**
708 * @i2c_devres_group:
709 *
710 * Devres group for DM i2c adapter lifetime management.
711 */
712 void *i2c_devres_group;
713
714 /**
715 * @oem_i2c:
716 *
717 * OEM i2c bus
718 */
719 struct amdgpu_i2c_adapter *oem_i2c;
720
721 /**
722 * @fused_io:
723 *
724 * dmub fused io interface
725 */
726 struct fused_io_sync {
727 struct completion replied;
728 char reply_data[0x40]; // Cannot include dmub_cmd here
729 } fused_io[8];
730 /**
731 * @hdmi_frl_status_polling_work:
732 *
733 * workqueue for 200ms frl status polling
734 */
735 struct workqueue_struct *hdmi_frl_status_polling_wq;
736 struct delayed_work hdmi_frl_status_polling_work;
737 unsigned int hdmi_frl_status_polling_delay_ms;
738
739 /**
740 * @dm_boot_time_crc_info:
741 *
742 * Buffer info for the boot time crc.
743 */
744 struct dm_boot_time_crc_info boot_time_crc_info;
745 };
746
747 enum dsc_clock_force_state {
748 DSC_CLK_FORCE_DEFAULT = 0,
749 DSC_CLK_FORCE_ENABLE,
750 DSC_CLK_FORCE_DISABLE,
751 };
752
753 struct dsc_preferred_settings {
754 enum dsc_clock_force_state dsc_force_enable;
755 uint32_t dsc_num_slices_v;
756 uint32_t dsc_num_slices_h;
757 uint32_t dsc_bits_per_pixel;
758 bool dsc_force_disable_passthrough;
759 };
760
761 enum mst_progress_status {
762 MST_STATUS_DEFAULT = 0,
763 MST_PROBE = BIT(0),
764 MST_REMOTE_EDID = BIT(1),
765 MST_ALLOCATE_NEW_PAYLOAD = BIT(2),
766 MST_CLEAR_ALLOCATED_PAYLOAD = BIT(3),
767 };
768
769 /**
770 * struct amdgpu_hdmi_vsdb_info - Keep track of the VSDB info
771 *
772 * AMDGPU supports FreeSync over HDMI by using the VSDB section, and this
773 * struct is useful to keep track of the display-specific information about
774 * FreeSync.
775 */
776 struct amdgpu_hdmi_vsdb_info {
777 /**
778 * @amd_vsdb_version: Vendor Specific Data Block Version, should be
779 * used to determine which Vendor Specific InfoFrame (VSIF) to send.
780 */
781 unsigned int amd_vsdb_version;
782
783 /**
784 * @freesync_supported: FreeSync Supported.
785 */
786 bool freesync_supported;
787
788 /**
789 * @min_refresh_rate_hz: FreeSync Minimum Refresh Rate in Hz.
790 */
791 unsigned int min_refresh_rate_hz;
792
793 /**
794 * @max_refresh_rate_hz: FreeSync Maximum Refresh Rate in Hz
795 */
796 unsigned int max_refresh_rate_hz;
797
798 /**
799 * @freesync_mccs_vcp_code: MCCS VCP code for freesync state
800 */
801 unsigned int freesync_mccs_vcp_code;
802
803 /**
804 * @replay_mode: Replay supported
805 */
806 bool replay_mode;
807 };
808
809 struct amdgpu_dm_connector {
810
811 struct drm_connector base;
812 uint32_t connector_id;
813 int bl_idx;
814
815 struct cec_notifier *notifier;
816
817 /* we need to mind the EDID between detect
818 and get modes due to analog/digital/tvencoder */
819 const struct drm_edid *drm_edid;
820
821 /* shared with amdgpu */
822 struct amdgpu_hpd hpd;
823
824 /* number of modes generated from EDID at 'dc_sink' */
825 int num_modes;
826
827 /* The 'old' sink - before an HPD.
828 * The 'current' sink is in dc_link->sink. */
829 struct dc_sink *dc_sink;
830 struct dc_link *dc_link;
831
832 /**
833 * @dc_em_sink: Reference to the emulated (virtual) sink.
834 */
835 struct dc_sink *dc_em_sink;
836
837 /* DM only */
838 struct drm_dp_mst_topology_mgr mst_mgr;
839 struct amdgpu_dm_dp_aux dm_dp_aux;
840 struct drm_dp_mst_port *mst_output_port;
841 struct amdgpu_dm_connector *mst_root;
842 struct drm_dp_aux *dsc_aux;
843 uint32_t mst_local_bw;
844 uint16_t vc_full_pbn;
845 struct mutex handle_mst_msg_ready;
846
847 /* branch device specific data */
848 uint32_t branch_ieee_oui;
849
850 /* TODO see if we can merge with ddc_bus or make a dm_connector */
851 struct amdgpu_i2c_adapter *i2c;
852
853 /* Monitor range limits */
854 /**
855 * @min_vfreq: Minimal frequency supported by the display in Hz. This
856 * value is set to zero when there is no FreeSync support.
857 */
858 int min_vfreq;
859
860 /**
861 * @max_vfreq: Maximum frequency supported by the display in Hz. This
862 * value is set to zero when there is no FreeSync support.
863 */
864 int max_vfreq ;
865
866 /* Audio instance - protected by audio_lock. */
867 int audio_inst;
868
869 struct mutex hpd_lock;
870
871 bool fake_enable;
872 uint8_t force_yuv_pixel_format;
873 struct dsc_preferred_settings dsc_settings;
874 struct psr_caps psr_caps;
875 union dp_downstream_port_present mst_downstream_port_present;
876 /* Cached display modes */
877 struct drm_display_mode freesync_vid_base;
878
879 int sr_skip_count;
880 bool disallow_edp_enter_psr;
881 bool disallow_edp_enter_replay;
882
883 union dwnstream_portxcaps mst_downstream_port_caps;
884
885 /* Record progress status of mst*/
886 uint8_t mst_status;
887
888 /* Automated testing */
889 bool timing_changed;
890 struct dc_crtc_timing *timing_requested;
891
892 /* Adaptive Sync */
893 bool pack_sdp_v1_3;
894 enum adaptive_sync_type as_type;
895 struct amdgpu_hdmi_vsdb_info vsdb_info;
896
897 /* HDMI HPD debounce support */
898 unsigned int hdmi_hpd_debounce_delay_ms;
899 struct delayed_work hdmi_hpd_debounce_work;
900 struct dc_sink *hdmi_prev_sink;
901
902 /* HDMI compliance automation */
903 bool hdmi_comp_auto;
904 };
905
amdgpu_dm_set_mst_status(uint8_t * status,uint8_t flags,bool set)906 static inline void amdgpu_dm_set_mst_status(uint8_t *status,
907 uint8_t flags, bool set)
908 {
909 if (set)
910 *status |= flags;
911 else
912 *status &= ~flags;
913 }
914
915 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base)
916
917 struct amdgpu_dm_wb_connector {
918 struct drm_writeback_connector base;
919 struct dc_link *link;
920 };
921
922 #define to_amdgpu_dm_wb_connector(x) container_of(x, struct amdgpu_dm_wb_connector, base)
923
924 extern const struct amdgpu_ip_block_version dm_ip_block;
925
926 /* enum amdgpu_transfer_function: pre-defined transfer function supported by AMD.
927 *
928 * It includes standardized transfer functions and pure power functions. The
929 * transfer function coefficients are available at modules/color/color_gamma.c
930 */
931 enum amdgpu_transfer_function {
932 AMDGPU_TRANSFER_FUNCTION_DEFAULT,
933 AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF,
934 AMDGPU_TRANSFER_FUNCTION_BT709_INV_OETF,
935 AMDGPU_TRANSFER_FUNCTION_PQ_EOTF,
936 AMDGPU_TRANSFER_FUNCTION_IDENTITY,
937 AMDGPU_TRANSFER_FUNCTION_GAMMA22_EOTF,
938 AMDGPU_TRANSFER_FUNCTION_GAMMA24_EOTF,
939 AMDGPU_TRANSFER_FUNCTION_GAMMA26_EOTF,
940 AMDGPU_TRANSFER_FUNCTION_SRGB_INV_EOTF,
941 AMDGPU_TRANSFER_FUNCTION_BT709_OETF,
942 AMDGPU_TRANSFER_FUNCTION_PQ_INV_EOTF,
943 AMDGPU_TRANSFER_FUNCTION_GAMMA22_INV_EOTF,
944 AMDGPU_TRANSFER_FUNCTION_GAMMA24_INV_EOTF,
945 AMDGPU_TRANSFER_FUNCTION_GAMMA26_INV_EOTF,
946 AMDGPU_TRANSFER_FUNCTION_COUNT
947 };
948
949 struct dm_plane_state {
950 struct drm_plane_state base;
951 struct dc_plane_state *dc_state;
952
953 /* Plane color mgmt */
954 /**
955 * @degamma_lut:
956 *
957 * 1D LUT for mapping framebuffer/plane pixel data before sampling or
958 * blending operations. It's usually applied to linearize input space.
959 * The blob (if not NULL) is an array of &struct drm_color_lut.
960 */
961 struct drm_property_blob *degamma_lut;
962 /**
963 * @degamma_tf:
964 *
965 * Predefined transfer function to tell DC driver the input space to
966 * linearize.
967 */
968 enum amdgpu_transfer_function degamma_tf;
969 /**
970 * @hdr_mult:
971 *
972 * Multiplier to 'gain' the plane. When PQ is decoded using the fixed
973 * func transfer function to the internal FP16 fb, 1.0 -> 80 nits (on
974 * AMD at least). When sRGB is decoded, 1.0 -> 1.0, obviously.
975 * Therefore, 1.0 multiplier = 80 nits for SDR content. So if you
976 * want, 203 nits for SDR content, pass in (203.0 / 80.0). Format is
977 * S31.32 sign-magnitude.
978 *
979 * HDR multiplier can wide range beyond [0.0, 1.0]. This means that PQ
980 * TF is needed for any subsequent linear-to-non-linear transforms.
981 */
982 __u64 hdr_mult;
983 /**
984 * @ctm:
985 *
986 * Color transformation matrix. The blob (if not NULL) is a &struct
987 * drm_color_ctm_3x4.
988 */
989 struct drm_property_blob *ctm;
990 /**
991 * @shaper_lut: shaper lookup table blob. The blob (if not NULL) is an
992 * array of &struct drm_color_lut.
993 */
994 struct drm_property_blob *shaper_lut;
995 /**
996 * @shaper_tf:
997 *
998 * Predefined transfer function to delinearize color space.
999 */
1000 enum amdgpu_transfer_function shaper_tf;
1001 /**
1002 * @lut3d: 3D lookup table blob. The blob (if not NULL) is an array of
1003 * &struct drm_color_lut.
1004 */
1005 struct drm_property_blob *lut3d;
1006 /**
1007 * @blend_lut: blend lut lookup table blob. The blob (if not NULL) is an
1008 * array of &struct drm_color_lut.
1009 */
1010 struct drm_property_blob *blend_lut;
1011 /**
1012 * @blend_tf:
1013 *
1014 * Pre-defined transfer function for converting plane pixel data before
1015 * applying blend LUT.
1016 */
1017 enum amdgpu_transfer_function blend_tf;
1018 };
1019
1020 enum amdgpu_dm_cursor_mode {
1021 DM_CURSOR_NATIVE_MODE = 0,
1022 DM_CURSOR_OVERLAY_MODE,
1023 };
1024
1025 struct dm_crtc_state {
1026 struct drm_crtc_state base;
1027 struct dc_stream_state *stream;
1028
1029 bool cm_has_degamma;
1030 bool cm_is_degamma_srgb;
1031
1032 bool mpo_requested;
1033
1034 int update_type;
1035 int active_planes;
1036
1037 int crc_skip_count;
1038
1039 bool freesync_vrr_info_changed;
1040
1041 bool mode_changed_independent_from_dsc;
1042 bool dsc_force_changed;
1043 bool vrr_supported;
1044 struct mod_freesync_config freesync_config;
1045 struct dc_info_packet vrr_infopacket;
1046
1047 int abm_level;
1048
1049 /**
1050 * @regamma_tf:
1051 *
1052 * Pre-defined transfer function for converting internal FB -> wire
1053 * encoding.
1054 */
1055 enum amdgpu_transfer_function regamma_tf;
1056
1057 enum amdgpu_dm_cursor_mode cursor_mode;
1058 };
1059
1060 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base)
1061
1062 struct dm_atomic_state {
1063 struct drm_private_state base;
1064
1065 struct dc_state *context;
1066 };
1067
1068 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base)
1069
1070 struct dm_connector_state {
1071 struct drm_connector_state base;
1072
1073 enum amdgpu_rmx_type scaling;
1074 uint8_t underscan_vborder;
1075 uint8_t underscan_hborder;
1076 bool underscan_enable;
1077 bool freesync_capable;
1078 bool update_hdcp;
1079 bool abm_sysfs_forbidden;
1080 uint8_t abm_level;
1081 int vcpi_slots;
1082 uint64_t pbn;
1083 };
1084
1085 #define to_dm_connector_state(x)\
1086 container_of((x), struct dm_connector_state, base)
1087
1088 #include "amdgpu_dm_connector.h"
1089
1090 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev);
1091
1092 /* 3D LUT max size is 17x17x17 (4913 entries) */
1093 #define MAX_COLOR_3DLUT_SIZE 17
1094 #define MAX_COLOR_3DLUT_BITDEPTH 12
1095 int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *adev,
1096 struct drm_plane_state *plane_state);
1097 /* 1D LUT size */
1098 #define MAX_COLOR_LUT_ENTRIES 4096
1099 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */
1100 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256
1101
1102 void amdgpu_dm_init_color_mod(void);
1103 int amdgpu_dm_create_color_properties(struct amdgpu_device *adev);
1104 int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state);
1105 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc);
1106 int amdgpu_dm_check_crtc_color_mgmt(struct dm_crtc_state *crtc,
1107 bool check_only);
1108 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
1109 struct drm_plane_state *plane_state,
1110 struct dc_plane_state *dc_plane_state);
1111
1112 void populate_hdmi_info_from_connector(bool enable_frl, struct drm_hdmi_info *info,
1113 struct dc_edid_caps *edid_caps);
1114
1115 int amdgpu_dm_process_dmub_aux_transfer_sync(struct dc_context *ctx, unsigned int link_index,
1116 struct aux_payload *payload, enum aux_return_code_type *operation_result);
1117
1118 bool amdgpu_dm_execute_fused_io(
1119 struct amdgpu_device *dev,
1120 struct dc_link *link,
1121 union dmub_rb_cmd *commands,
1122 uint8_t count,
1123 uint32_t timeout_us
1124 );
1125
1126 int amdgpu_dm_process_dmub_set_config_sync(struct dc_context *ctx, unsigned int link_index,
1127 struct set_config_cmd_payload *payload, enum set_config_status *operation_result);
1128
1129 int dm_atomic_get_state(struct drm_atomic_commit *state,
1130 struct dm_atomic_state **dm_state);
1131
1132 struct idle_workqueue *idle_create_workqueue(struct amdgpu_device *adev);
1133
1134 void *dm_allocate_gpu_mem(struct amdgpu_device *adev,
1135 enum dc_gpu_mem_alloc_type type,
1136 size_t size,
1137 long long *addr);
1138 void dm_free_gpu_mem(struct amdgpu_device *adev,
1139 enum dc_gpu_mem_alloc_type type,
1140 void *addr);
1141
1142 bool amdgpu_dm_is_headless(struct amdgpu_device *adev);
1143
1144 bool amdgpu_dm_crtc_complete_writeback(struct amdgpu_crtc *acrtc);
1145
1146 void retrieve_dmi_info(struct amdgpu_display_manager *dm);
1147 struct pci_dev;
1148 bool dm_should_disable_stutter(struct pci_dev *pdev);
1149
1150 void amdgpu_dm_emulated_link_detect(struct dc_link *link);
1151 void amdgpu_dm_apply_delay_after_dpcd_poweroff(struct amdgpu_device *adev,
1152 struct dc_sink *sink);
1153
1154 struct __drm_planes_state *amdgpu_dm_get_next_zpos(struct drm_atomic_commit *state,
1155 struct __drm_planes_state *prev);
1156
1157 /*
1158 * Use the uniqueness of the plane's (zpos, drm obj ID) combination to iterate
1159 * by descending zpos, as read from the new plane state. This is the same
1160 * ordering as defined by drm_atomic_normalize_zpos().
1161 */
1162 #define for_each_oldnew_plane_in_descending_zpos(__state, plane, old_plane_state, new_plane_state) \
1163 for (struct __drm_planes_state *__i = amdgpu_dm_get_next_zpos((__state), NULL); \
1164 __i != NULL; __i = amdgpu_dm_get_next_zpos((__state), __i)) \
1165 for_each_if(((plane) = __i->ptr, \
1166 (void)(plane) /* Only to avoid unused-but-set-variable warning */, \
1167 (old_plane_state) = __i->old_state, \
1168 (new_plane_state) = __i->new_state, 1))
1169
1170 #if IS_ENABLED(CONFIG_DRM_AMD_DC_KUNIT_TEST)
1171 struct amdgpu_ip_block;
1172 bool dm_is_idle(struct amdgpu_ip_block *ip_block);
1173 int dm_wait_for_idle(struct amdgpu_ip_block *ip_block);
1174 int dm_soft_reset(struct amdgpu_ip_block *ip_block);
1175 int dm_set_clockgating_state(struct amdgpu_ip_block *ip_block,
1176 enum amd_clockgating_state state);
1177 int dm_set_powergating_state(struct amdgpu_ip_block *ip_block,
1178 enum amd_powergating_state state);
1179 void dm_bandwidth_update(struct amdgpu_device *adev);
1180 u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc);
1181 int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
1182 u32 *vbl, u32 *position);
1183 struct dm_atomic_state *dm_atomic_get_new_state(struct drm_atomic_commit *state);
1184 void dm_atomic_destroy_state(struct drm_private_obj *obj,
1185 struct drm_private_state *state);
1186 int dm_plane_layer_index_cmp(const void *a, const void *b);
1187 int fill_plane_color_attributes(const struct drm_plane_state *plane_state,
1188 const enum surface_pixel_format format,
1189 enum dc_color_space *color_space);
1190 bool modereset_required(struct drm_crtc_state *crtc_state);
1191 bool is_scaling_state_different(const struct dm_connector_state *dm_state,
1192 const struct dm_connector_state *old_dm_state);
1193 void set_multisync_trigger_params(struct dc_stream_state *stream);
1194 void set_master_stream(struct dc_stream_state *stream_set[], int stream_count);
1195 void dm_enable_per_frame_crtc_master_sync(struct dc_state *context);
1196 struct hdcp_workqueue;
1197 bool is_content_protection_different(struct drm_crtc_state *new_crtc_state,
1198 struct drm_crtc_state *old_crtc_state,
1199 struct drm_connector_state *new_conn_state,
1200 struct drm_connector_state *old_conn_state,
1201 const struct drm_connector *connector,
1202 struct hdcp_workqueue *hdcp_w);
1203 #endif
1204
1205 #endif /* __AMDGPU_DM_H__ */
1206